69 uint32_t value, uint32_t *dscr);
77 static unsigned int ilog2(
unsigned int x)
117 if (phys_access == 0) {
146 if (phys_access == 0) {
177 LOG_ERROR(
"trying to enable mmu on target stopped with mmu disable");
192 LOG_DEBUG(
"%s, writing cp15 ctrl: %" PRIx32,
193 enable ?
"enable mmu" :
"disable mmu",
266 LOG_ERROR(
"Could not read DSCR register");
273 LOG_ERROR(
"Error waiting for InstrCompl=1");
283 uint32_t opcode, uint32_t *dscr_p)
289 dscr = dscr_p ? *dscr_p : 0;
291 LOG_DEBUG(
"exec opcode 0x%08" PRIx32, opcode);
306 LOG_ERROR(
"Error waiting for cortex_a_exec_opcode");
347 LOG_DEBUG(
"write DCC 0x%08" PRIx32, data);
390 LOG_ERROR(
"Error waiting for dpm prepare");
396 LOG_ERROR(
"DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
416 uint32_t opcode, uint32_t data)
433 uint8_t rt, uint32_t data)
454 uint32_t opcode, uint32_t data)
485 uint32_t opcode, uint32_t *data)
503 uint8_t rt, uint32_t *data)
523 uint32_t opcode, uint32_t *data)
542 uint32_t
addr, uint32_t control)
565 LOG_DEBUG(
"A: bpwp enable, vr %08x cr %08x",
566 (
unsigned) vr, (
unsigned) cr);
595 LOG_DEBUG(
"A: bpwp disable, cr %08x", (
unsigned) cr);
682 if (curr == gdb_target)
692 if (gdb_target && gdb_target !=
target)
787 target_addr_t *address,
int handle_breakpoints,
int debug_execution)
794 if (!debug_execution)
798 if (debug_execution) {
813 armv7m->core_cache->reg_list[
ARMV7M_XPSR].dirty =
true;
814 armv7m->core_cache->reg_list[
ARMV7M_XPSR].valid =
true;
821 resume_pc = *address;
823 *address = resume_pc;
830 resume_pc &= 0xFFFFFFFC;
840 LOG_ERROR(
"How do I resume into Jazelle state??");
843 LOG_ERROR(
"Shouldn't be in AARCH64 state");
846 LOG_DEBUG(
"resume pc = 0x%08" PRIx32, resume_pc);
869 if (handle_breakpoints) {
875 cortex_m3_single_step_core(
target);
904 LOG_ERROR(
"DSCR InstrCompl must be set before leaving debug!");
946 handle_breakpoints, 0);
954 target_addr_t address,
int handle_breakpoints,
int debug_execution)
975 if (!debug_execution) {
1045 uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
1046 cortex_a_read_cp(
target, &cp15_control_register, 15, 0, 1, 0, 0);
1047 LOG_DEBUG(
"cp15_control_register = 0x%08x", cp15_control_register);
1049 cortex_a_read_cp(
target, &cp15_cacr, 15, 0, 1, 0, 2);
1050 LOG_DEBUG(
"cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
1052 cortex_a_read_cp(
target, &cp15_nacr, 15, 0, 1, 1, 2);
1053 LOG_DEBUG(
"cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
1115 unsigned long bit_mask,
unsigned long value)
1129 dscr |= value & bit_mask;
1138 int handle_breakpoints)
1164 handle_breakpoints = 1;
1165 if (handle_breakpoints) {
1172 stepbreakpoint.
address = address;
1173 stepbreakpoint.
asid = 0;
1177 stepbreakpoint.
is_set =
false;
1203 LOG_ERROR(
"timeout waiting for target halt");
1252 uint8_t byte_addr_select = 0x0F;
1263 while (brp_list[brp_i].
used && (brp_i < cortex_a->brp_num))
1265 if (brp_i >= cortex_a->
brp_num) {
1266 LOG_ERROR(
"ERROR Can not find free Breakpoint Register Pair");
1272 control = ((matchmode & 0x7) << 20)
1273 | (byte_addr_select << 5)
1275 brp_list[brp_i].
used =
true;
1280 brp_list[brp_i].
value);
1288 LOG_DEBUG(
"brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32, brp_i,
1290 brp_list[brp_i].
value);
1346 uint8_t byte_addr_select = 0x0F;
1356 while ((brp_list[brp_i].
used ||
1357 (brp_list[brp_i].
type !=
BRP_CONTEXT)) && (brp_i < cortex_a->brp_num))
1360 if (brp_i >= cortex_a->
brp_num) {
1361 LOG_ERROR(
"ERROR Can not find free Breakpoint Register Pair");
1366 control = ((matchmode & 0x7) << 20)
1367 | (byte_addr_select << 5)
1369 brp_list[brp_i].
used =
true;
1374 brp_list[brp_i].
value);
1382 LOG_DEBUG(
"brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32, brp_i,
1384 brp_list[brp_i].
value);
1394 uint32_t control_ctx, control_iva;
1395 uint8_t ctx_byte_addr_select = 0x0F;
1396 uint8_t iva_byte_addr_select = 0x0F;
1397 uint8_t ctx_machmode = 0x03;
1398 uint8_t iva_machmode = 0x01;
1408 while ((brp_list[brp_1].
used ||
1409 (brp_list[brp_1].
type !=
BRP_CONTEXT)) && (brp_1 < cortex_a->brp_num))
1412 LOG_DEBUG(
"brp(CTX) found num: %d", brp_1);
1413 if (brp_1 >= cortex_a->
brp_num) {
1414 LOG_ERROR(
"ERROR Can not find free Breakpoint Register Pair");
1418 while ((brp_list[brp_2].
used ||
1419 (brp_list[brp_2].
type !=
BRP_NORMAL)) && (brp_2 < cortex_a->brp_num))
1422 LOG_DEBUG(
"brp(IVA) found num: %d", brp_2);
1423 if (brp_2 >= cortex_a->
brp_num) {
1424 LOG_ERROR(
"ERROR Can not find free Breakpoint Register Pair");
1430 control_ctx = ((ctx_machmode & 0x7) << 20)
1433 | (ctx_byte_addr_select << 5)
1435 brp_list[brp_1].
used =
true;
1437 brp_list[brp_1].
control = control_ctx;
1440 brp_list[brp_1].
value);
1449 control_iva = ((iva_machmode & 0x7) << 20)
1451 | (iva_byte_addr_select << 5)
1453 brp_list[brp_2].
used =
true;
1455 brp_list[brp_2].
control = control_iva;
1458 brp_list[brp_2].
value);
1486 if (brp_i >= cortex_a->
brp_num) {
1487 LOG_DEBUG(
"Invalid BRP number in breakpoint");
1490 LOG_DEBUG(
"rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32, brp_i,
1492 brp_list[brp_i].
used =
false;
1493 brp_list[brp_i].
value = 0;
1502 brp_list[brp_i].
value);
1505 if ((brp_j < 0) || (brp_j >= cortex_a->
brp_num)) {
1506 LOG_DEBUG(
"Invalid BRP number in breakpoint");
1509 LOG_DEBUG(
"rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32, brp_j,
1511 brp_list[brp_j].
used =
false;
1512 brp_list[brp_j].
value = 0;
1521 brp_list[brp_j].
value);
1530 if (brp_i >= cortex_a->
brp_num) {
1531 LOG_DEBUG(
"Invalid BRP number in breakpoint");
1534 LOG_DEBUG(
"rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32, brp_i,
1536 brp_list[brp_i].
used =
false;
1537 brp_list[brp_i].
value = 0;
1546 brp_list[brp_i].
value);
1592 LOG_INFO(
"no hardware breakpoint available");
1608 LOG_INFO(
"no hardware breakpoint available");
1624 LOG_INFO(
"no hardware breakpoint available");
1673 uint8_t address_mask;
1674 uint8_t byte_address_select;
1675 uint8_t load_store_access_control = 0x3;
1686 while (wrp_list[wrp_i].
used && (wrp_i < cortex_a->wrp_num))
1689 if (wrp_i >= cortex_a->
wrp_num) {
1690 LOG_ERROR(
"ERROR Can not find free Watchpoint Register Pair");
1696 LOG_WARNING(
"watchpoint length must be a power of 2");
1701 LOG_WARNING(
"watchpoint address must be aligned at length");
1721 byte_address_select = 0x0f;
1727 byte_address_select = 0xff;
1734 control = (address_mask << 24) |
1735 (byte_address_select << 5) |
1736 (load_store_access_control << 3) |
1738 wrp_list[wrp_i].
used =
true;
1739 wrp_list[wrp_i].
value = address;
1744 wrp_list[wrp_i].
value);
1754 LOG_DEBUG(
"wp %i control 0x%0" PRIx32
" value 0x%0" PRIx32, wrp_i,
1756 wrp_list[wrp_i].
value);
1782 if (wrp_i >= cortex_a->
wrp_num) {
1783 LOG_DEBUG(
"Invalid WRP number in watchpoint");
1786 LOG_DEBUG(
"wrp %i control 0x%0" PRIx32
" value 0x%0" PRIx32, wrp_i,
1788 wrp_list[wrp_i].
used =
false;
1789 wrp_list[wrp_i].
value = 0;
1798 wrp_list[wrp_i].
value);
1819 LOG_INFO(
"no hardware watchpoint available");
1913 LOG_WARNING(
"%s: ran after reset and before halt ...",
1938 if (new_dscr != *dscr) {
1951 uint32_t value, uint32_t *dscr)
1958 if ((*dscr &
mask) == value)
1966 LOG_ERROR(
"Could not read DSCR register");
1969 if ((*dscr &
mask) == value)
1972 LOG_ERROR(
"timeout waiting for DSCR bit change");
1980 uint32_t *data, uint32_t *dscr)
2014 uint32_t *dfsr, uint32_t *dscr)
2034 uint32_t data, uint32_t *dscr)
2067 uint32_t dfsr, uint32_t *dscr)
2086 if (dfsr & (1 << 9)) {
2090 if (upper4 == 1 || upper4 == 2 || upper4 == 3 || upper4 == 15)
2098 status = ((dfsr >> 6) & 0x10) | (dfsr & 0xf);
2137 uint32_t data, opcode;
2186 uint32_t
count,
const uint8_t *
buffer, uint32_t *dscr)
2215 uint32_t address, uint32_t
size,
2219 int retval, final_retval;
2222 uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
2224 LOG_DEBUG(
"Writing CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32,
2268 if (
size == 4 && (address % 4) == 0) {
2273 switch (address % 4) {
2291 final_retval = retval;
2296 final_retval = retval;
2301 final_retval = retval;
2331 LOG_ERROR(
"data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32, fault_dfar, fault_dfsr);
2334 final_retval = retval;
2339 LOG_ERROR(
"error restoring dfar/dfsr - dscr = 0x%08" PRIx32, dscr);
2355 final_retval = retval;
2360 final_retval = retval;
2364 return final_retval;
2395 uint32_t opcode, data;
2430 *
buffer = (uint8_t) data;
2532 uint32_t address, uint32_t
size,
2536 int retval, final_retval;
2539 uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
2541 LOG_DEBUG(
"Reading CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32,
2585 if (
size == 4 && (address % 4) == 0) {
2590 switch (address % 4) {
2609 final_retval = retval;
2614 final_retval = retval;
2619 final_retval = retval;
2637 LOG_ERROR(
"data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32, fault_dfar, fault_dfsr);
2640 final_retval = retval;
2645 LOG_ERROR(
"error restoring dfar/dfsr - dscr = 0x%08" PRIx32, dscr);
2661 final_retval = retval;
2666 final_retval = retval;
2670 return final_retval;
2762 for (
size = 1; size < 4 && count >=
size * 2 + (address &
size);
size *= 2) {
2763 if (address &
size) {
2796 for (
size = 1; size < 4 && count >=
size * 2 + (address &
size);
size *= 2) {
2797 if (address &
size) {
2851 LOG_ERROR(
"Timeout waiting for dtr tx full");
2873 uint32_t didr, cpuid, dbg_osreg, dbg_idpfr1;
2880 LOG_ERROR(
"Could not find APB-AP for debug access");
2894 LOG_ERROR(
"Could not initialize the APB-AP");
2901 LOG_DEBUG(
"%s's dbgbase is not set, trying to detect using the ROM table",
2907 LOG_ERROR(
"Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
2917 LOG_WARNING(
"Debug base address for target %s has bit 31 set to 0. Access to debug registers will likely fail!\n"
2930 LOG_DEBUG(
"Examine %s failed",
"CPUID");
2935 LOG_DEBUG(
"cpuid = 0x%08" PRIx32, cpuid);
2937 cortex_a->
didr = didr;
2938 cortex_a->
cpuid = cpuid;
2977 LOG_ERROR(
"target->coreid %" PRId32
" OSLock sticky, core not powered?",
2990 if (dbg_idpfr1 & 0x000000f0) {
2991 LOG_DEBUG(
"target->coreid %" PRId32
" has security extensions",
2995 if (dbg_idpfr1 & 0x0000f000) {
2996 LOG_DEBUG(
"target->coreid %" PRId32
" has virtualization extensions",
3013 cortex_a->
brp_num = ((didr >> 24) & 0x0F) + 1;
3019 for (i = 0; i < cortex_a->
brp_num; i++) {
3033 cortex_a->
wrp_num = ((didr >> 28) & 0x0F) + 1;
3037 for (i = 0; i < cortex_a->
wrp_num; i++) {
3185 LOG_ERROR(
"%s: target not halted", __func__);
3201 int mmu_enabled = 0;
3249 static const struct jim_nvp nvp_maskisr_modes[] = {
3252 { .name =
NULL, .value = -1 },
3277 static const struct jim_nvp nvp_dacrfixup_modes[] = {
3280 { .name =
NULL, .value = -1 },
3300 .
name =
"cache_info",
3301 .handler = cortex_a_handle_cache_info_command,
3303 .help =
"display information about target caches",
3308 .handler = cortex_a_handle_dbginit_command,
3310 .help =
"Initialize core debug",
3315 .handler = handle_cortex_a_mask_interrupts_command,
3317 .help =
"mask cortex_a interrupts",
3318 .usage =
"['on'|'off']",
3321 .name =
"dacrfixup",
3322 .handler = handle_cortex_a_dacrfixup_command,
3324 .help =
"set domain access control (DACR) to all-manager "
3326 .usage =
"['on'|'off']",
3347 .help =
"Cortex-A command group",
3405 .handler = cortex_a_handle_dbginit_command,
3407 .help =
"Initialize core debug",
3412 .handler = handle_cortex_a_mask_interrupts_command,
3414 .help =
"mask cortex_r4 interrupts",
3415 .usage =
"['on'|'off']",
3425 .
name =
"cortex_r4",
3427 .help =
"Cortex-R4 command group",
3435 .
name =
"cortex_r4",
#define CPUDBG_LOCKACCESS
int arm_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Runs ARM code in the target to check whether a memory block holds all ones.
int arm_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Runs ARM code in the target to calculate a CRC32 checksum.
int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
void arm_free_reg_cache(struct arm *arm)
const char * arm_get_gdb_arch(struct target *target)
const struct command_registration arm_command_handlers[]
struct reg * arm_reg_current(struct arm *arm, unsigned regnum)
Returns handle to the register currently mapped to a given number.
int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type, target_addr_t *addr, int32_t core_id)
int mem_ap_read_buf_noincr(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
int adiv5_verify_config(struct adiv5_private_config *pc)
int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Asynchronous (queued) write of a word to memory or a system register.
int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
int dap_find_get_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
int mem_ap_write_buf_noincr(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Synchronous read of a word from memory or a system register.
struct adiv5_ap * dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
int dap_put_ap(struct adiv5_ap *ap)
int mem_ap_init(struct adiv5_ap *ap)
Initialize a DAP.
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Synchronous write of a word to memory or a system register.
static int dap_run(struct adiv5_dap *dap)
Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they ar...
#define ARM_CS_C9_DEVTYPE_CORE_DEBUG
void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
int arm_dpm_read_current_registers(struct arm_dpm *dpm)
Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or ...
int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
int arm_dpm_setup(struct arm_dpm *dpm)
Hooks up this DPM to its associated target; call only once.
int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
Writes all modified core registers for all processor modes.
void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
int arm_dpm_initialize(struct arm_dpm *dpm)
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affec...
#define DRCR_CLEAR_EXCEPTIONS
#define DSCR_STICKY_ABORT_IMPRECISE
#define DSCR_EXT_DCC_FAST_MODE
#define DSCR_DTRRX_FULL_LATCHED
#define DSCR_RUN_MODE(dscr)
#define DSCR_STICKY_ABORT_PRECISE
#define DSCR_EXT_DCC_NON_BLOCKING
#define PRSR_STICKY_RESET_STATUS
#define PRSR_POWERUP_STATUS
#define DSCR_EXT_DCC_MASK
#define DSCR_CORE_RESTARTED
#define DSCR_HALT_DBG_MODE
#define DSCR_DTRTX_FULL_LATCHED
Macros used to generate various ARM or Thumb opcodes.
#define ARMV4_5_STC(p, u, d, w, cp, crd, rn, imm)
#define ARMV4_5_LDC(p, u, d, w, cp, crd, rn, imm)
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
#define ARMV4_5_STRH_IP(rd, rn)
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
#define ARMV4_5_LDRH_IP(rd, rn)
#define ARMV4_5_LDRB_IP(rd, rn)
#define ARMV4_5_LDRW_IP(rd, rn)
#define ARMV4_5_STRW_IP(rd, rn)
#define ARMV4_5_STRB_IP(rd, rn)
int arm_semihosting(struct target *target, int *retval)
Checks for and processes an ARM semihosting request.
int arm_semihosting_init(struct target *target)
Initialize ARM semihosting support.
int armv7a_handle_cache_info_command(struct command_invocation *cmd, struct armv7a_cache_common *armv7a_cache)
int armv7a_read_ttbcr(struct target *target)
int armv7a_arch_state(struct target *target)
const struct command_registration armv7a_command_handlers[]
int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
int armv7a_identify_cache(struct target *target)
static struct armv7a_common * target_to_armv7a(struct target *target)
int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt, uint32_t size)
int armv7a_cache_auto_flush_on_write(struct target *target, uint32_t virt, uint32_t size)
int armv7a_cache_flush_virt(struct target *target, uint32_t virt, uint32_t size)
int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt, uint32_t size)
const struct command_registration armv7a_mmu_command_handlers[]
int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, target_addr_t *val, int meminfo)
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
struct breakpoint * breakpoint_find(struct target *target, target_addr_t address)
static void watchpoint_set(struct watchpoint *watchpoint, unsigned int number)
static void breakpoint_hw_set(struct breakpoint *breakpoint, unsigned int hw_number)
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
static int cortex_a_dpm_finish(struct arm_dpm *dpm)
static int cortex_a_read_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static int cortex_a_mmu(struct target *target, int *enabled)
static int cortex_a_target_create(struct target *target, Jim_Interp *interp)
static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
static int cortex_a_exec_opcode(struct target *target, uint32_t opcode, uint32_t *dscr_p)
static const struct command_registration cortex_a_command_handlers[]
static int cortex_a_write_dcc(struct cortex_a_common *a, uint32_t data)
static int cortex_a_write_dfar_dfsr(struct target *target, uint32_t dfar, uint32_t dfsr, uint32_t *dscr)
static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr)
static int cortex_a_write_buffer(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer)
static int cortex_a_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer)
static int cortex_a_init_debug_access(struct target *target)
static int cortex_a_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
Remove a watchpoint from an Cortex-A target.
static int cortex_a_instr_cpsr_sync(struct arm_dpm *dpm)
static const struct command_registration cortex_r4_exec_command_handlers[]
static const struct command_registration cortex_a_exec_command_handlers[]
static int cortex_a_read_cpu_memory_slow(struct target *target, uint32_t size, uint32_t count, uint8_t *buffer, uint32_t *dscr)
static int cortex_a_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static int cortex_a_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
static int cortex_a_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
static int cortex_a_read_copro(struct target *target, uint32_t opcode, uint32_t *data, uint32_t *dscr)
static int cortex_a_instr_read_data_dcc(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
static int cortex_a_restore_context(struct target *target, bool bpwp)
static int cortex_a_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
static int cortex_a_handle_target_request(void *priv)
static int cortex_a_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
Add a watchpoint to an Cortex-A target.
static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
Sets a watchpoint for an Cortex-A target in one of the watchpoint units.
static int cortex_a_init_arch_info(struct target *target, struct cortex_a_common *cortex_a, struct adiv5_dap *dap)
static int cortex_a_instr_write_data_r0(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
static int cortex_a_post_debug_entry(struct target *target)
struct target_type cortexr4_target
static int update_halt_gdb(struct target *target)
static int cortex_a_read_cpu_memory_fast(struct target *target, uint32_t count, uint8_t *buffer, uint32_t *dscr)
static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
static int cortex_r4_target_create(struct target *target, Jim_Interp *interp)
static int cortex_a_add_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
static int cortex_a_examine(struct target *target)
static int cortex_a_write_cpu_memory_slow(struct target *target, uint32_t size, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
static int cortex_a_halt_smp(struct target *target)
static int cortex_a_add_context_breakpoint(struct target *target, struct breakpoint *breakpoint)
static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
static int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
static int cortex_a_deassert_reset(struct target *target)
static int cortex_a_write_copro(struct target *target, uint32_t opcode, uint32_t data, uint32_t *dscr)
static int cortex_a_read_dfar_dfsr(struct target *target, uint32_t *dfar, uint32_t *dfsr, uint32_t *dscr)
static int cortex_a_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
Unset an existing watchpoint and clear the used watchpoint unit.
static int cortex_a_internal_restore(struct target *target, int current, target_addr_t *address, int handle_breakpoints, int debug_execution)
static int cortex_a_set_dcc_mode(struct target *target, uint32_t mode, uint32_t *dscr)
static int cortex_a_mmu_modify(struct target *target, int enable)
static int cortex_a_virt2phys(struct target *target, target_addr_t virt, target_addr_t *phys)
static int cortex_a_examine_first(struct target *target)
static int cortex_a_instr_read_data_r0(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool force)
static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, uint32_t addr, uint32_t control)
static int cortex_a_init_target(struct command_context *cmd_ctx, struct target *target)
static int cortex_a_poll(struct target *target)
static void cortex_a_deinit_target(struct target *target)
static int cortex_a_restore_cp15_control_reg(struct target *target)
static const struct command_registration cortex_r4_command_handlers[]
static int cortex_a_post_memaccess(struct target *target, int phys_access)
static int cortex_a_write_cpu_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
COMMAND_HANDLER(cortex_a_handle_cache_info_command)
static int cortex_a_set_breakpoint(struct target *target, struct breakpoint *breakpoint, uint8_t matchmode)
static int cortex_a_halt(struct target *target)
static int cortex_a_instr_write_data_dcc(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data, uint32_t *dscr_p)
static int cortex_a_write_cpu_memory_fast(struct target *target, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
static int cortex_a_set_context_breakpoint(struct target *target, struct breakpoint *breakpoint, uint8_t matchmode)
static int cortex_a_prep_memaccess(struct target *target, int phys_access)
static int cortex_a_read_cpu_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
static int cortex_a_internal_restart(struct target *target)
static int cortex_a_dfsr_to_error_code(uint32_t dfsr)
static int cortex_a_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
static int cortex_a_instr_write_data_rt_dcc(struct arm_dpm *dpm, uint8_t rt, uint32_t data)
static int cortex_a_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
static int cortex_a_debug_entry(struct target *target)
static int cortex_a_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
static int cortex_a_instr_read_data_rt_dcc(struct arm_dpm *dpm, uint8_t rt, uint32_t *data)
static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask, uint32_t value, uint32_t *dscr)
static struct cortex_a_common * dpm_to_a(struct arm_dpm *dpm)
static int cortex_a_write_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
static int cortex_a_assert_reset(struct target *target)
struct target_type cortexa_target
static struct target * get_cortex_a(struct target *target, int32_t coreid)
static unsigned int ilog2(unsigned int x)
static struct cortex_a_common * target_to_cortex_a(struct target *target)
#define CORTEX_A_COMMON_MAGIC
static struct esp_usb_jtag * priv
struct jim_nvp * jim_nvp_name2value_simple(const struct jim_nvp *p, const char *name)
struct jim_nvp * jim_nvp_value2name_simple(const struct jim_nvp *p, int value)
bool transport_is_jtag(void)
Returns true if the current debug session is using JTAG as its transport.
int adapter_deassert_reset(void)
enum reset_types jtag_get_reset_config(void)
int adapter_assert_reset(void)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
void register_cache_invalidate(struct reg_cache *cache)
Marks the contents of the register cache as invalid (and clean).
size_t size
Size of the control block search area.
const struct command_registration smp_command_handlers[]
#define foreach_smp_target(pos, head)
uint64_t ap_num
ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coheren...
struct adiv5_dap * dap
DAP this AP belongs to.
uint32_t memaccess_tck
Configures how many extra tck clocks are added after starting a MEM-AP access before we try to read i...
This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
This wraps an implementation of DPM primitives.
int(* instr_read_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from dcc after execution.
uint64_t didr
Cache of DIDR.
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
int(* bpwp_enable)(struct arm_dpm *dpm, unsigned index_value, uint32_t addr, uint32_t control)
Enables one breakpoint or watchpoint by writing to the hardware registers.
int(* instr_write_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
int(* bpwp_disable)(struct arm_dpm *dpm, unsigned index_value)
Disables one breakpoint or watchpoint by clearing its hardware control registers.
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
int(* instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
int(* instr_cpsr_sync)(struct arm_dpm *dpm)
Optional core-specific operation invoked after CPSR writes.
uint32_t dscr
Recent value of DSCR.
Represents a generic ARM core, with standard application registers.
enum arm_core_type core_type
Indicates what registers are in the ARM state core register set.
int(* mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
Read coprocessor register.
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
struct adiv5_dap * dap
For targets conforming to ARM Debug Interface v5, this handle references the Debug Access Port (DAP) ...
struct reg * pc
Handle to the PC; valid in all core modes.
struct reg_cache * core_cache
int(* mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
Write coprocessor register.
struct reg * spsr
Handle to the SPSR; valid only in core modes with an SPSR.
int arm_vfp_version
Floating point or VFP version, 0 if disabled.
struct target * target
Backpointer to the target.
enum arm_state core_state
Record the current core state: ARM, Thumb, or otherwise.
int(* post_debug_entry)(struct target *target)
int(* examine_debug_reason)(struct target *target)
struct armv7a_mmu_common armv7a_mmu
struct adiv5_ap * debug_ap
void(* pre_restore_context)(struct target *target)
struct armv7a_cache_common armv7a_cache
int(* read_physical_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
enum breakpoint_type type
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
struct armv7a_common armv7a_common
struct cortex_a_wrp * wrp_list
struct cortex_a_brp * brp_list
uint32_t cp15_control_reg_curr
enum cortex_a_dacrfixup_mode dacrfixup_mode
unsigned int common_magic
enum cortex_a_isrmasking_mode isrmasking_mode
uint32_t cp15_control_reg
Name Value Pairs, aka: NVP.
This holds methods shared between all instances of a given target type.
const char * name
Name of this type of target.
struct gdb_service * gdb_service
enum target_debug_reason debug_reason
struct list_head * smp_targets
int target_call_event_callbacks(struct target *target, enum target_event event)
void target_free_all_working_areas(struct target *target)
void target_buffer_set_u16(struct target *target, uint8_t *buffer, uint16_t value)
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
bool target_has_event_action(struct target *target, enum target_event event)
Returns true only if the target has a handler for the specified event.
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
int target_register_timer_callback(int(*callback)(void *priv), unsigned int time_ms, enum target_timer_type type, void *priv)
The period is very approximate, the callback can happen much more often or much more rarely than spec...
uint16_t target_buffer_get_u16(struct target *target, const uint8_t *buffer)
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
struct target * get_current_target(struct command_context *cmd_ctx)
void target_handle_event(struct target *target, enum target_event e)
uint32_t target_buffer_get_u32(struct target *target, const uint8_t *buffer)
#define ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_INIT_FAILED
#define ERROR_TARGET_UNALIGNED_ACCESS
#define ERROR_TARGET_INVALID
@ TARGET_TIMER_TYPE_PERIODIC
@ TARGET_EVENT_DEBUG_RESUMED
@ TARGET_EVENT_DEBUG_HALTED
@ TARGET_EVENT_RESET_ASSERT
static const char * target_name(struct target *target)
Returns the instance-specific name of the specified target.
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
static void target_set_examined(struct target *target)
Sets the examined flag for the given target.
static bool target_was_examined(struct target *target)
#define ERROR_TARGET_DATA_ABORT
#define ERROR_TARGET_TRANSLATION_FAULT
int target_request(struct target *target, uint32_t request)
#define container_of(ptr, type, member)
Cast a member of a structure out to the containing structure.