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17 #ifndef OPENOCD_TARGET_ARM_OPCODES_H
18 #define OPENOCD_TARGET_ARM_OPCODES_H
33 #define ARMV4_5_STMIA(rn, list, s, w) \
34 (0xe8800000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
42 #define ARMV4_5_LDMIA(rn, list, s, w) \
43 (0xe8900000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
46 #define ARMV4_5_NOP (0xe1a08008)
52 #define ARMV4_5_MRS(rn, r) (0xe10f0000 | ((r) << 22) | ((rn) << 12))
58 #define ARMV4_5_STR(rd, rn) (0xe5800000 | ((rd) << 12) | ((rn) << 16))
64 #define ARMV4_5_LDR(rd, rn) (0xe5900000 | ((rd) << 12) | ((rn) << 16))
72 #define ARMV4_5_MSR_GP(rm, field, r) \
73 (0xe120f000 | (rm) | ((field) << 16) | ((r) << 22))
74 #define ARMV4_5_MSR_IM(im, rotate, field, r) \
75 (0xe320f000 | (im) | ((rotate) << 8) | ((field) << 16) | ((r) << 22))
81 #define ARMV4_5_LDRW_IP(rd, rn) (0xe4900004 | ((rd) << 12) | ((rn) << 16))
87 #define ARMV4_5_LDRH_IP(rd, rn) (0xe0d000b2 | ((rd) << 12) | ((rn) << 16))
93 #define ARMV4_5_LDRB_IP(rd, rn) (0xe4d00001 | ((rd) << 12) | ((rn) << 16))
99 #define ARMV4_5_STRW_IP(rd, rn) (0xe4800004 | ((rd) << 12) | ((rn) << 16))
105 #define ARMV4_5_STRH_IP(rd, rn) (0xe0c000b2 | ((rd) << 12) | ((rn) << 16))
111 #define ARMV4_5_STRB_IP(rd, rn) (0xe4c00001 | ((rd) << 12) | ((rn) << 16))
117 #define ARMV4_5_B(im, l) (0xea000000 | (im) | ((l) << 24))
122 #define ARMV4_5_BX(rm) (0xe12fff10 | (rm))
134 #define ARMV4_5_VMOV(op, rt2, rt, m, vm) \
135 (0xec400b10 | ((op) << 20) | ((rt2) << 16) | \
136 ((rt) << 12) | ((m) << 5) | (vm))
141 #define ARMV4_5_VMRS(rt) (0xeef10a10 | ((rt) << 12))
146 #define ARMV4_5_VMSR(rt) (0xeee10a10 | ((rt) << 12))
159 #define ARMV4_5_STC(p, u, d, w, cp, crd, rn, imm) \
160 (0xec000000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
161 ((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm)>>2))
174 #define ARMV4_5_LDC(p, u, d, w, cp, crd, rn, imm) \
175 (0xec100000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
176 ((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm) >> 2))
186 #define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2) \
187 (0xee100010 | (crm) | ((op2) << 5) | ((cp) << 8) \
188 | ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
198 #define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2) \
199 (0xee000010 | (crm) | ((op2) << 5) | ((cp) << 8) \
200 | ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
205 #define ARMV5_BKPT(im) (0xe1200070 | ((im & 0xfff0) << 4) | (im & 0xf))
223 #define ARMV4_5_T_STR(rd, rn) \
224 ((0x6000 | (rd) | ((rn) << 3)) | \
225 ((0x6000 | (rd) | ((rn) << 3)) << 16))
231 #define ARMV4_5_T_LDR(rd, rn) \
232 ((0x6800 | ((rn) << 3) | (rd)) \
233 | ((0x6800 | ((rn) << 3) | (rd)) << 16))
239 #define ARMV4_5_T_LDMIA(rn, list) \
240 ((0xc800 | ((rn) << 8) | (list)) \
241 | ((0xc800 | ((rn) << 8) | (list)) << 16))
246 #define ARMV4_5_T_LDR_PCREL(rd) \
247 ((0x4800 | ((rd) << 8)) \
248 | ((0x4800 | ((rd) << 8)) << 16))
254 #define ARMV4_5_T_MOV(rd, rm) \
255 ((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
256 (((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) \
257 | ((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
258 (((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) << 16))
264 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
270 #define ARMV4_5_T_MOV_IM(rd, im) \
271 ((0x2000 | ((rd) << 8) | (im)) \
272 | ((0x2000 | ((rd) << 8) | (im)) << 16))
277 #define ARMV4_5_T_BX(rm) \
278 ((0x4700 | ((rm) << 3)) \
279 | ((0x4700 | ((rm) << 3)) << 16))
284 #define ARMV4_5_T_B(imm) \
286 | ((0xe000 | (imm)) << 16))
291 #define ARMV5_T_BKPT(im) \
293 | ((0xbe00 | (im)) << 16))
300 #define ARM_T2_MRS(rd, sysm) \
301 ((0xF3EF) | ((0x8000 | (rd << 8) | sysm) << 16))
308 #define ARM_T2_MSR(sysm, rn) \
309 ((0xF380 | (rn << 8)) | ((0x8800 | sysm) << 16))
319 #define ARM_T2_CPSID(_if) \
320 ((0xB660 | (1 << 8) | ((_if)&0x3)) \
321 | ((0xB660 | (1 << 8) | ((_if)&0x3)) << 16))
322 #define ARM_T2_CPSIE(_if) \
323 ((0xB660 | (0 << 8) | ((_if)&0x3)) \
324 | ((0xB660 | (0 << 8) | ((_if)&0x3)) << 16))