armv4_5.c File Reference

Include dependency graph for armv4_5.c:

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Enumerations
enum	{   ARMV4_5_SPSR_FIQ = 32 , ARMV4_5_SPSR_IRQ = 33 , ARMV4_5_SPSR_SVC = 34 , ARMV4_5_SPSR_ABT = 35 ,   ARMV4_5_SPSR_UND = 36 , ARM_SPSR_MON = 41 , ARM_SPSR_HYP = 43 }

Functions
int	arm_arch_state (struct target *target)
int	arm_blank_check_memory (struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
	Runs ARM code in the target to check whether a memory block holds all ones. More...
struct reg_cache *	arm_build_reg_cache (struct target *target, struct arm *arm)
int	arm_checksum_memory (struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
	Runs ARM code in the target to calculate a CRC32 checksum. More...
static int	arm_default_mcr (struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
static int	arm_default_mrc (struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
void	arm_free_reg_cache (struct arm *arm)
static int	arm_full_context (struct target *target)
static void	arm_gdb_dummy_init (void)
const char *	arm_get_gdb_arch (struct target *target)
int	arm_get_gdb_reg_list (struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
int	arm_init_arch_info (struct target *target, struct arm *arm)
const char *	arm_mode_name (unsigned psr_mode)
	Map PSR mode bits to the name of an ARM processor operating mode. More...
int	arm_mode_to_number (enum arm_mode mode)
	Map PSR mode bits to linear number indexing armv4_5_core_reg_map. More...
struct reg *	arm_reg_current (struct arm *arm, unsigned regnum)
	Returns handle to the register currently mapped to a given number. More...
void	arm_set_cpsr (struct arm *arm, uint32_t cpsr)
	Configures host-side ARM records to reflect the specified CPSR. More...
static int	armv4_5_get_core_reg (struct reg *reg)
enum arm_mode	armv4_5_number_to_mode (int number)
	Map linear number indexing armv4_5_core_reg_map to PSR mode bits. More...
int	armv4_5_run_algorithm (struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
static int	armv4_5_run_algorithm_completion (struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
int	armv4_5_run_algorithm_inner (struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int(*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info))
static int	armv4_5_set_core_reg (struct reg *reg, uint8_t *buf)
	COMMAND_HANDLER (handle_arm_core_state_command)
	COMMAND_HANDLER (handle_arm_disassemble_command)
	COMMAND_HANDLER (handle_armv4_5_reg_command)
bool	is_arm_mode (unsigned psr_mode)
	Return true iff the parameter denotes a valid ARM processor mode. More...
static int	jim_mcrmrc (Jim_Interp *interp, int argc, Jim_Obj *const *argv)

Variables
static const uint8_t	arm_abt_indices [3]
const struct command_registration	arm_all_profiles_command_handlers []
const struct command_registration	arm_command_handlers []
struct {
unsigned   cookie
unsigned   gdb_index
enum arm_mode   mode
const char *   name
}	arm_core_regs []
static const struct command_registration	arm_exec_command_handlers []
static const uint8_t	arm_fiq_indices [8]
static struct reg_feature	arm_gdb_dummy_fp_features
static struct reg	arm_gdb_dummy_fp_reg
	Dummy FPA registers are required to support GDB on ARM. More...
static const uint8_t	arm_gdb_dummy_fp_value [12]
static struct reg	arm_gdb_dummy_fps_reg
	Dummy FPA status registers are required to support GDB on ARM. More...
static const uint8_t	arm_gdb_dummy_fps_value [4]
static const uint8_t	arm_hyp_indices [2]
static const uint8_t	arm_irq_indices [3]
struct {
const uint8_t *   indices
unsigned short   n_indices
const char *   name
unsigned short   psr
}	arm_mode_data []
static const uint8_t	arm_mon_indices [3]
static const struct reg_arch_type	arm_reg_type
static const char *	arm_state_strings []
static const uint8_t	arm_svc_indices [3]
static const uint8_t	arm_und_indices [3]
static const uint8_t	arm_usr_indices [17]
struct {
uint32_t   bits
const char *   feature
const char *   group
unsigned int   id
enum arm_mode   mode
const char *   name
enum reg_type   type
}	arm_vfp_v3_regs []
const int	armv4_5_core_reg_map [9][17]

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
ARMV4_5_SPSR_FIQ
ARMV4_5_SPSR_IRQ
ARMV4_5_SPSR_SVC
ARMV4_5_SPSR_ABT
ARMV4_5_SPSR_UND
ARM_SPSR_MON
ARM_SPSR_HYP

Definition at line 32 of file armv4_5.c.

Function Documentation

arm_arch_state()

int arm_arch_state

(

struct target *

target

)

Definition at line 782 of file armv4_5.c.

References ARM_COMMON_MAGIC, arm_mode_name(), arm_state_strings, buf_get_u32(), arm::common_magic, arm::core_mode, arm::core_state, arm::cpsr, debug_reason_name(), ERROR_FAIL, ERROR_OK, semihosting::hit_fileio, semihosting::is_active, semihosting::is_fileio, LOG_ERROR, LOG_USER, arm::pc, target::semihosting, target_to_arm(), and reg::value.

Referenced by arm11_arch_state(), arm720t_arch_state(), arm920t_arch_state(), arm926ejs_arch_state(), armv7a_arch_state(), and xscale_arch_state().

arm_blank_check_memory()

int arm_blank_check_memory	(	struct target *	target,
		struct target_memory_check_block *	blocks,
		int	num_blocks,
		uint8_t	erased_value
	)

Runs ARM code in the target to check whether a memory block holds all ones.

NOR flash which has been erased, and thus may be written, holds all ones.

Definition at line 1595 of file armv4_5.c.

References working_area::address, arm::arch, ARM_ARCH_V4, ARM_COMMON_MAGIC, ARM_MODE_SVC, ARM_STATE_ARM, ARRAY_SIZE, buf_get_u32(), buf_set_u32(), arm_algorithm::common_magic, arm_algorithm::core_mode, arm_algorithm::core_state, destroy_reg_param(), ERROR_FAIL, ERROR_OK, init_reg_param(), le_to_h_u32(), LOG_ERROR, NULL, PARAM_IN_OUT, PARAM_OUT, target_memory_check_block::result, size, target_alloc_working_area(), target_free_working_area(), target_run_algorithm(), target_to_arm(), and target_write_u32().

arm_build_reg_cache()

struct reg_cache* arm_build_reg_cache	(	struct target *	target,
		struct arm *	arm
	)

Definition at line 646 of file armv4_5.c.

References reg::arch_info, arm_reg::arm, arm_core_regs, ARM_CORE_TYPE_SEC_EXT, ARM_CORE_TYPE_VIRT_EXT, ARM_MODE_HYP, ARM_MODE_MON, arm_reg_type, ARM_VFP_V3, arm_vfp_v3_regs, arm::arm_vfp_version, ARMV4_5_CPSR, ARRAY_SIZE, reg::caller_save, cookie, arm::core_cache, arm::core_type, arm::cpsr, reg::exist, reg::feature, reg::group, arm_reg::mode, mode, reg_feature::name, reg::name, reg_cache::name, reg_cache::next, NULL, arm_reg::num, reg_cache::num_regs, number, reg::number, arm::pc, reg::reg_data_type, reg_cache::reg_list, REG_TYPE_CODE_PTR, REG_TYPE_DATA_PTR, REG_TYPE_UINT32, reg::size, target, arm_reg::target, reg_data_type::type, reg::type, arm_reg::value, and reg::value.

Referenced by arm7tdmi_build_reg_cache(), arm9tdmi_build_reg_cache(), arm_dpm_setup(), and xscale_build_reg_cache().

arm_checksum_memory()

int arm_checksum_memory	(	struct target *	target,
		target_addr_t	address,
		uint32_t	count,
		uint32_t *	checksum
	)

Runs ARM code in the target to calculate a CRC32 checksum.

Definition at line 1522 of file armv4_5.c.

References working_area::address, arm::arch, ARM_ARCH_V4, ARM_COMMON_MAGIC, ARM_MODE_SVC, ARM_STATE_ARM, ARRAY_SIZE, buf_get_u32(), buf_set_u32(), arm_algorithm::common_magic, arm_algorithm::core_mode, arm_algorithm::core_state, count, destroy_reg_param(), ERROR_OK, init_reg_param(), le_to_h_u32(), LOG_ERROR, NULL, PARAM_IN_OUT, PARAM_OUT, target_alloc_working_area(), target_free_working_area(), target_run_algorithm(), target_to_arm(), target_write_u32(), and reg_param::value.

arm_default_mcr()

static int arm_default_mcr ( struct target *  target, int  cpnum, uint32_t  op1, uint32_t  op2, uint32_t  crn, uint32_t  crm, uint32_t  value  )

static

Definition at line 1696 of file armv4_5.c.

References ERROR_FAIL, LOG_ERROR, and target_type_name().

Referenced by arm_init_arch_info().

arm_default_mrc()

static int arm_default_mrc ( struct target *  target, int  cpnum, uint32_t  op1, uint32_t  op2, uint32_t  crn, uint32_t  crm, uint32_t *  value  )

static

Definition at line 1687 of file armv4_5.c.

References ERROR_FAIL, LOG_ERROR, and target_type_name().

Referenced by arm_init_arch_info().

arm_free_reg_cache()

void arm_free_reg_cache

(

struct arm *

arm

)

Definition at line 761 of file armv4_5.c.

References reg::arch_info, arm::core_cache, reg::feature, NULL, reg_cache::num_regs, reg::reg_data_type, and reg_cache::reg_list.

Referenced by arm11_dpm_deinit(), arm7tdmi_free_reg_cache(), arm920t_deinit_target(), arm926ejs_deinit_target(), arm946e_deinit_target(), arm966e_deinit_target(), arm9tdmi_deinit_target(), arm_dpm_setup(), cortex_a_deinit_target(), fa526_deinit_target(), and xscale_free_reg_cache().

arm_full_context()

static int arm_full_context ( struct target *  target )

static

Definition at line 1672 of file armv4_5.c.

References armv4_5_get_core_reg(), arm::core_cache, ERROR_OK, reg::exist, reg_cache::num_regs, reg_cache::reg_list, target_to_arm(), and reg::valid.

Referenced by arm_init_arch_info().

arm_gdb_dummy_init()

static void arm_gdb_dummy_init ( void  )

static

Definition at line 566 of file armv4_5.c.

arm_get_gdb_arch()

const char* arm_get_gdb_arch

(

struct target *

target

)

Definition at line 1189 of file armv4_5.c.

arm_get_gdb_reg_list()

int arm_get_gdb_reg_list	(	struct target *	target,
		struct reg **	reg_list[],
		int *	reg_list_size,
		enum target_register_class	reg_class
	)

Definition at line 1194 of file armv4_5.c.

References arm_core_regs, ARM_CORE_TYPE_SEC_EXT, ARM_CORE_TYPE_VIRT_EXT, arm_gdb_dummy_fp_reg, arm_gdb_dummy_fps_reg, ARM_MODE_HYP, ARM_MODE_MON, arm_reg_current(), ARM_VFP_V3, arm::arm_vfp_version, ARRAY_SIZE, arm::core_cache, arm::core_mode, arm::core_type, arm::cpsr, ERROR_FAIL, ERROR_OK, is_arm_mode(), LOG_ERROR, mode, reg::number, REG_CLASS_ALL, REG_CLASS_GENERAL, reg_cache::reg_list, reg::size, and target_to_arm().

arm_init_arch_info()

int arm_init_arch_info	(	struct target *	target,
		struct arm *	arm
	)

Definition at line 1705 of file armv4_5.c.

References target::arch_info, ARM_COMMON_MAGIC, ARM_CORE_TYPE_M_PROFILE, ARM_CORE_TYPE_STD, arm_default_mcr(), arm_default_mrc(), arm_full_context(), ARM_MODE_USR, arm_set_cpsr(), arm::common_magic, arm::core_type, ERROR_OK, arm::full_context, arm::mcr, arm::mrc, arm::read_core_reg, target, and arm::target.

Referenced by arm11_target_create(), armv7m_init_arch_info(), and xscale_init_arch_info().

arm_mode_name()

const char* arm_mode_name

(

unsigned

psr_mode

)

Map PSR mode bits to the name of an ARM processor operating mode.

Definition at line 171 of file armv4_5.c.

References arm_mode_data, ARRAY_SIZE, LOG_ERROR, and psr.

Referenced by adapter_debug_entry(), arm7_9_debug_entry(), arm7_9_restore_context(), arm_arch_state(), arm_set_cpsr(), armv7m_arch_state(), cortex_m_debug_entry(), and xscale_debug_entry().

arm_mode_to_number()

int arm_mode_to_number

(

enum arm_mode

mode

)

Map PSR mode bits to linear number indexing armv4_5_core_reg_map.

Definition at line 192 of file armv4_5.c.

References ARM_MODE_1176_MON, ARM_MODE_ABT, ARM_MODE_ANY, ARM_MODE_FIQ, ARM_MODE_HYP, ARM_MODE_IRQ, ARM_MODE_MON, ARM_MODE_SVC, ARM_MODE_SYS, ARM_MODE_UND, ARM_MODE_USR, LOG_ERROR, and mode.

Referenced by arm_set_cpsr().

arm_reg_current()

struct reg* arm_reg_current	(	struct arm *	arm,
		unsigned	regnum
	)

Returns handle to the register currently mapped to a given number.

Someone must have called arm_set_cpsr() before.

Parameters

arm	This core's state and registers are used.
regnum	From 0..15 corresponding to R0..R14 and PC. Note that R0..R7 don't require mapping; you may access those as the first eight entries in the register cache. Likewise R15 (PC) doesn't need mapping; you may also access it directly. However, R8..R14, and SPSR (arm->spsr) must be mapped. CPSR (arm->cpsr) is also not mapped.

Definition at line 502 of file armv4_5.c.

References arm::core_cache, LOG_ERROR, arm::map, NULL, and reg_cache::reg_list.

Referenced by arm7_9_debug_entry(), arm7_9_read_memory(), arm7_9_soft_reset_halt(), arm7_9_write_memory(), arm_dpm_read_current_registers(), arm_get_gdb_reg_list(), arm_semihosting(), COMMAND_HANDLER(), cortex_a_read_cpu_memory(), cortex_a_read_cpu_memory_slow(), cortex_a_write_cpu_memory(), cortex_a_write_cpu_memory_slow(), post_result(), and xscale_debug_entry().

arm_set_cpsr()

void arm_set_cpsr	(	struct arm *	arm,
		uint32_t	cpsr
	)

Configures host-side ARM records to reflect the specified CPSR.

Later, code can use arm_reg_current() to map register numbers according to how they are exposed by this mode.

Definition at line 438 of file armv4_5.c.

References arm_mode_name(), ARM_MODE_SYS, arm_mode_to_number(), ARM_MODE_USR, ARM_STATE_ARM, ARM_STATE_JAZELLE, arm_state_strings, ARM_STATE_THUMB, ARM_STATE_THUMB_EE, armv4_5_core_reg_map, buf_set_u32(), arm::core_cache, arm::core_mode, arm::core_state, arm::cpsr, reg::dirty, LOG_DEBUG, LOG_ERROR, LOG_WARNING, arm::map, mode, NULL, reg_cache::reg_list, arm::spsr, state, reg::valid, and reg::value.

Referenced by arm720t_soft_reset_halt(), arm7_9_debug_entry(), arm7_9_soft_reset_halt(), arm920t_soft_reset_halt(), arm926ejs_soft_reset_halt(), arm_dpm_read_current_registers(), arm_init_arch_info(), armv4_5_run_algorithm_inner(), and xscale_debug_entry().

armv4_5_get_core_reg()

static int armv4_5_get_core_reg ( struct reg *  reg )

static

Definition at line 574 of file armv4_5.c.

References reg::arch_info, arm_reg::arm, reg::dirty, ERROR_OK, ERROR_TARGET_NOT_HALTED, LOG_ERROR, arm_reg::mode, arm_reg::num, arm::read_core_reg, target::state, arm_reg::target, TARGET_HALTED, and reg::valid.

Referenced by arm_full_context().

armv4_5_number_to_mode()

enum arm_mode armv4_5_number_to_mode

(

int

number

)

Map linear number indexing armv4_5_core_reg_map to PSR mode bits.

Definition at line 192 of file armv4_5.c.

Referenced by arm7_9_full_context(), arm7_9_restore_context(), xscale_full_context(), and xscale_restore_banked().

armv4_5_run_algorithm()

int armv4_5_run_algorithm	(	struct target *	target,
		int	num_mem_params,
		struct mem_param *	mem_params,
		int	num_reg_params,
		struct reg_param *	reg_params,
		target_addr_t	entry_point,
		target_addr_t	exit_point,
		int	timeout_ms,
		void *	arch_info
	)

Definition at line 1496 of file armv4_5.c.

References reg::arch_info, armv4_5_run_algorithm_completion(), and armv4_5_run_algorithm_inner().

armv4_5_run_algorithm_completion()

static int armv4_5_run_algorithm_completion ( struct target *  target, uint32_t  exit_point, int  timeout_ms, void *  arch_info  )

static

Definition at line 1279 of file armv4_5.c.

References buf_get_u32(), ERROR_OK, ERROR_TARGET_TIMEOUT, LOG_WARNING, arm::pc, target::state, target_halt(), TARGET_HALTED, target_to_arm(), target_wait_state(), and reg::value.

Referenced by armv4_5_run_algorithm().

armv4_5_run_algorithm_inner()

int armv4_5_run_algorithm_inner	(	struct target *	target,
		int	num_mem_params,
		struct mem_param *	mem_params,
		int	num_reg_params,
		struct reg_param *	reg_params,
		uint32_t	entry_point,
		uint32_t	exit_point,
		int	timeout_ms,
		void *	arch_info,
		int(*)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)	run_it
	)

Definition at line 1311 of file armv4_5.c.

References arm::arch, reg::arch_info, ARM_ARCH_V4, ARM_COMMON_MAGIC, ARM_MODE_ANY, arm_set_cpsr(), ARM_STATE_ARM, ARM_STATE_THUMB, ARMV4_5_CORE_REG_MODE, armv4_5_set_core_reg(), BKPT_HARD, breakpoint_add(), breakpoint_remove(), buf_get_u32(), buf_set_u32(), arm_algorithm::common_magic, arm::core_cache, arm::core_mode, arm_algorithm::core_mode, arm::core_state, arm_algorithm::core_state, arm::cpsr, direction, reg::dirty, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, ERROR_TARGET_FAILURE, ERROR_TARGET_INVALID, ERROR_TARGET_NOT_HALTED, is_arm_mode(), LOG_DEBUG, LOG_ERROR, LOG_WARNING, PARAM_IN, PARAM_OUT, arm::read_core_reg, reg_param::reg_name, register_get_by_name(), size, reg_param::size, reg::size, target::state, TARGET_HALTED, target_read_buffer(), target_resume(), target_to_arm(), target_write_buffer(), reg::valid, and reg::value.

Referenced by arm7_9_bulk_write_memory(), and armv4_5_run_algorithm().

armv4_5_set_core_reg()

static int armv4_5_set_core_reg ( struct reg *  reg, uint8_t *  buf  )

static

Definition at line 595 of file armv4_5.c.

Referenced by armv4_5_run_algorithm_inner().

COMMAND_HANDLER() [1/3]

COMMAND_HANDLER

(

handle_arm_core_state_command

)

Definition at line 908 of file armv4_5.c.

References ARM_CORE_TYPE_M_PROFILE, ARM_STATE_ARM, arm_state_strings, ARM_STATE_THUMB, CMD, CMD_ARGC, CMD_ARGV, CMD_CTX, command_print(), arm::core_state, arm::core_type, ERROR_FAIL, ERROR_OK, get_current_target(), is_arm(), and target_to_arm().

COMMAND_HANDLER() [2/3]

COMMAND_HANDLER

(

handle_arm_disassemble_command

)

Definition at line 937 of file armv4_5.c.

References ARM_CORE_TYPE_M_PROFILE, CMD, CMD_ARGC, CMD_ARGV, CMD_CTX, COMMAND_PARSE_ADDRESS, COMMAND_PARSE_NUMBER, command_print(), arm::core_type, count, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, get_current_target(), is_arm(), LOG_ERROR, and target_to_arm().

COMMAND_HANDLER() [3/3]

COMMAND_HANDLER

(

handle_armv4_5_reg_command

)

Definition at line 808 of file armv4_5.c.

References ARM_CORE_TYPE_SEC_EXT, ARM_CORE_TYPE_STD, ARM_CORE_TYPE_VIRT_EXT, ARM_MODE_1176_MON, arm_mode_data, ARM_MODE_HYP, ARM_MODE_MON, ARM_MODE_SYS, ARM_MODE_USR, ARRAY_SIZE, buf_get_u32(), CMD, CMD_CTX, CMD_NAME, command_print(), arm::core_cache, arm::core_mode, arm::core_type, ERROR_FAIL, ERROR_OK, arm::full_context, get_current_target(), is_arm(), is_arm_mode(), LOG_ERROR, mode, n_indices, name, reg::name, output, psr, reg_cache::reg_list, regs, target::state, TARGET_HALTED, target_to_arm(), reg::valid, and reg::value.

is_arm_mode()

bool is_arm_mode

(

unsigned

psr_mode

)

Return true iff the parameter denotes a valid ARM processor mode.

Definition at line 182 of file armv4_5.c.

References arm_mode_data, ARRAY_SIZE, and psr.

Referenced by arm7_9_debug_entry(), arm7_9_full_context(), arm7_9_read_core_reg(), arm7_9_read_memory(), arm7_9_restore_context(), arm7_9_write_core_reg(), arm7_9_write_memory(), arm920t_read_cp15_interpreted(), arm920t_write_cp15_interpreted(), arm_get_gdb_reg_list(), armv4_5_run_algorithm_inner(), COMMAND_HANDLER(), and xscale_debug_entry().

jim_mcrmrc()

static int jim_mcrmrc ( Jim_Interp *  interp, int  argc, Jim_Obj *const *  argv  )

static

Definition at line 992 of file armv4_5.c.

Variable Documentation

arm_abt_indices

const uint8_t arm_abt_indices[3]

static

Initial value:

= {
    27, 28, ARMV4_5_SPSR_ABT,
}

Definition at line 59 of file armv4_5.c.

arm_all_profiles_command_handlers

const struct command_registration arm_all_profiles_command_handlers[]

Initial value:

= {
    {
        .name = "core_state",
        .handler = handle_arm_core_state_command,
        .mode = COMMAND_EXEC,
        .usage = "['arm'|'thumb']",
        .help = "display/change ARM core state",
    },
    {
        .name = "disassemble",
        .handler = handle_arm_disassemble_command,
        .mode = COMMAND_EXEC,
        .usage = "address [count ['thumb']]",
        .help = "disassemble instructions",
    },
    {
        .chain = semihosting_common_handlers,
    },
    COMMAND_REGISTRATION_DONE
}

Definition at line 992 of file armv4_5.c.

arm_command_handlers

const struct command_registration arm_command_handlers[]

Initial value:

= {
    {
        .name = "arm",
        .mode = COMMAND_ANY,
        .help = "ARM command group",
        .usage = "",
        .chain = arm_exec_command_handlers,
    },
    COMMAND_REGISTRATION_DONE
}

Definition at line 992 of file armv4_5.c.

const { ... } arm_core_regs[]

Referenced by arm_build_reg_cache(), and arm_get_gdb_reg_list().

arm_exec_command_handlers

const struct command_registration arm_exec_command_handlers[]

static

Initial value:

= {
    {
        .name = "reg",
        .handler = handle_armv4_5_reg_command,
        .mode = COMMAND_EXEC,
        .help = "display ARM core registers",
        .usage = "",
    },
    {
        .name = "mcr",
        .mode = COMMAND_EXEC,
        .jim_handler = &jim_mcrmrc,
        .help = "write coprocessor register",
        .usage = "cpnum op1 CRn CRm op2 value",
    },
    {
        .name = "mrc",
        .mode = COMMAND_EXEC,
        .jim_handler = &jim_mcrmrc,
        .help = "read coprocessor register",
        .usage = "cpnum op1 CRn CRm op2",
    },
    {
        .chain = arm_all_profiles_command_handlers,
    },
    COMMAND_REGISTRATION_DONE
}

Definition at line 992 of file armv4_5.c.

arm_fiq_indices

const uint8_t arm_fiq_indices[8]

static

Initial value:

= {
    16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
}

Definition at line 47 of file armv4_5.c.

arm_gdb_dummy_fp_features

struct reg_feature arm_gdb_dummy_fp_features

static

Initial value:

= {
    .name = "net.sourceforge.openocd.fake_fpa"
}

Definition at line 526 of file armv4_5.c.

arm_gdb_dummy_fp_reg

struct reg arm_gdb_dummy_fp_reg

static

Initial value:

= {
    .name = "GDB dummy FPA register",
    .value = (uint8_t *) arm_gdb_dummy_fp_value,
    .valid = true,
    .size = 96,
    .exist = false,
    .number = 16,
    .feature = &arm_gdb_dummy_fp_features,
    .group = "fake_fpa",
}

Dummy FPA registers are required to support GDB on ARM.

Register packets require eight obsolete FPA register values. Modern ARM cores use Vector Floating Point (VFP), if they have any floating point support. VFP is not FPA-compatible.

Definition at line 526 of file armv4_5.c.

Referenced by arm_get_gdb_reg_list().

arm_gdb_dummy_fp_value

const uint8_t arm_gdb_dummy_fp_value[12]

static

Definition at line 526 of file armv4_5.c.

arm_gdb_dummy_fps_reg

struct reg arm_gdb_dummy_fps_reg

static

Initial value:

= {
    .name = "GDB dummy FPA status register",
    .value = (uint8_t *) arm_gdb_dummy_fps_value,
    .valid = true,
    .size = 32,
    .exist = false,
    .number = 24,
    .feature = &arm_gdb_dummy_fp_features,
    .group = "fake_fpa",
}

Dummy FPA status registers are required to support GDB on ARM.

Register packets require an obsolete FPA status register.

Definition at line 549 of file armv4_5.c.

Referenced by arm_get_gdb_reg_list().

arm_gdb_dummy_fps_value

const uint8_t arm_gdb_dummy_fps_value[4]

static

Definition at line 549 of file armv4_5.c.

arm_hyp_indices

const uint8_t arm_hyp_indices[2]

static

Initial value:

= {
    42, ARM_SPSR_HYP,
}

Definition at line 71 of file armv4_5.c.

arm_irq_indices

const uint8_t arm_irq_indices[3]

static

Initial value:

= {
    23, 24, ARMV4_5_SPSR_IRQ,
}

Definition at line 51 of file armv4_5.c.

const { ... } arm_mode_data[]

Referenced by arm_mode_name(), COMMAND_HANDLER(), and is_arm_mode().

arm_mon_indices

const uint8_t arm_mon_indices[3]

static

Initial value:

= {
    39, 40, ARM_SPSR_MON,
}

Definition at line 67 of file armv4_5.c.

arm_reg_type

const struct reg_arch_type arm_reg_type

static

Initial value:

= {
    .get = armv4_5_get_core_reg,
    .set = armv4_5_set_core_reg,
}

Definition at line 595 of file armv4_5.c.

Referenced by arm_build_reg_cache().

arm_state_strings

const char* arm_state_strings[]

static

Initial value:

= {
    "ARM", "Thumb", "Jazelle", "ThumbEE",
}

Definition at line 250 of file armv4_5.c.

Referenced by arm_arch_state(), arm_set_cpsr(), and COMMAND_HANDLER().

arm_svc_indices

const uint8_t arm_svc_indices[3]

static

Initial value:

= {
    25, 26, ARMV4_5_SPSR_SVC,
}

Definition at line 55 of file armv4_5.c.

arm_und_indices

const uint8_t arm_und_indices[3]

static

Initial value:

= {
    29, 30, ARMV4_5_SPSR_UND,
}

Definition at line 63 of file armv4_5.c.

arm_usr_indices

const uint8_t arm_usr_indices[17]

static

Initial value:

= {
    0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
}

Definition at line 43 of file armv4_5.c.

const { ... } arm_vfp_v3_regs[]

Referenced by arm_build_reg_cache().

armv4_5_core_reg_map

const int armv4_5_core_reg_map[9][17]

Initial value:

= {
    {   
        0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
    },
    {   
        0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
    },
    {   
        0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
    },
    {   
        0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
    },
    {   
        0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
    },
    {   
        0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
    },
    {   
        0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
    },
    {   
        0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 39, 40, 15, 41,
    },
    {   
        0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 42, 14, 15, 43,
    }
}

Definition at line 403 of file armv4_5.c.

Referenced by arm_set_cpsr().

bits

uint32_t bits

Definition at line 359 of file armv4_5.c.

Referenced by armjtagew_tap_ensure_space(), armv4_5_get_cpsr(), avr32_ocd_clearbits(), avr32_ocd_setbits(), bitbang_execute_tms(), buspirate_tap_make_space(), jim_command_drscan(), jtag_check_value_inner(), jtag_vpi_queue_tdi(), jtag_vpi_queue_tdi_xfer(), jtag_vpi_tms_seq(), opendous_tap_append_step(), opendous_tap_ensure_space(), openjtag_add_scan(), openjtag_execute_tap_queue(), poll_target(), syncbb_execute_tms(), tap_state_queue_run(), target_address_max(), ublast_queue_tdi(), ublast_tms_seq(), vsllink_tms(), wait_for_debugint_clear(), xds110_flush(), xlnx_pcie_xvc_execute_tms(), xtensa_core_status_clear(), and xtensa_dm_core_status_clear().

cookie

unsigned cookie

Definition at line 275 of file armv4_5.c.

Referenced by arm_build_reg_cache().

feature

const char* feature

Definition at line 363 of file armv4_5.c.

Referenced by arc_build_bcr_reg_cache(), arc_build_reg_cache(), gdb_generate_target_description(), get_reg_features_list(), jim_arc_add_reg(), and or1k_build_reg_cache().

gdb_index

unsigned gdb_index

Definition at line 276 of file armv4_5.c.

group

const char* group

Definition at line 362 of file armv4_5.c.

Referenced by arc_build_bcr_reg_cache(), arc_build_reg_cache(), and gdb_generate_target_description().

id

unsigned int id

Definition at line 357 of file armv4_5.c.

indices

const uint8_t* indices

Definition at line 82 of file armv4_5.c.

mode

enum arm_mode mode

Definition at line 276 of file armv4_5.c.

Referenced by aarch64_do_restart_one(), aarch64_halt_one(), aarch64_restart_one(), arm7_9_read_core_reg(), arm7_9_write_core_reg(), arm_build_reg_cache(), arm_dpm_full_context(), arm_dpm_modeswitch(), arm_dpm_read_core_reg(), arm_dpm_write_core_reg(), arm_dpm_write_dirty_registers(), arm_get_gdb_reg_list(), arm_mode_to_number(), arm_set_cpsr(), armv4_5_get_mode(), armv7m_read_core_reg(), armv7m_write_core_reg(), armv8_dpm_full_context(), armv8_dpm_modeswitch(), at91sam7_set_flash_mode(), avr32_jtag_mwa_set_address(), avr32_jtag_nexus_set_address(), buspirate_jtag_set_mode(), buspirate_set_mode(), buspirate_swd_set_mode(), cmsis_dap_cmd_dap_connect(), cmsis_dap_cmd_dap_swo_mode(), command_context_mode(), COMMAND_HANDLER(), COMMAND_HELPER(), cortex_a_set_dcc_mode(), dap_queue_read_reg(), evaluate_srs(), find_file(), initialize_gpio(), jim_command_mode(), mpsse_clock_data(), mpsse_clock_data_in(), mpsse_clock_data_out(), mpsse_clock_tms_cs(), mpsse_clock_tms_cs_out(), mrvlqspi_set_write_status(), octospi_cmd(), open_file_from_path(), restore_gpio(), riscv_address_translate(), rtp_cs_component(), rtp_read_cs_regs(), rtp_rom_loop(), semihosting_common(), stlink_dap_init(), stlink_open(), stlink_usb_current_mode(), stlink_usb_exit_mode(), stlink_usb_init_mode(), xscale_full_context(), and xscale_restore_banked().

n_indices

unsigned short n_indices

Definition at line 81 of file armv4_5.c.

Referenced by COMMAND_HANDLER().

name

const char* name

Definition at line 76 of file armv4_5.c.

Referenced by __attribute__(), __register_commands(), adapter_assert_reset(), adapter_deassert_reset(), adapter_resets(), arc_build_bcr_reg_cache(), arc_build_reg_cache(), arc_reg_get_by_name(), arm_tpiu_swo_handle_event(), command_find_from_name(), COMMAND_HANDLER(), COMMAND_HELPER(), create_default_signal(), create_signal(), cti_find_reg_offset(), cti_instance_by_jim_obj(), dap_instance_by_jim_obj(), decode_dmi(), find_signal_by_name(), find_target(), flash_driver_find_by_name(), flash_driver_name_matches(), fm4_get_info_command(), ft232r_bit_name_to_number(), gdb_generate_target_description(), gdb_get_register_packet(), gdb_get_registers_packet(), gdb_set_register_packet(), gdb_set_registers_packet(), get_flash_bank_by_name(), get_flash_bank_by_name_noprobe(), get_flash_name_index(), get_gpio_index(), get_nand_device_by_name(), hwthread_get_thread_reg_list(), jim_adapter_name(), jim_arc_add_reg_type_flags(), jim_arc_add_reg_type_struct(), jim_arc_read_reg_name_field(), jim_nvp_name2value(), jim_nvp_name2value_nocase(), jim_nvp_name2value_nocase_simple(), jim_nvp_name2value_simple(), jim_set_result_nvp_unknown(), jim_target_types(), jtag_examine_chain_display(), kinetis_create_missing_banks(), kinetis_probe_chip(), linux_thread_extra_info(), msp432_probe(), nand_driver_find_by_name(), open_write_close(), or1k_create_reg_list(), parse_ranges(), pic32mx_info(), pic32mx_probe(), rcmd_offset(), read_channel_name(), register_get_by_name(), remove_service(), riot_get_thread_reg_list(), riot_update_threads(), rtos_create(), tap_state_by_name(), target_call_reset_callbacks(), target_create(), target_wait_state(), telnet_auto_complete(), transport_select(), ublast_init(), unregister_command(), xtensa_build_reg_cache(), xtensa_fetch_all_regs(), xtensa_write_dirty_registers(), and zephyr_create().

psr

unsigned short psr

Definition at line 77 of file armv4_5.c.

Referenced by arm_mode_name(), COMMAND_HANDLER(), and is_arm_mode().

type

enum reg_type type

Definition at line 359 of file armv4_5.c.