23 static uint32_t
arm_shift(uint8_t shift, uint32_t rm,
24 uint32_t shift_amount, uint8_t *carry)
26 uint32_t return_value = 0;
30 if ((shift_amount > 0) && (shift_amount <= 32)) {
31 return_value = rm << shift_amount;
32 *carry = rm >> (32 - shift_amount);
33 }
else if (shift_amount > 32) {
38 }
else if (shift == 0x1) {
39 if ((shift_amount > 0) && (shift_amount <= 32)) {
40 return_value = rm >> shift_amount;
41 *carry = (rm >> (shift_amount - 1)) & 1;
42 }
else if (shift_amount > 32) {
47 }
else if (shift == 0x2) {
48 if ((shift_amount > 0) && (shift_amount <= 32)) {
54 return_value = rm >> shift_amount;
56 return_value |= 0xffffffff << (32 - shift_amount);
57 }
else if (shift_amount > 32) {
58 if (rm & 0x80000000) {
59 return_value = 0xffffffff;
67 }
else if (shift == 0x3) {
68 if (shift_amount == 0)
71 shift_amount = shift_amount % 32;
72 return_value = (rm >> shift_amount) | (rm << (32 - shift_amount));
73 *carry = (return_value >> 31) & 0x1;
75 }
else if (shift == 0x4) {
76 return_value = rm >> 1;
88 uint8_t *shifter_carry_out)
90 uint32_t return_value;
98 *shifter_carry_out = sim->
get_cpsr(sim, 29, 1);
101 return_value = shifter_operand.
immediate.immediate;
102 else if (variant == 1) {
107 rm += 2 * instruction_size;
112 }
else if (variant == 2) {
118 rm += 2 * instruction_size;
121 rm, rs, shifter_carry_out);
123 LOG_ERROR(
"BUG: shifter_operand.variant not 0, 1 or 2");
124 return_value = 0xffffffff;
132 switch ((opcode & 0xf0000000) >> 28) {
134 if (cpsr & 0x40000000)
139 if (!(cpsr & 0x40000000))
144 if (cpsr & 0x20000000)
149 if (!(cpsr & 0x20000000))
154 if (cpsr & 0x80000000)
159 if (!(cpsr & 0x80000000))
164 if (cpsr & 0x10000000)
169 if (!(cpsr & 0x10000000))
174 if ((cpsr & 0x20000000) && !(cpsr & 0x40000000))
179 if (!(cpsr & 0x20000000) || (cpsr & 0x40000000))
184 if (((cpsr & 0x80000000) && (cpsr & 0x10000000))
185 || (!(cpsr & 0x80000000) && !(cpsr & 0x10000000)))
190 if (((cpsr & 0x80000000) && !(cpsr & 0x10000000))
191 || (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
196 if (!(cpsr & 0x40000000) &&
197 (((cpsr & 0x80000000) && (cpsr & 0x10000000))
198 || (!(cpsr & 0x80000000) && !(cpsr & 0x10000000))))
203 if ((cpsr & 0x40000000) ||
204 ((cpsr & 0x80000000) && !(cpsr & 0x10000000))
205 || (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
231 uint32_t current_pc = sim->
get_reg(sim, 15);
269 if ((
opcode & 0xf000) == 0xd000
281 if ((
opcode & 0xf800) == 0xf000) {
297 uint32_t target_address;
309 *dry_run_pc = target_address & ~1;
313 sim->
set_reg(sim, 15, target_address);
315 uint32_t old_pc = sim->
get_reg(sim, 15);
318 sim->
set_reg(sim, 15, target_address);
320 if (target_address & 0x1)
324 sim->
set_reg(sim, 15, target_address & 0xfffffffe);
326 uint32_t old_pc = sim->
get_reg(sim, 15);
330 if (target_address & 0x1)
334 sim->
set_reg(sim, 15, target_address & 0xfffffffe);
343 uint32_t rd, rn, shifter_operand;
344 uint8_t c = sim->
get_cpsr(sim, 29, 1);
364 rd = rn & shifter_operand;
366 rd = rn ^ shifter_operand;
368 rd = rn - shifter_operand;
370 rd = shifter_operand - rn;
372 rd = rn + shifter_operand;
374 rd = rn + shifter_operand + (c & 1);
376 rd = rn - shifter_operand - (c & 1) ? 0 : 1;
378 rd = shifter_operand - rn - (c & 1) ? 0 : 1;
380 rd = rn | shifter_operand;
382 rd = rn & ~(shifter_operand);
384 rd = shifter_operand;
386 rd = ~shifter_operand;
392 *dry_run_pc = rd & ~1;
420 uint32_t load_address = 0, modified_address = 0, load_value = 0;
438 uint8_t carry = sim->
get_cpsr(sim, 29, 1);
443 modified_address = rn +
offset;
445 modified_address = rn -
offset;
447 LOG_ERROR(
"BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
454 load_address = modified_address;
455 modified_address = rn;
461 load_address = modified_address;
478 *dry_run_pc = load_value & ~1;
504 uint32_t load_values[16];
507 for (i = 0; i < 16; i++) {
520 rn = rn - (bits_set * 4) + 4;
523 rn = rn - (bits_set * 4);
527 for (i = 0; i < 16; i++) {
529 if ((!dry_run_pc) || (i == 15))
537 *dry_run_pc = load_values[15] & ~1;
548 for (i = 0; i < 16; i++) {
551 uint32_t val = load_values[i];
587 for (i = 0; i < 16; i++) {
600 rn = rn - (bits_set * 4) + 4;
603 rn = rn - (bits_set * 4);
607 for (i = 0; i < 16; i++) {
620 }
else if (!dry_run_pc) {
623 LOG_ERROR(
"Unimplemented instruction, could not simulate it.");
Holds the interface to ARM cores.
arm_mode
Represent state of an ARM core.
arm_state
The PSR "T" and "J" bits define the mode of "classic ARM" cores.
static struct arm * target_to_arm(struct target *target)
Convert target handle to generic ARM target state handle.
int arm_evaluate_opcode(uint32_t opcode, uint32_t address, struct arm_instruction *instruction)
int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, struct arm_instruction *instruction)
static void armv4_5_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
static int thumb_pass_branch_condition(uint32_t cpsr, uint16_t opcode)
static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_t value)
int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
static uint32_t arm_shift(uint8_t shift, uint32_t rm, uint32_t shift_amount, uint8_t *carry)
static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface *sim, int reg)
static uint32_t arm_shifter_operand(struct arm_sim_interface *sim, int variant, union arm_shifter_operand shifter_operand, uint8_t *shifter_carry_out)
static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode)
static int pass_condition(uint32_t cpsr, uint32_t opcode)
static int arm_simulate_step_core(struct target *target, uint32_t *dry_run_pc, struct arm_sim_interface *sim)
static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim)
static uint32_t armv4_5_get_reg(struct arm_sim_interface *sim, int reg)
static enum arm_state armv4_5_get_state(struct arm_sim_interface *sim)
#define ARMV4_5_CORE_REG_MODE(cache, mode, num)
Support functions to access arbitrary bits in a byte array.
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
union arm_shifter_operand shifter_operand
struct arm_load_store_multiple_instr load_store_multiple
enum arm_instruction_type type
union arm_instruction::@65 info
unsigned instruction_size
struct arm_b_bl_bx_blx_instr b_bl_bx_blx
struct arm_load_store_instr load_store
struct arm_data_proc_instr data_proc
uint32_t(* get_reg_mode)(struct arm_sim_interface *sim, int reg)
enum arm_mode(* get_mode)(struct arm_sim_interface *sim)
void(* set_reg)(struct arm_sim_interface *sim, int reg, uint32_t value)
uint32_t(* get_cpsr)(struct arm_sim_interface *sim, int pos, int bits)
uint32_t(* get_reg)(struct arm_sim_interface *sim, int reg)
void(* set_state)(struct arm_sim_interface *sim, enum arm_state mode)
void(* set_reg_mode)(struct arm_sim_interface *sim, int reg, uint32_t value)
enum arm_state(* get_state)(struct arm_sim_interface *sim)
Represents a generic ARM core, with standard application registers.
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
struct reg * cpsr
Handle to the CPSR/xPSR; valid in all core modes.
struct reg_cache * core_cache
enum arm_state core_state
Record the current core state: ARM, Thumb, or otherwise.
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
struct arm_shifter_operand::@62 register_shift
struct arm_shifter_operand::@61 immediate_shift