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armv4_5.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2005 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  * *
7  * Copyright (C) 2008 by Spencer Oliver *
8  * spen@spen-soft.co.uk *
9  * *
10  * Copyright (C) 2008 by Oyvind Harboe *
11  * oyvind.harboe@zylin.com *
12  * *
13  * Copyright (C) 2018 by Liviu Ionescu *
14  * <ilg@livius.net> *
15  ***************************************************************************/
16 
17 #ifdef HAVE_CONFIG_H
18 #include "config.h"
19 #endif
20 
21 #include "arm.h"
22 #include "armv4_5.h"
23 #include "arm_jtag.h"
24 #include "breakpoints.h"
25 #include "arm_disassembler.h"
26 #include <helper/binarybuffer.h>
27 #include "algorithm.h"
28 #include "register.h"
29 #include "semihosting_common.h"
30 
31 /* offsets into armv4_5 core register cache */
32 enum {
33 /* ARMV4_5_CPSR = 31, */
41 };
42 
43 static const uint8_t arm_usr_indices[17] = {
44  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
45 };
46 
47 static const uint8_t arm_fiq_indices[8] = {
48  16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
49 };
50 
51 static const uint8_t arm_irq_indices[3] = {
52  23, 24, ARMV4_5_SPSR_IRQ,
53 };
54 
55 static const uint8_t arm_svc_indices[3] = {
56  25, 26, ARMV4_5_SPSR_SVC,
57 };
58 
59 static const uint8_t arm_abt_indices[3] = {
60  27, 28, ARMV4_5_SPSR_ABT,
61 };
62 
63 static const uint8_t arm_und_indices[3] = {
64  29, 30, ARMV4_5_SPSR_UND,
65 };
66 
67 static const uint8_t arm_mon_indices[3] = {
68  39, 40, ARM_SPSR_MON,
69 };
70 
71 static const uint8_t arm_hyp_indices[2] = {
72  42, ARM_SPSR_HYP,
73 };
74 
75 static const struct {
76  const char *name;
77  unsigned short psr;
78  /* For user and system modes, these list indices for all registers.
79  * otherwise they're just indices for the shadow registers and SPSR.
80  */
81  unsigned short n_indices;
82  const uint8_t *indices;
83 } arm_mode_data[] = {
84  /* Seven modes are standard from ARM7 on. "System" and "User" share
85  * the same registers; other modes shadow from 3 to 8 registers.
86  */
87  {
88  .name = "User",
89  .psr = ARM_MODE_USR,
90  .n_indices = ARRAY_SIZE(arm_usr_indices),
91  .indices = arm_usr_indices,
92  },
93  {
94  .name = "FIQ",
95  .psr = ARM_MODE_FIQ,
96  .n_indices = ARRAY_SIZE(arm_fiq_indices),
97  .indices = arm_fiq_indices,
98  },
99  {
100  .name = "Supervisor",
101  .psr = ARM_MODE_SVC,
102  .n_indices = ARRAY_SIZE(arm_svc_indices),
103  .indices = arm_svc_indices,
104  },
105  {
106  .name = "Abort",
107  .psr = ARM_MODE_ABT,
108  .n_indices = ARRAY_SIZE(arm_abt_indices),
109  .indices = arm_abt_indices,
110  },
111  {
112  .name = "IRQ",
113  .psr = ARM_MODE_IRQ,
114  .n_indices = ARRAY_SIZE(arm_irq_indices),
115  .indices = arm_irq_indices,
116  },
117  {
118  .name = "Undefined instruction",
119  .psr = ARM_MODE_UND,
120  .n_indices = ARRAY_SIZE(arm_und_indices),
121  .indices = arm_und_indices,
122  },
123  {
124  .name = "System",
125  .psr = ARM_MODE_SYS,
126  .n_indices = ARRAY_SIZE(arm_usr_indices),
127  .indices = arm_usr_indices,
128  },
129  /* TrustZone "Security Extensions" add a secure monitor mode.
130  * This is distinct from a "debug monitor" which can support
131  * non-halting debug, in conjunction with some debuggers.
132  */
133  {
134  .name = "Secure Monitor",
135  .psr = ARM_MODE_MON,
136  .n_indices = ARRAY_SIZE(arm_mon_indices),
137  .indices = arm_mon_indices,
138  },
139  {
140  .name = "Secure Monitor ARM1176JZF-S",
141  .psr = ARM_MODE_1176_MON,
142  .n_indices = ARRAY_SIZE(arm_mon_indices),
143  .indices = arm_mon_indices,
144  },
145 
146  /* These special modes are currently only supported
147  * by ARMv6M and ARMv7M profiles */
148  {
149  .name = "Thread",
150  .psr = ARM_MODE_THREAD,
151  },
152  {
153  .name = "Thread (User)",
154  .psr = ARM_MODE_USER_THREAD,
155  },
156  {
157  .name = "Handler",
158  .psr = ARM_MODE_HANDLER,
159  },
160 
161  /* armv7-a with virtualization extension */
162  {
163  .name = "Hypervisor",
164  .psr = ARM_MODE_HYP,
165  .n_indices = ARRAY_SIZE(arm_hyp_indices),
166  .indices = arm_hyp_indices,
167  },
168 };
169 
171 const char *arm_mode_name(unsigned psr_mode)
172 {
173  for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
174  if (arm_mode_data[i].psr == psr_mode)
175  return arm_mode_data[i].name;
176  }
177  LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
178  return "UNRECOGNIZED";
179 }
180 
182 bool is_arm_mode(unsigned psr_mode)
183 {
184  for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
185  if (arm_mode_data[i].psr == psr_mode)
186  return true;
187  }
188  return false;
189 }
190 
193 {
194  switch (mode) {
195  case ARM_MODE_ANY:
196  /* map MODE_ANY to user mode */
197  case ARM_MODE_USR:
198  return 0;
199  case ARM_MODE_FIQ:
200  return 1;
201  case ARM_MODE_IRQ:
202  return 2;
203  case ARM_MODE_SVC:
204  return 3;
205  case ARM_MODE_ABT:
206  return 4;
207  case ARM_MODE_UND:
208  return 5;
209  case ARM_MODE_SYS:
210  return 6;
211  case ARM_MODE_MON:
212  case ARM_MODE_1176_MON:
213  return 7;
214  case ARM_MODE_HYP:
215  return 8;
216  default:
217  LOG_ERROR("invalid mode value encountered %d", mode);
218  return -1;
219  }
220 }
221 
224 {
225  switch (number) {
226  case 0:
227  return ARM_MODE_USR;
228  case 1:
229  return ARM_MODE_FIQ;
230  case 2:
231  return ARM_MODE_IRQ;
232  case 3:
233  return ARM_MODE_SVC;
234  case 4:
235  return ARM_MODE_ABT;
236  case 5:
237  return ARM_MODE_UND;
238  case 6:
239  return ARM_MODE_SYS;
240  case 7:
241  return ARM_MODE_MON;
242  case 8:
243  return ARM_MODE_HYP;
244  default:
245  LOG_ERROR("mode index out of bounds %d", number);
246  return ARM_MODE_ANY;
247  }
248 }
249 
250 static const char *arm_state_strings[] = {
251  "ARM", "Thumb", "Jazelle", "ThumbEE",
252 };
253 
254 /* Templates for ARM core registers.
255  *
256  * NOTE: offsets in this table are coupled to the arm_mode_data
257  * table above, the armv4_5_core_reg_map array below, and also to
258  * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
259  */
260 static const struct {
261  /* The name is used for e.g. the "regs" command. */
262  const char *name;
263 
264  /* The {cookie, mode} tuple uniquely identifies one register.
265  * In a given mode, cookies 0..15 map to registers R0..R15,
266  * with R13..R15 usually called SP, LR, PC.
267  *
268  * MODE_ANY is used as *input* to the mapping, and indicates
269  * various special cases (sigh) and errors.
270  *
271  * Cookie 16 is (currently) confusing, since it indicates
272  * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
273  * (Exception modes have both CPSR and SPSR registers ...)
274  */
275  unsigned cookie;
276  unsigned gdb_index;
277  enum arm_mode mode;
278 } arm_core_regs[] = {
279  /* IMPORTANT: we guarantee that the first eight cached registers
280  * correspond to r0..r7, and the fifteenth to PC, so that callers
281  * don't need to map them.
282  */
283  [0] = { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
284  [1] = { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
285  [2] = { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
286  [3] = { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
287  [4] = { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
288  [5] = { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
289  [6] = { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
290  [7] = { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
291 
292  /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
293  * them as MODE_ANY creates special cases. (ANY means
294  * "not mapped" elsewhere; here it's "everything but FIQ".)
295  */
296  [8] = { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
297  [9] = { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
298  [10] = { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
299  [11] = { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
300  [12] = { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
301 
302  /* Historical GDB mapping of indices:
303  * - 13-14 are sp and lr, but banked counterparts are used
304  * - 16-24 are left for deprecated 8 FPA + 1 FPS
305  * - 25 is the cpsr
306  */
307 
308  /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
309  [13] = { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
310  [14] = { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
311 
312  /* guaranteed to be at index 15 */
313  [15] = { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
314  [16] = { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
315  [17] = { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
316  [18] = { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
317  [19] = { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
318  [20] = { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
319 
320  [21] = { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
321  [22] = { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
322 
323  [23] = { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
324  [24] = { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
325 
326  [25] = { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
327  [26] = { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
328 
329  [27] = { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
330  [28] = { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
331 
332  [29] = { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
333  [30] = { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
334 
335  [31] = { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
336  [32] = { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
337  [33] = { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
338  [34] = { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
339  [35] = { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
340  [36] = { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
341 
342  /* These are only used for GDB target description, banked registers are accessed instead */
343  [37] = { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
344  [38] = { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
345 
346  /* These exist only when the Security Extension (TrustZone) is present */
347  [39] = { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
348  [40] = { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
349  [41] = { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
350 
351  /* These exist only when the Virtualization Extensions is present */
352  [42] = { .name = "sp_hyp", .cookie = 13, .mode = ARM_MODE_HYP, .gdb_index = 51, },
353  [43] = { .name = "spsr_hyp", .cookie = 16, .mode = ARM_MODE_HYP, .gdb_index = 52, },
354 };
355 
356 static const struct {
357  unsigned int id;
358  const char *name;
359  uint32_t bits;
360  enum arm_mode mode;
361  enum reg_type type;
362  const char *group;
363  const char *feature;
364 } arm_vfp_v3_regs[] = {
365  { ARM_VFP_V3_D0, "d0", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
366  { ARM_VFP_V3_D1, "d1", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
367  { ARM_VFP_V3_D2, "d2", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
368  { ARM_VFP_V3_D3, "d3", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
369  { ARM_VFP_V3_D4, "d4", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
370  { ARM_VFP_V3_D5, "d5", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
371  { ARM_VFP_V3_D6, "d6", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
372  { ARM_VFP_V3_D7, "d7", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
373  { ARM_VFP_V3_D8, "d8", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
374  { ARM_VFP_V3_D9, "d9", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
375  { ARM_VFP_V3_D10, "d10", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
376  { ARM_VFP_V3_D11, "d11", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
377  { ARM_VFP_V3_D12, "d12", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
378  { ARM_VFP_V3_D13, "d13", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
379  { ARM_VFP_V3_D14, "d14", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
380  { ARM_VFP_V3_D15, "d15", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
381  { ARM_VFP_V3_D16, "d16", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
382  { ARM_VFP_V3_D17, "d17", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
383  { ARM_VFP_V3_D18, "d18", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
384  { ARM_VFP_V3_D19, "d19", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
385  { ARM_VFP_V3_D20, "d20", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
386  { ARM_VFP_V3_D21, "d21", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
387  { ARM_VFP_V3_D22, "d22", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
388  { ARM_VFP_V3_D23, "d23", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
389  { ARM_VFP_V3_D24, "d24", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
390  { ARM_VFP_V3_D25, "d25", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
391  { ARM_VFP_V3_D26, "d26", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
392  { ARM_VFP_V3_D27, "d27", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
393  { ARM_VFP_V3_D28, "d28", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
394  { ARM_VFP_V3_D29, "d29", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
395  { ARM_VFP_V3_D30, "d30", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
396  { ARM_VFP_V3_D31, "d31", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
397  { ARM_VFP_V3_FPSCR, "fpscr", 32, ARM_MODE_ANY, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp"},
398 };
399 
400 /* map core mode (USR, FIQ, ...) and register number to
401  * indices into the register cache
402  */
403 const int armv4_5_core_reg_map[9][17] = {
404  { /* USR */
405  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
406  },
407  { /* FIQ (8 shadows of USR, vs normal 3) */
408  0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
409  },
410  { /* IRQ */
411  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
412  },
413  { /* SVC */
414  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
415  },
416  { /* ABT */
417  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
418  },
419  { /* UND */
420  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
421  },
422  { /* SYS (same registers as USR) */
423  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
424  },
425  { /* MON */
426  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 39, 40, 15, 41,
427  },
428  { /* HYP */
429  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 42, 14, 15, 43,
430  }
431 };
432 
438 void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
439 {
440  enum arm_mode mode = cpsr & 0x1f;
441  int num;
442 
443  /* NOTE: this may be called very early, before the register
444  * cache is set up. We can't defend against many errors, in
445  * particular against CPSRs that aren't valid *here* ...
446  */
447  if (arm->cpsr) {
448  buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
449  arm->cpsr->valid = true;
450  arm->cpsr->dirty = false;
451  }
452 
453  arm->core_mode = mode;
454 
455  /* mode_to_number() warned; set up a somewhat-sane mapping */
456  num = arm_mode_to_number(mode);
457  if (num < 0) {
458  mode = ARM_MODE_USR;
459  num = 0;
460  }
461 
462  arm->map = &armv4_5_core_reg_map[num][0];
463  arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
464  ? NULL
465  : arm->core_cache->reg_list + arm->map[16];
466 
467  /* Older ARMs won't have the J bit */
468  enum arm_state state;
469 
470  if (cpsr & (1 << 5)) { /* T */
471  if (cpsr & (1 << 24)) { /* J */
472  LOG_WARNING("ThumbEE -- incomplete support");
474  } else
476  } else {
477  if (cpsr & (1 << 24)) { /* J */
478  LOG_ERROR("Jazelle state handling is BROKEN!");
480  } else
482  }
483  arm->core_state = state;
484 
485  LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
488 }
489 
502 struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
503 {
504  struct reg *r;
505 
506  if (regnum > 16)
507  return NULL;
508 
509  if (!arm->map) {
510  LOG_ERROR("Register map is not available yet, the target is not fully initialised");
511  r = arm->core_cache->reg_list + regnum;
512  } else
513  r = arm->core_cache->reg_list + arm->map[regnum];
514 
515  /* e.g. invalid CPSR said "secure monitor" mode on a core
516  * that doesn't support it...
517  */
518  if (!r) {
519  LOG_ERROR("Invalid CPSR mode");
520  r = arm->core_cache->reg_list + regnum;
521  }
522 
523  return r;
524 }
525 
526 static const uint8_t arm_gdb_dummy_fp_value[12];
527 
528 static struct reg_feature arm_gdb_dummy_fp_features = {
529  .name = "net.sourceforge.openocd.fake_fpa"
530 };
531 
538 static struct reg arm_gdb_dummy_fp_reg = {
539  .name = "GDB dummy FPA register",
540  .value = (uint8_t *) arm_gdb_dummy_fp_value,
541  .valid = true,
542  .size = 96,
543  .exist = false,
544  .number = 16,
546  .group = "fake_fpa",
547 };
548 
549 static const uint8_t arm_gdb_dummy_fps_value[4];
550 
555 static struct reg arm_gdb_dummy_fps_reg = {
556  .name = "GDB dummy FPA status register",
557  .value = (uint8_t *) arm_gdb_dummy_fps_value,
558  .valid = true,
559  .size = 32,
560  .exist = false,
561  .number = 24,
563  .group = "fake_fpa",
564 };
565 
566 static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
567 
568 static void arm_gdb_dummy_init(void)
569 {
572 }
573 
574 static int armv4_5_get_core_reg(struct reg *reg)
575 {
576  int retval;
577  struct arm_reg *reg_arch_info = reg->arch_info;
578  struct target *target = reg_arch_info->target;
579 
580  if (target->state != TARGET_HALTED) {
581  LOG_ERROR("Target not halted");
583  }
584 
585  retval = reg_arch_info->arm->read_core_reg(target, reg,
586  reg_arch_info->num, reg_arch_info->mode);
587  if (retval == ERROR_OK) {
588  reg->valid = true;
589  reg->dirty = false;
590  }
591 
592  return retval;
593 }
594 
595 static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
596 {
597  struct arm_reg *reg_arch_info = reg->arch_info;
598  struct target *target = reg_arch_info->target;
599  struct arm *armv4_5_target = target_to_arm(target);
600  uint32_t value = buf_get_u32(buf, 0, 32);
601 
602  if (target->state != TARGET_HALTED) {
603  LOG_ERROR("Target not halted");
605  }
606 
607  /* Except for CPSR, the "reg" command exposes a writeback model
608  * for the register cache.
609  */
610  if (reg == armv4_5_target->cpsr) {
611  arm_set_cpsr(armv4_5_target, value);
612 
613  /* Older cores need help to be in ARM mode during halt
614  * mode debug, so we clear the J and T bits if we flush.
615  * For newer cores (v6/v7a/v7r) we don't need that, but
616  * it won't hurt since CPSR is always flushed anyway.
617  */
618  if (armv4_5_target->core_mode !=
619  (enum arm_mode)(value & 0x1f)) {
620  LOG_DEBUG("changing ARM core mode to '%s'",
621  arm_mode_name(value & 0x1f));
622  value &= ~((1 << 24) | (1 << 5));
623  uint8_t t[4];
624  buf_set_u32(t, 0, 32, value);
625  armv4_5_target->write_core_reg(target, reg,
626  16, ARM_MODE_ANY, t);
627  }
628  } else {
629  buf_set_u32(reg->value, 0, 32, value);
630  if (reg->size == 64) {
631  value = buf_get_u32(buf + 4, 0, 32);
632  buf_set_u32(reg->value + 4, 0, 32, value);
633  }
634  reg->valid = true;
635  }
636  reg->dirty = true;
637 
638  return ERROR_OK;
639 }
640 
641 static const struct reg_arch_type arm_reg_type = {
643  .set = armv4_5_set_core_reg,
644 };
645 
647 {
649  int num_core_regs = num_regs;
652 
653  struct reg_cache *cache = malloc(sizeof(struct reg_cache));
654  struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
655  struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
656  int i;
657 
658  if (!cache || !reg_list || !reg_arch_info) {
659  free(cache);
660  free(reg_list);
661  free(reg_arch_info);
662  return NULL;
663  }
664 
665  cache->name = "ARM registers";
666  cache->next = NULL;
667  cache->reg_list = reg_list;
668  cache->num_regs = 0;
669 
670  for (i = 0; i < num_core_regs; i++) {
671  /* Skip registers this core doesn't expose */
675  continue;
678  continue;
679 
680  /* REVISIT handle Cortex-M, which only shadows R13/SP */
681 
682  reg_arch_info[i].num = arm_core_regs[i].cookie;
683  reg_arch_info[i].mode = arm_core_regs[i].mode;
684  reg_arch_info[i].target = target;
685  reg_arch_info[i].arm = arm;
686 
687  reg_list[i].name = arm_core_regs[i].name;
688  reg_list[i].number = arm_core_regs[i].gdb_index;
689  reg_list[i].size = 32;
690  reg_list[i].value = reg_arch_info[i].value;
691  reg_list[i].type = &arm_reg_type;
692  reg_list[i].arch_info = &reg_arch_info[i];
693  reg_list[i].exist = true;
694 
695  /* This really depends on the calling convention in use */
696  reg_list[i].caller_save = false;
697 
698  /* Registers data type, as used by GDB target description */
699  reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
700  switch (arm_core_regs[i].cookie) {
701  case 13:
702  reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR;
703  break;
704  case 14:
705  case 15:
706  reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR;
707  break;
708  default:
709  reg_list[i].reg_data_type->type = REG_TYPE_UINT32;
710  break;
711  }
712 
713  /* let GDB shows banked registers only in "info all-reg" */
714  reg_list[i].feature = malloc(sizeof(struct reg_feature));
715  if (reg_list[i].number <= 15 || reg_list[i].number == 25) {
716  reg_list[i].feature->name = "org.gnu.gdb.arm.core";
717  reg_list[i].group = "general";
718  } else {
719  reg_list[i].feature->name = "net.sourceforge.openocd.banked";
720  reg_list[i].group = "banked";
721  }
722 
723  cache->num_regs++;
724  }
725 
726  int j;
727  for (i = num_core_regs, j = 0; i < num_regs; i++, j++) {
728  reg_arch_info[i].num = arm_vfp_v3_regs[j].id;
729  reg_arch_info[i].mode = arm_vfp_v3_regs[j].mode;
730  reg_arch_info[i].target = target;
731  reg_arch_info[i].arm = arm;
732 
733  reg_list[i].name = arm_vfp_v3_regs[j].name;
734  reg_list[i].number = arm_vfp_v3_regs[j].id;
735  reg_list[i].size = arm_vfp_v3_regs[j].bits;
736  reg_list[i].value = reg_arch_info[i].value;
737  reg_list[i].type = &arm_reg_type;
738  reg_list[i].arch_info = &reg_arch_info[i];
739  reg_list[i].exist = true;
740 
741  reg_list[i].caller_save = false;
742 
743  reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
744  reg_list[i].reg_data_type->type = arm_vfp_v3_regs[j].type;
745 
746  reg_list[i].feature = malloc(sizeof(struct reg_feature));
747  reg_list[i].feature->name = arm_vfp_v3_regs[j].feature;
748 
749  reg_list[i].group = arm_vfp_v3_regs[j].group;
750 
751  cache->num_regs++;
752  }
753 
754  arm->pc = reg_list + 15;
755  arm->cpsr = reg_list + ARMV4_5_CPSR;
756  arm->core_cache = cache;
757 
758  return cache;
759 }
760 
762 {
763  if (!arm || !arm->core_cache)
764  return;
765 
766  struct reg_cache *cache = arm->core_cache;
767 
768  for (unsigned int i = 0; i < cache->num_regs; i++) {
769  struct reg *reg = &cache->reg_list[i];
770 
771  free(reg->feature);
772  free(reg->reg_data_type);
773  }
774 
775  free(cache->reg_list[0].arch_info);
776  free(cache->reg_list);
777  free(cache);
778 
779  arm->core_cache = NULL;
780 }
781 
783 {
784  struct arm *arm = target_to_arm(target);
785 
787  LOG_ERROR("BUG: called for a non-ARM target");
788  return ERROR_FAIL;
789  }
790 
791  /* avoid filling log waiting for fileio reply */
793  return ERROR_OK;
794 
795  LOG_USER("target halted in %s state due to %s, current mode: %s\n"
796  "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s%s",
800  buf_get_u32(arm->cpsr->value, 0, 32),
801  buf_get_u32(arm->pc->value, 0, 32),
802  (target->semihosting && target->semihosting->is_active) ? ", semihosting" : "",
803  (target->semihosting && target->semihosting->is_fileio) ? " fileio" : "");
804 
805  return ERROR_OK;
806 }
807 
808 COMMAND_HANDLER(handle_armv4_5_reg_command)
809 {
811  struct arm *arm = target_to_arm(target);
812  struct reg *regs;
813 
814  if (!is_arm(arm)) {
815  command_print(CMD, "current target isn't an ARM");
816  return ERROR_FAIL;
817  }
818 
819  if (target->state != TARGET_HALTED) {
820  command_print(CMD, "error: target must be halted for register accesses");
821  return ERROR_FAIL;
822  }
823 
824  if (arm->core_type != ARM_CORE_TYPE_STD) {
826  "Microcontroller Profile not supported - use standard reg cmd");
827  return ERROR_OK;
828  }
829 
830  if (!is_arm_mode(arm->core_mode)) {
831  LOG_ERROR("not a valid arm core mode - communication failure?");
832  return ERROR_FAIL;
833  }
834 
835  if (!arm->full_context) {
836  command_print(CMD, "error: target doesn't support %s",
837  CMD_NAME);
838  return ERROR_FAIL;
839  }
840 
842 
843  for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
844  const char *name;
845  char *sep = "\n";
846  char *shadow = "";
847 
849  continue;
850 
851  /* label this bank of registers (or shadows) */
852  switch (arm_mode_data[mode].psr) {
853  case ARM_MODE_SYS:
854  continue;
855  case ARM_MODE_USR:
856  name = "System and User";
857  sep = "";
858  break;
859  case ARM_MODE_HYP:
861  continue;
862  /* FALLTHROUGH */
863  case ARM_MODE_MON:
864  case ARM_MODE_1176_MON:
867  continue;
868  /* FALLTHROUGH */
869  default:
870  name = arm_mode_data[mode].name;
871  shadow = "shadow ";
872  break;
873  }
874  command_print(CMD, "%s%s mode %sregisters",
875  sep, name, shadow);
876 
877  /* display N rows of up to 4 registers each */
878  for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
879  char output[80];
880  int output_len = 0;
881 
882  for (unsigned j = 0; j < 4; j++, i++) {
883  uint32_t value;
884  struct reg *reg = regs;
885 
886  if (i >= arm_mode_data[mode].n_indices)
887  break;
888 
889  reg += arm_mode_data[mode].indices[i];
890 
891  /* REVISIT be smarter about faults... */
892  if (!reg->valid)
894 
895  value = buf_get_u32(reg->value, 0, 32);
896  output_len += snprintf(output + output_len,
897  sizeof(output) - output_len,
898  "%8s: %8.8" PRIx32 " ",
899  reg->name, value);
900  }
901  command_print(CMD, "%s", output);
902  }
903  }
904 
905  return ERROR_OK;
906 }
907 
908 COMMAND_HANDLER(handle_arm_core_state_command)
909 {
911  struct arm *arm = target_to_arm(target);
912  int ret = ERROR_OK;
913 
914  if (!is_arm(arm)) {
915  command_print(CMD, "current target isn't an ARM");
916  return ERROR_FAIL;
917  }
918 
919  if (CMD_ARGC > 0) {
920  if (strcmp(CMD_ARGV[0], "arm") == 0) {
922  command_print(CMD, "arm mode not supported on Cortex-M");
923  ret = ERROR_FAIL;
924  } else {
926  }
927  }
928  if (strcmp(CMD_ARGV[0], "thumb") == 0)
930  }
931 
932  command_print(CMD, "core state: %s", arm_state_strings[arm->core_state]);
933 
934  return ret;
935 }
936 
937 COMMAND_HANDLER(handle_arm_disassemble_command)
938 {
939 #if HAVE_CAPSTONE
941 
942  if (!target) {
943  LOG_ERROR("No target selected");
944  return ERROR_FAIL;
945  }
946 
947  struct arm *arm = target_to_arm(target);
948  target_addr_t address;
949  unsigned int count = 1;
950  bool thumb = false;
951 
952  if (!is_arm(arm)) {
953  command_print(CMD, "current target isn't an ARM");
954  return ERROR_FAIL;
955  }
956 
958  /* armv7m is always thumb mode */
959  thumb = true;
960  }
961 
962  switch (CMD_ARGC) {
963  case 3:
964  if (strcmp(CMD_ARGV[2], "thumb") != 0)
966  thumb = true;
967  /* FALL THROUGH */
968  case 2:
970  /* FALL THROUGH */
971  case 1:
972  COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
973  if (address & 0x01) {
974  if (!thumb) {
975  command_print(CMD, "Disassemble as Thumb");
976  thumb = true;
977  }
978  address &= ~1;
979  }
980  break;
981  default:
983  }
984 
985  return arm_disassemble(CMD, target, address, count, thumb);
986 #else
987  command_print(CMD, "capstone disassembly framework required");
988  return ERROR_FAIL;
989 #endif
990 }
991 
992 static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
993 {
994  struct command_context *context;
995  struct target *target;
996  struct arm *arm;
997  int retval;
998 
999  context = current_command_context(interp);
1000  assert(context);
1001 
1002  target = get_current_target(context);
1003  if (!target) {
1004  LOG_ERROR("%s: no current target", __func__);
1005  return JIM_ERR;
1006  }
1007  if (!target_was_examined(target)) {
1008  LOG_ERROR("%s: not yet examined", target_name(target));
1009  return JIM_ERR;
1010  }
1012  if (!is_arm(arm)) {
1013  LOG_ERROR("%s: not an ARM", target_name(target));
1014  return JIM_ERR;
1015  }
1016 
1017  if ((argc < 6) || (argc > 7)) {
1018  /* FIXME use the command name to verify # params... */
1019  LOG_ERROR("%s: wrong number of arguments", __func__);
1020  return JIM_ERR;
1021  }
1022 
1023  int cpnum;
1024  uint32_t op1;
1025  uint32_t op2;
1026  uint32_t crn;
1027  uint32_t crm;
1028  uint32_t value;
1029  long l;
1030 
1031  /* NOTE: parameter sequence matches ARM instruction set usage:
1032  * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
1033  * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
1034  * The "rX" is necessarily omitted; it uses Tcl mechanisms.
1035  */
1036  retval = Jim_GetLong(interp, argv[1], &l);
1037  if (retval != JIM_OK)
1038  return retval;
1039  if (l & ~0xf) {
1040  LOG_ERROR("%s: %s %d out of range", __func__,
1041  "coprocessor", (int) l);
1042  return JIM_ERR;
1043  }
1044  cpnum = l;
1045 
1046  retval = Jim_GetLong(interp, argv[2], &l);
1047  if (retval != JIM_OK)
1048  return retval;
1049  if (l & ~0x7) {
1050  LOG_ERROR("%s: %s %d out of range", __func__,
1051  "op1", (int) l);
1052  return JIM_ERR;
1053  }
1054  op1 = l;
1055 
1056  retval = Jim_GetLong(interp, argv[3], &l);
1057  if (retval != JIM_OK)
1058  return retval;
1059  if (l & ~0xf) {
1060  LOG_ERROR("%s: %s %d out of range", __func__,
1061  "CRn", (int) l);
1062  return JIM_ERR;
1063  }
1064  crn = l;
1065 
1066  retval = Jim_GetLong(interp, argv[4], &l);
1067  if (retval != JIM_OK)
1068  return retval;
1069  if (l & ~0xf) {
1070  LOG_ERROR("%s: %s %d out of range", __func__,
1071  "CRm", (int) l);
1072  return JIM_ERR;
1073  }
1074  crm = l;
1075 
1076  retval = Jim_GetLong(interp, argv[5], &l);
1077  if (retval != JIM_OK)
1078  return retval;
1079  if (l & ~0x7) {
1080  LOG_ERROR("%s: %s %d out of range", __func__,
1081  "op2", (int) l);
1082  return JIM_ERR;
1083  }
1084  op2 = l;
1085 
1086  value = 0;
1087 
1088  /* FIXME don't assume "mrc" vs "mcr" from the number of params;
1089  * that could easily be a typo! Check both...
1090  *
1091  * FIXME change the call syntax here ... simplest to just pass
1092  * the MRC() or MCR() instruction to be executed. That will also
1093  * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
1094  * if that's ever needed.
1095  */
1096  if (argc == 7) {
1097  retval = Jim_GetLong(interp, argv[6], &l);
1098  if (retval != JIM_OK)
1099  return retval;
1100  value = l;
1101 
1102  /* NOTE: parameters reordered! */
1103  /* ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2) */
1104  retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value);
1105  if (retval != ERROR_OK)
1106  return JIM_ERR;
1107  } else {
1108  /* NOTE: parameters reordered! */
1109  /* ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2) */
1110  retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value);
1111  if (retval != ERROR_OK)
1112  return JIM_ERR;
1113 
1114  Jim_SetResult(interp, Jim_NewIntObj(interp, value));
1115  }
1116 
1117  return JIM_OK;
1118 }
1119 
1120 static const struct command_registration arm_exec_command_handlers[] = {
1121  {
1122  .name = "reg",
1123  .handler = handle_armv4_5_reg_command,
1124  .mode = COMMAND_EXEC,
1125  .help = "display ARM core registers",
1126  .usage = "",
1127  },
1128  {
1129  .name = "mcr",
1130  .mode = COMMAND_EXEC,
1131  .jim_handler = &jim_mcrmrc,
1132  .help = "write coprocessor register",
1133  .usage = "cpnum op1 CRn CRm op2 value",
1134  },
1135  {
1136  .name = "mrc",
1137  .mode = COMMAND_EXEC,
1138  .jim_handler = &jim_mcrmrc,
1139  .help = "read coprocessor register",
1140  .usage = "cpnum op1 CRn CRm op2",
1141  },
1142  {
1144  },
1146 };
1147 
1149  {
1150  .name = "core_state",
1151  .handler = handle_arm_core_state_command,
1152  .mode = COMMAND_EXEC,
1153  .usage = "['arm'|'thumb']",
1154  .help = "display/change ARM core state",
1155  },
1156  {
1157  .name = "disassemble",
1158  .handler = handle_arm_disassemble_command,
1159  .mode = COMMAND_EXEC,
1160  .usage = "address [count ['thumb']]",
1161  .help = "disassemble instructions",
1162  },
1163  {
1164  .chain = semihosting_common_handlers,
1165  },
1167 };
1168 
1169 const struct command_registration arm_command_handlers[] = {
1170  {
1171  .name = "arm",
1172  .mode = COMMAND_ANY,
1173  .help = "ARM command group",
1174  .usage = "",
1175  .chain = arm_exec_command_handlers,
1176  },
1178 };
1179 
1180 /*
1181  * gdb for arm targets (e.g. arm-none-eabi-gdb) supports several variants
1182  * of arm architecture. You can list them using the autocompletion of gdb
1183  * command prompt by typing "set architecture " and then press TAB key.
1184  * The default, selected automatically, is "arm".
1185  * Let's use the default value, here, to make gdb-multiarch behave in the
1186  * same way as a gdb for arm. This can be changed later on. User can still
1187  * set the specific architecture variant with the gdb command.
1188  */
1189 const char *arm_get_gdb_arch(struct target *target)
1190 {
1191  return "arm";
1192 }
1193 
1195  struct reg **reg_list[], int *reg_list_size,
1196  enum target_register_class reg_class)
1197 {
1198  struct arm *arm = target_to_arm(target);
1199  unsigned int i;
1200 
1201  if (!is_arm_mode(arm->core_mode)) {
1202  LOG_ERROR("not a valid arm core mode - communication failure?");
1203  return ERROR_FAIL;
1204  }
1205 
1206  switch (reg_class) {
1207  case REG_CLASS_GENERAL:
1208  *reg_list_size = 26;
1209  *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1210 
1211  for (i = 0; i < 16; i++)
1212  (*reg_list)[i] = arm_reg_current(arm, i);
1213 
1214  /* For GDB compatibility, take FPA registers size into account and zero-fill it*/
1215  for (i = 16; i < 24; i++)
1216  (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1217  (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1218 
1219  (*reg_list)[25] = arm->cpsr;
1220 
1221  return ERROR_OK;
1222 
1223  case REG_CLASS_ALL:
1224  switch (arm->core_type) {
1225  case ARM_CORE_TYPE_SEC_EXT:
1226  *reg_list_size = 51;
1227  break;
1229  *reg_list_size = 53;
1230  break;
1231  default:
1232  *reg_list_size = 48;
1233  }
1234  unsigned int list_size_core = *reg_list_size;
1235  if (arm->arm_vfp_version == ARM_VFP_V3)
1236  *reg_list_size += 33;
1237 
1238  *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1239 
1240  for (i = 0; i < 16; i++)
1241  (*reg_list)[i] = arm_reg_current(arm, i);
1242 
1243  for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
1244  int reg_index = arm->core_cache->reg_list[i].number;
1245 
1246  if (arm_core_regs[i].mode == ARM_MODE_MON
1249  continue;
1250  if (arm_core_regs[i].mode == ARM_MODE_HYP
1252  continue;
1253  (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
1254  }
1255 
1256  /* When we supply the target description, there is no need for fake FPA */
1257  for (i = 16; i < 24; i++) {
1258  (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1259  (*reg_list)[i]->size = 0;
1260  }
1261  (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1262  (*reg_list)[24]->size = 0;
1263 
1264  if (arm->arm_vfp_version == ARM_VFP_V3) {
1265  unsigned int num_core_regs = ARRAY_SIZE(arm_core_regs);
1266  for (i = 0; i < 33; i++)
1267  (*reg_list)[list_size_core + i] = &(arm->core_cache->reg_list[num_core_regs + i]);
1268  }
1269 
1270  return ERROR_OK;
1271 
1272  default:
1273  LOG_ERROR("not a valid register class type in query.");
1274  return ERROR_FAIL;
1275  }
1276 }
1277 
1278 /* wait for execution to complete and check exit point */
1280  uint32_t exit_point,
1281  int timeout_ms,
1282  void *arch_info)
1283 {
1284  int retval;
1285  struct arm *arm = target_to_arm(target);
1286 
1287  retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
1288  if (retval != ERROR_OK)
1289  return retval;
1290  if (target->state != TARGET_HALTED) {
1291  retval = target_halt(target);
1292  if (retval != ERROR_OK)
1293  return retval;
1294  retval = target_wait_state(target, TARGET_HALTED, 500);
1295  if (retval != ERROR_OK)
1296  return retval;
1297  return ERROR_TARGET_TIMEOUT;
1298  }
1299 
1300  /* fast exit: ARMv5+ code can use BKPT */
1301  if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
1302  LOG_WARNING(
1303  "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1304  buf_get_u32(arm->pc->value, 0, 32));
1305  return ERROR_TARGET_TIMEOUT;
1306  }
1307 
1308  return ERROR_OK;
1309 }
1310 
1312  int num_mem_params, struct mem_param *mem_params,
1313  int num_reg_params, struct reg_param *reg_params,
1314  uint32_t entry_point, uint32_t exit_point,
1315  int timeout_ms, void *arch_info,
1316  int (*run_it)(struct target *target, uint32_t exit_point,
1317  int timeout_ms, void *arch_info))
1318 {
1319  struct arm *arm = target_to_arm(target);
1320  struct arm_algorithm *arm_algorithm_info = arch_info;
1322  uint32_t context[17];
1323  uint32_t cpsr;
1324  int exit_breakpoint_size = 0;
1325  int i;
1326  int retval = ERROR_OK;
1327 
1328  LOG_DEBUG("Running algorithm");
1329 
1330  if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
1331  LOG_ERROR("current target isn't an ARMV4/5 target");
1332  return ERROR_TARGET_INVALID;
1333  }
1334 
1335  if (target->state != TARGET_HALTED) {
1336  LOG_WARNING("target not halted");
1337  return ERROR_TARGET_NOT_HALTED;
1338  }
1339 
1340  if (!is_arm_mode(arm->core_mode)) {
1341  LOG_ERROR("not a valid arm core mode - communication failure?");
1342  return ERROR_FAIL;
1343  }
1344 
1345  /* armv5 and later can terminate with BKPT instruction; less overhead */
1346  if (!exit_point && arm->arch == ARM_ARCH_V4) {
1347  LOG_ERROR("ARMv4 target needs HW breakpoint location");
1348  return ERROR_FAIL;
1349  }
1350 
1351  /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
1352  * they'll be restored later.
1353  */
1354  for (i = 0; i <= 16; i++) {
1355  struct reg *r;
1356 
1358  arm_algorithm_info->core_mode, i);
1359  if (!r->valid)
1360  arm->read_core_reg(target, r, i,
1361  arm_algorithm_info->core_mode);
1362  context[i] = buf_get_u32(r->value, 0, 32);
1363  }
1364  cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
1365 
1366  for (i = 0; i < num_mem_params; i++) {
1367  if (mem_params[i].direction == PARAM_IN)
1368  continue;
1369  retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
1370  mem_params[i].value);
1371  if (retval != ERROR_OK)
1372  return retval;
1373  }
1374 
1375  for (i = 0; i < num_reg_params; i++) {
1376  if (reg_params[i].direction == PARAM_IN)
1377  continue;
1378 
1379  struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, false);
1380  if (!reg) {
1381  LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1383  }
1384 
1385  if (reg->size != reg_params[i].size) {
1386  LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1387  reg_params[i].reg_name);
1389  }
1390 
1391  retval = armv4_5_set_core_reg(reg, reg_params[i].value);
1392  if (retval != ERROR_OK)
1393  return retval;
1394  }
1395 
1396  arm->core_state = arm_algorithm_info->core_state;
1397  if (arm->core_state == ARM_STATE_ARM)
1398  exit_breakpoint_size = 4;
1399  else if (arm->core_state == ARM_STATE_THUMB)
1400  exit_breakpoint_size = 2;
1401  else {
1402  LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1404  }
1405 
1406  if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
1407  LOG_DEBUG("setting core_mode: 0x%2.2x",
1408  arm_algorithm_info->core_mode);
1409  buf_set_u32(arm->cpsr->value, 0, 5,
1410  arm_algorithm_info->core_mode);
1411  arm->cpsr->dirty = true;
1412  arm->cpsr->valid = true;
1413  }
1414 
1415  /* terminate using a hardware or (ARMv5+) software breakpoint */
1416  if (exit_point) {
1417  retval = breakpoint_add(target, exit_point,
1418  exit_breakpoint_size, BKPT_HARD);
1419  if (retval != ERROR_OK) {
1420  LOG_ERROR("can't add HW breakpoint to terminate algorithm");
1421  return ERROR_TARGET_FAILURE;
1422  }
1423  }
1424 
1425  retval = target_resume(target, 0, entry_point, 1, 1);
1426  if (retval != ERROR_OK)
1427  return retval;
1428  retval = run_it(target, exit_point, timeout_ms, arch_info);
1429 
1430  if (exit_point)
1431  breakpoint_remove(target, exit_point);
1432 
1433  if (retval != ERROR_OK)
1434  return retval;
1435 
1436  for (i = 0; i < num_mem_params; i++) {
1437  if (mem_params[i].direction != PARAM_OUT) {
1438  int retvaltemp = target_read_buffer(target, mem_params[i].address,
1439  mem_params[i].size,
1440  mem_params[i].value);
1441  if (retvaltemp != ERROR_OK)
1442  retval = retvaltemp;
1443  }
1444  }
1445 
1446  for (i = 0; i < num_reg_params; i++) {
1447  if (reg_params[i].direction != PARAM_OUT) {
1448 
1450  reg_params[i].reg_name,
1451  false);
1452  if (!reg) {
1453  LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1454  retval = ERROR_COMMAND_SYNTAX_ERROR;
1455  continue;
1456  }
1457 
1458  if (reg->size != reg_params[i].size) {
1459  LOG_ERROR(
1460  "BUG: register '%s' size doesn't match reg_params[i].size",
1461  reg_params[i].reg_name);
1462  retval = ERROR_COMMAND_SYNTAX_ERROR;
1463  continue;
1464  }
1465 
1466  buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1467  }
1468  }
1469 
1470  /* restore everything we saved before (17 or 18 registers) */
1471  for (i = 0; i <= 16; i++) {
1472  uint32_t regvalue;
1474  arm_algorithm_info->core_mode, i).value, 0, 32);
1475  if (regvalue != context[i]) {
1476  LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1478  arm_algorithm_info->core_mode, i).name, context[i]);
1480  arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
1481  ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1482  i).valid = true;
1483  ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1484  i).dirty = true;
1485  }
1486  }
1487 
1488  arm_set_cpsr(arm, cpsr);
1489  arm->cpsr->dirty = true;
1490 
1491  arm->core_state = core_state;
1492 
1493  return retval;
1494 }
1495 
1497  int num_mem_params,
1498  struct mem_param *mem_params,
1499  int num_reg_params,
1500  struct reg_param *reg_params,
1501  target_addr_t entry_point,
1502  target_addr_t exit_point,
1503  int timeout_ms,
1504  void *arch_info)
1505 {
1507  num_mem_params,
1508  mem_params,
1509  num_reg_params,
1510  reg_params,
1511  (uint32_t)entry_point,
1512  (uint32_t)exit_point,
1513  timeout_ms,
1514  arch_info,
1516 }
1517 
1523  target_addr_t address, uint32_t count, uint32_t *checksum)
1524 {
1525  struct working_area *crc_algorithm;
1526  struct arm_algorithm arm_algo;
1527  struct arm *arm = target_to_arm(target);
1528  struct reg_param reg_params[2];
1529  int retval;
1530  uint32_t i;
1531  uint32_t exit_var = 0;
1532 
1533  static const uint8_t arm_crc_code_le[] = {
1534 #include "../../contrib/loaders/checksum/armv4_5_crc.inc"
1535  };
1536 
1537  assert(sizeof(arm_crc_code_le) % 4 == 0);
1538 
1540  sizeof(arm_crc_code_le), &crc_algorithm);
1541  if (retval != ERROR_OK)
1542  return retval;
1543 
1544  /* convert code into a buffer in target endianness */
1545  for (i = 0; i < ARRAY_SIZE(arm_crc_code_le) / 4; i++) {
1546  retval = target_write_u32(target,
1547  crc_algorithm->address + i * sizeof(uint32_t),
1548  le_to_h_u32(&arm_crc_code_le[i * 4]));
1549  if (retval != ERROR_OK)
1550  goto cleanup;
1551  }
1552 
1553  arm_algo.common_magic = ARM_COMMON_MAGIC;
1554  arm_algo.core_mode = ARM_MODE_SVC;
1555  arm_algo.core_state = ARM_STATE_ARM;
1556 
1557  init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
1558  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1559 
1560  buf_set_u32(reg_params[0].value, 0, 32, address);
1561  buf_set_u32(reg_params[1].value, 0, 32, count);
1562 
1563  /* 20 second timeout/megabyte */
1564  int timeout = 20000 * (1 + (count / (1024 * 1024)));
1565 
1566  /* armv4 must exit using a hardware breakpoint */
1567  if (arm->arch == ARM_ARCH_V4)
1568  exit_var = crc_algorithm->address + sizeof(arm_crc_code_le) - 8;
1569 
1570  retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
1571  crc_algorithm->address,
1572  exit_var,
1573  timeout, &arm_algo);
1574 
1575  if (retval == ERROR_OK)
1576  *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1577  else
1578  LOG_ERROR("error executing ARM crc algorithm");
1579 
1580  destroy_reg_param(&reg_params[0]);
1581  destroy_reg_param(&reg_params[1]);
1582 
1583 cleanup:
1584  target_free_working_area(target, crc_algorithm);
1585 
1586  return retval;
1587 }
1588 
1596  struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
1597 {
1598  struct working_area *check_algorithm;
1599  struct reg_param reg_params[3];
1600  struct arm_algorithm arm_algo;
1601  struct arm *arm = target_to_arm(target);
1602  int retval;
1603  uint32_t i;
1604  uint32_t exit_var = 0;
1605 
1606  static const uint8_t check_code_le[] = {
1607 #include "../../contrib/loaders/erase_check/armv4_5_erase_check.inc"
1608  };
1609 
1610  assert(sizeof(check_code_le) % 4 == 0);
1611 
1612  if (erased_value != 0xff) {
1613  LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
1614  erased_value);
1615  return ERROR_FAIL;
1616  }
1617 
1618  /* make sure we have a working area */
1620  sizeof(check_code_le), &check_algorithm);
1621  if (retval != ERROR_OK)
1622  return retval;
1623 
1624  /* convert code into a buffer in target endianness */
1625  for (i = 0; i < ARRAY_SIZE(check_code_le) / 4; i++) {
1626  retval = target_write_u32(target,
1627  check_algorithm->address
1628  + i * sizeof(uint32_t),
1629  le_to_h_u32(&check_code_le[i * 4]));
1630  if (retval != ERROR_OK)
1631  goto cleanup;
1632  }
1633 
1634  arm_algo.common_magic = ARM_COMMON_MAGIC;
1635  arm_algo.core_mode = ARM_MODE_SVC;
1636  arm_algo.core_state = ARM_STATE_ARM;
1637 
1638  init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1639  buf_set_u32(reg_params[0].value, 0, 32, blocks[0].address);
1640 
1641  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1642  buf_set_u32(reg_params[1].value, 0, 32, blocks[0].size);
1643 
1644  init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
1645  buf_set_u32(reg_params[2].value, 0, 32, erased_value);
1646 
1647  /* armv4 must exit using a hardware breakpoint */
1648  if (arm->arch == ARM_ARCH_V4)
1649  exit_var = check_algorithm->address + sizeof(check_code_le) - 4;
1650 
1651  retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
1652  check_algorithm->address,
1653  exit_var,
1654  10000, &arm_algo);
1655 
1656  if (retval == ERROR_OK)
1657  blocks[0].result = buf_get_u32(reg_params[2].value, 0, 32);
1658 
1659  destroy_reg_param(&reg_params[0]);
1660  destroy_reg_param(&reg_params[1]);
1661  destroy_reg_param(&reg_params[2]);
1662 
1663 cleanup:
1664  target_free_working_area(target, check_algorithm);
1665 
1666  if (retval != ERROR_OK)
1667  return retval;
1668 
1669  return 1; /* only one block has been checked */
1670 }
1671 
1672 static int arm_full_context(struct target *target)
1673 {
1674  struct arm *arm = target_to_arm(target);
1675  unsigned num_regs = arm->core_cache->num_regs;
1676  struct reg *reg = arm->core_cache->reg_list;
1677  int retval = ERROR_OK;
1678 
1679  for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
1680  if (!reg->exist || reg->valid)
1681  continue;
1682  retval = armv4_5_get_core_reg(reg);
1683  }
1684  return retval;
1685 }
1686 
1687 static int arm_default_mrc(struct target *target, int cpnum,
1688  uint32_t op1, uint32_t op2,
1689  uint32_t crn, uint32_t crm,
1690  uint32_t *value)
1691 {
1692  LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
1693  return ERROR_FAIL;
1694 }
1695 
1696 static int arm_default_mcr(struct target *target, int cpnum,
1697  uint32_t op1, uint32_t op2,
1698  uint32_t crn, uint32_t crm,
1699  uint32_t value)
1700 {
1701  LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
1702  return ERROR_FAIL;
1703 }
1704 
1705 int arm_init_arch_info(struct target *target, struct arm *arm)
1706 {
1707  target->arch_info = arm;
1708  arm->target = target;
1709 
1711 
1712  /* core_type may be overridden by subtype logic */
1716  }
1717 
1718  /* default full_context() has no core-specific optimizations */
1719  if (!arm->full_context && arm->read_core_reg)
1721 
1722  if (!arm->mrc)
1723  arm->mrc = arm_default_mrc;
1724  if (!arm->mcr)
1725  arm->mcr = arm_default_mcr;
1726 
1727  return ERROR_OK;
1728 }
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
Definition: algorithm.c:29
void destroy_reg_param(struct reg_param *param)
Definition: algorithm.c:37
@ PARAM_OUT
Definition: algorithm.h:16
@ PARAM_IN
Definition: algorithm.h:15
@ PARAM_IN_OUT
Definition: algorithm.h:17
Holds the interface to ARM cores.
@ ARM_VFP_V3
Definition: arm.h:155
#define ARM_COMMON_MAGIC
Definition: arm.h:158
@ ARM_ARCH_V4
Definition: arm.h:55
static bool is_arm(struct arm *arm)
Definition: arm.h:249
arm_mode
Represent state of an ARM core.
Definition: arm.h:74
@ ARM_MODE_IRQ
Definition: arm.h:77
@ ARM_MODE_HANDLER
Definition: arm.h:88
@ ARM_MODE_SYS
Definition: arm.h:84
@ ARM_MODE_HYP
Definition: arm.h:81
@ ARM_MODE_MON
Definition: arm.h:79
@ ARM_MODE_FIQ
Definition: arm.h:76
@ ARM_MODE_UND
Definition: arm.h:82
@ ARM_MODE_1176_MON
Definition: arm.h:83
@ ARM_MODE_ANY
Definition: arm.h:98
@ ARM_MODE_USR
Definition: arm.h:75
@ ARM_MODE_SVC
Definition: arm.h:78
@ ARM_MODE_USER_THREAD
Definition: arm.h:87
@ ARM_MODE_ABT
Definition: arm.h:80
@ ARM_MODE_THREAD
Definition: arm.h:86
arm_state
The PSR "T" and "J" bits define the mode of "classic ARM" cores.
Definition: arm.h:142
@ ARM_STATE_JAZELLE
Definition: arm.h:145
@ ARM_STATE_THUMB
Definition: arm.h:144
@ ARM_STATE_ARM
Definition: arm.h:143
@ ARM_STATE_THUMB_EE
Definition: arm.h:146
@ ARM_VFP_V3_D14
Definition: arm.h:117
@ ARM_VFP_V3_D24
Definition: arm.h:127
@ ARM_VFP_V3_D9
Definition: arm.h:112
@ ARM_VFP_V3_D1
Definition: arm.h:104
@ ARM_VFP_V3_D17
Definition: arm.h:120
@ ARM_VFP_V3_D19
Definition: arm.h:122
@ ARM_VFP_V3_D4
Definition: arm.h:107
@ ARM_VFP_V3_D15
Definition: arm.h:118
@ ARM_VFP_V3_D10
Definition: arm.h:113
@ ARM_VFP_V3_D3
Definition: arm.h:106
@ ARM_VFP_V3_D31
Definition: arm.h:134
@ ARM_VFP_V3_D16
Definition: arm.h:119
@ ARM_VFP_V3_D22
Definition: arm.h:125
@ ARM_VFP_V3_D5
Definition: arm.h:108
@ ARM_VFP_V3_D18
Definition: arm.h:121
@ ARM_VFP_V3_D26
Definition: arm.h:129
@ ARM_VFP_V3_D7
Definition: arm.h:110
@ ARM_VFP_V3_D23
Definition: arm.h:126
@ ARM_VFP_V3_D21
Definition: arm.h:124
@ ARM_VFP_V3_D28
Definition: arm.h:131
@ ARM_VFP_V3_D2
Definition: arm.h:105
@ ARM_VFP_V3_D27
Definition: arm.h:130
@ ARM_VFP_V3_D29
Definition: arm.h:132
@ ARM_VFP_V3_D11
Definition: arm.h:114
@ ARM_VFP_V3_FPSCR
Definition: arm.h:135
@ ARM_VFP_V3_D20
Definition: arm.h:123
@ ARM_VFP_V3_D13
Definition: arm.h:116
@ ARM_VFP_V3_D12
Definition: arm.h:115
@ ARM_VFP_V3_D6
Definition: arm.h:109
@ ARM_VFP_V3_D8
Definition: arm.h:111
@ ARM_VFP_V3_D0
Definition: arm.h:103
@ ARM_VFP_V3_D30
Definition: arm.h:133
@ ARM_VFP_V3_D25
Definition: arm.h:128
static struct arm * target_to_arm(struct target *target)
Convert target handle to generic ARM target state handle.
Definition: arm.h:243
@ ARM_CORE_TYPE_SEC_EXT
Definition: arm.h:47
@ ARM_CORE_TYPE_VIRT_EXT
Definition: arm.h:48
@ ARM_CORE_TYPE_M_PROFILE
Definition: arm.h:49
@ ARM_CORE_TYPE_STD
Definition: arm.h:46
int arm_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Runs ARM code in the target to check whether a memory block holds all ones.
Definition: armv4_5.c:1595
static const struct reg_arch_type arm_reg_type
Definition: armv4_5.c:641
static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
Definition: armv4_5.c:595
static const uint8_t arm_svc_indices[3]
Definition: armv4_5.c:55
static const uint8_t arm_gdb_dummy_fp_value[12]
Definition: armv4_5.c:526
unsigned cookie
Definition: armv4_5.c:275
static const uint8_t arm_irq_indices[3]
Definition: armv4_5.c:51
const struct command_registration arm_all_profiles_command_handlers[]
Definition: armv4_5.c:1148
const uint8_t * indices
Definition: armv4_5.c:82
int arm_arch_state(struct target *target)
Definition: armv4_5.c:782
enum arm_mode mode
Definition: armv4_5.c:277
int arm_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Runs ARM code in the target to calculate a CRC32 checksum.
Definition: armv4_5.c:1522
static const struct @69 arm_vfp_v3_regs[]
int arm_mode_to_number(enum arm_mode mode)
Map PSR mode bits to linear number indexing armv4_5_core_reg_map.
Definition: armv4_5.c:192
unsigned short n_indices
Definition: armv4_5.c:81
static struct reg arm_gdb_dummy_fp_reg
Dummy FPA registers are required to support GDB on ARM.
Definition: armv4_5.c:538
static const char * arm_state_strings[]
Definition: armv4_5.c:250
COMMAND_HANDLER(handle_armv4_5_reg_command)
Definition: armv4_5.c:808
static const struct @68 arm_core_regs[]
static int arm_full_context(struct target *target)
Definition: armv4_5.c:1672
static const uint8_t arm_abt_indices[3]
Definition: armv4_5.c:59
struct reg_cache * arm_build_reg_cache(struct target *target, struct arm *arm)
Definition: armv4_5.c:646
static const uint8_t arm_hyp_indices[2]
Definition: armv4_5.c:71
const char * group
Definition: armv4_5.c:362
int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: armv4_5.c:1194
const int armv4_5_core_reg_map[9][17]
Definition: armv4_5.c:403
static struct reg arm_gdb_dummy_fps_reg
Dummy FPA status registers are required to support GDB on ARM.
Definition: armv4_5.c:555
static const struct @67 arm_mode_data[]
static const uint8_t arm_fiq_indices[8]
Definition: armv4_5.c:47
static int arm_default_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
Definition: armv4_5.c:1687
static int armv4_5_get_core_reg(struct reg *reg)
Definition: armv4_5.c:574
int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
Definition: armv4_5.c:1496
const char * name
Definition: armv4_5.c:76
void arm_free_reg_cache(struct arm *arm)
Definition: armv4_5.c:761
static const uint8_t arm_usr_indices[17]
Definition: armv4_5.c:43
static struct reg_feature arm_gdb_dummy_fp_features
Definition: armv4_5.c:528
enum reg_type type
Definition: armv4_5.c:361
static const uint8_t arm_mon_indices[3]
Definition: armv4_5.c:67
const char * arm_get_gdb_arch(struct target *target)
Definition: armv4_5.c:1189
unsigned int id
Definition: armv4_5.c:357
bool is_arm_mode(unsigned psr_mode)
Return true iff the parameter denotes a valid ARM processor mode.
Definition: armv4_5.c:182
static const uint8_t arm_und_indices[3]
Definition: armv4_5.c:63
static const struct command_registration arm_exec_command_handlers[]
Definition: armv4_5.c:1120
const struct command_registration arm_command_handlers[]
Definition: armv4_5.c:1169
const char * arm_mode_name(unsigned psr_mode)
Map PSR mode bits to the name of an ARM processor operating mode.
Definition: armv4_5.c:171
static void arm_gdb_dummy_init(void)
Definition: armv4_5.c:566
static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
Definition: armv4_5.c:1279
unsigned short psr
Definition: armv4_5.c:77
enum arm_mode armv4_5_number_to_mode(int number)
Map linear number indexing armv4_5_core_reg_map to PSR mode bits.
Definition: armv4_5.c:223
int arm_init_arch_info(struct target *target, struct arm *arm)
Definition: armv4_5.c:1705
@ ARMV4_5_SPSR_UND
Definition: armv4_5.c:38
@ ARMV4_5_SPSR_ABT
Definition: armv4_5.c:37
@ ARMV4_5_SPSR_IRQ
Definition: armv4_5.c:35
@ ARM_SPSR_MON
Definition: armv4_5.c:39
@ ARMV4_5_SPSR_SVC
Definition: armv4_5.c:36
@ ARM_SPSR_HYP
Definition: armv4_5.c:40
@ ARMV4_5_SPSR_FIQ
Definition: armv4_5.c:34
void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
Configures host-side ARM records to reflect the specified CPSR.
Definition: armv4_5.c:438
int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int(*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info))
Definition: armv4_5.c:1311
const char * feature
Definition: armv4_5.c:363
struct reg * arm_reg_current(struct arm *arm, unsigned regnum)
Returns handle to the register currently mapped to a given number.
Definition: armv4_5.c:502
unsigned gdb_index
Definition: armv4_5.c:276
static int arm_default_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
Definition: armv4_5.c:1696
static const uint8_t arm_gdb_dummy_fps_value[4]
Definition: armv4_5.c:549
static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
Definition: armv4_5.c:992
uint32_t bits
Definition: armv4_5.c:359
#define ARMV4_5_CORE_REG_MODE(cache, mode, num)
Definition: armv4_5.h:32
@ ARMV4_5_CPSR
Definition: armv4_5.h:36
Support functions to access arbitrary bits in a byte array.
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:98
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:30
void breakpoint_remove(struct target *target, target_addr_t address)
Definition: breakpoints.c:329
int breakpoint_add(struct target *target, target_addr_t address, uint32_t length, enum breakpoint_type type)
Definition: breakpoints.c:204
@ BKPT_HARD
Definition: breakpoints.h:18
struct command_context * current_command_context(Jim_Interp *interp)
Definition: command.c:187
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:473
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:140
#define CMD_NAME
Use this macro to access the name of the command being handled, rather than accessing the variable di...
Definition: command.h:160
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:155
#define COMMAND_PARSE_ADDRESS(in, out)
Definition: command.h:435
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:385
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:150
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:425
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:145
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:247
@ COMMAND_ANY
Definition: command.h:42
@ COMMAND_EXEC
Definition: command.h:40
enum esirisc_reg_num number
Definition: esirisc.c:87
struct esp_usb_jtag __attribute__
Definition: armv8.c:804
static uint16_t output
Definition: ftdi.c:118
static uint16_t direction
Definition: ftdi.c:119
static const struct @101 regs[]
#define LOG_USER(expr ...)
Definition: log.h:126
#define LOG_WARNING(expr ...)
Definition: log.h:120
#define ERROR_FAIL
Definition: log.h:161
#define LOG_ERROR(expr ...)
Definition: log.h:123
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:155
void register_init_dummy(struct reg *reg)
Definition: register.c:124
struct reg * register_get_by_name(struct reg_cache *first, const char *name, bool search_all)
Definition: register.c:50
reg_type
Definition: register.h:19
@ REG_TYPE_INT
Definition: register.h:21
@ REG_TYPE_IEEE_DOUBLE
Definition: register.h:37
@ REG_TYPE_UINT32
Definition: register.h:30
@ REG_TYPE_CODE_PTR
Definition: register.h:33
@ REG_TYPE_DATA_PTR
Definition: register.h:34
struct target * target
Definition: rtt/rtt.c:26
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
const struct command_registration semihosting_common_handlers[]
unsigned int common_magic
Definition: arm.h:256
enum arm_mode core_mode
Definition: arm.h:258
enum arm_state core_state
Definition: arm.h:259
Definition: arm.h:262
int num
Definition: arm.h:263
struct arm * arm
Definition: arm.h:266
uint8_t value[16]
Definition: arm.h:267
enum arm_mode mode
Definition: arm.h:264
struct target * target
Definition: arm.h:265
Represents a generic ARM core, with standard application registers.
Definition: arm.h:167
int(* full_context)(struct target *target)
Retrieve all core registers, for display.
Definition: arm.h:213
enum arm_arch arch
ARM architecture version.
Definition: arm.h:194
void * arch_info
Definition: arm.h:233
enum arm_core_type core_type
Indicates what registers are in the ARM state core register set.
Definition: arm.h:185
int(* mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
Read coprocessor register.
Definition: arm.h:222
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
Definition: arm.h:188
struct reg * cpsr
Handle to the CPSR/xPSR; valid in all core modes.
Definition: arm.h:176
struct reg * pc
Handle to the PC; valid in all core modes.
Definition: arm.h:173
int(* write_core_reg)(struct target *target, struct reg *reg, int num, enum arm_mode mode, uint8_t *value)
Definition: arm.h:218
const int * map
Support for arm_reg_current()
Definition: arm.h:182
int(* read_core_reg)(struct target *target, struct reg *reg, int num, enum arm_mode mode)
Retrieve a single core register.
Definition: arm.h:216
struct reg_cache * core_cache
Definition: arm.h:170
int(* mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
Write coprocessor register.
Definition: arm.h:228
struct reg * spsr
Handle to the SPSR; valid only in core modes with an SPSR.
Definition: arm.h:179
unsigned int common_magic
Definition: arm.h:168
int arm_vfp_version
Floating point or VFP version, 0 if disabled.
Definition: arm.h:197
struct target * target
Backpointer to the target.
Definition: arm.h:202
enum arm_state core_state
Record the current core state: ARM, Thumb, or otherwise.
Definition: arm.h:191
const char * name
Definition: command.h:229
int(* get)(struct reg *reg)
Definition: register.h:152
const char * name
Definition: register.h:145
unsigned num_regs
Definition: register.h:148
struct reg * reg_list
Definition: register.h:147
struct reg_cache * next
Definition: register.h:146
enum reg_type type
Definition: register.h:100
const char * name
Definition: register.h:42
uint32_t size
Definition: algorithm.h:29
uint8_t * value
Definition: algorithm.h:30
const char * reg_name
Definition: algorithm.h:28
Definition: register.h:111
bool caller_save
Definition: register.h:119
bool valid
Definition: register.h:126
bool exist
Definition: register.h:128
uint32_t size
Definition: register.h:132
const char * group
Definition: register.h:138
uint8_t * value
Definition: register.h:122
struct reg_feature * feature
Definition: register.h:117
struct reg_data_type * reg_data_type
Definition: register.h:135
uint32_t number
Definition: register.h:115
void * arch_info
Definition: register.h:140
bool dirty
Definition: register.h:124
const struct reg_arch_type * type
Definition: register.h:141
const char * name
Definition: register.h:113
bool hit_fileio
A flag reporting whether semihosting fileio operation is active.
bool is_fileio
A flag reporting whether semihosting fileio is active.
bool is_active
A flag reporting whether semihosting is active.
Definition: target.h:120
struct semihosting * semihosting
Definition: target.h:210
enum target_state state
Definition: target.h:162
void * arch_info
Definition: target.h:169
Definition: psoc6.c:84
target_addr_t address
Definition: target.h:90
int target_halt(struct target *target)
Definition: target.c:585
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2408
int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
Definition: target.c:2473
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2129
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2707
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2187
int target_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
Downloads a target-specific native code algorithm to the target, and executes it.
Definition: target.c:846
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:536
const char * debug_reason_name(struct target *t)
Definition: target.c:289
const char * target_type_name(struct target *target)
Get the target type name.
Definition: target.c:809
int target_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Make the target (re)start executing using its saved execution context (possibly with some modificatio...
Definition: target.c:634
int target_wait_state(struct target *target, enum target_state state, int ms)
Definition: target.c:3270
target_register_class
Definition: target.h:114
@ REG_CLASS_GENERAL
Definition: target.h:116
@ REG_CLASS_ALL
Definition: target.h:115
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:792
#define ERROR_TARGET_INVALID
Definition: target.h:789
@ TARGET_HALTED
Definition: target.h:55
static const char * target_name(struct target *target)
Returns the instance-specific name of the specified target.
Definition: target.h:234
#define ERROR_TARGET_TIMEOUT
Definition: target.h:791
static bool target_was_examined(struct target *target)
Definition: target.h:438
#define ERROR_TARGET_FAILURE
Definition: target.h:793
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57
uint64_t target_addr_t
Definition: types.h:335
static uint32_t le_to_h_u32(const uint8_t *buf)
Definition: types.h:112
#define NULL
Definition: usb.h:16
uint8_t state[4]
Definition: vdebug.c:21
uint8_t count[4]
Definition: vdebug.c:22