44 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
ARMV4_5_CPSR,
100 .name =
"Supervisor",
118 .name =
"Undefined instruction",
134 .name =
"Secure Monitor",
140 .name =
"Secure Monitor ARM1176JZF-S",
153 .name =
"Thread (User)",
163 .name =
"Hypervisor",
177 LOG_ERROR(
"unrecognized psr mode: %#02x", psr_mode);
178 return "UNRECOGNIZED";
251 "ARM",
"Thumb",
"Jazelle",
"ThumbEE",
260 static const struct {
283 [0] = { .name =
"r0", .cookie = 0, .mode =
ARM_MODE_ANY, .gdb_index = 0, },
284 [1] = { .name =
"r1", .cookie = 1, .mode =
ARM_MODE_ANY, .gdb_index = 1, },
285 [2] = { .name =
"r2", .cookie = 2, .mode =
ARM_MODE_ANY, .gdb_index = 2, },
286 [3] = { .name =
"r3", .cookie = 3, .mode =
ARM_MODE_ANY, .gdb_index = 3, },
287 [4] = { .name =
"r4", .cookie = 4, .mode =
ARM_MODE_ANY, .gdb_index = 4, },
288 [5] = { .name =
"r5", .cookie = 5, .mode =
ARM_MODE_ANY, .gdb_index = 5, },
289 [6] = { .name =
"r6", .cookie = 6, .mode =
ARM_MODE_ANY, .gdb_index = 6, },
290 [7] = { .name =
"r7", .cookie = 7, .mode =
ARM_MODE_ANY, .gdb_index = 7, },
296 [8] = { .name =
"r8", .cookie = 8, .mode =
ARM_MODE_ANY, .gdb_index = 8, },
297 [9] = { .name =
"r9", .cookie = 9, .mode =
ARM_MODE_ANY, .gdb_index = 9, },
298 [10] = { .name =
"r10", .cookie = 10, .mode =
ARM_MODE_ANY, .gdb_index = 10, },
299 [11] = { .name =
"r11", .cookie = 11, .mode =
ARM_MODE_ANY, .gdb_index = 11, },
300 [12] = { .name =
"r12", .cookie = 12, .mode =
ARM_MODE_ANY, .gdb_index = 12, },
309 [13] = { .name =
"sp_usr", .cookie = 13, .mode =
ARM_MODE_USR, .gdb_index = 26, },
310 [14] = { .name =
"lr_usr", .cookie = 14, .mode =
ARM_MODE_USR, .gdb_index = 27, },
313 [15] = { .name =
"pc", .cookie = 15, .mode =
ARM_MODE_ANY, .gdb_index = 15, },
314 [16] = { .name =
"r8_fiq", .cookie = 8, .mode =
ARM_MODE_FIQ, .gdb_index = 28, },
315 [17] = { .name =
"r9_fiq", .cookie = 9, .mode =
ARM_MODE_FIQ, .gdb_index = 29, },
316 [18] = { .name =
"r10_fiq", .cookie = 10, .mode =
ARM_MODE_FIQ, .gdb_index = 30, },
317 [19] = { .name =
"r11_fiq", .cookie = 11, .mode =
ARM_MODE_FIQ, .gdb_index = 31, },
318 [20] = { .name =
"r12_fiq", .cookie = 12, .mode =
ARM_MODE_FIQ, .gdb_index = 32, },
320 [21] = { .name =
"sp_fiq", .cookie = 13, .mode =
ARM_MODE_FIQ, .gdb_index = 33, },
321 [22] = { .name =
"lr_fiq", .cookie = 14, .mode =
ARM_MODE_FIQ, .gdb_index = 34, },
323 [23] = { .name =
"sp_irq", .cookie = 13, .mode =
ARM_MODE_IRQ, .gdb_index = 35, },
324 [24] = { .name =
"lr_irq", .cookie = 14, .mode =
ARM_MODE_IRQ, .gdb_index = 36, },
326 [25] = { .name =
"sp_svc", .cookie = 13, .mode =
ARM_MODE_SVC, .gdb_index = 37, },
327 [26] = { .name =
"lr_svc", .cookie = 14, .mode =
ARM_MODE_SVC, .gdb_index = 38, },
329 [27] = { .name =
"sp_abt", .cookie = 13, .mode =
ARM_MODE_ABT, .gdb_index = 39, },
330 [28] = { .name =
"lr_abt", .cookie = 14, .mode =
ARM_MODE_ABT, .gdb_index = 40, },
332 [29] = { .name =
"sp_und", .cookie = 13, .mode =
ARM_MODE_UND, .gdb_index = 41, },
333 [30] = { .name =
"lr_und", .cookie = 14, .mode =
ARM_MODE_UND, .gdb_index = 42, },
335 [31] = { .name =
"cpsr", .cookie = 16, .mode =
ARM_MODE_ANY, .gdb_index = 25, },
336 [32] = { .name =
"spsr_fiq", .cookie = 16, .mode =
ARM_MODE_FIQ, .gdb_index = 43, },
337 [33] = { .name =
"spsr_irq", .cookie = 16, .mode =
ARM_MODE_IRQ, .gdb_index = 44, },
338 [34] = { .name =
"spsr_svc", .cookie = 16, .mode =
ARM_MODE_SVC, .gdb_index = 45, },
339 [35] = { .name =
"spsr_abt", .cookie = 16, .mode =
ARM_MODE_ABT, .gdb_index = 46, },
340 [36] = { .name =
"spsr_und", .cookie = 16, .mode =
ARM_MODE_UND, .gdb_index = 47, },
343 [37] = { .name =
"sp", .cookie = 13, .mode =
ARM_MODE_ANY, .gdb_index = 13, },
344 [38] = { .name =
"lr", .cookie = 14, .mode =
ARM_MODE_ANY, .gdb_index = 14, },
347 [39] = { .name =
"sp_mon", .cookie = 13, .mode =
ARM_MODE_MON, .gdb_index = 48, },
348 [40] = { .name =
"lr_mon", .cookie = 14, .mode =
ARM_MODE_MON, .gdb_index = 49, },
349 [41] = { .name =
"spsr_mon", .cookie = 16, .mode =
ARM_MODE_MON, .gdb_index = 50, },
352 [42] = { .name =
"sp_hyp", .cookie = 13, .mode =
ARM_MODE_HYP, .gdb_index = 51, },
353 [43] = { .name =
"spsr_hyp", .cookie = 16, .mode =
ARM_MODE_HYP, .gdb_index = 52, },
356 static const struct {
405 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
408 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
411 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
414 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
417 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
420 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
423 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
426 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 39, 40, 15, 41,
429 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 42, 14, 15, 43,
470 if (cpsr & (1 << 5)) {
471 if (cpsr & (1 << 24)) {
477 if (cpsr & (1 << 24)) {
478 LOG_ERROR(
"Jazelle state handling is BROKEN!");
485 LOG_DEBUG(
"set CPSR %#8.8x: %s mode, %s state", (
unsigned) cpsr,
510 LOG_ERROR(
"Register map is not available yet, the target is not fully initialised");
529 .
name =
"net.sourceforge.openocd.fake_fpa"
539 .
name =
"GDB dummy FPA register",
556 .
name =
"GDB dummy FPA status register",
586 reg_arch_info->
num, reg_arch_info->
mode);
610 if (
reg == armv4_5_target->
cpsr) {
620 LOG_DEBUG(
"changing ARM core mode to '%s'",
622 value &= ~((1 << 24) | (1 << 5));
654 struct reg *reg_list = calloc(num_regs,
sizeof(
struct reg));
655 struct arm_reg *reg_arch_info = calloc(num_regs,
sizeof(
struct arm_reg));
658 if (!cache || !reg_list || !reg_arch_info) {
665 cache->
name =
"ARM registers";
670 for (i = 0; i < num_core_regs; i++) {
685 reg_arch_info[i].
arm =
arm;
689 reg_list[i].
size = 32;
692 reg_list[i].
arch_info = ®_arch_info[i];
693 reg_list[i].
exist =
true;
715 if (reg_list[i].
number <= 15 || reg_list[i].
number == 25) {
716 reg_list[i].
feature->
name =
"org.gnu.gdb.arm.core";
717 reg_list[i].
group =
"general";
719 reg_list[i].
feature->
name =
"net.sourceforge.openocd.banked";
720 reg_list[i].
group =
"banked";
727 for (i = num_core_regs, j = 0; i < num_regs; i++, j++) {
731 reg_arch_info[i].
arm =
arm;
738 reg_list[i].
arch_info = ®_arch_info[i];
739 reg_list[i].
exist =
true;
754 arm->
pc = reg_list + 15;
768 for (
unsigned int i = 0; i < cache->
num_regs; i++) {
787 LOG_ERROR(
"BUG: called for a non-ARM target");
795 LOG_USER(
"target halted in %s state due to %s, current mode: %s\n"
796 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"%s%s",
826 "Microcontroller Profile not supported - use standard reg cmd");
831 LOG_ERROR(
"not a valid arm core mode - communication failure?");
856 name =
"System and User";
882 for (
unsigned j = 0; j < 4; j++, i++) {
896 output_len += snprintf(
output + output_len,
897 sizeof(
output) - output_len,
898 "%8s: %8.8" PRIx32
" ",
920 if (strcmp(
CMD_ARGV[0],
"arm") == 0) {
928 if (strcmp(
CMD_ARGV[0],
"thumb") == 0)
949 unsigned int count = 1;
964 if (strcmp(
CMD_ARGV[2],
"thumb") != 0)
973 if (address & 0x01) {
992 static int jim_mcrmrc(Jim_Interp *interp,
int argc, Jim_Obj *
const *argv)
1004 LOG_ERROR(
"%s: no current target", __func__);
1017 if ((argc < 6) || (argc > 7)) {
1019 LOG_ERROR(
"%s: wrong number of arguments", __func__);
1036 retval = Jim_GetLong(interp, argv[1], &l);
1037 if (retval != JIM_OK)
1040 LOG_ERROR(
"%s: %s %d out of range", __func__,
1041 "coprocessor", (
int) l);
1046 retval = Jim_GetLong(interp, argv[2], &l);
1047 if (retval != JIM_OK)
1050 LOG_ERROR(
"%s: %s %d out of range", __func__,
1056 retval = Jim_GetLong(interp, argv[3], &l);
1057 if (retval != JIM_OK)
1060 LOG_ERROR(
"%s: %s %d out of range", __func__,
1066 retval = Jim_GetLong(interp, argv[4], &l);
1067 if (retval != JIM_OK)
1070 LOG_ERROR(
"%s: %s %d out of range", __func__,
1076 retval = Jim_GetLong(interp, argv[5], &l);
1077 if (retval != JIM_OK)
1080 LOG_ERROR(
"%s: %s %d out of range", __func__,
1097 retval = Jim_GetLong(interp, argv[6], &l);
1098 if (retval != JIM_OK)
1104 retval =
arm->
mcr(
target, cpnum, op1, op2, crn, crm, value);
1110 retval =
arm->
mrc(
target, cpnum, op1, op2, crn, crm, &value);
1114 Jim_SetResult(interp, Jim_NewIntObj(interp, value));
1123 .handler = handle_armv4_5_reg_command,
1125 .help =
"display ARM core registers",
1132 .help =
"write coprocessor register",
1133 .usage =
"cpnum op1 CRn CRm op2 value",
1139 .help =
"read coprocessor register",
1140 .usage =
"cpnum op1 CRn CRm op2",
1150 .
name =
"core_state",
1151 .handler = handle_arm_core_state_command,
1153 .usage =
"['arm'|'thumb']",
1154 .help =
"display/change ARM core state",
1157 .name =
"disassemble",
1158 .handler = handle_arm_disassemble_command,
1160 .usage =
"address [count ['thumb']]",
1161 .help =
"disassemble instructions",
1173 .help =
"ARM command group",
1195 struct reg **reg_list[],
int *reg_list_size,
1202 LOG_ERROR(
"not a valid arm core mode - communication failure?");
1206 switch (reg_class) {
1208 *reg_list_size = 26;
1209 *reg_list = malloc(
sizeof(
struct reg *) * (*reg_list_size));
1211 for (i = 0; i < 16; i++)
1215 for (i = 16; i < 24; i++)
1226 *reg_list_size = 51;
1229 *reg_list_size = 53;
1232 *reg_list_size = 48;
1234 unsigned int list_size_core = *reg_list_size;
1236 *reg_list_size += 33;
1238 *reg_list = malloc(
sizeof(
struct reg *) * (*reg_list_size));
1240 for (i = 0; i < 16; i++)
1257 for (i = 16; i < 24; i++) {
1259 (*reg_list)[i]->
size = 0;
1262 (*reg_list)[24]->
size = 0;
1266 for (i = 0; i < 33; i++)
1273 LOG_ERROR(
"not a valid register class type in query.");
1280 uint32_t exit_point,
1303 "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32
"",
1312 int num_mem_params,
struct mem_param *mem_params,
1313 int num_reg_params,
struct reg_param *reg_params,
1314 uint32_t entry_point, uint32_t exit_point,
1316 int (*run_it)(
struct target *
target, uint32_t exit_point,
1322 uint32_t context[17];
1324 int exit_breakpoint_size = 0;
1331 LOG_ERROR(
"current target isn't an ARMV4/5 target");
1341 LOG_ERROR(
"not a valid arm core mode - communication failure?");
1347 LOG_ERROR(
"ARMv4 target needs HW breakpoint location");
1354 for (i = 0; i <= 16; i++) {
1366 for (i = 0; i < num_mem_params; i++) {
1370 mem_params[i].
value);
1375 for (i = 0; i < num_reg_params; i++) {
1381 LOG_ERROR(
"BUG: register '%s' not found", reg_params[i].reg_name);
1386 LOG_ERROR(
"BUG: register '%s' size doesn't match reg_params[i].size",
1387 reg_params[i].reg_name);
1398 exit_breakpoint_size = 4;
1400 exit_breakpoint_size = 2;
1402 LOG_ERROR(
"BUG: can't execute algorithms when not in ARM or Thumb state");
1420 LOG_ERROR(
"can't add HW breakpoint to terminate algorithm");
1436 for (i = 0; i < num_mem_params; i++) {
1440 mem_params[i].
value);
1442 retval = retvaltemp;
1446 for (i = 0; i < num_reg_params; i++) {
1453 LOG_ERROR(
"BUG: register '%s' not found", reg_params[i].reg_name);
1460 "BUG: register '%s' size doesn't match reg_params[i].size",
1461 reg_params[i].reg_name);
1471 for (i = 0; i <= 16; i++) {
1474 arm_algorithm_info->
core_mode, i).value, 0, 32);
1475 if (regvalue != context[i]) {
1476 LOG_DEBUG(
"restoring register %s with value 0x%8.8" PRIx32
"",
1478 arm_algorithm_info->
core_mode, i).name, context[i]);
1480 arm_algorithm_info->
core_mode, i).value, 0, 32, context[i]);
1511 (uint32_t)entry_point,
1512 (uint32_t)exit_point,
1531 uint32_t exit_var = 0;
1533 static const uint8_t arm_crc_code_le[] = {
1534 #include "../../contrib/loaders/checksum/armv4_5_crc.inc"
1537 assert(
sizeof(arm_crc_code_le) % 4 == 0);
1540 sizeof(arm_crc_code_le), &crc_algorithm);
1545 for (i = 0; i <
ARRAY_SIZE(arm_crc_code_le) / 4; i++) {
1547 crc_algorithm->
address + i *
sizeof(uint32_t),
1568 exit_var = crc_algorithm->
address +
sizeof(arm_crc_code_le) - 8;
1578 LOG_ERROR(
"error executing ARM crc algorithm");
1604 uint32_t exit_var = 0;
1606 static const uint8_t check_code_le[] = {
1607 #include "../../contrib/loaders/erase_check/armv4_5_erase_check.inc"
1610 assert(
sizeof(check_code_le) % 4 == 0);
1612 if (erased_value != 0xff) {
1613 LOG_ERROR(
"Erase value 0x%02" PRIx8
" not yet supported for ARMv4/v5 targets",
1620 sizeof(check_code_le), &check_algorithm);
1625 for (i = 0; i <
ARRAY_SIZE(check_code_le) / 4; i++) {
1628 + i *
sizeof(uint32_t),
1639 buf_set_u32(reg_params[0].value, 0, 32, blocks[0].address);
1645 buf_set_u32(reg_params[2].value, 0, 32, erased_value);
1649 exit_var = check_algorithm->
address +
sizeof(check_code_le) - 4;
1679 for (; num_regs && retval ==
ERROR_OK; num_regs--,
reg++) {
1688 uint32_t op1, uint32_t op2,
1689 uint32_t crn, uint32_t crm,
1697 uint32_t op1, uint32_t op2,
1698 uint32_t crn, uint32_t crm,
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
void destroy_reg_param(struct reg_param *param)
Holds the interface to ARM cores.
static bool is_arm(struct arm *arm)
arm_mode
Represent state of an ARM core.
arm_state
The PSR "T" and "J" bits define the mode of "classic ARM" cores.
static struct arm * target_to_arm(struct target *target)
Convert target handle to generic ARM target state handle.
@ ARM_CORE_TYPE_M_PROFILE
int arm_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Runs ARM code in the target to check whether a memory block holds all ones.
static const struct reg_arch_type arm_reg_type
static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
static const uint8_t arm_svc_indices[3]
static const uint8_t arm_gdb_dummy_fp_value[12]
static const uint8_t arm_irq_indices[3]
const struct command_registration arm_all_profiles_command_handlers[]
int arm_arch_state(struct target *target)
int arm_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Runs ARM code in the target to calculate a CRC32 checksum.
static const struct @69 arm_vfp_v3_regs[]
int arm_mode_to_number(enum arm_mode mode)
Map PSR mode bits to linear number indexing armv4_5_core_reg_map.
static struct reg arm_gdb_dummy_fp_reg
Dummy FPA registers are required to support GDB on ARM.
static const char * arm_state_strings[]
COMMAND_HANDLER(handle_armv4_5_reg_command)
static const struct @68 arm_core_regs[]
static int arm_full_context(struct target *target)
static const uint8_t arm_abt_indices[3]
struct reg_cache * arm_build_reg_cache(struct target *target, struct arm *arm)
static const uint8_t arm_hyp_indices[2]
int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
const int armv4_5_core_reg_map[9][17]
static struct reg arm_gdb_dummy_fps_reg
Dummy FPA status registers are required to support GDB on ARM.
static const struct @67 arm_mode_data[]
static const uint8_t arm_fiq_indices[8]
static int arm_default_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
static int armv4_5_get_core_reg(struct reg *reg)
int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
void arm_free_reg_cache(struct arm *arm)
static const uint8_t arm_usr_indices[17]
static struct reg_feature arm_gdb_dummy_fp_features
static const uint8_t arm_mon_indices[3]
const char * arm_get_gdb_arch(struct target *target)
bool is_arm_mode(unsigned psr_mode)
Return true iff the parameter denotes a valid ARM processor mode.
static const uint8_t arm_und_indices[3]
static const struct command_registration arm_exec_command_handlers[]
const struct command_registration arm_command_handlers[]
const char * arm_mode_name(unsigned psr_mode)
Map PSR mode bits to the name of an ARM processor operating mode.
static void arm_gdb_dummy_init(void)
static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
enum arm_mode armv4_5_number_to_mode(int number)
Map linear number indexing armv4_5_core_reg_map to PSR mode bits.
int arm_init_arch_info(struct target *target, struct arm *arm)
void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
Configures host-side ARM records to reflect the specified CPSR.
int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int(*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info))
struct reg * arm_reg_current(struct arm *arm, unsigned regnum)
Returns handle to the register currently mapped to a given number.
static int arm_default_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
static const uint8_t arm_gdb_dummy_fps_value[4]
static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
#define ARMV4_5_CORE_REG_MODE(cache, mode, num)
Support functions to access arbitrary bits in a byte array.
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
void breakpoint_remove(struct target *target, target_addr_t address)
int breakpoint_add(struct target *target, target_addr_t address, uint32_t length, enum breakpoint_type type)
struct command_context * current_command_context(Jim_Interp *interp)
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CMD_NAME
Use this macro to access the name of the command being handled, rather than accessing the variable di...
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define COMMAND_PARSE_ADDRESS(in, out)
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
enum esirisc_reg_num number
struct esp_usb_jtag __attribute__
static uint16_t direction
static const struct @101 regs[]
#define LOG_USER(expr ...)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_DEBUG(expr ...)
void register_init_dummy(struct reg *reg)
struct reg * register_get_by_name(struct reg_cache *first, const char *name, bool search_all)
size_t size
Size of the control block search area.
const struct command_registration semihosting_common_handlers[]
unsigned int common_magic
enum arm_state core_state
Represents a generic ARM core, with standard application registers.
int(* full_context)(struct target *target)
Retrieve all core registers, for display.
enum arm_arch arch
ARM architecture version.
enum arm_core_type core_type
Indicates what registers are in the ARM state core register set.
int(* mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
Read coprocessor register.
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
struct reg * cpsr
Handle to the CPSR/xPSR; valid in all core modes.
struct reg * pc
Handle to the PC; valid in all core modes.
int(* write_core_reg)(struct target *target, struct reg *reg, int num, enum arm_mode mode, uint8_t *value)
const int * map
Support for arm_reg_current()
int(* read_core_reg)(struct target *target, struct reg *reg, int num, enum arm_mode mode)
Retrieve a single core register.
struct reg_cache * core_cache
int(* mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
Write coprocessor register.
struct reg * spsr
Handle to the SPSR; valid only in core modes with an SPSR.
unsigned int common_magic
int arm_vfp_version
Floating point or VFP version, 0 if disabled.
struct target * target
Backpointer to the target.
enum arm_state core_state
Record the current core state: ARM, Thumb, or otherwise.
int(* get)(struct reg *reg)
struct reg_feature * feature
struct reg_data_type * reg_data_type
const struct reg_arch_type * type
bool hit_fileio
A flag reporting whether semihosting fileio operation is active.
bool is_fileio
A flag reporting whether semihosting fileio is active.
bool is_active
A flag reporting whether semihosting is active.
struct semihosting * semihosting
int target_halt(struct target *target)
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
int target_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
Downloads a target-specific native code algorithm to the target, and executes it.
struct target * get_current_target(struct command_context *cmd_ctx)
const char * debug_reason_name(struct target *t)
const char * target_type_name(struct target *target)
Get the target type name.
int target_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Make the target (re)start executing using its saved execution context (possibly with some modificatio...
int target_wait_state(struct target *target, enum target_state state, int ms)
#define ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_INVALID
static const char * target_name(struct target *target)
Returns the instance-specific name of the specified target.
#define ERROR_TARGET_TIMEOUT
static bool target_was_examined(struct target *target)
#define ERROR_TARGET_FAILURE
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
static uint32_t le_to_h_u32(const uint8_t *buf)