33 "AArch32",
"Thumb",
"Jazelle",
"ThumbEE",
"AArch64",
113 LOG_ERROR(
"unrecognized psr mode: %#02x", psr_mode);
114 return "UNRECOGNIZED";
436 uint32_t value_r0 = 0, value_r1 = 0;
437 unsigned num = (regnum -
ARMV8_V0) << 1;
442 reg_r1->
dirty =
true;
458 *lvalue = ((*lvalue) << 32) | value_r0;
473 *hvalue = ((*hvalue) << 32) | value_r0;
570 uint32_t value_r0 = 0, value_r1 = 0;
571 unsigned num = (regnum -
ARMV8_V0) << 1;
576 reg_r1->
dirty =
true;
577 value_r1 = lvalue >> 32;
578 value_r0 = lvalue & 0xFFFFFFFF;
596 value_r1 = hvalue >> 32;
597 value_r0 = hvalue & 0xFFFFFFFF;
653 if (mpidr & 1U<<31) {
656 armv8->
cpu_id = mpidr & 0x3;
662 LOG_ERROR(
"mpidr not in multiprocessor format");
677 uint32_t
mode = cpsr & 0x1F;
692 if ((cpsr & 0x10) != 0) {
694 if (cpsr & (1 << 5)) {
695 if (cpsr & (1 << 24)) {
701 if (cpsr & (1 << 24)) {
702 LOG_ERROR(
"Jazelle state handling is BROKEN!");
715 LOG_DEBUG(
"set CPSR %#8.8x: %s mode, %s state", (
unsigned) cpsr,
722 uint32_t dfsr, ifsr, dfar, ifar;
758 LOG_USER(
"Data fault registers DFSR: %8.8" PRIx32
759 ", DFAR: %8.8" PRIx32, dfsr, dfar);
760 LOG_USER(
"Instruction fault registers IFSR: %8.8" PRIx32
761 ", IFAR: %8.8" PRIx32, ifsr, ifar);
798 LOG_INFO(
"Unknown physical address size");
808 uint32_t ttbcr, ttbcr_n;
809 int retval = dpm->
prepare(dpm);
821 ttbcr_n = ttbcr & 0x7;
833 LOG_DEBUG(
"ttbr1 %s, ttbr0_mask %" PRIx32
" ttbr1_mask %" PRIx32,
834 (ttbcr_n != 0) ?
"used" :
"not used",
869 armv8->
va_size = 64 - (ttbcr & 0x3F);
882 armv8->
va_size = 64 - (ttbcr & 0x3F);
893 armv8->
va_size = 64 - (ttbcr_64 & 0x3F);
939 static const char *
const shared_name[] = {
940 "Non-",
"UNDEFINED ",
"Outer ",
"Inner "
943 static const char *
const secure_name[] = {
944 "Secure",
"Not Secure"
997 LOG_ERROR(
"Address translation failed at stage %i, FST=%x, PTW=%i",
998 ((
int)(par >> 9) & 1)+1, (
int)(par >> 1) & 0x3f, (
int)(par >> 8) & 1);
1003 *val = (par & 0xFFFFFFFFF000UL) | (va & 0xFFF);
1005 int SH = (par >> 7) & 3;
1006 int NS = (par >> 9) & 1;
1007 int ATTR = (par >> 56) & 0xFF;
1009 char *memtype = (ATTR & 0xF0) == 0 ?
"Device Memory" :
"Normal Memory";
1012 shared_name[SH], secure_name[NS]);
1024 uint32_t edeccr = 0;
1025 unsigned int argp = 0;
1028 static const struct jim_nvp nvp_ecatch_modes[] = {
1029 { .
name =
"off", .value = 0 },
1030 { .name =
"nsec_el1", .value = (1 << 5) },
1031 { .name =
"nsec_el2", .value = (2 << 5) },
1032 { .name =
"nsec_el12", .value = (3 << 5) },
1033 { .name =
"sec_el1", .value = (1 << 1) },
1034 { .name =
"sec_el3", .value = (4 << 1) },
1035 { .name =
"sec_el13", .value = (5 << 1) },
1036 { .name =
NULL, .value = -1 },
1041 const char *sec =
NULL, *nsec =
NULL;
1056 if (!sec || !nsec) {
1057 LOG_WARNING(
"Exception Catch: unknown exception catch configuration: EDECCR = %02" PRIx32, edeccr & 0xff);
1061 command_print(
CMD,
"Exception Catch: Secure: %s, Non-Secure: %s", sec, nsec);
1089 if (armv8_cache->
info == -1) {
1127 LOG_ERROR(
"BUG: called for a non-ARM target");
1131 LOG_USER(
"%s halted in %s state due to %s, current mode: %s\n"
1132 "cpsr: 0x%8.8" PRIx32
" pc: 0x%" PRIx64
"%s",
1146 static const char *
const state[] = {
1147 "disabled",
"enabled"
1154 LOG_ERROR(
"BUG: called for a non-Armv8 target");
1163 LOG_USER(
"MMU: %s, D-Cache: %s, I-Cache: %s",
1169 armv8_show_fault_registers(
target);
1323 static const struct {
1426 static const struct {
1488 #define ARMV8_NUM_REGS ARRAY_SIZE(armv8_regs)
1489 #define ARMV8_NUM_REGS32 ARRAY_SIZE(armv8_regs32)
1520 }
else if (
reg->
size <= 128) {
1586 reg64->
valid =
true;
1589 reg64->
dirty =
true;
1609 struct reg *reg_list = calloc(num_regs,
sizeof(
struct reg));
1610 struct reg *reg_list32 = calloc(num_regs32,
sizeof(
struct reg));
1611 struct arm_reg *arch_info = calloc(num_regs,
sizeof(
struct arm_reg));
1616 cache->
name =
"Aarch64 registers";
1617 cache->
next = cache32;
1621 for (i = 0; i < num_regs; i++) {
1635 reg_list[i].
exist =
true;
1643 LOG_ERROR(
"unable to allocate feature list");
1652 LOG_ERROR(
"unable to allocate reg type list");
1660 cache32->
name =
"Aarch32 registers";
1665 for (i = 0; i < num_regs32; i++) {
1672 reg_list32[i].
number = i;
1673 reg_list32[i].
exist =
true;
1681 LOG_ERROR(
"unable to allocate feature list");
1687 LOG_ERROR(
"unable to allocate reg type list");
1713 for (i = 0; i < cache->
num_regs; i++) {
1734 cache32 = cache->
next;
1742 .
name =
"catch_exc",
1743 .handler = armv8_handle_exception_catch_command,
1745 .help =
"configure exception catch",
1746 .usage =
"[(nsec_el1,nsec_el2,sec_el1,sec_el3)+,off]",
1758 struct reg **reg_list[],
int *reg_list_size,
1768 switch (reg_class) {
1771 *reg_list = malloc(
sizeof(
struct reg *) * (*reg_list_size));
1773 for (i = 0; i < *reg_list_size; i++)
1779 *reg_list = malloc(
sizeof(
struct reg *) * (*reg_list_size));
1781 for (i = 0; i < *reg_list_size; i++)
1787 LOG_ERROR(
"not a valid register class type in query.");
1795 switch (reg_class) {
1798 *
reg_list = malloc(
sizeof(
struct reg *) * (*reg_list_size));
1800 for (i = 0; i < *reg_list_size; i++)
1805 *reg_list_size = cache32->
num_regs;
1806 *
reg_list = malloc(
sizeof(
struct reg *) * (*reg_list_size));
1808 for (i = 0; i < *reg_list_size; i++)
1813 LOG_ERROR(
"not a valid register class type in query.");
1832 tmp |= value &
mask;
int arm_arch_state(struct target *target)
arm_mode
Represent state of an ARM core.
arm_state
The PSR "T" and "J" bits define the mode of "classic ARM" cores.
static struct arm * target_to_arm(struct target *target)
Convert target handle to generic ARM target state handle.
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Synchronous read of a word from memory or a system register.
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Synchronous write of a word to memory or a system register.
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
#define ARMV4_5_VMOV(op, rt2, rt, m, vm)
static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *regval)
int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
static int armv8_get_core_reg32(struct reg *reg)
int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value)
static int armv8_get_core_reg(struct reg *reg)
static struct reg_data_type_flags_field aarch64_cpsr_fields[]
static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum, uint64_t lvalue, uint64_t hvalue)
int armv8_read_mpidr(struct armv8_common *armv8)
static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t value)
void armv8_free_reg_cache(struct target *target)
static void armv8_show_fault_registers32(struct armv8_common *armv8)
static const struct @80 armv8_regs32[]
int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val)
static struct reg_data_type_vector aarch64_vector_types[]
static __attribute__((unused))
static int armv8_setup_semihosting(struct target *target, int enable)
static struct reg_data_type_bitfield aarch64_cpsr_bits[]
static int armv8_read_reg_simdfp_aarch64(struct armv8_common *armv8, int regnum, uint64_t *lvalue, uint64_t *hvalue)
static struct reg_data_type aarch64_fpu_union[]
static int armv8_set_core_reg(struct reg *reg, uint8_t *buf)
static int armv8_read_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum, uint64_t *lvalue, uint64_t *hvalue)
struct reg * armv8_reg_current(struct arm *arm, unsigned regnum)
struct reg_data_type * data_type
const char * armv8_get_gdb_arch(struct target *target)
int armv8_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
static const char *const armv8_state_strings[]
static const struct reg_arch_type armv8_reg_type
static struct reg_data_type_union_field aarch64v_union_fields[]
int armv8_arch_state(struct target *target)
static struct reg_data_type aarch64v[]
int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va, target_addr_t *val, int meminfo)
static struct reg_data_type_union_field aarch64_union_fields_vnh[]
static int armv8_write_reg_simdfp_aarch64(struct armv8_common *armv8, int regnum, uint64_t lvalue, uint64_t hvalue)
static struct reg_data_type aarch64_flags_cpsr[]
static void armv8_free_cache(struct reg_cache *cache, bool regs32)
static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regval)
const struct command_registration armv8_command_handlers[]
static struct reg_data_type_union aarch64v_union[]
static struct reg_data_type_union_field aarch64_union_fields_vnd[]
void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
Configures host-side ARM records to reflect the specified CPSR.
static struct reg_data_type_union_field aarch64_union_fields_vnq[]
const char * armv8_mode_name(unsigned psr_mode)
Map PSR mode bits to the name of an ARM processor operating mode.
COMMAND_HANDLER(armv8_handle_exception_catch_command)
static const struct @78 armv8_mode_data[]
static int armv8_set_core_reg32(struct reg *reg, uint8_t *buf)
static const struct @79 armv8_regs[]
struct reg_cache * armv8_build_reg_cache(struct target *target)
Builds cache of architecturally defined registers.
static uint8_t armv8_pa_size(uint32_t ps)
static struct reg_data_type aarch64_vector_base_types[]
static struct reg_data_type_flags aarch64_cpsr_flags[]
static struct reg_data_type_union_field aarch64_union_fields_vnb[]
static int armv8_aarch64_state(struct target *target)
void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64)
static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t value_64)
static struct reg_data_type_union_field aarch64_union_fields_vns[]
static const struct reg_arch_type armv8_reg32_type
int armv8_handle_cache_info_command(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache)
static struct reg_data_type_union aarch64_union_types[]
static struct reg_data_type aarch64_fpu_vector[]
static struct armv8_common * target_to_armv8(struct target *target)
static unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
#define ARMV8_COMMON_MAGIC
int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
#define ARMV8_MRC_DLR(rt)
#define ARMV8_MCR_DLR(rt)
#define ARMV8_MSR_GP(system, rt)
#define ARMV8_MSR_DLR(rt)
#define ARMV8_MCR_DSPSR(rt)
#define ARMV8_MOVTSP_64(rt)
#define ARMV8_MOV_VFP_GPR(rd, rn, index)
#define ARMV8_MRS_DSPSR(rt)
#define ARMV8_MSR_FPCR(rt)
#define ARMV8_MRS(system, rt)
#define ARMV8_MSR_FPSR(rt)
#define ARMV8_MRS_DLR(rt)
#define ARMV8_MRS_FPCR(rt)
#define ARMV8_MOV_GPR_VFP(rd, rn, index)
#define ARMV8_SYS(system, rt)
#define ARMV8_MRS_XPSR_T1(r, rd)
#define ARMV8_MSR_GP_XPSR_T1(r, rn, mask)
#define ARMV8_MSR_GP_T1(r, m1, rd, m)
#define ARMV8_MSR_DSPSR(rt)
#define ARMV8_MRS_FPSR(rt)
#define ARMV8_MRS_T1(r, m1, rd, m)
#define ARMV8_MRC_DSPSR(rt)
#define SYSTEM_DBG_DBGDTR_EL0
#define ARMV8_MOVFSP_64(rt)
Support functions to access arbitrary bits in a byte array.
static void buf_set_u64(uint8_t *_buffer, unsigned first, unsigned num, uint64_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
static uint64_t buf_get_u64(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 64-bit word.
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
struct jim_nvp * jim_nvp_name2value_simple(const struct jim_nvp *p, const char *name)
struct jim_nvp * jim_nvp_value2name_simple(const struct jim_nvp *p, int value)
#define LOG_USER(expr ...)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
This wraps an implementation of DPM primitives.
target_addr_t wp_addr
Target dependent watchpoint address.
int(* instr_read_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from dcc after execution.
int(* instr_write_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Runs one instruction, writing data to R0 before execution.
int(* instr_read_data_dcc_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
int(* instr_write_data_dcc_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
int(* instr_write_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
int(* instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
int(* instr_read_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Represents a generic ARM core, with standard application registers.
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
struct reg * cpsr
Handle to the CPSR/xPSR; valid in all core modes.
struct reg * pc
Handle to the PC; valid in all core modes.
int(* setup_semihosting)(struct target *target, int enable)
int(* read_core_reg)(struct target *target, struct reg *reg, int num, enum arm_mode mode)
Retrieve a single core register.
struct reg_cache * core_cache
struct arm_dpm * dpm
Handle for the debug module, if one is present.
unsigned int common_magic
struct target * target
Backpointer to the target.
enum arm_state core_state
Record the current core state: ARM, Thumb, or otherwise.
int(* display_cache_info)(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache)
int(* flush_all_data_cache)(struct target *target)
struct armv8_mmu_common armv8_mmu
int(* read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value)
int(* write_reg_u128)(struct armv8_common *armv8, int num, uint64_t lvalue, uint64_t hvalue)
struct adiv5_ap * debug_ap
int(* read_reg_u128)(struct armv8_common *armv8, int num, uint64_t *lvalue, uint64_t *hvalue)
unsigned int common_magic
int(* write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value)
uint8_t multi_processor_system
struct armv8_cache_common armv8_cache
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Name Value Pairs, aka: NVP.
int(* get)(struct reg *reg)
struct reg_feature * feature
struct reg_data_type * reg_data_type
const struct reg_arch_type * type
bool is_active
A flag reporting whether semihosting is active.
struct semihosting * semihosting
enum target_debug_reason debug_reason
struct reg_cache * reg_cache
struct target * get_current_target(struct command_context *cmd_ctx)
const char * debug_reason_name(struct target *t)
#define ERROR_TARGET_NOT_HALTED
static const char * target_name(struct target *target)
Returns the instance-specific name of the specified target.
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.