7 #ifndef OPENOCD_TARGET_ARMV8_H
8 #define OPENOCD_TARGET_ARMV8_H
111 #define ARMV8_COMMON_MAGIC 0x0A450AAAU
217 uint64_t *lvalue, uint64_t *hvalue);
219 uint64_t lvalue, uint64_t hvalue);
239 #define CPUV8_DBG_MAINID0 0xD00
240 #define CPUV8_DBG_CPUFEATURE0 0xD20
241 #define CPUV8_DBG_DBGFEATURE0 0xD28
242 #define CPUV8_DBG_MEMFEATURE0 0xD38
244 #define CPUV8_DBG_LOCKACCESS 0xFB0
245 #define CPUV8_DBG_LOCKSTATUS 0xFB4
247 #define CPUV8_DBG_EDESR 0x20
248 #define CPUV8_DBG_EDECR 0x24
249 #define CPUV8_DBG_EDWAR0 0x30
250 #define CPUV8_DBG_EDWAR1 0x34
251 #define CPUV8_DBG_DSCR 0x088
252 #define CPUV8_DBG_DRCR 0x090
253 #define CPUV8_DBG_ECCR 0x098
254 #define CPUV8_DBG_PRCR 0x310
255 #define CPUV8_DBG_PRSR 0x314
257 #define CPUV8_DBG_DTRRX 0x080
258 #define CPUV8_DBG_ITR 0x084
259 #define CPUV8_DBG_SCR 0x088
260 #define CPUV8_DBG_DTRTX 0x08c
262 #define CPUV8_DBG_BVR_BASE 0x400
263 #define CPUV8_DBG_BCR_BASE 0x408
264 #define CPUV8_DBG_WVR_BASE 0x800
265 #define CPUV8_DBG_WCR_BASE 0x808
266 #define CPUV8_DBG_VCR 0x01C
268 #define CPUV8_DBG_OSLAR 0x300
270 #define CPUV8_DBG_AUTHSTATUS 0xFB8
272 #define PAGE_SIZE_4KB 0x1000
273 #define PAGE_SIZE_4KB_LEVEL0_BITS 39
274 #define PAGE_SIZE_4KB_LEVEL1_BITS 30
275 #define PAGE_SIZE_4KB_LEVEL2_BITS 21
276 #define PAGE_SIZE_4KB_LEVEL3_BITS 12
278 #define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
279 #define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
280 #define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
281 #define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
283 #define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
318 return (core_mode >> 2) & 3;
Holds the interface to ARM cores.
arm_mode
Represent state of an ARM core.
This defines formats and data structures used to talk to ADIv5 entities.
int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value)
int armv8_identify_cache(struct armv8_common *armv8)
int armv8_read_mpidr(struct armv8_common *armv8)
void armv8_free_reg_cache(struct target *target)
static struct armv8_common * target_to_armv8(struct target *target)
int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val)
@ ARMV8_RUNCONTROL_UNKNOWN
@ ARMV8_RUNCONTROL_RESUME
int armv8_arch_state(struct target *target)
int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va, target_addr_t *val, int meminfo)
static bool is_armv8(struct armv8_common *armv8)
const struct command_registration armv8_command_handlers[]
void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
Configures host-side ARM records to reflect the specified CPSR.
const char * armv8_mode_name(unsigned psr_mode)
Map PSR mode bits to the name of an ARM processor operating mode.
static unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64)
#define ARMV8_COMMON_MAGIC
int armv8_handle_cache_info_command(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache)
size_t size
Size of the control block search area.
This represents an ARM Debug Interface (v5) Access Port (AP).
This wraps an implementation of DPM primitives.
Represents a generic ARM core, with standard application registers.
struct armv8_cachesize d_u_size
struct armv8_cachesize i_size
struct armv8_arch_cache arch[6]
int(* display_cache_info)(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache)
int(* flush_all_data_cache)(struct target *target)
struct reg_cache * core_cache
enum run_control_op last_run_control_op
struct armv8_mmu_common armv8_mmu
int(* read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value)
int(* write_reg_u128)(struct armv8_common *armv8, int num, uint64_t lvalue, uint64_t hvalue)
struct adiv5_ap * debug_ap
int(* read_reg_u128)(struct armv8_common *armv8, int num, uint64_t *lvalue, uint64_t *hvalue)
unsigned int common_magic
void(* pre_restore_context)(struct target *target)
int(* examine_debug_reason)(struct target *target)
int(* write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value)
int(* post_debug_entry)(struct target *target)
uint8_t multi_processor_system
int(* read_physical_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
struct armv8_cache_common armv8_cache
When run_command is called, a new instance will be created on the stack, filled with the proper value...
#define container_of(ptr, type, member)
Cast a member of a structure out to the containing structure.