OpenOCD
armv8.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2015 by David Ung *
5  ***************************************************************************/
6 
7 #ifndef OPENOCD_TARGET_ARMV8_H
8 #define OPENOCD_TARGET_ARMV8_H
9 
10 #include "arm_adi_v5.h"
11 #include "arm.h"
12 #include "armv4_5_mmu.h"
13 #include "armv4_5_cache.h"
14 #include "armv8_dpm.h"
15 #include "arm_cti.h"
16 
17 enum {
18  ARMV8_R0 = 0,
49 
50  ARMV8_SP = 31,
51  ARMV8_PC = 32,
52  ARMV8_XPSR = 33,
53 
54  ARMV8_V0 = 34,
88 
92 
96 
100 
102 };
103 
109 };
110 
111 #define ARMV8_COMMON_MAGIC 0x0A450AAAU
112 
113 /* VA to PA translation operations opc2 values*/
114 #define V2PCWPR 0
115 #define V2PCWPW 1
116 #define V2PCWUR 2
117 #define V2PCWUW 3
118 #define V2POWPR 4
119 #define V2POWPW 5
120 #define V2POWUR 6
121 #define V2POWUW 7
122 /* L210/L220 cache controller support */
124  uint32_t base;
125  uint32_t way;
126 };
127 
129  uint32_t level_num;
130  /* cache dimensioning */
131  uint32_t linelen;
132  uint32_t associativity;
133  uint32_t nsets;
134  uint32_t cachesize;
135  /* info for set way operation on cache */
136  uint32_t index;
137  uint32_t index_shift;
138  uint32_t way;
139  uint32_t way_shift;
140 };
141 
142 /* information about one architecture cache at any level */
144  int ctype; /* cache type, CLIDR encoding */
145  struct armv8_cachesize d_u_size; /* data cache */
146  struct armv8_cachesize i_size; /* instruction cache */
147 };
148 
150  int info;
151  int loc;
152  uint32_t iminline;
153  uint32_t dminline;
154  struct armv8_arch_cache arch[6]; /* cache info, L1 - L7 */
157 
158  /* l2 external unified cache if some */
159  void *l2_cache;
162  struct armv8_cache_common *armv8_cache);
163 };
164 
166  /* following field mmu working way */
167  int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
168  uint64_t ttbr0_mask;/* masked to be used */
169 
170  uint32_t ttbcr; /* cache for ttbcr register */
171  uint32_t ttbr_mask[2];
172  uint32_t ttbr_range[2];
173 
175  uint32_t size, uint32_t count, uint8_t *buffer);
177  uint32_t mmu_enabled;
178 };
179 
180 struct armv8_common {
181  unsigned int common_magic;
182 
183  struct arm arm;
185 
186  /* Core Debug Unit */
187  struct arm_dpm dpm;
190 
191  const uint32_t *opcodes;
192 
193  /* mdir */
195  uint8_t cluster_id;
196  uint8_t cpu_id;
197 
198  /* armv8 aarch64 need below information for page translation */
199  uint8_t va_size;
200  uint8_t pa_size;
201  uint32_t page_size;
202  uint64_t ttbr_base;
203 
205 
206  struct arm_cti *cti;
207 
208  /* last run-control command issued to this target (resume, halt, step) */
210 
211  /* Direct processor core register read and writes */
212  int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
213  int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
214 
215  /* SIMD/FPU registers read/write interface */
216  int (*read_reg_u128)(struct armv8_common *armv8, int num,
217  uint64_t *lvalue, uint64_t *hvalue);
218  int (*write_reg_u128)(struct armv8_common *armv8, int num,
219  uint64_t lvalue, uint64_t hvalue);
220 
222  int (*post_debug_entry)(struct target *target);
223 
225 };
226 
227 static inline struct armv8_common *
229 {
230  return container_of(target->arch_info, struct armv8_common, arm);
231 }
232 
233 static inline bool is_armv8(struct armv8_common *armv8)
234 {
235  return armv8->common_magic == ARMV8_COMMON_MAGIC;
236 }
237 
238 /* register offsets from armv8.debug_base */
239 #define CPUV8_DBG_MAINID0 0xD00
240 #define CPUV8_DBG_CPUFEATURE0 0xD20
241 #define CPUV8_DBG_DBGFEATURE0 0xD28
242 #define CPUV8_DBG_MEMFEATURE0 0xD38
243 
244 #define CPUV8_DBG_LOCKACCESS 0xFB0
245 #define CPUV8_DBG_LOCKSTATUS 0xFB4
246 
247 #define CPUV8_DBG_EDESR 0x20
248 #define CPUV8_DBG_EDECR 0x24
249 #define CPUV8_DBG_EDWAR0 0x30
250 #define CPUV8_DBG_EDWAR1 0x34
251 #define CPUV8_DBG_DSCR 0x088
252 #define CPUV8_DBG_DRCR 0x090
253 #define CPUV8_DBG_ECCR 0x098
254 #define CPUV8_DBG_PRCR 0x310
255 #define CPUV8_DBG_PRSR 0x314
256 
257 #define CPUV8_DBG_DTRRX 0x080
258 #define CPUV8_DBG_ITR 0x084
259 #define CPUV8_DBG_SCR 0x088
260 #define CPUV8_DBG_DTRTX 0x08c
261 
262 #define CPUV8_DBG_BVR_BASE 0x400
263 #define CPUV8_DBG_BCR_BASE 0x408
264 #define CPUV8_DBG_WVR_BASE 0x800
265 #define CPUV8_DBG_WCR_BASE 0x808
266 #define CPUV8_DBG_VCR 0x01C
267 
268 #define CPUV8_DBG_OSLAR 0x300
269 
270 #define CPUV8_DBG_AUTHSTATUS 0xFB8
271 
272 #define PAGE_SIZE_4KB 0x1000
273 #define PAGE_SIZE_4KB_LEVEL0_BITS 39
274 #define PAGE_SIZE_4KB_LEVEL1_BITS 30
275 #define PAGE_SIZE_4KB_LEVEL2_BITS 21
276 #define PAGE_SIZE_4KB_LEVEL3_BITS 12
277 
278 #define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
279 #define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
280 #define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
281 #define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
282 
283 #define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
284 
285 int armv8_arch_state(struct target *target);
286 int armv8_read_mpidr(struct armv8_common *armv8);
287 int armv8_identify_cache(struct armv8_common *armv8);
288 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
290  target_addr_t *val, int meminfo);
292 
294  struct armv8_cache_common *armv8_cache);
295 
296 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
297 
298 static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
299 {
300  switch (core_mode) {
301  /* Aarch32 modes */
302  case ARM_MODE_USR:
303  return 0;
304  case ARM_MODE_SVC:
305  case ARM_MODE_ABT: /* FIXME: EL3? */
306  case ARM_MODE_IRQ: /* FIXME: EL3? */
307  case ARM_MODE_FIQ: /* FIXME: EL3? */
308  case ARM_MODE_UND: /* FIXME: EL3? */
309  case ARM_MODE_SYS: /* FIXME: EL3? */
310  return 1;
311  /* case ARM_MODE_HYP:
312  * return 2;
313  */
314  case ARM_MODE_MON:
315  return 3;
316  /* all Aarch64 modes */
317  default:
318  return (core_mode >> 2) & 3;
319  }
320 }
321 
322 const char *armv8_mode_name(unsigned psr_mode);
323 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
324 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
325 
326 extern void armv8_free_reg_cache(struct target *target);
327 
328 extern const struct command_registration armv8_command_handlers[];
329 
330 #endif /* OPENOCD_TARGET_ARMV8_H */
Holds the interface to ARM cores.
arm_mode
Represent state of an ARM core.
Definition: arm.h:74
@ ARM_MODE_IRQ
Definition: arm.h:77
@ ARM_MODE_SYS
Definition: arm.h:84
@ ARM_MODE_MON
Definition: arm.h:79
@ ARM_MODE_FIQ
Definition: arm.h:76
@ ARM_MODE_UND
Definition: arm.h:82
@ ARM_MODE_USR
Definition: arm.h:75
@ ARM_MODE_SVC
Definition: arm.h:78
@ ARM_MODE_ABT
Definition: arm.h:80
This defines formats and data structures used to talk to ADIv5 entities.
int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
Definition: armv8.c:1104
int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value)
Definition: armv8.c:1819
int armv8_identify_cache(struct armv8_common *armv8)
Definition: armv8_cache.c:296
int armv8_read_mpidr(struct armv8_common *armv8)
Definition: armv8.c:632
void armv8_free_reg_cache(struct target *target)
Definition: armv8.c:1726
static struct armv8_common * target_to_armv8(struct target *target)
Definition: armv8.h:228
int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val)
Definition: armv8.c:922
run_control_op
Definition: armv8.h:104
@ ARMV8_RUNCONTROL_HALT
Definition: armv8.h:107
@ ARMV8_RUNCONTROL_UNKNOWN
Definition: armv8.h:105
@ ARMV8_RUNCONTROL_RESUME
Definition: armv8.h:106
@ ARMV8_RUNCONTROL_STEP
Definition: armv8.h:108
int armv8_arch_state(struct target *target)
Definition: armv8.c:1144
int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va, target_addr_t *val, int meminfo)
Definition: armv8.c:928
static bool is_armv8(struct armv8_common *armv8)
Definition: armv8.h:233
const struct command_registration armv8_command_handlers[]
Definition: armv8.c:1740
void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
Configures host-side ARM records to reflect the specified CPSR.
Definition: armv8.c:675
@ ARMV8_V27
Definition: armv8.h:81
@ ARMV8_R14
Definition: armv8.h:32
@ ARMV8_ESR_EL2
Definition: armv8.h:94
@ ARMV8_R20
Definition: armv8.h:38
@ ARMV8_V16
Definition: armv8.h:70
@ ARMV8_V1
Definition: armv8.h:55
@ ARMV8_V11
Definition: armv8.h:65
@ ARMV8_R0
Definition: armv8.h:18
@ ARMV8_V23
Definition: armv8.h:77
@ ARMV8_V2
Definition: armv8.h:56
@ ARMV8_R12
Definition: armv8.h:30
@ ARMV8_R21
Definition: armv8.h:39
@ ARMV8_R5
Definition: armv8.h:23
@ ARMV8_V5
Definition: armv8.h:59
@ ARMV8_ESR_EL1
Definition: armv8.h:90
@ ARMV8_V12
Definition: armv8.h:66
@ ARMV8_V4
Definition: armv8.h:58
@ ARMV8_V25
Definition: armv8.h:79
@ ARMV8_R7
Definition: armv8.h:25
@ ARMV8_V14
Definition: armv8.h:68
@ ARMV8_R9
Definition: armv8.h:27
@ ARMV8_LAST_REG
Definition: armv8.h:101
@ ARMV8_V18
Definition: armv8.h:72
@ ARMV8_R17
Definition: armv8.h:35
@ ARMV8_R23
Definition: armv8.h:41
@ ARMV8_V6
Definition: armv8.h:60
@ ARMV8_R18
Definition: armv8.h:36
@ ARMV8_R1
Definition: armv8.h:19
@ ARMV8_SPSR_EL3
Definition: armv8.h:99
@ ARMV8_SPSR_EL2
Definition: armv8.h:95
@ ARMV8_R24
Definition: armv8.h:42
@ ARMV8_V19
Definition: armv8.h:73
@ ARMV8_R22
Definition: armv8.h:40
@ ARMV8_SP
Definition: armv8.h:50
@ ARMV8_R6
Definition: armv8.h:24
@ ARMV8_R29
Definition: armv8.h:47
@ ARMV8_V3
Definition: armv8.h:57
@ ARMV8_V7
Definition: armv8.h:61
@ ARMV8_V31
Definition: armv8.h:85
@ ARMV8_V17
Definition: armv8.h:71
@ ARMV8_V13
Definition: armv8.h:67
@ ARMV8_R25
Definition: armv8.h:43
@ ARMV8_V28
Definition: armv8.h:82
@ ARMV8_V9
Definition: armv8.h:63
@ ARMV8_V22
Definition: armv8.h:76
@ ARMV8_ELR_EL3
Definition: armv8.h:97
@ ARMV8_XPSR
Definition: armv8.h:52
@ ARMV8_R30
Definition: armv8.h:48
@ ARMV8_V8
Definition: armv8.h:62
@ ARMV8_R27
Definition: armv8.h:45
@ ARMV8_R4
Definition: armv8.h:22
@ ARMV8_FPCR
Definition: armv8.h:87
@ ARMV8_V24
Definition: armv8.h:78
@ ARMV8_R8
Definition: armv8.h:26
@ ARMV8_PC
Definition: armv8.h:51
@ ARMV8_V0
Definition: armv8.h:54
@ ARMV8_SPSR_EL1
Definition: armv8.h:91
@ ARMV8_R13
Definition: armv8.h:31
@ ARMV8_ELR_EL2
Definition: armv8.h:93
@ ARMV8_V29
Definition: armv8.h:83
@ ARMV8_ESR_EL3
Definition: armv8.h:98
@ ARMV8_R10
Definition: armv8.h:28
@ ARMV8_V26
Definition: armv8.h:80
@ ARMV8_V10
Definition: armv8.h:64
@ ARMV8_R28
Definition: armv8.h:46
@ ARMV8_R3
Definition: armv8.h:21
@ ARMV8_R26
Definition: armv8.h:44
@ ARMV8_V21
Definition: armv8.h:75
@ ARMV8_V15
Definition: armv8.h:69
@ ARMV8_V20
Definition: armv8.h:74
@ ARMV8_R16
Definition: armv8.h:34
@ ARMV8_V30
Definition: armv8.h:84
@ ARMV8_R11
Definition: armv8.h:29
@ ARMV8_FPSR
Definition: armv8.h:86
@ ARMV8_ELR_EL1
Definition: armv8.h:89
@ ARMV8_R15
Definition: armv8.h:33
@ ARMV8_R2
Definition: armv8.h:20
@ ARMV8_R19
Definition: armv8.h:37
const char * armv8_mode_name(unsigned psr_mode)
Map PSR mode bits to the name of an ARM processor operating mode.
Definition: armv8.c:107
static unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
Definition: armv8.h:298
void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64)
Definition: armv8.c:615
#define ARMV8_COMMON_MAGIC
Definition: armv8.h:111
int armv8_handle_cache_info_command(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache)
Definition: armv8.c:1086
int mask
Definition: esirisc.c:1698
struct target * target
Definition: rtt/rtt.c:26
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
This represents an ARM Debug Interface (v5) Access Port (AP).
Definition: arm_adi_v5.h:243
This wraps an implementation of DPM primitives.
Definition: arm_dpm.h:47
Represents a generic ARM core, with standard application registers.
Definition: arm.h:167
struct armv8_cachesize d_u_size
Definition: armv8.h:145
struct armv8_cachesize i_size
Definition: armv8.h:146
uint32_t iminline
Definition: armv8.h:152
void * l2_cache
Definition: armv8.h:159
uint32_t dminline
Definition: armv8.h:153
int d_u_cache_enabled
Definition: armv8.h:156
struct armv8_arch_cache arch[6]
Definition: armv8.h:154
int(* display_cache_info)(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache)
Definition: armv8.h:161
int(* flush_all_data_cache)(struct target *target)
Definition: armv8.h:160
int i_cache_enabled
Definition: armv8.h:155
uint32_t way_shift
Definition: armv8.h:139
uint32_t associativity
Definition: armv8.h:132
uint32_t index
Definition: armv8.h:136
uint32_t index_shift
Definition: armv8.h:137
uint32_t way
Definition: armv8.h:138
uint32_t level_num
Definition: armv8.h:129
uint32_t nsets
Definition: armv8.h:133
uint32_t linelen
Definition: armv8.h:131
uint32_t cachesize
Definition: armv8.h:134
uint8_t va_size
Definition: armv8.h:199
uint32_t page_size
Definition: armv8.h:201
struct arm_dpm dpm
Definition: armv8.h:187
uint64_t ttbr_base
Definition: armv8.h:202
target_addr_t debug_base
Definition: armv8.h:188
struct reg_cache * core_cache
Definition: armv8.h:184
uint8_t cpu_id
Definition: armv8.h:196
enum run_control_op last_run_control_op
Definition: armv8.h:209
struct armv8_mmu_common armv8_mmu
Definition: armv8.h:204
int(* read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value)
Definition: armv8.h:212
int(* write_reg_u128)(struct armv8_common *armv8, int num, uint64_t lvalue, uint64_t hvalue)
Definition: armv8.h:218
struct adiv5_ap * debug_ap
Definition: armv8.h:189
int(* read_reg_u128)(struct armv8_common *armv8, int num, uint64_t *lvalue, uint64_t *hvalue)
Definition: armv8.h:216
unsigned int common_magic
Definition: armv8.h:181
struct arm_cti * cti
Definition: armv8.h:206
void(* pre_restore_context)(struct target *target)
Definition: armv8.h:224
int(* examine_debug_reason)(struct target *target)
Definition: armv8.h:221
int(* write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value)
Definition: armv8.h:213
uint8_t cluster_id
Definition: armv8.h:195
const uint32_t * opcodes
Definition: armv8.h:191
uint8_t pa_size
Definition: armv8.h:200
int(* post_debug_entry)(struct target *target)
Definition: armv8.h:222
uint8_t multi_processor_system
Definition: armv8.h:194
uint32_t base
Definition: armv8.h:124
uint32_t way
Definition: armv8.h:125
int32_t ttbr1_used
Definition: armv8.h:167
uint64_t ttbr0_mask
Definition: armv8.h:168
uint32_t mmu_enabled
Definition: armv8.h:177
uint32_t ttbr_mask[2]
Definition: armv8.h:171
uint32_t ttbcr
Definition: armv8.h:170
int(* read_physical_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: armv8.h:174
struct armv8_cache_common armv8_cache
Definition: armv8.h:176
uint32_t ttbr_range[2]
Definition: armv8.h:172
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
Definition: register.h:111
Definition: target.h:120
void * arch_info
Definition: target.h:169
uint64_t target_addr_t
Definition: types.h:335
#define container_of(ptr, type, member)
Cast a member of a structure out to the containing structure.
Definition: types.h:68
uint8_t cmd
Definition: vdebug.c:1
uint8_t count[4]
Definition: vdebug.c:22