This wraps an implementation of DPM primitives. More...
Data Fields | |
| struct arm * | arm |
| struct reg *(* | arm_reg_current )(struct arm *arm, unsigned regnum) |
| int(* | bpwp_disable )(struct arm_dpm *dpm, unsigned index_value) |
| Disables one breakpoint or watchpoint by clearing its hardware control registers. More... | |
| int(* | bpwp_enable )(struct arm_dpm *dpm, unsigned index_value, uint32_t addr, uint32_t control) |
| Enables one breakpoint or watchpoint by writing to the hardware registers. More... | |
| struct dpm_bp * | dbp |
| uint64_t | didr |
| Cache of DIDR. More... | |
| uint32_t | dscr |
| Recent value of DSCR. More... | |
| struct dpm_wp * | dwp |
| int(* | finish )(struct arm_dpm *dpm) |
| Invoke after a series of instruction operations. More... | |
| int(* | instr_cpsr_sync )(struct arm_dpm *dpm) |
| Optional core-specific operation invoked after CPSR writes. More... | |
| int(* | instr_execute )(struct arm_dpm *dpm, uint32_t opcode) |
| Runs one instruction. More... | |
| int(* | instr_read_data_dcc )(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data) |
| Runs one instruction, reading data from dcc after execution. More... | |
| int(* | instr_read_data_dcc_64 )(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data) |
| int(* | instr_read_data_r0 )(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data) |
| Runs one instruction, reading data from r0 after execution. More... | |
| int(* | instr_read_data_r0_64 )(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data) |
| int(* | instr_write_data_dcc )(struct arm_dpm *dpm, uint32_t opcode, uint32_t data) |
| Runs one instruction, writing data to DCC before execution. More... | |
| int(* | instr_write_data_dcc_64 )(struct arm_dpm *dpm, uint32_t opcode, uint64_t data) |
| int(* | instr_write_data_r0 )(struct arm_dpm *dpm, uint32_t opcode, uint32_t data) |
| Runs one instruction, writing data to R0 before execution. More... | |
| int(* | instr_write_data_r0_64 )(struct arm_dpm *dpm, uint32_t opcode, uint64_t data) |
| Runs one instruction, writing data to R0 before execution. More... | |
| unsigned int | last_el |
| Recent exception level on armv8. More... | |
| unsigned | nbp |
| unsigned | nwp |
| int(* | prepare )(struct arm_dpm *dpm) |
| Invoke before a series of instruction operations. More... | |
| target_addr_t | wp_addr |
| Target dependent watchpoint address. More... | |
Detailed Description
This wraps an implementation of DPM primitives.
Each interface provider supplies a structure like this, which is the glue between upper level code and the lower level hardware access.
It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with support for CPU register access.
Field Documentation
◆ arm
| struct arm* arm_dpm::arm |
Definition at line 48 of file arm_dpm.h.
Referenced by aarch64_dpm_setup(), arm11_dpm_deinit(), arm11_dpm_init(), arm_dpm_initialize(), arm_dpm_modeswitch(), arm_dpm_read_core_reg(), arm_dpm_read_current_registers(), arm_dpm_read_reg(), arm_dpm_report_dscr(), arm_dpm_report_wfar(), arm_dpm_setup(), arm_dpm_write_core_reg(), arm_dpm_write_dirty_registers(), armv8_dpm_handle_exception(), armv8_dpm_initialize(), armv8_dpm_modeswitch(), armv8_dpm_read_current_registers(), armv8_dpm_report_dscr(), armv8_dpm_setup(), armv8_dpm_write_dirty_registers(), armv8_read_reg_simdfp_aarch32(), armv8_write_reg_simdfp_aarch32(), cortex_a_bpwp_disable(), cortex_a_bpwp_enable(), cortex_a_deinit_target(), cortex_a_dpm_prepare(), cortex_a_dpm_setup(), cortex_a_instr_cpsr_sync(), decode_cache_reg(), dpm_maybe_update_bpwp(), dpmv8_bpwp_disable(), dpmv8_dpm_prepare(), dpmv8_exec_opcode(), dpmv8_instr_cpsr_sync(), dpmv8_instr_read_data_dcc(), dpmv8_instr_read_data_dcc_64(), dpmv8_instr_read_data_r0(), dpmv8_instr_read_data_r0_64(), dpmv8_instr_write_data_dcc(), dpmv8_instr_write_data_dcc_64(), dpmv8_instr_write_data_r0(), dpmv8_instr_write_data_r0_64(), dpmv8_maybe_update_bpwp(), dpmv8_read_reg(), and dpmv8_write_reg().
◆ arm_reg_current
Definition at line 95 of file arm_dpm.h.
Referenced by armv8_dpm_setup().
◆ bpwp_disable
| int(* arm_dpm::bpwp_disable) (struct arm_dpm *dpm, unsigned index_value) |
Disables one breakpoint or watchpoint by clearing its hardware control registers.
Indices are the same ones accepted by bpwp_enable().
Definition at line 117 of file arm_dpm.h.
Referenced by arm11_dpm_init(), arm_dpm_initialize(), armv8_dpm_initialize(), armv8_dpm_setup(), cortex_a_dpm_setup(), dpm_maybe_update_bpwp(), and dpmv8_maybe_update_bpwp().
◆ bpwp_enable
| int(* arm_dpm::bpwp_enable) (struct arm_dpm *dpm, unsigned index_value, uint32_t addr, uint32_t control) |
Enables one breakpoint or watchpoint by writing to the hardware registers.
The specified breakpoint/watchpoint must currently be disabled. Indices 0..15 are used for breakpoints; indices 16..31 are for watchpoints.
Definition at line 109 of file arm_dpm.h.
Referenced by arm11_dpm_init(), cortex_a_dpm_setup(), dpm_add_breakpoint(), dpm_add_watchpoint(), dpm_maybe_update_bpwp(), dpmv8_add_breakpoint(), dpmv8_add_watchpoint(), and dpmv8_maybe_update_bpwp().
◆ dbp
| struct dpm_bp* arm_dpm::dbp |
Definition at line 126 of file arm_dpm.h.
Referenced by aarch64_deinit_target(), arm11_dpm_deinit(), arm_dpm_initialize(), arm_dpm_setup(), arm_dpm_write_dirty_registers(), armv8_dpm_initialize(), armv8_dpm_setup(), armv8_dpm_write_dirty_registers(), cortex_a_deinit_target(), dpm_add_breakpoint(), dpm_remove_breakpoint(), dpmv8_add_breakpoint(), and dpmv8_remove_breakpoint().
◆ didr
| uint64_t arm_dpm::didr |
Cache of DIDR.
Definition at line 51 of file arm_dpm.h.
Referenced by aarch64_dpm_setup(), arm11_dpm_init(), arm_dpm_setup(), armv8_dpm_setup(), and cortex_a_dpm_setup().
◆ dscr
| uint32_t arm_dpm::dscr |
Recent value of DSCR.
Definition at line 137 of file arm_dpm.h.
Referenced by aarch64_debug_entry(), aarch64_read_cpu_memory(), aarch64_write_cpu_memory(), arm_dpm_report_dscr(), armv8_dpm_handle_exception(), armv8_dpm_report_dscr(), cortex_a_deinit_target(), dpmv8_dpm_prepare(), dpmv8_exec_opcode(), dpmv8_instr_cpsr_sync(), dpmv8_instr_read_data_dcc(), dpmv8_instr_read_data_dcc_64(), dpmv8_instr_read_data_r0(), dpmv8_instr_read_data_r0_64(), and dpmv8_instr_write_data_r0_64().
◆ dwp
| struct dpm_wp* arm_dpm::dwp |
Definition at line 127 of file arm_dpm.h.
Referenced by aarch64_deinit_target(), arm11_dpm_deinit(), arm_dpm_initialize(), arm_dpm_setup(), arm_dpm_write_dirty_registers(), armv8_dpm_initialize(), armv8_dpm_setup(), armv8_dpm_write_dirty_registers(), cortex_a_deinit_target(), dpm_add_watchpoint(), dpm_remove_watchpoint(), dpm_watchpoint_setup(), dpmv8_add_watchpoint(), dpmv8_remove_watchpoint(), and dpmv8_watchpoint_setup().
◆ finish
| int(* arm_dpm::finish) (struct arm_dpm *dpm) |
Invoke after a series of instruction operations.
Definition at line 57 of file arm_dpm.h.
Referenced by arm11_dpm_init(), arm_dpm_full_context(), arm_dpm_read_core_reg(), arm_dpm_read_current_registers(), arm_dpm_write_core_reg(), arm_dpm_write_dirty_registers(), arm_semihosting(), armv7a_identify_cache(), armv7a_l1_d_cache_clean_inval_all(), armv7a_l1_d_cache_clean_virt(), armv7a_l1_d_cache_flush_virt(), armv7a_l1_d_cache_inval_virt(), armv7a_l1_i_cache_inval_all(), armv7a_l1_i_cache_inval_virt(), armv7a_mmu_translate_va_pa(), armv7a_read_midr(), armv7a_read_mpidr(), armv7a_read_ttbcr(), armv7a_show_fault_registers(), armv8_cache_d_inner_clean_inval_all(), armv8_cache_d_inner_flush_virt(), armv8_cache_i_inner_inval_virt(), armv8_dpm_full_context(), armv8_dpm_read_core_reg(), armv8_dpm_read_current_registers(), armv8_dpm_setup(), armv8_dpm_write_core_reg(), armv8_dpm_write_dirty_registers(), armv8_identify_cache(), armv8_mmu_translate_va_pa(), armv8_read_mpidr(), armv8_show_fault_registers32(), cortex_a_dpm_setup(), dpm_mcr(), dpm_mrc(), dpmv8_mcr(), and dpmv8_mrc().
◆ instr_cpsr_sync
| int(* arm_dpm::instr_cpsr_sync) (struct arm_dpm *dpm) |
Optional core-specific operation invoked after CPSR writes.
Definition at line 80 of file arm_dpm.h.
Referenced by aarch64_debug_entry(), arm_dpm_modeswitch(), armv8_dpm_setup(), armv8_dpm_write_dirty_registers(), cortex_a_dpm_setup(), and dpm_write_reg().
◆ instr_execute
| int(* arm_dpm::instr_execute) (struct arm_dpm *dpm, uint32_t opcode) |
Runs one instruction.
Definition at line 60 of file arm_dpm.h.
Referenced by aarch64_read_cpu_memory_fast(), aarch64_read_cpu_memory_slow(), aarch64_write_cpu_memory_slow(), armv8_dpm_modeswitch(), and armv8_dpm_setup().
◆ instr_read_data_dcc
| int(* arm_dpm::instr_read_data_dcc) (struct arm_dpm *dpm, uint32_t opcode, uint32_t *data) |
Runs one instruction, reading data from dcc after execution.
Definition at line 85 of file arm_dpm.h.
Referenced by arm11_dpm_init(), arm_dpm_read_reg(), armv8_dpm_setup(), armv8_read_reg32(), armv8_read_reg_simdfp_aarch32(), cortex_a_dpm_setup(), and dpm_read_reg_u64().
◆ instr_read_data_dcc_64
| int(* arm_dpm::instr_read_data_dcc_64) (struct arm_dpm *dpm, uint32_t opcode, uint64_t *data) |
Definition at line 88 of file arm_dpm.h.
Referenced by armv8_dpm_setup(), and armv8_read_reg().
◆ instr_read_data_r0
| int(* arm_dpm::instr_read_data_r0) (struct arm_dpm *dpm, uint32_t opcode, uint32_t *data) |
Runs one instruction, reading data from r0 after execution.
Definition at line 92 of file arm_dpm.h.
Referenced by aarch64_post_debug_entry(), arm11_dpm_init(), arm_dpm_read_current_registers(), arm_dpm_read_reg(), arm_semihosting(), armv7a_identify_cache(), armv7a_mmu_translate_va_pa(), armv7a_read_midr(), armv7a_read_mpidr(), armv7a_read_ttbcr(), armv7a_show_fault_registers(), armv8_dpm_read_current_registers(), armv8_dpm_setup(), armv8_identify_cache(), armv8_read_mpidr(), armv8_read_reg(), armv8_read_reg32(), armv8_read_reg_simdfp_aarch32(), armv8_show_fault_registers32(), cortex_a_dpm_setup(), decode_cache_reg(), dpm_mrc(), dpm_read_reg_u64(), and dpmv8_mrc().
◆ instr_read_data_r0_64
| int(* arm_dpm::instr_read_data_r0_64) (struct arm_dpm *dpm, uint32_t opcode, uint64_t *data) |
Definition at line 95 of file arm_dpm.h.
Referenced by armv8_dpm_setup(), armv8_mmu_translate_va_pa(), armv8_read_reg(), and armv8_read_reg_simdfp_aarch64().
◆ instr_write_data_dcc
| int(* arm_dpm::instr_write_data_dcc) (struct arm_dpm *dpm, uint32_t opcode, uint32_t data) |
Runs one instruction, writing data to DCC before execution.
Definition at line 65 of file arm_dpm.h.
Referenced by aarch64_read_cpu_memory(), aarch64_write_cpu_memory(), arm11_dpm_init(), armv8_dpm_setup(), armv8_write_reg32(), armv8_write_reg_simdfp_aarch32(), cortex_a_dpm_setup(), dpm_write_reg(), and dpm_write_reg_u64().
◆ instr_write_data_dcc_64
| int(* arm_dpm::instr_write_data_dcc_64) (struct arm_dpm *dpm, uint32_t opcode, uint64_t data) |
Definition at line 68 of file arm_dpm.h.
Referenced by aarch64_read_cpu_memory(), aarch64_write_cpu_memory(), armv8_dpm_setup(), and armv8_write_reg().
◆ instr_write_data_r0
| int(* arm_dpm::instr_write_data_r0) (struct arm_dpm *dpm, uint32_t opcode, uint32_t data) |
Runs one instruction, writing data to R0 before execution.
Definition at line 72 of file arm_dpm.h.
Referenced by aarch64_mmu_modify(), aarch64_restore_system_control_reg(), arm11_dpm_init(), arm_dpm_modeswitch(), armv7a_identify_cache(), armv7a_l1_d_cache_clean_virt(), armv7a_l1_d_cache_flush_level(), armv7a_l1_d_cache_flush_virt(), armv7a_l1_d_cache_inval_virt(), armv7a_l1_i_cache_inval_all(), armv7a_l1_i_cache_inval_virt(), armv7a_mmu_translate_va_pa(), armv8_cache_d_inner_flush_level(), armv8_dpm_modeswitch(), armv8_dpm_setup(), armv8_identify_cache(), armv8_write_reg(), armv8_write_reg32(), armv8_write_reg_simdfp_aarch32(), cortex_a_dpm_setup(), decode_cache_reg(), dpm_mcr(), dpm_write_pc_core_state(), dpm_write_reg(), dpm_write_reg_u64(), and dpmv8_mcr().
◆ instr_write_data_r0_64
| int(* arm_dpm::instr_write_data_r0_64) (struct arm_dpm *dpm, uint32_t opcode, uint64_t data) |
Runs one instruction, writing data to R0 before execution.
Definition at line 76 of file arm_dpm.h.
Referenced by armv8_cache_d_inner_flush_virt(), armv8_cache_i_inner_inval_virt(), armv8_dpm_setup(), armv8_mmu_translate_va_pa(), armv8_write_reg(), and armv8_write_reg_simdfp_aarch64().
◆ last_el
| unsigned int arm_dpm::last_el |
Recent exception level on armv8.
Definition at line 140 of file arm_dpm.h.
Referenced by armv8_dpm_modeswitch(), armv8_dpm_read_current_registers(), armv8_dpm_report_dscr(), armv8_dpm_write_dirty_registers(), and dpmv8_exec_opcode().
◆ nbp
| unsigned arm_dpm::nbp |
Definition at line 124 of file arm_dpm.h.
Referenced by arm11_dpm_init(), arm_dpm_initialize(), arm_dpm_setup(), arm_dpm_write_dirty_registers(), armv8_dpm_initialize(), armv8_dpm_setup(), armv8_dpm_write_dirty_registers(), dpm_add_breakpoint(), dpm_remove_breakpoint(), dpmv8_add_breakpoint(), and dpmv8_remove_breakpoint().
◆ nwp
| unsigned arm_dpm::nwp |
Definition at line 125 of file arm_dpm.h.
Referenced by arm11_dpm_init(), arm_dpm_initialize(), arm_dpm_setup(), arm_dpm_write_dirty_registers(), armv8_dpm_initialize(), armv8_dpm_setup(), armv8_dpm_write_dirty_registers(), dpm_add_watchpoint(), dpm_remove_watchpoint(), dpmv8_add_watchpoint(), and dpmv8_remove_watchpoint().
◆ prepare
| int(* arm_dpm::prepare) (struct arm_dpm *dpm) |
Invoke before a series of instruction operations.
Definition at line 54 of file arm_dpm.h.
Referenced by arm11_dpm_init(), arm_dpm_full_context(), arm_dpm_read_core_reg(), arm_dpm_read_current_registers(), arm_dpm_write_core_reg(), arm_dpm_write_dirty_registers(), arm_semihosting(), armv7a_identify_cache(), armv7a_l1_d_cache_clean_inval_all(), armv7a_l1_d_cache_clean_virt(), armv7a_l1_d_cache_flush_virt(), armv7a_l1_d_cache_inval_virt(), armv7a_l1_i_cache_inval_all(), armv7a_l1_i_cache_inval_virt(), armv7a_mmu_translate_va_pa(), armv7a_read_midr(), armv7a_read_mpidr(), armv7a_read_ttbcr(), armv7a_show_fault_registers(), armv8_cache_d_inner_clean_inval_all(), armv8_cache_d_inner_flush_virt(), armv8_cache_i_inner_inval_virt(), armv8_dpm_full_context(), armv8_dpm_read_core_reg(), armv8_dpm_read_current_registers(), armv8_dpm_setup(), armv8_dpm_write_core_reg(), armv8_dpm_write_dirty_registers(), armv8_identify_cache(), armv8_mmu_translate_va_pa(), armv8_read_mpidr(), armv8_show_fault_registers32(), cortex_a_dpm_setup(), dpm_mcr(), dpm_mrc(), dpmv8_mcr(), and dpmv8_mrc().
◆ wp_addr
| target_addr_t arm_dpm::wp_addr |
Target dependent watchpoint address.
Either the address of the instruction which triggered a watchpoint or the memory address whose access triggered a watchpoint.
Definition at line 134 of file arm_dpm.h.
Referenced by aarch64_debug_entry(), aarch64_hit_watchpoint(), arm11_arch_state(), and arm_dpm_report_wfar().
The documentation for this struct was generated from the following file:
