34 uint32_t dfsr, ifsr, dfar, ifar;
71 LOG_USER(
"Data fault registers DFSR: %8.8" PRIx32
72 ", DFAR: %8.8" PRIx32, dfsr, dfar);
73 LOG_USER(
"Instruction fault registers IFSR: %8.8" PRIx32
74 ", IFAR: %8.8" PRIx32, ifsr, ifar);
99 armv7a->
rev = (midr & 0xf);
100 armv7a->
partnum = (midr >> 4) & 0xfff;
101 armv7a->
arch = (midr >> 16) & 0xf;
102 armv7a->
variant = (midr >> 20) & 0xf;
104 LOG_DEBUG(
"%s rev %" PRIx32
", partnum %" PRIx32
", arch %" PRIx32
105 ", variant %" PRIx32
", implementor %" PRIx32,
122 uint32_t ttbcr, ttbcr_n;
139 ttbcr_n = ttbcr & 0x7;
143 for (ttbidx = 0; ttbidx < 2; ttbidx++) {
167 if ((armv7a->
partnum & 0xf) == 0) {
172 LOG_DEBUG(
"ttbr1 %s, ttbr0_mask %" PRIx32
" ttbr1_mask %" PRIx32,
173 (ttbcr_n != 0) ?
"used" :
"not used",
190 l2x_cache->
base = base;
191 l2x_cache->
way = way;
195 LOG_INFO(
"outer cache already initialized\n");
204 LOG_ERROR(
"smp target : outer cache already initialized\n");
238 if (armv7a_cache->
info == -1) {
243 for (cl = 0; cl < armv7a_cache->
loc; cl++) {
246 if (arch->
ctype & 1) {
248 "L%d I-Cache: linelen %" PRIu32
249 ", associativity %" PRIu32
251 ", cachesize %" PRIu32
" KBytes",
259 if (arch->
ctype >= 2) {
261 "L%d D-Cache: linelen %" PRIu32
262 ", associativity %" PRIu32
264 ", cachesize %" PRIu32
" KBytes",
274 command_print(
cmd,
"Outer unified cache Base Address 0x%" PRIx32
", %" PRIu32
" ways",
275 l2x_cache->
base, l2x_cache->
way);
305 armv7a->
cpu_id = mpidr & 0xf;
306 LOG_INFO(
"%s: MPIDR level2 %x, cluster %x, core %x, %s, %s",
315 LOG_ERROR(
"MPIDR not in multiprocessor format");
331 (cl << 1) | (ct == 1 ? 1 : 0));
347 size.linelen = 16 << (cache_reg & 0x7);
348 size.associativity = ((cache_reg >> 3) & 0x3ff) + 1;
349 size.nsets = ((cache_reg >> 13) & 0x7fff) + 1;
353 size.index_shift = (cache_reg & 0x7) + 4;
354 size.index = (cache_reg >> 13) & 0x7fff;
355 size.way = ((cache_reg >> 3) & 0x3ff);
357 while (((
size.way << i) & 0x80000000) == 0)
370 uint32_t csselr, clidr, ctr;
388 cache->
iminline = 4UL << (ctr & 0xf);
389 cache->
dminline = 4UL << ((ctr & 0xf0000) >> 16);
390 LOG_DEBUG(
"ctr %" PRIx32
" ctr.iminline %" PRIu32
" ctr.dminline %" PRIu32,
401 cache->
loc = (clidr & 0x7000000) >> 24;
402 LOG_DEBUG(
"Number of cache levels to PoC %" PRId32, cache->
loc);
413 for (cl = 0; cl < cache->
loc; clidr >>= 3, cl++) {
430 LOG_DEBUG(
"data/unified cache index %" PRIu32
" << %" PRIu32
", way %" PRIu32
" << %" PRIu32,
436 LOG_DEBUG(
"cacheline %" PRIu32
" bytes %" PRIu32
" KBytes asso %" PRIu32
" ways",
450 LOG_DEBUG(
"instruction cache index %" PRIu32
" << %" PRIu32
", way %" PRIu32
" << %" PRIu32,
456 LOG_DEBUG(
"cacheline %" PRIu32
" bytes %" PRIu32
" KBytes asso %" PRIu32
" ways",
497 LOG_ERROR(
"Failed to read VCR register\n");
510 LOG_ERROR(
"Failed to write VCR register\n");
534 static const char *
state[] = {
535 "disabled",
"enabled"
542 LOG_ERROR(
"BUG: called for a non-ARMv7A target");
549 LOG_USER(
"D-Cache: %s, I-Cache: %s",
553 LOG_USER(
"MMU: %s, D-Cache: %s, I-Cache: %s",
568 .handler = handle_cache_l2x,
570 .help =
"configure l2x cache",
571 .usage =
"[base_addr] [number_of_way]",
579 .
name =
"cache_config",
581 .help =
"cache configuration for a target",
int arm_arch_state(struct target *target)
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Synchronous read of a word from memory or a system register.
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Synchronous write of a word to memory or a system register.
Macros used to generate various ARM or Thumb opcodes.
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
static const struct command_registration l2_cache_commands[]
int armv7a_handle_cache_info_command(struct command_invocation *cmd, struct armv7a_cache_common *armv7a_cache)
int armv7a_read_ttbcr(struct target *target)
int armv7a_arch_state(struct target *target)
static const struct command_registration l2x_cache_command_handlers[]
static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t *cache_reg)
static struct armv7a_cachesize decode_cache_reg(uint32_t cache_reg)
const struct command_registration armv7a_command_handlers[]
static void armv7a_show_fault_registers(struct target *target)
static int armv7a_read_mpidr(struct target *target)
COMMAND_HANDLER(handle_cache_l2x)
int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
static int armv7a_read_midr(struct target *target)
static int armv7a_setup_semihosting(struct target *target, int enable)
int armv7a_identify_cache(struct target *target)
#define ARMV7_COMMON_MAGIC
static struct armv7a_common * target_to_armv7a(struct target *target)
int armv7a_cache_auto_flush_all_data(struct target *target)
const struct command_registration arm7a_cache_command_handlers[]
#define CACHE_LEVEL_HAS_UNIFIED_CACHE
#define CACHE_LEVEL_HAS_I_CACHE
#define CACHE_LEVEL_HAS_D_CACHE
Support functions to access arbitrary bits in a byte array.
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
#define LOG_USER(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
size_t size
Size of the control block search area.
#define foreach_smp_target(pos, head)
This wraps an implementation of DPM primitives.
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
int(* instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
Represents a generic ARM core, with standard application registers.
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
int(* setup_semihosting)(struct target *target, int enable)
struct arm_dpm * dpm
Handle for the debug module, if one is present.
unsigned int common_magic
struct target * target
Backpointer to the target.
struct armv7a_cachesize i_size
struct armv7a_cachesize d_u_size
int(* flush_all_data_cache)(struct target *target)
struct armv7a_arch_cache arch[6]
uint8_t multi_threading_processor
uint8_t multi_processor_system
struct armv7a_mmu_common armv7a_mmu
struct adiv5_ap * debug_ap
unsigned int common_magic
struct armv7a_cache_common armv7a_cache
When run_command is called, a new instance will be created on the stack, filled with the proper value...
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
struct list_head * smp_targets
struct target * get_current_target(struct command_context *cmd_ctx)
static const char * target_name(struct target *target)
Returns the instance-specific name of the specified target.