This file implements support for the ARM Debug Interface version 5 (ADIv5) debugging architecture. More...

Include dependency graph for arm_adi_v5.c:

Data Structures
struct	cs_component_vals
	Holds registers and coordinates of a CoreSight component. More...

struct	dap_lookup_data

struct	dap_part_nums

struct	rtp_ops
	Actions/operations to be executed while parsing ROM tables. More...

Macros
#define	ARCH_ID(architect, archid)

#define	CORESIGHT_COMPONENT_FOUND (1)
	Value used only during lookup of a CoreSight component in ROM table. More...

#define	DAP_POWER_DOMAIN_TIMEOUT (10)

#define	DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK \| ARM_CS_C9_DEVARCH_ARCHID_MASK)

#define	DEVARCH_MEM_AP ARCH_ID(ARM_ID, 0x0A17)

#define	DEVARCH_ROM_C_0X9 ARCH_ID(ARM_ID, 0x0AF7)

#define	DEVARCH_UNKNOWN_V2 ARCH_ID(ARM_ID, 0x0A47)

#define	ROM_TABLE_MAX_DEPTH (16)

Enumerations
enum	adiv5_cfg_param { CFG_DAP , CFG_AP_NUM , CFG_BASEADDR , CFG_CTIBASE }

enum	coresight_access_mode { CS_ACCESS_AP , CS_ACCESS_MEM_AP }
	Method to access the CoreSight component. More...

Functions
static struct adiv5_ap *	_dap_get_ap (struct adiv5_dap *dap, uint64_t ap_num)

int	adiv5_jim_configure (struct target target, struct jim_getopt_info goi)

int	adiv5_jim_mem_ap_spot_configure (struct adiv5_mem_ap_spot cfg, struct jim_getopt_info goi)

static int	adiv5_jim_spot_configure (struct jim_getopt_info goi, struct adiv5_dap dap_p, uint64_t ap_num_p, uint32_t *base_p)

int	adiv5_mem_ap_spot_init (struct adiv5_mem_ap_spot *p)

int	adiv5_verify_config (struct adiv5_private_config *pc)

int	adiv6_dap_read_baseptr (struct command_invocation cmd, struct adiv5_dap dap, uint64_t *baseptr)

static const char *	ap_type_to_description (enum ap_type type)

static const char *	class0x9_devarch_description (uint32_t devarch)

	COMMAND_HANDLER (dap_apcsw_command)

	COMMAND_HANDLER (dap_apid_command)

	COMMAND_HANDLER (dap_apreg_command)

	COMMAND_HANDLER (dap_apsel_command)

	COMMAND_HANDLER (dap_baseaddr_command)

	COMMAND_HANDLER (dap_dpreg_command)

	COMMAND_HANDLER (dap_memaccess_command)

	COMMAND_HANDLER (dap_nu_npcx_quirks_command)

	COMMAND_HANDLER (dap_ti_be_32_quirks_command)

	COMMAND_HANDLER (handle_dap_info_command)

static int	dap_devtype_display (struct command_invocation *cmd, uint32_t devtype)

int	dap_dp_init (struct adiv5_dap *dap)
	Initialize a DAP. More...

int	dap_dp_init_or_reconnect (struct adiv5_dap *dap)
	Initialize a DAP or do reconnect if DAP is not accessible. More...

int	dap_find_get_ap (struct adiv5_dap dap, enum ap_type type_to_find, struct adiv5_ap *ap_out)

struct adiv5_ap *	dap_get_ap (struct adiv5_dap *dap, uint64_t ap_num)

struct adiv5_ap *	dap_get_config_ap (struct adiv5_dap *dap, uint64_t ap_num)

static int	dap_get_debugbase (struct adiv5_ap ap, target_addr_t dbgbase, uint32_t *apid)

static int	dap_info_ap_header (struct adiv5_ap ap, int depth, void priv)

int	dap_info_command (struct command_invocation cmd, struct adiv5_ap ap)

static int	dap_info_cs_component (int retval, struct cs_component_vals v, int depth, void priv)

static int	dap_info_mem_ap_header (int retval, struct adiv5_ap ap, target_addr_t dbgbase, uint32_t apid, int depth, void priv)

static int	dap_info_rom_table_entry (int retval, int depth, unsigned int offset, uint64_t romentry, void *priv)

void	dap_invalidate_cache (struct adiv5_dap *dap)
	Invalidate cached DP select and cached TAR and CSW of all APs. More...

int	dap_lookup_cs_component (struct adiv5_ap ap, uint8_t type, target_addr_t addr, int32_t core_id)

static int	dap_lookup_cs_component_cs_component (int retval, struct cs_component_vals v, int depth, void priv)

int	dap_put_ap (struct adiv5_ap *ap)

static int	dap_queue_read_reg (enum coresight_access_mode mode, struct adiv5_ap ap, uint64_t component_base, unsigned int reg, uint32_t value)
	Helper to read CoreSight component's registers, either on the bus behind a MEM-AP or directly in the AP. More...

int	dap_to_jtag (struct adiv5_dap *dap)
	Put the debug link into JTAG mode, if the target supports it. More...

int	dap_to_swd (struct adiv5_dap *dap)
	Put the debug link into SWD mode, if the target supports it. More...

static bool	is_ap_in_use (struct adiv5_ap *ap)

bool	is_ap_num_valid (struct adiv5_dap *dap, uint64_t ap_num)

static uint32_t	max_tar_block_size (uint32_t tar_autoincr_block, target_addr_t address)

static uint32_t	mem_ap_get_tar_increment (struct adiv5_ap *ap)

int	mem_ap_init (struct adiv5_ap *ap)
	Initialize a DAP. More...

static int	mem_ap_read (struct adiv5_ap ap, uint8_t buffer, uint32_t size, uint32_t count, target_addr_t adr, bool addrinc)
	Synchronous read of a block of memory, using a specific access size. More...

int	mem_ap_read_atomic_u32 (struct adiv5_ap ap, target_addr_t address, uint32_t value)
	Synchronous read of a word from memory or a system register. More...

int	mem_ap_read_buf (struct adiv5_ap ap, uint8_t buffer, uint32_t size, uint32_t count, target_addr_t address)

int	mem_ap_read_buf_noincr (struct adiv5_ap ap, uint8_t buffer, uint32_t size, uint32_t count, target_addr_t address)

static int	mem_ap_read_tar (struct adiv5_ap ap, target_addr_t tar)

int	mem_ap_read_u32 (struct adiv5_ap ap, target_addr_t address, uint32_t value)
	Asynchronous (queued) read of a word from memory or a system register. More...

static int	mem_ap_setup_csw (struct adiv5_ap *ap, uint32_t csw)

static int	mem_ap_setup_tar (struct adiv5_ap *ap, target_addr_t tar)

static int	mem_ap_setup_transfer (struct adiv5_ap *ap, uint32_t csw, target_addr_t tar)
	Queue transactions setting up transfer parameters for the currently selected MEM-AP. More...

static void	mem_ap_update_tar_cache (struct adiv5_ap *ap)

static int	mem_ap_write (struct adiv5_ap ap, const uint8_t buffer, uint32_t size, uint32_t count, target_addr_t address, bool addrinc)
	Synchronous write of a block of memory, using a specific access size. More...

int	mem_ap_write_atomic_u32 (struct adiv5_ap *ap, target_addr_t address, uint32_t value)
	Synchronous write of a word to memory or a system register. More...

int	mem_ap_write_buf (struct adiv5_ap ap, const uint8_t buffer, uint32_t size, uint32_t count, target_addr_t address)

int	mem_ap_write_buf_noincr (struct adiv5_ap ap, const uint8_t buffer, uint32_t size, uint32_t count, target_addr_t address)

int	mem_ap_write_u32 (struct adiv5_ap *ap, target_addr_t address, uint32_t value)
	Asynchronous (queued) write of a word to memory or a system register. More...

static const struct dap_part_nums *	pidr_to_part_num (unsigned int designer_id, unsigned int part_num)

static int	rtp_ap (const struct rtp_ops ops, struct adiv5_ap ap, int depth)

static int	rtp_cs_component (enum coresight_access_mode mode, const struct rtp_ops ops, struct adiv5_ap ap, target_addr_t dbgbase, bool *is_mem_ap, int depth)

static int	rtp_ops_ap_header (const struct rtp_ops ops, struct adiv5_ap ap, int depth)
	Wrapper around struct rtp_ops::ap_header. More...

static int	rtp_ops_cs_component (const struct rtp_ops ops, int retval, struct cs_component_vals v, int depth)
	Wrapper around struct rtp_ops::cs_component. More...

static int	rtp_ops_mem_ap_header (const struct rtp_ops ops, int retval, struct adiv5_ap ap, uint64_t dbgbase, uint32_t apid, int depth)
	Wrapper around struct rtp_ops::mem_ap_header. More...

static int	rtp_ops_rom_table_entry (const struct rtp_ops *ops, int retval, int depth, unsigned int offset, uint64_t romentry)
	Wrapper around struct rtp_ops::rom_table_entry. More...

static int	rtp_read_cs_regs (enum coresight_access_mode mode, struct adiv5_ap ap, target_addr_t component_base, struct cs_component_vals v)
	Read the CoreSight registers needed during ROM Table Parsing (RTP). More...

static int	rtp_rom_loop (enum coresight_access_mode mode, const struct rtp_ops ops, struct adiv5_ap ap, target_addr_t base_address, int depth, unsigned int width, unsigned int max_entries)

Variables
struct {
const char * description

enum ap_type type

}	ap_types []

struct {
uint32_t arch_id

const char * description

}	class0x9_devarch []

static const char *	class_description [16]

const struct command_registration	dap_instance_commands []

static const struct dap_part_nums	dap_part_nums []

static const struct jim_nvp	nvp_config_opts []

Detailed Description

This file implements support for the ARM Debug Interface version 5 (ADIv5) debugging architecture.

Compared with previous versions, this includes a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message transport, and focuses on memory mapped resources as defined by the CoreSight architecture.

A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two basic components: a Debug Port (DP) transporting messages to and from a debugger, and an Access Port (AP) accessing resources. Three types of DP are defined. One uses only JTAG for communication, and is called JTAG-DP. One uses only SWD for communication, and is called SW-DP. The third can use either SWD or JTAG, and is called SWJ-DP. The most common type of AP is used to access memory mapped resources and is called a MEM-AP. Also a JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.

This programming interface allows DAP pipelined operations through a transaction queue. This primarily affects AP operations (such as using a MEM-AP to access memory or registers). If the current transaction has not finished by the time the next one must begin, and the ORUNDETECT bit is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and further AP operations will fail. There are two basic methods to avoid such overrun errors. One involves polling for status instead of using transaction pipelining. The other involves adding delays to ensure the AP has enough time to complete one operation before starting the next one. (For JTAG these delays are controlled by memaccess_tck.)

Definition in file arm_adi_v5.c.

Macro Definition Documentation

◆ ARCH_ID

#define ARCH_ID	(	architect,
		archid
	)

Value:

    ( \
    (((architect) << ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \
    (((archid) << ARM_CS_C9_DEVARCH_ARCHID_SHIFT) & ARM_CS_C9_DEVARCH_ARCHID_MASK) \
)

Definition at line 905 of file arm_adi_v5.c.

◆ CORESIGHT_COMPONENT_FOUND

#define CORESIGHT_COMPONENT_FOUND (1)

Value used only during lookup of a CoreSight component in ROM table.

Return CORESIGHT_COMPONENT_FOUND when component is found. Return ERROR_OK when component is not found yet. Return any other ERROR_* in case of error.

Definition at line 1739 of file arm_adi_v5.c.

◆ DAP_POWER_DOMAIN_TIMEOUT

#define DAP_POWER_DOMAIN_TIMEOUT (10)

Definition at line 649 of file arm_adi_v5.c.

◆ DEVARCH_ID_MASK

#define DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)

Definition at line 939 of file arm_adi_v5.c.

◆ DEVARCH_MEM_AP

#define DEVARCH_MEM_AP ARCH_ID(ARM_ID, 0x0A17)

Definition at line 940 of file arm_adi_v5.c.

◆ DEVARCH_ROM_C_0X9

#define DEVARCH_ROM_C_0X9 ARCH_ID(ARM_ID, 0x0AF7)

Definition at line 941 of file arm_adi_v5.c.

◆ DEVARCH_UNKNOWN_V2

#define DEVARCH_UNKNOWN_V2 ARCH_ID(ARM_ID, 0x0A47)

Definition at line 942 of file arm_adi_v5.c.

◆ ROM_TABLE_MAX_DEPTH

#define ROM_TABLE_MAX_DEPTH (16)

Definition at line 1731 of file arm_adi_v5.c.

Enumeration Type Documentation

◆ adiv5_cfg_param

enum adiv5_cfg_param

Enumerator
CFG_DAP
CFG_AP_NUM
CFG_BASEADDR
CFG_CTIBASE

Definition at line 2212 of file arm_adi_v5.c.

◆ coresight_access_mode

enum coresight_access_mode

Method to access the CoreSight component.

On ADIv5, CoreSight components are on the bus behind a MEM-AP. On ADIv6, CoreSight components can either be on the bus behind a MEM-AP or directly in the AP.

Enumerator
CS_ACCESS_AP
CS_ACCESS_MEM_AP

Definition at line 1200 of file arm_adi_v5.c.

Function Documentation

◆ _dap_get_ap()

static struct adiv5_ap* _dap_get_ap	(	struct adiv5_dap *	dap,
		uint64_t	ap_num
	)

static

Definition at line 1057 of file arm_adi_v5.c.

References adiv5_dap::ap, adiv5_ap::ap_num, adiv5_ap::dap, DP_APSEL_MAX, is_adiv6(), is_ap_in_use(), is_ap_num_valid(), LOG_ERROR, NULL, and adiv5_ap::refcount.

Referenced by dap_get_ap(), and dap_get_config_ap().

◆ adiv5_jim_configure()

int adiv5_jim_configure	(	struct target *	target,
		struct jim_getopt_info *	goi
	)

Definition at line 2330 of file arm_adi_v5.c.

References adiv5_jim_spot_configure(), adiv5_private_config::ap_num, adiv5_private_config::dap, target::dap_configured, DP_APSEL_INVALID, target::has_dap, jim_getopt_info::interp, LOG_ERROR, NULL, target::private_config, adiv5_dap::tap, target::tap, and target::tap_configured.

Referenced by aarch64_jim_configure(), and xtensa_chip_jim_configure().

◆ adiv5_jim_mem_ap_spot_configure()

int adiv5_jim_mem_ap_spot_configure	(	struct adiv5_mem_ap_spot *	cfg,
		struct jim_getopt_info *	goi
	)

Definition at line 2377 of file arm_adi_v5.c.

References adiv5_jim_spot_configure(), adiv5_mem_ap_spot::ap_num, adiv5_mem_ap_spot::base, and adiv5_mem_ap_spot::dap.

Referenced by arm_tpiu_swo_configure(), and cti_configure().

◆ adiv5_jim_spot_configure()

static int adiv5_jim_spot_configure	(	struct jim_getopt_info *	goi,
		struct adiv5_dap **	dap_p,
		uint64_t *	ap_num_p,
		uint32_t *	base_p
	)

static

Definition at line 2227 of file arm_adi_v5.c.

References adiv5_dap_name(), jim_getopt_info::argc, jim_getopt_info::argv, CFG_AP_NUM, CFG_BASEADDR, CFG_CTIBASE, CFG_DAP, dap_instance_by_jim_obj(), DP_APSEL_INVALID, DP_APSEL_MAX, jim_getopt_info::interp, jim_getopt_info::isconfigure, jim_getopt_obj(), jim_getopt_wide(), jim_nvp_name2value_obj(), LOG_WARNING, NULL, nvp_config_opts, and jim_nvp::value.

Referenced by adiv5_jim_configure(), and adiv5_jim_mem_ap_spot_configure().

◆ adiv5_mem_ap_spot_init()

int adiv5_mem_ap_spot_init ( struct adiv5_mem_ap_spot * p )

Definition at line 2383 of file arm_adi_v5.c.

References adiv5_mem_ap_spot::ap_num, adiv5_mem_ap_spot::base, adiv5_mem_ap_spot::dap, DP_APSEL_INVALID, ERROR_OK, and NULL.

Referenced by cti_create(), and jim_arm_tpiu_swo_create().

◆ adiv5_verify_config()

int adiv5_verify_config ( struct adiv5_private_config * pc )

Definition at line 2366 of file arm_adi_v5.c.

References adiv5_private_config::dap, ERROR_FAIL, and ERROR_OK.

Referenced by aarch64_target_create(), cortex_m_target_create(), cortex_r4_target_create(), and xtensa_chip_target_create().

◆ adiv6_dap_read_baseptr()

int adiv6_dap_read_baseptr	(	struct command_invocation *	cmd,
		struct adiv5_dap *	dap,
		uint64_t *	baseptr
	)

Definition at line 1168 of file arm_adi_v5.c.

References adiv5_dap::asize, cmd, command_print(), dap_dp_read_atomic(), dap_queue_dp_read(), DP_BASEPTR0, DP_BASEPTR0_VALID, DP_BASEPTR1, ERROR_FAIL, and ERROR_OK.

Referenced by COMMAND_HANDLER().

◆ ap_type_to_description()

static const char* ap_type_to_description ( enum ap_type type )

static

Definition at line 971 of file arm_adi_v5.c.

References ap_types, ARRAY_SIZE, and type.

Referenced by dap_find_get_ap(), and dap_info_mem_ap_header().

◆ class0x9_devarch_description()

static const char* class0x9_devarch_description ( uint32_t devarch )

static

Definition at line 944 of file arm_adi_v5.c.

References ARM_CS_C9_DEVARCH_PRESENT, ARRAY_SIZE, class0x9_devarch, description, and DEVARCH_ID_MASK.

Referenced by dap_info_cs_component().

◆ COMMAND_HANDLER() [1/10]

COMMAND_HANDLER ( dap_apcsw_command )

Definition at line 2557 of file arm_adi_v5.c.

References adiv5_get_dap(), adiv5_dap::apsel, CMD, CMD_ARGC, CMD_ARGV, CMD_DATA, COMMAND_PARSE_NUMBER, command_print(), CSW_ADDRINC_MASK, CSW_AHB_DEFAULT, adiv5_ap::csw_default, CSW_SIZE_MASK, adiv5_ap::dap, dap_get_ap(), dap_get_config_ap(), dap_put_ap(), ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, and LOG_ERROR.

◆ COMMAND_HANDLER() [2/10]

COMMAND_HANDLER ( dap_apid_command )

Definition at line 2614 of file arm_adi_v5.c.

References adiv5_get_dap(), AP_REG_IDR, adiv5_dap::apsel, CMD, CMD_ARGC, CMD_ARGV, CMD_DATA, COMMAND_PARSE_NUMBER, command_print(), adiv5_ap::dap, dap_get_ap(), dap_put_ap(), dap_queue_ap_read(), dap_run(), ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, and is_ap_num_valid().

◆ COMMAND_HANDLER() [3/10]

COMMAND_HANDLER ( dap_apreg_command )

◆ COMMAND_HANDLER() [4/10]

COMMAND_HANDLER ( dap_apsel_command )

Definition at line 2533 of file arm_adi_v5.c.

References adiv5_get_dap(), adiv5_dap::apsel, CMD, CMD_ARGC, CMD_ARGV, CMD_DATA, COMMAND_PARSE_NUMBER, command_print(), ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, and is_ap_num_valid().

◆ COMMAND_HANDLER() [5/10]

COMMAND_HANDLER ( dap_baseaddr_command )

Definition at line 2434 of file arm_adi_v5.c.

References adiv5_get_dap(), adiv5_dap::apsel, adiv5_ap::cfg_reg, CMD, CMD_ARGC, CMD_ARGV, CMD_DATA, COMMAND_PARSE_NUMBER, command_print(), adiv5_ap::dap, dap_get_ap(), dap_put_ap(), dap_queue_ap_read(), dap_run(), ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, is_64bit_ap(), is_ap_num_valid(), MEM_AP_REG_BASE, MEM_AP_REG_BASE64, MEM_AP_REG_CFG, and MEM_AP_REG_CFG_INVALID.

◆ COMMAND_HANDLER() [6/10]

COMMAND_HANDLER ( dap_dpreg_command )

Definition at line 2738 of file arm_adi_v5.c.

References adiv5_get_dap(), CMD, CMD_ARGC, CMD_ARGV, CMD_DATA, COMMAND_PARSE_NUMBER, command_print(), dap_queue_dp_read(), dap_queue_dp_write(), dap_run(), ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, and ERROR_OK.

◆ COMMAND_HANDLER() [7/10]

COMMAND_HANDLER ( dap_memaccess_command )

Definition at line 2497 of file arm_adi_v5.c.

References adiv5_get_dap(), adiv5_dap::apsel, CMD, CMD_ARGC, CMD_ARGV, CMD_DATA, COMMAND_PARSE_NUMBER, command_print(), adiv5_ap::dap, dap_get_ap(), dap_get_config_ap(), dap_put_ap(), ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, and adiv5_ap::memaccess_tck.

◆ COMMAND_HANDLER() [8/10]

COMMAND_HANDLER ( dap_nu_npcx_quirks_command )

Definition at line 2778 of file arm_adi_v5.c.

References adiv5_get_dap(), CALL_COMMAND_HANDLER, CMD_DATA, and adiv5_dap::nu_npcx_quirks.

◆ COMMAND_HANDLER() [9/10]

COMMAND_HANDLER ( dap_ti_be_32_quirks_command )

Definition at line 2771 of file arm_adi_v5.c.

References adiv5_get_dap(), CALL_COMMAND_HANDLER, CMD_DATA, and adiv5_dap::ti_be_32_quirks.

◆ COMMAND_HANDLER() [10/10]

COMMAND_HANDLER ( handle_dap_info_command )

Definition at line 2391 of file arm_adi_v5.c.

References adiv5_get_dap(), adiv6_dap_read_baseptr(), adiv5_dap::apsel, CMD, CMD_ARGC, CMD_ARGV, CMD_DATA, COMMAND_PARSE_NUMBER, command_print(), adiv5_ap::dap, dap_get_ap(), dap_info_command(), dap_put_ap(), ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, is_adiv6(), and is_ap_num_valid().

◆ dap_devtype_display()

static int dap_devtype_display	(	struct command_invocation *	cmd,
		uint32_t	devtype
	)

static

Definition at line 1474 of file arm_adi_v5.c.

References ARM_CS_C9_DEVTYPE_MAJOR_MASK, ARM_CS_C9_DEVTYPE_MAJOR_SHIFT, ARM_CS_C9_DEVTYPE_MASK, ARM_CS_C9_DEVTYPE_SUB_MASK, ARM_CS_C9_DEVTYPE_SUB_SHIFT, cmd, command_print(), and ERROR_OK.

Referenced by dap_info_cs_component().

◆ dap_dp_init()

int dap_dp_init ( struct adiv5_dap * dap )

Initialize a DAP.

This sets up the power domains, prepares the DP for further use and activates overrun checking.

Parameters

dap	The DAP being initialized.

Definition at line 675 of file arm_adi_v5.c.

References adiv5_dap_name(), CDBGPWRUPACK, CDBGPWRUPREQ, CORUNDETECT, CSYSPWRUPACK, CSYSPWRUPREQ, dap_dp_poll_register(), dap_invalidate_cache(), DAP_POWER_DOMAIN_TIMEOUT, dap_queue_dp_read(), dap_queue_dp_write(), dap_run(), adiv5_dap::do_reconnect, DP_CTRL_STAT, adiv5_dap::dp_ctrl_stat, ERROR_OK, adiv5_dap::ignore_syspwrupack, LOG_DEBUG, NULL, and SSTICKYERR.

Referenced by dap_dp_init_or_reconnect(), handle_reset_halt(), jtag_connect(), stlink_dap_op_connect(), swd_connect(), and vdebug_dap_connect().

◆ dap_dp_init_or_reconnect()

int dap_dp_init_or_reconnect ( struct adiv5_dap * dap )

Initialize a DAP or do reconnect if DAP is not accessible.

Parameters

dap	The DAP being initialized.

Definition at line 752 of file arm_adi_v5.c.

References adiv5_dap_name(), CDBGPWRUPREQ, dap_ops::connect, CSYSPWRUPREQ, dap_dp_init(), dap_dp_read_atomic(), adiv5_dap::do_reconnect, DP_CTRL_STAT, adiv5_dap::dp_ctrl_stat, LOG_DEBUG, NULL, and adiv5_dap::ops.

Referenced by cortex_m_assert_reset(), and cortex_m_deassert_reset().

◆ dap_find_get_ap()

int dap_find_get_ap	(	struct adiv5_dap *	dap,
		enum ap_type	type_to_find,
		struct adiv5_ap **	ap_out
	)

Definition at line 1009 of file arm_adi_v5.c.

References adiv5_ap::ap_num, AP_REG_IDR, AP_TYPE_MASK, ap_type_to_description(), adiv5_ap::dap, dap_get_ap(), dap_put_ap(), dap_queue_ap_read(), dap_run(), DP_APSEL_MAX, ERROR_FAIL, ERROR_OK, is_adiv6(), and LOG_DEBUG.

Referenced by aarch64_examine_first(), cortex_a_examine_first(), cortex_m_find_mem_ap(), and xtensa_dm_examine().

◆ dap_get_ap()

struct adiv5_ap* dap_get_ap	(	struct adiv5_dap *	dap,
		uint64_t	ap_num
	)

Definition at line 1091 of file arm_adi_v5.c.

References _dap_get_ap(), adiv5_ap::ap_num, adiv5_ap::dap, LOG_DEBUG, and adiv5_ap::refcount.

Referenced by aarch64_examine_first(), ap_read_register(), ap_write_register(), COMMAND_HANDLER(), cortex_a_examine_first(), cortex_m_examine(), cti_create(), dap_find_get_ap(), jim_arm_tpiu_swo_enable(), kinetis_ke_mdm_read_register(), kinetis_ke_mdm_write_register(), kinetis_mdm_read_register(), kinetis_mdm_write_register(), mem_ap_examine(), rtp_rom_loop(), and xtensa_dm_examine().

◆ dap_get_config_ap()

struct adiv5_ap* dap_get_config_ap	(	struct adiv5_dap *	dap,
		uint64_t	ap_num
	)

Definition at line 1100 of file arm_adi_v5.c.

References _dap_get_ap(), adiv5_ap::ap_num, adiv5_ap::config_ap_never_release, adiv5_ap::dap, LOG_DEBUG, and adiv5_ap::refcount.

Referenced by COMMAND_HANDLER().

◆ dap_get_debugbase()

static int dap_get_debugbase	(	struct adiv5_ap *	ap,
		target_addr_t *	dbgbase,
		uint32_t *	apid
	)

static

Definition at line 1132 of file arm_adi_v5.c.

References adiv5_dap::ap, AP_REG_IDR, adiv5_ap::cfg_reg, adiv5_ap::dap, dap_queue_ap_read(), dap_run(), ERROR_OK, is_64bit_ap(), MEM_AP_REG_BASE, MEM_AP_REG_BASE64, MEM_AP_REG_CFG, and MEM_AP_REG_CFG_INVALID.

Referenced by rtp_ap().

◆ dap_info_ap_header()

static int dap_info_ap_header	(	struct adiv5_ap *	ap,
		int	depth,
		void *	priv
	)

static

Definition at line 1939 of file arm_adi_v5.c.

References adiv5_ap::ap_num, cmd, command_print(), ERROR_FAIL, ERROR_OK, priv, and ROM_TABLE_MAX_DEPTH.

Referenced by dap_info_command().

◆ dap_info_command()

int dap_info_command	(	struct command_invocation *	cmd,
		struct adiv5_ap *	ap
	)

Definition at line 2124 of file arm_adi_v5.c.

References rtp_ops::ap_header, cmd, dap_info_ap_header(), dap_info_cs_component(), dap_info_mem_ap_header(), dap_info_rom_table_entry(), and rtp_ap().

Referenced by COMMAND_HANDLER().

◆ dap_info_cs_component()

static int dap_info_cs_component	(	int	retval,
		struct cs_component_vals *	v,
		int	depth,
		void *	priv
	)

static

Definition at line 2006 of file arm_adi_v5.c.

References ARM_CS_C1_MEMTYPE_SYSMEM_MASK, ARM_CS_C9_DEVARCH_ARCHITECT, ARM_CS_C9_DEVARCH_PRESENT, ARM_CS_C9_DEVARCH_REVISION, ARM_CS_C9_DEVID_SYSMEM_MASK, ARM_CS_CIDR_CLASS, ARM_CS_CLASS_0X1_ROM_TABLE, ARM_CS_CLASS_0X9_CS_COMPONENT, ARM_CS_PIDR_DESIGNER, ARM_CS_PIDR_JEDEC, ARM_CS_PIDR_PART, ARM_CS_PIDR_SIZE, cs_component_vals::cid, class0x9_devarch_description(), class_description, cmd, command_print(), cs_component_vals::component_base, CS_ACCESS_MEM_AP, dap_devtype_display(), dap_part_nums::designer_id, cs_component_vals::devarch, DEVARCH_ID_MASK, DEVARCH_ROM_C_0X9, cs_component_vals::devid, cs_component_vals::devtype_memtype, ERROR_FAIL, ERROR_OK, dap_part_nums::full, is_valid_arm_cs_cidr(), jep106_manufacturer(), cs_component_vals::mode, dap_part_nums::part_num, cs_component_vals::pid, pidr_to_part_num(), priv, ROM_TABLE_MAX_DEPTH, size, TARGET_ADDR_FMT, and dap_part_nums::type.

Referenced by dap_info_command().

◆ dap_info_mem_ap_header()

static int dap_info_mem_ap_header	(	int	retval,
		struct adiv5_ap *	ap,
		target_addr_t	dbgbase,
		uint32_t	apid,
		int	depth,
		void *	priv
	)

static

Definition at line 1952 of file arm_adi_v5.c.

References adiv5_ap::ap_num, AP_REG_IDR_CLASS_MASK, AP_REG_IDR_CLASS_MEM_AP, AP_REG_IDR_CLASS_SHIFT, AP_TYPE_MASK, ap_type_to_description(), cmd, command_print(), ERROR_FAIL, ERROR_OK, is_64bit_ap(), priv, ROM_TABLE_MAX_DEPTH, and TARGET_ADDR_FMT.

Referenced by dap_info_command().

◆ dap_info_rom_table_entry()

static int dap_info_rom_table_entry	(	int	retval,
		int	depth,
		unsigned int	offset,
		uint64_t	romentry,
		void *	priv
	)

static

Definition at line 2092 of file arm_adi_v5.c.

References ARM_CS_ROMENTRY_PRESENT, cmd, command_print(), ERROR_OK, offset, and priv.

Referenced by dap_info_command().

◆ dap_invalidate_cache()

void dap_invalidate_cache ( struct adiv5_dap * dap )

Invalidate cached DP select and cached TAR and CSW of all APs.

Definition at line 656 of file arm_adi_v5.c.

References adiv5_dap::ap, adiv5_ap::csw_value, DP_APSEL_MAX, DP_SELECT_INVALID, adiv5_dap::last_read, NULL, adiv5_dap::select, and adiv5_ap::tar_valid.

Referenced by dap_dp_init(), stlink_dap_op_connect(), swd_connect_multidrop(), and swd_connect_single().

◆ dap_lookup_cs_component()

int dap_lookup_cs_component	(	struct adiv5_ap *	ap,
		uint8_t	type,
		target_addr_t *	addr,
		int32_t	core_id
	)

Definition at line 2178 of file arm_adi_v5.c.

References addr, rtp_ops::ap_header, dap_lookup_data::ap_num, adiv5_ap::ap_num, dap_lookup_data::component_base, CORESIGHT_COMPONENT_FOUND, dap_lookup_cs_component_cs_component(), ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, LOG_DEBUG, NULL, rtp_ap(), type, and dap_lookup_data::type.

Referenced by aarch64_examine_first(), and cortex_a_examine_first().

◆ dap_lookup_cs_component_cs_component()

static int dap_lookup_cs_component_cs_component	(	int	retval,
		struct cs_component_vals *	v,
		int	depth,
		void *	priv
	)

static

Definition at line 2148 of file arm_adi_v5.c.

References cs_component_vals::ap, dap_lookup_data::ap_num, adiv5_ap::ap_num, ARM_CS_C9_DEVTYPE_MASK, ARM_CS_CIDR_CLASS, ARM_CS_CLASS_0X9_CS_COMPONENT, cs_component_vals::cid, cs_component_vals::component_base, dap_lookup_data::component_base, CORESIGHT_COMPONENT_FOUND, cs_component_vals::devtype_memtype, ERROR_OK, dap_lookup_data::idx, is_valid_arm_cs_cidr(), priv, and dap_lookup_data::type.

Referenced by dap_lookup_cs_component().

◆ dap_put_ap()

int dap_put_ap ( struct adiv5_ap * ap )

◆ dap_queue_read_reg()

static int dap_queue_read_reg	(	enum coresight_access_mode	mode,
		struct adiv5_ap *	ap,
		uint64_t	component_base,
		unsigned int	reg,
		uint32_t *	value
	)

static

Helper to read CoreSight component's registers, either on the bus behind a MEM-AP or directly in the AP.

Parameters

mode	Method to access the component (AP or MEM-AP).
ap	Pointer to AP containing the component.
component_base	On MEM-AP access method, base address of the component.
reg	Offset of the component's register to read.
value	Pointer to the store the read value.

Returns: ERROR_OK on success, else a fault code.

Definition at line 1229 of file arm_adi_v5.c.

References CS_ACCESS_AP, dap_queue_ap_read(), mem_ap_read_u32(), and mode.

Referenced by rtp_read_cs_regs(), and rtp_rom_loop().

◆ dap_to_jtag()

int dap_to_jtag ( struct adiv5_dap * dap )

Put the debug link into JTAG mode, if the target supports it.

The link's initial mode may be either SWD or JTAG.

Note that targets implemented with SW-DP do not support JTAG, and that some targets which could otherwise support it may have been configured to disable JTAG signaling

Parameters

dap	The DAP used

Returns: ERROR_OK or else a fault code.

Definition at line 872 of file arm_adi_v5.c.

References dap_send_sequence(), LOG_DEBUG, and SWD_TO_JTAG.

Referenced by COMMAND_HANDLER().

◆ dap_to_swd()

int dap_to_swd ( struct adiv5_dap * dap )

Put the debug link into SWD mode, if the target supports it.

The link's initial mode may be either JTAG (for example, with SWJ-DP after reset) or SWD.

Note that targets using the JTAG-DP do not support SWD, and that some targets which could otherwise support it may have been configured to disable SWD signaling

Parameters

dap	The DAP used

Returns: ERROR_OK or else a fault code.

Definition at line 854 of file arm_adi_v5.c.

References dap_send_sequence(), JTAG_TO_SWD, and LOG_DEBUG.

Referenced by COMMAND_HANDLER().

◆ is_ap_in_use()

static bool is_ap_in_use ( struct adiv5_ap * ap )

inlinestatic

Definition at line 1052 of file arm_adi_v5.c.

References adiv5_ap::config_ap_never_release, and adiv5_ap::refcount.

Referenced by _dap_get_ap(), and dap_put_ap().

◆ is_ap_num_valid()

bool is_ap_num_valid	(	struct adiv5_dap *	dap,
		uint64_t	ap_num
	)

Definition at line 980 of file arm_adi_v5.c.

References adiv5_dap::asize, DP_APSEL_MAX, and is_adiv6().

Referenced by _dap_get_ap(), and COMMAND_HANDLER().

◆ max_tar_block_size()

static uint32_t max_tar_block_size	(	uint32_t	tar_autoincr_block,
		target_addr_t	address
	)

static

Definition at line 82 of file arm_adi_v5.c.

Referenced by mem_ap_read(), mem_ap_update_tar_cache(), and mem_ap_write().

◆ mem_ap_get_tar_increment()

static uint32_t mem_ap_get_tar_increment ( struct adiv5_ap * ap )

static

Definition at line 156 of file arm_adi_v5.c.

References CSW_16BIT, CSW_32BIT, CSW_8BIT, CSW_ADDRINC_MASK, CSW_ADDRINC_PACKED, CSW_ADDRINC_SINGLE, CSW_SIZE_MASK, and adiv5_ap::csw_value.

Referenced by mem_ap_update_tar_cache().

◆ mem_ap_init()

int mem_ap_init ( struct adiv5_ap * ap )

Initialize a DAP.

This sets up the power domains, prepares the DP for further use, and arranges to use AP #0 for all AP operations until dap_ap-select() changes that policy.

Parameters

ap	The MEM-AP being initialized.

Definition at line 783 of file arm_adi_v5.c.

References adiv5_dap::ap, adiv5_ap::cfg_reg, CSW_8BIT, CSW_ADDRINC_PACKED, adiv5_ap::csw_value, adiv5_ap::dap, dap_queue_ap_read(), dap_run(), ERROR_OK, LOG_DEBUG, MEM_AP_REG_CFG, MEM_AP_REG_CFG_BE, MEM_AP_REG_CFG_LA, MEM_AP_REG_CFG_LD, MEM_AP_REG_CSW, mem_ap_setup_transfer(), adiv5_ap::packed_transfers, adiv5_ap::tar_valid, adiv5_dap::ti_be_32_quirks, and adiv5_ap::unaligned_access_bad.

Referenced by aarch64_examine_first(), cortex_a_examine_first(), cortex_m_examine(), mem_ap_examine(), and xtensa_dm_examine().

◆ mem_ap_read()

static int mem_ap_read	(	struct adiv5_ap *	ap,
		uint8_t *	buffer,
		uint32_t	size,
		uint32_t	count,
		target_addr_t	adr,
		bool	addrinc
	)

static

Synchronous read of a block of memory, using a specific access size.

Parameters

ap	The MEM-AP to access.
buffer	The data buffer to receive the data. No particular alignment is assumed.
size	Which access size to use, in bytes. 1, 2 or 4.
count	The number of reads to do (in size units, not bytes).
adr	Address to be read; it must be readable by the currently selected MEM-AP.
addrinc	Whether the target address should be increased after each read or not. This should normally be true, except when reading from e.g. a FIFO.

Returns: ERROR_OK on success, otherwise an error code.

Definition at line 484 of file arm_adi_v5.c.

References adiv5_dap::ap, buffer, count, CSW_16BIT, CSW_32BIT, CSW_8BIT, CSW_ADDRINC_OFF, CSW_ADDRINC_PACKED, CSW_ADDRINC_SINGLE, adiv5_ap::dap, dap_queue_ap_read(), dap_run(), ERROR_FAIL, ERROR_OK, ERROR_TARGET_UNALIGNED_ACCESS, LOG_ERROR, max_tar_block_size(), mem_ap_read_tar(), MEM_AP_REG_DRW, mem_ap_setup_csw(), mem_ap_setup_tar(), mem_ap_update_tar_cache(), adiv5_ap::packed_transfers, size, adiv5_ap::tar_autoincr_block, TARGET_ADDR_FMT, adiv5_dap::ti_be_32_quirks, and adiv5_ap::unaligned_access_bad.

Referenced by mem_ap_read_buf(), and mem_ap_read_buf_noincr().

◆ mem_ap_read_atomic_u32()

int mem_ap_read_atomic_u32	(	struct adiv5_ap *	ap,
		target_addr_t	address,
		uint32_t *	value
	)

Synchronous read of a word from memory or a system register.

As a side effect, this flushes any queued transactions.

Parameters

ap	The MEM-AP to access.
address	Address of the 32-bit word to read; it must be readable by the currently selected MEM-AP.
value	points to where the result will be stored.

Returns: ERROR_OK for success; *value holds the result. Otherwise a fault code.

Definition at line 259 of file arm_adi_v5.c.

References adiv5_ap::dap, dap_run(), ERROR_OK, and mem_ap_read_u32().

Referenced by aarch64_check_state_one(), aarch64_clear_reset_catch(), aarch64_debug_entry(), aarch64_enable_reset_catch(), aarch64_handle_target_request(), aarch64_init_debug_access(), aarch64_prepare_restart_one(), aarch64_read_cpu_memory(), aarch64_read_cpu_memory_fast(), aarch64_read_cpu_memory_slow(), aarch64_step(), aarch64_write_cpu_memory(), arm_cti_ack_events(), arm_cti_mod_reg_bits(), arm_cti_read_reg(), armv7a_setup_semihosting(), armv8_set_dbgreg_bits(), COMMAND_HANDLER(), cortex_a_debug_entry(), cortex_a_deinit_target(), cortex_a_examine_first(), cortex_a_handle_target_request(), cortex_a_init_debug_access(), cortex_a_internal_restart(), cortex_a_poll(), cortex_a_read_copro(), cortex_a_read_cpu_memory(), cortex_a_read_cpu_memory_fast(), cortex_a_read_cpu_memory_slow(), cortex_a_read_dcc(), cortex_a_set_dscr_bits(), cortex_a_wait_dscr_bits(), cortex_a_wait_instrcmpl(), cortex_a_write_cpu_memory(), cortex_m_assert_reset(), cortex_m_clear_halt(), cortex_m_endreset_event(), cortex_m_examine_exception_reason(), cortex_m_load_core_reg_u32(), cortex_m_read_dhcsr_atomic_sticky(), cortex_m_soft_reset_halt(), dpmv8_dpm_prepare(), dpmv8_exec_opcode(), dpmv8_read_dcc(), and dpmv8_read_dcc_64().

◆ mem_ap_read_buf()

int mem_ap_read_buf	(	struct adiv5_ap *	ap,
		uint8_t *	buffer,
		uint32_t	size,
		uint32_t	count,
		target_addr_t	address
	)

Definition at line 622 of file arm_adi_v5.c.

References adiv5_dap::ap, buffer, count, mem_ap_read(), and size.

Referenced by cortex_m_read_memory(), mem_ap_read_memory(), xtensa_dm_queue_pwr_reg_read(), and xtensa_dm_queue_reg_read().

◆ mem_ap_read_buf_noincr()

int mem_ap_read_buf_noincr	(	struct adiv5_ap *	ap,
		uint8_t *	buffer,
		uint32_t	size,
		uint32_t	count,
		target_addr_t	address
	)

Definition at line 634 of file arm_adi_v5.c.

References adiv5_dap::ap, buffer, count, mem_ap_read(), and size.

Referenced by aarch64_read_cpu_memory_fast(), cortex_a_read_cpu_memory_fast(), cortex_m_dcc_read(), and cortex_m_profiling().

◆ mem_ap_read_tar()

static int mem_ap_read_tar	(	struct adiv5_ap *	ap,
		target_addr_t *	tar
	)

static

Definition at line 129 of file arm_adi_v5.c.

References adiv5_ap::dap, dap_queue_ap_read(), dap_run(), ERROR_OK, is_64bit_ap(), MEM_AP_REG_TAR, MEM_AP_REG_TAR64, adiv5_ap::tar_valid, and adiv5_ap::tar_value.

Referenced by mem_ap_read(), and mem_ap_write().

◆ mem_ap_read_u32()

int mem_ap_read_u32	(	struct adiv5_ap *	ap,
		target_addr_t	address,
		uint32_t *	value
	)

Asynchronous (queued) read of a word from memory or a system register.

Parameters

ap	The MEM-AP to access.
address	Address of the 32-bit word to read; it must be readable by the currently selected MEM-AP.
value	points to where the word will be stored when the transaction queue is flushed (assuming no errors).

Returns: ERROR_OK for success. Otherwise a fault code.

Definition at line 230 of file arm_adi_v5.c.

References CSW_32BIT, CSW_ADDRINC_MASK, adiv5_ap::csw_value, adiv5_ap::dap, dap_queue_ap_read(), ERROR_OK, MEM_AP_REG_BD0, and mem_ap_setup_transfer().

Referenced by aarch64_examine_first(), COMMAND_HANDLER(), cortex_m_debug_entry(), cortex_m_examine_exception_reason(), cortex_m_fast_read_all_regs(), cortex_m_load_core_reg_u32(), cortex_m_queue_reg_read(), cortex_m_store_core_reg_u32(), dap_queue_read_reg(), dpmv8_dpm_prepare(), and mem_ap_read_atomic_u32().

◆ mem_ap_setup_csw()

static int mem_ap_setup_csw	(	struct adiv5_ap *	ap,
		uint32_t	csw
	)

static

Definition at line 93 of file arm_adi_v5.c.

References adiv5_ap::csw_default, adiv5_ap::csw_value, adiv5_ap::dap, dap_queue_ap_write(), ERROR_OK, and MEM_AP_REG_CSW.

Referenced by mem_ap_read(), mem_ap_setup_transfer(), and mem_ap_write().

◆ mem_ap_setup_tar()

static int mem_ap_setup_tar	(	struct adiv5_ap *	ap,
		target_addr_t	tar
	)

static

Definition at line 109 of file arm_adi_v5.c.

References adiv5_ap::dap, dap_queue_ap_write(), ERROR_OK, is_64bit_ap(), MEM_AP_REG_TAR, MEM_AP_REG_TAR64, adiv5_ap::tar_valid, and adiv5_ap::tar_value.

Referenced by mem_ap_read(), mem_ap_setup_transfer(), and mem_ap_write().

◆ mem_ap_setup_transfer()

static int mem_ap_setup_transfer	(	struct adiv5_ap *	ap,
		uint32_t	csw,
		target_addr_t	tar
	)

static

Queue transactions setting up transfer parameters for the currently selected MEM-AP.

Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2 initiate data reads or writes using memory or peripheral addresses. If the CSW is configured for it, the TAR may be automatically incremented after each transfer.

Parameters

ap	The MEM-AP.
csw	MEM-AP Control/Status Word (CSW) register to assign. If this matches the cached value, the register is not changed.
tar	MEM-AP Transfer Address Register (TAR) to assign. If this matches the cached address, the register is not changed.

Returns: ERROR_OK if the transaction was properly queued, else a fault code.

Definition at line 207 of file arm_adi_v5.c.

References ERROR_OK, mem_ap_setup_csw(), and mem_ap_setup_tar().

Referenced by mem_ap_init(), mem_ap_read_u32(), and mem_ap_write_u32().

◆ mem_ap_update_tar_cache()

static void mem_ap_update_tar_cache ( struct adiv5_ap * ap )

static

Definition at line 178 of file arm_adi_v5.c.

References max_tar_block_size(), mem_ap_get_tar_increment(), adiv5_ap::tar_autoincr_block, adiv5_ap::tar_valid, and adiv5_ap::tar_value.

Referenced by mem_ap_read(), and mem_ap_write().

◆ mem_ap_write()

static int mem_ap_write	(	struct adiv5_ap *	ap,
		const uint8_t *	buffer,
		uint32_t	size,
		uint32_t	count,
		target_addr_t	address,
		bool	addrinc
	)

static

Synchronous write of a block of memory, using a specific access size.

Parameters

ap	The MEM-AP to access.
buffer	The data buffer to write. No particular alignment is assumed.
size	Which access size to use, in bytes. 1, 2 or 4.
count	The number of writes to do (in size units, not bytes).
address	Address to be written; it must be writable by the currently selected MEM-AP.
addrinc	Whether the target address should be increased for each write or not. This should normally be true, except when writing to e.g. a FIFO.

Returns: ERROR_OK on success, otherwise an error code.

Definition at line 334 of file arm_adi_v5.c.

References adiv5_dap::ap, buffer, count, CSW_16BIT, CSW_32BIT, CSW_8BIT, CSW_ADDRINC_OFF, CSW_ADDRINC_PACKED, CSW_ADDRINC_SINGLE, adiv5_ap::dap, dap_queue_ap_write(), dap_run(), ERROR_OK, ERROR_TARGET_UNALIGNED_ACCESS, LOG_ERROR, max_tar_block_size(), mem_ap_read_tar(), MEM_AP_REG_DRW, mem_ap_setup_csw(), mem_ap_setup_tar(), mem_ap_update_tar_cache(), adiv5_dap::nu_npcx_quirks, adiv5_ap::packed_transfers, size, adiv5_ap::tar_autoincr_block, TARGET_ADDR_FMT, adiv5_dap::ti_be_32_quirks, and adiv5_ap::unaligned_access_bad.

Referenced by mem_ap_write_buf(), and mem_ap_write_buf_noincr().

◆ mem_ap_write_atomic_u32()

int mem_ap_write_atomic_u32	(	struct adiv5_ap *	ap,
		target_addr_t	address,
		uint32_t	value
	)

Synchronous write of a word to memory or a system register.

As a side effect, this flushes any queued transactions.

Parameters

ap	The MEM-AP to access.
address	Address to be written; it must be writable by the currently selected MEM-AP.
value	Word that will be written.

Returns: ERROR_OK for success; the data was written. Otherwise a fault code.

Definition at line 311 of file arm_adi_v5.c.

References adiv5_ap::dap, dap_run(), ERROR_OK, and mem_ap_write_u32().

Referenced by aarch64_assert_reset(), aarch64_clear_reset_catch(), aarch64_dap_write_memap_register_u32(), aarch64_debug_entry(), aarch64_enable_reset_catch(), aarch64_examine_first(), aarch64_init_debug_access(), aarch64_prepare_restart_one(), aarch64_read_cpu_memory(), aarch64_read_cpu_memory_fast(), aarch64_read_cpu_memory_slow(), aarch64_step(), aarch64_write_cpu_memory(), aarch64_write_cpu_memory_fast(), aarch64_write_cpu_memory_slow(), arm_cti_ack_events(), arm_cti_enable(), arm_cti_mod_reg_bits(), arm_cti_write_reg(), armv7a_setup_semihosting(), armv8_set_dbgreg_bits(), COMMAND_HANDLER(), cortex_a_dap_write_memap_register_u32(), cortex_a_deassert_reset(), cortex_a_debug_entry(), cortex_a_deinit_target(), cortex_a_examine_first(), cortex_a_halt(), cortex_a_init_debug_access(), cortex_a_internal_restart(), cortex_a_read_cpu_memory(), cortex_a_read_cpu_memory_fast(), cortex_a_set_dcc_mode(), cortex_a_set_dscr_bits(), cortex_a_write_copro(), cortex_a_write_cpu_memory(), cortex_a_write_cpu_memory_fast(), cortex_a_write_cpu_memory_slow(), cortex_m_assert_reset(), cortex_m_clear_halt(), cortex_m_fast_read_all_regs(), cortex_m_load_core_reg_u32(), cortex_m_soft_reset_halt(), cortex_m_store_core_reg_u32(), cortex_m_write_debug_halt_mask(), dpmv8_bpwp_disable(), handle_reset_halt(), and wrap_write_u32().

◆ mem_ap_write_buf()

int mem_ap_write_buf	(	struct adiv5_ap *	ap,
		const uint8_t *	buffer,
		uint32_t	size,
		uint32_t	count,
		target_addr_t	address
	)

Definition at line 628 of file arm_adi_v5.c.

References adiv5_dap::ap, buffer, count, mem_ap_write(), and size.

Referenced by COMMAND_HANDLER(), and cortex_m_write_memory().

◆ mem_ap_write_buf_noincr()

int mem_ap_write_buf_noincr	(	struct adiv5_ap *	ap,
		const uint8_t *	buffer,
		uint32_t	size,
		uint32_t	count,
		target_addr_t	address
	)

Definition at line 640 of file arm_adi_v5.c.

References adiv5_dap::ap, buffer, count, mem_ap_write(), and size.

Referenced by aarch64_write_cpu_memory_fast(), cortex_a_write_cpu_memory_fast(), and cortex_m_dcc_read().

◆ mem_ap_write_u32()

int mem_ap_write_u32	(	struct adiv5_ap *	ap,
		target_addr_t	address,
		uint32_t	value
	)

Asynchronous (queued) write of a word to memory or a system register.

Parameters

ap	The MEM-AP to access.
address	Address to be written; it must be writable by the currently selected MEM-AP.
value	Word that will be written to the address when transaction queue is flushed (assuming no errors).

Returns: ERROR_OK for success. Otherwise a fault code.

Definition at line 282 of file arm_adi_v5.c.

References CSW_32BIT, CSW_ADDRINC_MASK, adiv5_ap::csw_value, adiv5_ap::dap, dap_queue_ap_write(), ERROR_OK, MEM_AP_REG_BD0, and mem_ap_setup_transfer().

Referenced by armv8_dpm_handle_exception(), COMMAND_HANDLER(), cortex_a_exec_opcode(), cortex_a_init_debug_access(), cortex_a_write_dcc(), cortex_m_assert_reset(), cortex_m_endreset_event(), cortex_m_load_core_reg_u32(), cortex_m_queue_reg_read(), cortex_m_soft_reset_halt(), cortex_m_store_core_reg_u32(), dpmv8_exec_opcode(), dpmv8_write_dcc(), dpmv8_write_dcc_64(), mem_ap_write_atomic_u32(), xtensa_dm_queue_pwr_reg_read(), xtensa_dm_queue_pwr_reg_write(), and xtensa_dm_queue_reg_write().

◆ pidr_to_part_num()

static const struct dap_part_nums* pidr_to_part_num	(	unsigned int	designer_id,
		unsigned int	part_num
	)

static

Definition at line 1460 of file arm_adi_v5.c.

References ARRAY_SIZE, dap_part_nums::designer_id, dap_part_nums::part_num, and dap_part_nums::type.

Referenced by dap_info_cs_component().

◆ rtp_ap()

static int rtp_ap	(	const struct rtp_ops *	ops,
		struct adiv5_ap *	ap,
		int	depth
	)

static

Definition at line 1882 of file arm_adi_v5.c.

References AP_REG_IDR_CLASS_MASK, AP_REG_IDR_CLASS_MEM_AP, AP_REG_IDR_CLASS_SHIFT, CORESIGHT_COMPONENT_FOUND, CS_ACCESS_AP, CS_ACCESS_MEM_AP, adiv5_ap::dap, dap_get_debugbase(), ERROR_FAIL, ERROR_OK, is_64bit_ap(), is_adiv6(), NULL, ROM_TABLE_MAX_DEPTH, rtp_cs_component(), rtp_ops_ap_header(), and rtp_ops_mem_ap_header().

Referenced by dap_info_command(), dap_lookup_cs_component(), and rtp_rom_loop().

◆ rtp_cs_component()

static int rtp_cs_component	(	enum coresight_access_mode	mode,
		const struct rtp_ops *	ops,
		struct adiv5_ap *	ap,
		target_addr_t	dbgbase,
		bool *	is_mem_ap,
		int	depth
	)

static

◆ rtp_ops_ap_header()

static int rtp_ops_ap_header	(	const struct rtp_ops *	ops,
		struct adiv5_ap *	ap,
		int	depth
	)

static

Wrapper around struct rtp_ops::ap_header.

Definition at line 1673 of file arm_adi_v5.c.

References cs_component_vals::ap, rtp_ops::ap_header, ERROR_OK, and rtp_ops::priv.

Referenced by rtp_ap().

◆ rtp_ops_cs_component()

static int rtp_ops_cs_component	(	const struct rtp_ops *	ops,
		int	retval,
		struct cs_component_vals *	v,
		int	depth
	)

static

Wrapper around struct rtp_ops::cs_component.

Input parameter retval is propagated.

Definition at line 1702 of file arm_adi_v5.c.

References rtp_ops::cs_component, ERROR_OK, and rtp_ops::priv.

Referenced by rtp_cs_component().

◆ rtp_ops_mem_ap_header()

static int rtp_ops_mem_ap_header	(	const struct rtp_ops *	ops,
		int	retval,
		struct adiv5_ap *	ap,
		uint64_t	dbgbase,
		uint32_t	apid,
		int	depth
	)

static

Wrapper around struct rtp_ops::mem_ap_header.

Input parameter retval is propagated.

Definition at line 1686 of file arm_adi_v5.c.

References cs_component_vals::ap, ERROR_OK, rtp_ops::mem_ap_header, and rtp_ops::priv.

Referenced by rtp_ap().

◆ rtp_ops_rom_table_entry()

static int rtp_ops_rom_table_entry	(	const struct rtp_ops *	ops,
		int	retval,
		int	depth,
		unsigned int	offset,
		uint64_t	romentry
	)

static

Wrapper around struct rtp_ops::rom_table_entry.

Input parameter retval is propagated.

Definition at line 1718 of file arm_adi_v5.c.

References ERROR_OK, offset, rtp_ops::priv, and rtp_ops::rom_table_entry.

Referenced by rtp_rom_loop().

◆ rtp_read_cs_regs()

static int rtp_read_cs_regs	(	enum coresight_access_mode	mode,
		struct adiv5_ap *	ap,
		target_addr_t	component_base,
		struct cs_component_vals *	v
	)

static

Read the CoreSight registers needed during ROM Table Parsing (RTP).

Parameters

mode	Method to access the component (AP or MEM-AP).
ap	Pointer to AP containing the component.
component_base	On MEM-AP access method, base address of the component.
v	Pointer to the struct holding the value of registers.

Returns: ERROR_OK on success, else a fault code.

Definition at line 1249 of file arm_adi_v5.c.

Referenced by rtp_cs_component().

◆ rtp_rom_loop()

static int rtp_rom_loop	(	enum coresight_access_mode	mode,
		const struct rtp_ops *	ops,
		struct adiv5_ap *	ap,
		target_addr_t	base_address,
		int	depth,
		unsigned int	width,
		unsigned int	max_entries
	)

static

Definition at line 1745 of file arm_adi_v5.c.

References cs_component_vals::ap, adiv5_ap::ap_num, ARM_CS_ALIGN, ARM_CS_ROMENTRY_OFFSET_MASK, ARM_CS_ROMENTRY_PRESENT, cs_component_vals::component_base, CORESIGHT_COMPONENT_FOUND, CS_ACCESS_AP, adiv5_ap::dap, dap_get_ap(), dap_put_ap(), dap_queue_read_reg(), dap_run(), ERROR_OK, is_64bit_ap(), IS_ALIGNED, LOG_DEBUG, mode, NULL, offset, rtp_ap(), rtp_cs_component(), rtp_ops_rom_table_entry(), and width.

Referenced by rtp_cs_component().

Variable Documentation

◆

const { ... } ap_types[]

Initial value:

= {
    { AP_TYPE_JTAG_AP,  "JTAG-AP" },
    { AP_TYPE_COM_AP,   "COM-AP" },
    { AP_TYPE_AHB3_AP,  "MEM-AP AHB3" },
    { AP_TYPE_APB_AP,   "MEM-AP APB2 or APB3" },
    { AP_TYPE_AXI_AP,   "MEM-AP AXI3 or AXI4" },
    { AP_TYPE_AHB5_AP,  "MEM-AP AHB5" },
    { AP_TYPE_APB4_AP,  "MEM-AP APB4" },
    { AP_TYPE_AXI5_AP,  "MEM-AP AXI5" },
    { AP_TYPE_AHB5H_AP, "MEM-AP AHB5 with enhanced HPROT" },
}

Referenced by ap_type_to_description().

◆ arch_id

uint32_t arch_id

Definition at line 911 of file arm_adi_v5.c.

◆

const { ... } class0x9_devarch[]

Initial value:

= {
    
    { ARCH_ID(ARM_ID, 0x0A00), "RAS architecture" },
    { ARCH_ID(ARM_ID, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" },
    { ARCH_ID(ARM_ID, 0x1A02), "DWT architecture" },
    { ARCH_ID(ARM_ID, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" },
    { ARCH_ID(ARM_ID, 0x2A04), "Processor debug architecture (ARMv8-M)" },
    { ARCH_ID(ARM_ID, 0x6A05), "Processor debug architecture (ARMv8-R)" },
    { ARCH_ID(ARM_ID, 0x0A10), "PC sample-based profiling" },
    { ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },
    { ARCH_ID(ARM_ID, 0x1A14), "Cross Trigger Interface (CTI) architecture" },
    { ARCH_ID(ARM_ID, 0x6A15), "Processor debug architecture (v8.0-A)" },
    { ARCH_ID(ARM_ID, 0x7A15), "Processor debug architecture (v8.1-A)" },
    { ARCH_ID(ARM_ID, 0x8A15), "Processor debug architecture (v8.2-A)" },
    { ARCH_ID(ARM_ID, 0x2A16), "Processor Performance Monitor (PMU) architecture" },
    { ARCH_ID(ARM_ID, 0x0A17), "Memory Access Port v2 architecture" },
    { ARCH_ID(ARM_ID, 0x0A27), "JTAG Access Port v2 architecture" },
    { ARCH_ID(ARM_ID, 0x0A31), "Basic trace router" },
    { ARCH_ID(ARM_ID, 0x0A37), "Power requestor" },
    { ARCH_ID(ARM_ID, 0x0A47), "Unknown Access Port v2 architecture" },
    { ARCH_ID(ARM_ID, 0x0A50), "HSSTP architecture" },
    { ARCH_ID(ARM_ID, 0x0A63), "System Trace Macrocell (STM) architecture" },
    { ARCH_ID(ARM_ID, 0x0A75), "CoreSight ELA architecture" },
    { ARCH_ID(ARM_ID, 0x0AF7), "CoreSight ROM architecture" },
}

Referenced by class0x9_devarch_description().

◆ class_description

const char* class_description[16]

static

Initial value:

= {
    [0x0] = "Generic verification component",
    [0x1] = "ROM table",
    [0x2] = "Reserved",
    [0x3] = "Reserved",
    [0x4] = "Reserved",
    [0x5] = "Reserved",
    [0x6] = "Reserved",
    [0x7] = "Reserved",
    [0x8] = "Reserved",
    [0x9] = "CoreSight component",
    [0xA] = "Reserved",
    [0xB] = "Peripheral Test Block",
    [0xC] = "Reserved",
    [0xD] = "OptimoDE DESS", 
    [0xE] = "Generic IP component",
    [0xF] = "CoreLink, PrimeCell or System component",
}

Definition at line 886 of file arm_adi_v5.c.

Referenced by dap_info_cs_component().

◆ dap_instance_commands

const struct command_registration dap_instance_commands[]

Definition at line 2778 of file arm_adi_v5.c.

Referenced by dap_create().

◆ dap_part_nums

const struct dap_part_nums dap_part_nums[]

static

◆ description

const char* description

Definition at line 912 of file arm_adi_v5.c.

Referenced by class0x9_devarch_description(), decode_dmi(), and mpsse_open().

◆ nvp_config_opts

const struct jim_nvp nvp_config_opts[]

static

Initial value:

= {
    { .name = "-dap",       .value = CFG_DAP },
    { .name = "-ap-num",    .value = CFG_AP_NUM },
    { .name = "-baseaddr",  .value = CFG_BASEADDR },
    { .name = "-ctibase",   .value = CFG_CTIBASE }, 
    { .name = NULL, .value = -1 }
}

Definition at line 2178 of file arm_adi_v5.c.

Referenced by adiv5_jim_spot_configure().

◆ type

enum ap_type type

Definition at line 912 of file arm_adi_v5.c.

Referenced by ap_type_to_description(), and dap_lookup_cs_component().

Data Structures

Macros

Enumerations

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ ARCH_ID

◆ CORESIGHT_COMPONENT_FOUND

◆ DAP_POWER_DOMAIN_TIMEOUT

◆ DEVARCH_ID_MASK

◆ DEVARCH_MEM_AP

◆ DEVARCH_ROM_C_0X9

◆ DEVARCH_UNKNOWN_V2

◆ ROM_TABLE_MAX_DEPTH

Enumeration Type Documentation

◆ adiv5_cfg_param

◆ coresight_access_mode

Function Documentation

◆ _dap_get_ap()

◆ adiv5_jim_configure()

◆ adiv5_jim_mem_ap_spot_configure()

◆ adiv5_jim_spot_configure()

◆ adiv5_mem_ap_spot_init()

◆ adiv5_verify_config()

◆ adiv6_dap_read_baseptr()

◆ ap_type_to_description()

◆ class0x9_devarch_description()

◆ COMMAND_HANDLER() [1/10]

◆ COMMAND_HANDLER() [2/10]

◆ COMMAND_HANDLER() [3/10]

◆ COMMAND_HANDLER() [4/10]

◆ COMMAND_HANDLER() [5/10]

◆ COMMAND_HANDLER() [6/10]

◆ COMMAND_HANDLER() [7/10]

◆ COMMAND_HANDLER() [8/10]

◆ COMMAND_HANDLER() [9/10]

◆ COMMAND_HANDLER() [10/10]

◆ dap_devtype_display()

◆ dap_dp_init()

◆ dap_dp_init_or_reconnect()

◆ dap_find_get_ap()

◆ dap_get_ap()

◆ dap_get_config_ap()

◆ dap_get_debugbase()

◆ dap_info_ap_header()

◆ dap_info_command()

◆ dap_info_cs_component()

◆ dap_info_mem_ap_header()

◆ dap_info_rom_table_entry()

◆ dap_invalidate_cache()

◆ dap_lookup_cs_component()

◆ dap_lookup_cs_component_cs_component()

◆ dap_put_ap()

◆ dap_queue_read_reg()

◆ dap_to_jtag()

◆ dap_to_swd()

◆ is_ap_in_use()

◆ is_ap_num_valid()

◆ max_tar_block_size()

◆ mem_ap_get_tar_increment()

◆ mem_ap_init()

◆ mem_ap_read()

◆ mem_ap_read_atomic_u32()

◆ mem_ap_read_buf()

◆ mem_ap_read_buf_noincr()

◆ mem_ap_read_tar()

◆ mem_ap_read_u32()

◆ mem_ap_setup_csw()

◆ mem_ap_setup_tar()

◆ mem_ap_setup_transfer()

◆ mem_ap_update_tar_cache()

◆ mem_ap_write()

◆ mem_ap_write_atomic_u32()

◆ mem_ap_write_buf()

◆ mem_ap_write_buf_noincr()

◆ mem_ap_write_u32()

◆ pidr_to_part_num()

◆ rtp_ap()

◆ rtp_cs_component()