OpenOCD
arm_adi_v5.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2006 by Magnus Lundin *
5  * lundin@mlu.mine.nu *
6  * *
7  * Copyright (C) 2008 by Spencer Oliver *
8  * spen@spen-soft.co.uk *
9  * *
10  * Copyright (C) 2019-2021, Ampere Computing LLC *
11  ***************************************************************************/
12 
13 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
14 #define OPENOCD_TARGET_ARM_ADI_V5_H
15 
23 #include <helper/list.h>
24 #include "arm_jtag.h"
25 #include "helper/bits.h"
26 
27 /* JEP106 ID for ARM */
28 #define ARM_ID 0x23B
29 
30 /* three-bit ACK values for SWD access (sent LSB first) */
31 #define SWD_ACK_OK 0x1
32 #define SWD_ACK_WAIT 0x2
33 #define SWD_ACK_FAULT 0x4
34 
35 #define DPAP_WRITE 0
36 #define DPAP_READ 1
37 
38 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
39 
40 /* A[3:0] for DP registers; A[1:0] are always zero.
41  * - JTAG accesses all of these via JTAG_DP_DPACC, except for
42  * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
43  * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
44  */
45 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
46 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
47 #define DP_DPIDR1 BANK_REG(0x1, 0x0) /* DPv3: ro */
48 #define DP_BASEPTR0 BANK_REG(0x2, 0x0) /* DPv3: ro */
49 #define DP_BASEPTR1 BANK_REG(0x3, 0x0) /* DPv3: ro */
50 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
51 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
52 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
53 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
54 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
55 #define DP_SELECT1 BANK_REG(0x5, 0x4) /* DPv3: ro */
56 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
57 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
58 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
59 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
60 
61 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
62 
63 /* Fields of DP_DPIDR register */
64 #define DP_DPIDR_VERSION_SHIFT 12
65 #define DP_DPIDR_VERSION_MASK (0xFUL << DP_DPIDR_VERSION_SHIFT)
66 
67 /* Fields of the DP's AP ABORT register */
68 #define DAPABORT (1UL << 0)
69 #define STKCMPCLR (1UL << 1) /* SWD-only */
70 #define STKERRCLR (1UL << 2) /* SWD-only */
71 #define WDERRCLR (1UL << 3) /* SWD-only */
72 #define ORUNERRCLR (1UL << 4) /* SWD-only */
73 
74 /* Fields of register DP_DPIDR1 */
75 #define DP_DPIDR1_ASIZE_MASK (0x7F)
76 #define DP_DPIDR1_ERRMODE BIT(7)
77 
78 /* Fields of register DP_BASEPTR0 */
79 #define DP_BASEPTR0_VALID BIT(0)
80 
81 /* Fields of the DP's CTRL/STAT register */
82 #define CORUNDETECT (1UL << 0)
83 #define SSTICKYORUN (1UL << 1)
84 /* 3:2 - transaction mode (e.g. pushed compare) */
85 #define SSTICKYCMP (1UL << 4)
86 #define SSTICKYERR (1UL << 5)
87 #define READOK (1UL << 6) /* SWD-only */
88 #define WDATAERR (1UL << 7) /* SWD-only */
89 /* 11:8 - mask lanes for pushed compare or verify ops */
90 /* 21:12 - transaction counter */
91 #define CDBGRSTREQ (1UL << 26)
92 #define CDBGRSTACK (1UL << 27)
93 #define CDBGPWRUPREQ (1UL << 28)
94 #define CDBGPWRUPACK (1UL << 29)
95 #define CSYSPWRUPREQ (1UL << 30)
96 #define CSYSPWRUPACK (1UL << 31)
97 
98 #define DP_DLPIDR_PROTVSN 1u
99 
100 #define DP_SELECT_APSEL 0xFF000000
101 #define DP_SELECT_APBANK 0x000000F0
102 #define DP_SELECT_DPBANK 0x0000000F
103 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
104 
105 #define DP_APSEL_MAX (255) /* for ADIv5 only */
106 #define DP_APSEL_INVALID 0xF00 /* more than DP_APSEL_MAX and not ADIv6 aligned 4k */
107 
108 #define DP_TARGETSEL_INVALID 0xFFFFFFFFU
109 #define DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU
110 #define DP_TARGETSEL_INSTANCEID_MASK 0xF0000000U
111 #define DP_TARGETSEL_INSTANCEID_SHIFT 28
112 
113 
114 /* MEM-AP register addresses */
115 #define ADIV5_MEM_AP_REG_CSW (0x00)
116 #define ADIV5_MEM_AP_REG_TAR (0x04)
117 #define ADIV5_MEM_AP_REG_TAR64 (0x08) /* RW: Large Physical Address Extension */
118 #define ADIV5_MEM_AP_REG_DRW (0x0C) /* RW: Data Read/Write register */
119 #define ADIV5_MEM_AP_REG_BD0 (0x10) /* RW: Banked Data register 0-3 */
120 #define ADIV5_MEM_AP_REG_BD1 (0x14)
121 #define ADIV5_MEM_AP_REG_BD2 (0x18)
122 #define ADIV5_MEM_AP_REG_BD3 (0x1C)
123 #define ADIV5_MEM_AP_REG_MBT (0x20) /* --: Memory Barrier Transfer register */
124 #define ADIV5_MEM_AP_REG_BASE64 (0xF0) /* RO: Debug Base Address (LA) register */
125 #define ADIV5_MEM_AP_REG_CFG (0xF4) /* RO: Configuration register */
126 #define ADIV5_MEM_AP_REG_BASE (0xF8) /* RO: Debug Base Address register */
127 
128 #define ADIV6_MEM_AP_REG_CSW (0xD00 + ADIV5_MEM_AP_REG_CSW)
129 #define ADIV6_MEM_AP_REG_TAR (0xD00 + ADIV5_MEM_AP_REG_TAR)
130 #define ADIV6_MEM_AP_REG_TAR64 (0xD00 + ADIV5_MEM_AP_REG_TAR64)
131 #define ADIV6_MEM_AP_REG_DRW (0xD00 + ADIV5_MEM_AP_REG_DRW)
132 #define ADIV6_MEM_AP_REG_BD0 (0xD00 + ADIV5_MEM_AP_REG_BD0)
133 #define ADIV6_MEM_AP_REG_BD1 (0xD00 + ADIV5_MEM_AP_REG_BD1)
134 #define ADIV6_MEM_AP_REG_BD2 (0xD00 + ADIV5_MEM_AP_REG_BD2)
135 #define ADIV6_MEM_AP_REG_BD3 (0xD00 + ADIV5_MEM_AP_REG_BD3)
136 #define ADIV6_MEM_AP_REG_MBT (0xD00 + ADIV5_MEM_AP_REG_MBT)
137 #define ADIV6_MEM_AP_REG_BASE64 (0xD00 + ADIV5_MEM_AP_REG_BASE64)
138 #define ADIV6_MEM_AP_REG_CFG (0xD00 + ADIV5_MEM_AP_REG_CFG)
139 #define ADIV6_MEM_AP_REG_BASE (0xD00 + ADIV5_MEM_AP_REG_BASE)
140 
141 #define MEM_AP_REG_CSW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CSW : ADIV5_MEM_AP_REG_CSW)
142 #define MEM_AP_REG_TAR(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR : ADIV5_MEM_AP_REG_TAR)
143 #define MEM_AP_REG_TAR64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR64 : ADIV5_MEM_AP_REG_TAR64)
144 #define MEM_AP_REG_DRW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_DRW : ADIV5_MEM_AP_REG_DRW)
145 #define MEM_AP_REG_BD0(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD0 : ADIV5_MEM_AP_REG_BD0)
146 #define MEM_AP_REG_BD1(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD1 : ADIV5_MEM_AP_REG_BD1)
147 #define MEM_AP_REG_BD2(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD2 : ADIV5_MEM_AP_REG_BD2)
148 #define MEM_AP_REG_BD3(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD3 : ADIV5_MEM_AP_REG_BD3)
149 #define MEM_AP_REG_MBT(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_MBT : ADIV5_MEM_AP_REG_MBT)
150 #define MEM_AP_REG_BASE64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE64 : ADIV5_MEM_AP_REG_BASE64)
151 #define MEM_AP_REG_CFG(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CFG : ADIV5_MEM_AP_REG_CFG)
152 #define MEM_AP_REG_BASE(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE : ADIV5_MEM_AP_REG_BASE)
153 
154 /* Generic AP register address */
155 #define ADIV5_AP_REG_IDR (0xFC) /* RO: Identification Register */
156 #define ADIV6_AP_REG_IDR (0xD00 + ADIV5_AP_REG_IDR)
157 #define AP_REG_IDR(dap) (is_adiv6(dap) ? ADIV6_AP_REG_IDR : ADIV5_AP_REG_IDR)
158 
159 /* Fields of the MEM-AP's CSW register */
160 #define CSW_SIZE_MASK 7
161 #define CSW_8BIT 0
162 #define CSW_16BIT 1
163 #define CSW_32BIT 2
164 #define CSW_ADDRINC_MASK (3UL << 4)
165 #define CSW_ADDRINC_OFF 0UL
166 #define CSW_ADDRINC_SINGLE (1UL << 4)
167 #define CSW_ADDRINC_PACKED (2UL << 4)
168 #define CSW_DEVICE_EN (1UL << 6)
169 #define CSW_TRIN_PROG (1UL << 7)
170 
171 /* All fields in bits 12 and above are implementation-defined
172  * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
173  * Some bits are shared between buses
174  */
175 #define CSW_SPIDEN (1UL << 23)
176 #define CSW_DBGSWENABLE (1UL << 31)
177 
178 /* AHB: Privileged */
179 #define CSW_AHB_HPROT1 (1UL << 25)
180 /* AHB: set HMASTER signals to AHB-AP ID */
181 #define CSW_AHB_MASTER_DEBUG (1UL << 29)
182 /* AHB5: non-secure access via HNONSEC
183  * AHB3: SBO, UNPREDICTABLE if zero */
184 #define CSW_AHB_SPROT (1UL << 30)
185 /* AHB: initial value of csw_default */
186 #define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
187 
188 /* AXI: Privileged */
189 #define CSW_AXI_ARPROT0_PRIV (1UL << 28)
190 /* AXI: Non-secure */
191 #define CSW_AXI_ARPROT1_NONSEC (1UL << 29)
192 /* AXI: initial value of csw_default */
193 #define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
194 
195 /* APB: initial value of csw_default */
196 #define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
197 
198 /* Fields of the MEM-AP's CFG register */
199 #define MEM_AP_REG_CFG_BE BIT(0)
200 #define MEM_AP_REG_CFG_LA BIT(1)
201 #define MEM_AP_REG_CFG_LD BIT(2)
202 #define MEM_AP_REG_CFG_INVALID 0xFFFFFFF8
203 
204 /* Fields of the MEM-AP's IDR register */
205 #define AP_REG_IDR_REVISION_MASK (0xF0000000)
206 #define AP_REG_IDR_REVISION_SHIFT (28)
207 #define AP_REG_IDR_DESIGNER_MASK (0x0FFE0000)
208 #define AP_REG_IDR_DESIGNER_SHIFT (17)
209 #define AP_REG_IDR_CLASS_MASK (0x0001E000)
210 #define AP_REG_IDR_CLASS_SHIFT (13)
211 #define AP_REG_IDR_VARIANT_MASK (0x000000F0)
212 #define AP_REG_IDR_VARIANT_SHIFT (4)
213 #define AP_REG_IDR_TYPE_MASK (0x0000000F)
214 #define AP_REG_IDR_TYPE_SHIFT (0)
215 
216 #define AP_REG_IDR_CLASS_NONE (0x0)
217 #define AP_REG_IDR_CLASS_COM (0x1)
218 #define AP_REG_IDR_CLASS_MEM_AP (0x8)
219 
220 #define AP_REG_IDR_VALUE(d, c, t) (\
221  (((d) << AP_REG_IDR_DESIGNER_SHIFT) & AP_REG_IDR_DESIGNER_MASK) | \
222  (((c) << AP_REG_IDR_CLASS_SHIFT) & AP_REG_IDR_CLASS_MASK) | \
223  (((t) << AP_REG_IDR_TYPE_SHIFT) & AP_REG_IDR_TYPE_MASK) \
224 )
225 
226 #define AP_TYPE_MASK (AP_REG_IDR_DESIGNER_MASK | AP_REG_IDR_CLASS_MASK | AP_REG_IDR_TYPE_MASK)
227 
228 /* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
237 };
238 
243 struct adiv5_ap {
247  struct adiv5_dap *dap;
248 
254  uint64_t ap_num;
255 
259  uint32_t csw_default;
260 
266  uint32_t csw_value;
267 
274 
279  uint32_t memaccess_tck;
280 
281  /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
283 
284  /* true if packed transfers are supported by the MEM-AP */
286 
287  /* true if unaligned memory access is not supported by the MEM-AP */
289 
290  /* true if tar_value is in sync with TAR register */
291  bool tar_valid;
292 
293  /* MEM AP configuration register indicating LPAE support */
294  uint32_t cfg_reg;
295 
296  /* references counter */
297  unsigned int refcount;
298 
299  /* AP referenced during config. Never put it, even when refcount reaches zero */
301 };
302 
303 
320 struct adiv5_dap {
321  const struct dap_ops *ops;
322 
323  /* dap transaction list for WAIT support */
324  struct list_head cmd_journal;
325 
326  /* pool for dap_cmd objects */
327  struct list_head cmd_pool;
328 
329  /* number of dap_cmd objects in the pool */
331 
332  struct jtag_tap *tap;
333  /* Control config */
334  uint32_t dp_ctrl_stat;
335 
336  struct adiv5_ap ap[DP_APSEL_MAX + 1];
337 
338  /* The current manually selected AP by the "dap apsel" command */
339  uint64_t apsel;
340 
345  uint64_t select;
346 
347  /* information about current pending SWjDP-AHBAP transaction */
348  uint8_t ack;
349 
354  uint32_t *last_read;
355 
356  /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
357  * despite lack of support in the ARMv7 architecture. Memory access through
358  * the AHB-AP has strange byte ordering these processors, and we need to
359  * swizzle appropriately. */
361 
362  /* The Nuvoton NPCX M4 has an issue with writing to non-4-byte-aligned mmios.
363  * The work around is to repeat the data in all 4 bytes of DRW */
365 
371 
377 
381 
388 
393 
395  unsigned int adi_version;
396 
397  /* ADIv6 only field indicating ROM Table address size */
398  unsigned int asize;
399 };
400 
408 struct dap_ops {
410  int (*connect)(struct adiv5_dap *dap);
411 
413  int (*send_sequence)(struct adiv5_dap *dap, enum swd_special_seq seq);
414 
416  int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
417  uint32_t *data);
419  int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
420  uint32_t data);
421 
423  int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
424  uint32_t *data);
426  int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
427  uint32_t data);
428 
430  int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
431 
433  int (*run)(struct adiv5_dap *dap);
434 
437  int (*sync)(struct adiv5_dap *dap);
438 
440  void (*quit)(struct adiv5_dap *dap);
441 };
442 
443 /*
444  * Access Port types
445  */
446 enum ap_type {
450  AP_TYPE_APB_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 2), /* APB2 or APB3 Memory-AP */
451  AP_TYPE_AXI_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 4), /* AXI3 or AXI4 Memory-AP */
455  AP_TYPE_AHB5H_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 8), /* AHB5 with enhanced HPROT Memory-AP */
456 };
457 
458 /* Check the ap->cfg_reg Long Address field (bit 1)
459  *
460  * 0b0: The AP only supports physical addresses 32 bits or smaller
461  * 0b1: The AP supports physical addresses larger than 32 bits
462  *
463  * @param ap The AP used for reading.
464  *
465  * @return true for 64 bit, false for 32 bit
466  */
467 static inline bool is_64bit_ap(struct adiv5_ap *ap)
468 {
469  return (ap->cfg_reg & MEM_AP_REG_CFG_LA) != 0;
470 }
471 
479 static inline bool is_adiv6(const struct adiv5_dap *dap)
480 {
481  return dap->adi_version == 6;
482 }
483 
492 static inline int dap_send_sequence(struct adiv5_dap *dap,
493  enum swd_special_seq seq)
494 {
495  assert(dap->ops);
496  return dap->ops->send_sequence(dap, seq);
497 }
498 
511 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
512  unsigned reg, uint32_t *data)
513 {
514  assert(dap->ops);
515  return dap->ops->queue_dp_read(dap, reg, data);
516 }
517 
529 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
530  unsigned reg, uint32_t data)
531 {
532  assert(dap->ops);
533  return dap->ops->queue_dp_write(dap, reg, data);
534 }
535 
546 static inline int dap_queue_ap_read(struct adiv5_ap *ap,
547  unsigned reg, uint32_t *data)
548 {
549  assert(ap->dap->ops);
550  if (ap->refcount == 0) {
551  ap->refcount = 1;
552  LOG_ERROR("BUG: refcount AP#0x%" PRIx64 " used without get", ap->ap_num);
553  }
554  return ap->dap->ops->queue_ap_read(ap, reg, data);
555 }
556 
566 static inline int dap_queue_ap_write(struct adiv5_ap *ap,
567  unsigned reg, uint32_t data)
568 {
569  assert(ap->dap->ops);
570  if (ap->refcount == 0) {
571  ap->refcount = 1;
572  LOG_ERROR("BUG: refcount AP#0x%" PRIx64 " used without get", ap->ap_num);
573  }
574  return ap->dap->ops->queue_ap_write(ap, reg, data);
575 }
576 
588 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
589 {
590  assert(dap->ops);
591  return dap->ops->queue_ap_abort(dap, ack);
592 }
593 
604 static inline int dap_run(struct adiv5_dap *dap)
605 {
606  assert(dap->ops);
607  return dap->ops->run(dap);
608 }
609 
610 static inline int dap_sync(struct adiv5_dap *dap)
611 {
612  assert(dap->ops);
613  if (dap->ops->sync)
614  return dap->ops->sync(dap);
615  return ERROR_OK;
616 }
617 
618 static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
619  uint32_t *value)
620 {
621  int retval;
622 
623  retval = dap_queue_dp_read(dap, reg, value);
624  if (retval != ERROR_OK)
625  return retval;
626 
627  return dap_run(dap);
628 }
629 
630 static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
631  uint32_t mask, uint32_t value, int timeout)
632 {
633  assert(timeout > 0);
634  assert((value & mask) == value);
635 
636  int ret;
637  uint32_t regval;
638  LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
639  reg, mask, value);
640  do {
641  ret = dap_dp_read_atomic(dap, reg, &regval);
642  if (ret != ERROR_OK)
643  return ret;
644 
645  if ((regval & mask) == value)
646  break;
647 
648  alive_sleep(10);
649  } while (--timeout);
650 
651  if (!timeout) {
652  LOG_DEBUG("DAP: poll %x timeout", reg);
653  return ERROR_WAIT;
654  } else {
655  return ERROR_OK;
656  }
657 }
658 
659 /* Queued MEM-AP memory mapped single word transfers. */
660 int mem_ap_read_u32(struct adiv5_ap *ap,
661  target_addr_t address, uint32_t *value);
662 int mem_ap_write_u32(struct adiv5_ap *ap,
663  target_addr_t address, uint32_t value);
664 
665 /* Synchronous MEM-AP memory mapped single word transfers. */
667  target_addr_t address, uint32_t *value);
669  target_addr_t address, uint32_t value);
670 
671 /* Synchronous MEM-AP memory mapped bus block transfers. */
672 int mem_ap_read_buf(struct adiv5_ap *ap,
673  uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
674 int mem_ap_write_buf(struct adiv5_ap *ap,
675  const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
676 
677 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
679  uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
681  const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
682 
683 /* Initialisation of the debug system, power domains and registers */
684 int dap_dp_init(struct adiv5_dap *dap);
685 int dap_dp_init_or_reconnect(struct adiv5_dap *dap);
686 int mem_ap_init(struct adiv5_ap *ap);
687 
688 /* Invalidate cached DP select and cached TAR and CSW of all APs */
689 void dap_invalidate_cache(struct adiv5_dap *dap);
690 
691 /* read ADIv6 baseptr register */
692 int adiv6_dap_read_baseptr(struct command_invocation *cmd, struct adiv5_dap *dap, target_addr_t *baseptr);
693 
694 /* test if ap_num is valid, based on current knowledge of dap */
695 bool is_ap_num_valid(struct adiv5_dap *dap, uint64_t ap_num);
696 
697 /* Probe Access Ports to find a particular type. Increment AP refcount */
698 int dap_find_get_ap(struct adiv5_dap *dap,
699  enum ap_type type_to_find,
700  struct adiv5_ap **ap_out);
701 
702 /* Return AP with specified ap_num. Increment AP refcount */
703 struct adiv5_ap *dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num);
704 
705 /* Return AP with specified ap_num. Increment AP refcount and keep it non-zero */
706 struct adiv5_ap *dap_get_config_ap(struct adiv5_dap *dap, uint64_t ap_num);
707 
708 /* Decrement AP refcount and release the AP when refcount reaches zero */
709 int dap_put_ap(struct adiv5_ap *ap);
710 
712 static inline bool dap_is_multidrop(struct adiv5_dap *dap)
713 {
715 }
716 
717 /* Lookup CoreSight component */
718 int dap_lookup_cs_component(struct adiv5_ap *ap,
719  uint8_t type, target_addr_t *addr, int32_t idx);
720 
721 struct target;
722 
723 /* Put debug link into SWD mode */
724 int dap_to_swd(struct adiv5_dap *dap);
725 
726 /* Put debug link into JTAG mode */
727 int dap_to_jtag(struct adiv5_dap *dap);
728 
729 extern const struct command_registration dap_instance_commands[];
730 
731 struct arm_dap_object;
732 extern struct adiv5_dap *dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o);
733 extern struct adiv5_dap *adiv5_get_dap(struct arm_dap_object *obj);
734 extern int dap_info_command(struct command_invocation *cmd,
735  struct adiv5_ap *ap);
736 extern int dap_register_commands(struct command_context *cmd_ctx);
737 extern const char *adiv5_dap_name(struct adiv5_dap *self);
738 extern const struct swd_driver *adiv5_dap_swd_driver(struct adiv5_dap *self);
739 extern int dap_cleanup_all(void);
740 
742  uint64_t ap_num;
743  struct adiv5_dap *dap;
744 };
745 
746 extern int adiv5_verify_config(struct adiv5_private_config *pc);
747 extern int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi);
748 
750  struct adiv5_dap *dap;
751  uint64_t ap_num;
752  uint32_t base;
753 };
754 
755 extern int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p);
757  struct jim_getopt_info *goi);
758 
759 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */
struct adiv5_ap * dap_get_config_ap(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1100
int dap_cleanup_all(void)
Definition: arm_dap.c:153
static int dap_queue_ap_write(struct adiv5_ap *ap, unsigned reg, uint32_t data)
Queue an AP register write.
Definition: arm_adi_v5.h:566
int mem_ap_read_buf(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:622
static bool is_64bit_ap(struct adiv5_ap *ap)
Definition: arm_adi_v5.h:467
int mem_ap_read_buf_noincr(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:634
ap_type
Definition: arm_adi_v5.h:446
@ AP_TYPE_APB_AP
Definition: arm_adi_v5.h:450
@ AP_TYPE_AXI_AP
Definition: arm_adi_v5.h:451
@ AP_TYPE_APB4_AP
Definition: arm_adi_v5.h:453
@ AP_TYPE_AHB3_AP
Definition: arm_adi_v5.h:449
@ AP_TYPE_COM_AP
Definition: arm_adi_v5.h:448
@ AP_TYPE_AHB5H_AP
Definition: arm_adi_v5.h:455
@ AP_TYPE_JTAG_AP
Definition: arm_adi_v5.h:447
@ AP_TYPE_AXI5_AP
Definition: arm_adi_v5.h:454
@ AP_TYPE_AHB5_AP
Definition: arm_adi_v5.h:452
int adiv5_verify_config(struct adiv5_private_config *pc)
Definition: arm_adi_v5.c:2366
static int dap_queue_dp_write(struct adiv5_dap *dap, unsigned reg, uint32_t data)
Queue a DP register write.
Definition: arm_adi_v5.h:529
int dap_info_command(struct command_invocation *cmd, struct adiv5_ap *ap)
Definition: arm_adi_v5.c:2124
#define AP_REG_IDR_CLASS_COM
Definition: arm_adi_v5.h:217
static int dap_queue_dp_read(struct adiv5_dap *dap, unsigned reg, uint32_t *data)
Queue a DP register read.
Definition: arm_adi_v5.h:511
int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Asynchronous (queued) read of a word from memory or a system register.
Definition: arm_adi_v5.c:230
int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p)
Definition: arm_adi_v5.c:2383
#define ARM_ID
Definition: arm_adi_v5.h:28
int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Asynchronous (queued) write of a word to memory or a system register.
Definition: arm_adi_v5.c:282
struct adiv5_dap * dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o)
Definition: arm_dap.c:72
bool is_ap_num_valid(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:980
static int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
Queue an AP abort operation.
Definition: arm_adi_v5.h:588
static int dap_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
Send an adi-v5 sequence to the DAP.
Definition: arm_adi_v5.h:492
int adiv6_dap_read_baseptr(struct command_invocation *cmd, struct adiv5_dap *dap, target_addr_t *baseptr)
Definition: arm_adi_v5.c:1168
#define AP_REG_IDR_CLASS_MEM_AP
Definition: arm_adi_v5.h:218
static int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg, uint32_t *value)
Definition: arm_adi_v5.h:618
const struct swd_driver * adiv5_dap_swd_driver(struct adiv5_dap *self)
Definition: arm_dap.c:62
int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
Definition: arm_adi_v5.c:2330
int dap_find_get_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
Definition: arm_adi_v5.c:1009
int mem_ap_write_buf_noincr(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:640
int dap_to_jtag(struct adiv5_dap *dap)
Put the debug link into JTAG mode, if the target supports it.
Definition: arm_adi_v5.c:872
int dap_register_commands(struct command_context *cmd_ctx)
Definition: arm_dap.c:536
int dap_dp_init_or_reconnect(struct adiv5_dap *dap)
Initialize a DAP or do reconnect if DAP is not accessible.
Definition: arm_adi_v5.c:752
int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type, target_addr_t *addr, int32_t idx)
Definition: arm_adi_v5.c:2178
#define DP_APSEL_MAX
Definition: arm_adi_v5.h:105
int dap_dp_init(struct adiv5_dap *dap)
Initialize a DAP.
Definition: arm_adi_v5.c:675
static int dap_sync(struct adiv5_dap *dap)
Definition: arm_adi_v5.h:610
struct adiv5_dap * adiv5_get_dap(struct arm_dap_object *obj)
Definition: arm_dap.c:68
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Synchronous read of a word from memory or a system register.
Definition: arm_adi_v5.c:259
int dap_to_swd(struct adiv5_dap *dap)
Put the debug link into SWD mode, if the target supports it.
Definition: arm_adi_v5.c:854
struct adiv5_ap * dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1091
int dap_put_ap(struct adiv5_ap *ap)
Definition: arm_adi_v5.c:1111
#define MEM_AP_REG_CFG_LA
Definition: arm_adi_v5.h:200
int mem_ap_init(struct adiv5_ap *ap)
Initialize a DAP.
Definition: arm_adi_v5.c:783
int mem_ap_write_buf(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:628
swd_special_seq
Definition: arm_adi_v5.h:229
@ DORMANT_TO_JTAG
Definition: arm_adi_v5.h:236
@ JTAG_TO_SWD
Definition: arm_adi_v5.h:231
@ DORMANT_TO_SWD
Definition: arm_adi_v5.h:235
@ LINE_RESET
Definition: arm_adi_v5.h:230
@ JTAG_TO_DORMANT
Definition: arm_adi_v5.h:232
@ SWD_TO_DORMANT
Definition: arm_adi_v5.h:234
@ SWD_TO_JTAG
Definition: arm_adi_v5.h:233
static int dap_queue_ap_read(struct adiv5_ap *ap, unsigned reg, uint32_t *data)
Queue an AP register read.
Definition: arm_adi_v5.h:546
const char * adiv5_dap_name(struct adiv5_dap *self)
Definition: arm_dap.c:56
void dap_invalidate_cache(struct adiv5_dap *dap)
Invalidate cached DP select and cached TAR and CSW of all APs.
Definition: arm_adi_v5.c:656
const struct command_registration dap_instance_commands[]
Definition: arm_adi_v5.c:2785
static bool is_adiv6(const struct adiv5_dap *dap)
Check if DAP is ADIv6.
Definition: arm_adi_v5.h:479
#define AP_REG_IDR_VALUE(d, c, t)
Definition: arm_adi_v5.h:220
static int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg, uint32_t mask, uint32_t value, int timeout)
Definition: arm_adi_v5.h:630
static int dap_run(struct adiv5_dap *dap)
Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they ar...
Definition: arm_adi_v5.h:604
static bool dap_is_multidrop(struct adiv5_dap *dap)
Check if SWD multidrop configuration is valid.
Definition: arm_adi_v5.h:712
#define AP_REG_IDR_CLASS_NONE
Definition: arm_adi_v5.h:216
int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg, struct jim_getopt_info *goi)
Definition: arm_adi_v5.c:2377
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Synchronous write of a word to memory or a system register.
Definition: arm_adi_v5.c:311
int mask
Definition: esirisc.c:1698
uint8_t type
Definition: esp_usb_jtag.c:0
void alive_sleep(uint64_t ms)
Definition: log.c:460
#define ERROR_WAIT
Definition: log.h:162
#define LOG_ERROR(expr ...)
Definition: log.h:123
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:155
uint32_t addr
Definition: nuttx.c:65
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
This represents an ARM Debug Interface (v5) Access Port (AP).
Definition: arm_adi_v5.h:243
bool unaligned_access_bad
Definition: arm_adi_v5.h:288
bool config_ap_never_release
Definition: arm_adi_v5.h:300
bool tar_valid
Definition: arm_adi_v5.h:291
bool packed_transfers
Definition: arm_adi_v5.h:285
uint32_t tar_autoincr_block
Definition: arm_adi_v5.h:282
unsigned int refcount
Definition: arm_adi_v5.h:297
uint64_t ap_num
ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coheren...
Definition: arm_adi_v5.h:254
struct adiv5_dap * dap
DAP this AP belongs to.
Definition: arm_adi_v5.h:247
uint32_t memaccess_tck
Configures how many extra tck clocks are added after starting a MEM-AP access before we try to read i...
Definition: arm_adi_v5.h:279
uint32_t cfg_reg
Definition: arm_adi_v5.h:294
uint32_t csw_default
Default value for (MEM-AP) AP_REG_CSW register.
Definition: arm_adi_v5.h:259
target_addr_t tar_value
Cache for (MEM-AP) AP_REG_TAR register value This is written to configure the address being read or w...
Definition: arm_adi_v5.h:273
uint32_t csw_value
Cache for (MEM-AP) AP_REG_CSW register value.
Definition: arm_adi_v5.h:266
This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
Definition: arm_adi_v5.h:320
uint8_t ack
Definition: arm_adi_v5.h:348
bool ti_be_32_quirks
Definition: arm_adi_v5.h:360
unsigned int adi_version
Indicates ADI version (5, 6 or 0 for unknown) being used.
Definition: arm_adi_v5.h:395
struct list_head cmd_journal
Definition: arm_adi_v5.h:324
struct adiv5_ap ap[DP_APSEL_MAX+1]
Definition: arm_adi_v5.h:336
size_t cmd_pool_size
Definition: arm_adi_v5.h:330
bool stlink_flush_ap_write
STLINK adapter need to know if last AP operation was read or write, and in case of write has to flush...
Definition: arm_adi_v5.h:370
uint32_t dp_ctrl_stat
Definition: arm_adi_v5.h:334
bool multidrop_instance_id_valid
TINSTANCE field of multidrop_targetsel has been configured.
Definition: arm_adi_v5.h:387
bool do_reconnect
Signals that an attempt to reestablish communication afresh should be performed before the next acces...
Definition: arm_adi_v5.h:376
const struct dap_ops * ops
Definition: arm_adi_v5.h:321
uint32_t * last_read
Holds the pointer to the destination word for the last queued read, for use with posted AP read seque...
Definition: arm_adi_v5.h:354
uint64_t apsel
Definition: arm_adi_v5.h:339
struct jtag_tap * tap
Definition: arm_adi_v5.h:332
bool switch_through_dormant
Record if enter in SWD required passing through DORMANT.
Definition: arm_adi_v5.h:392
uint32_t multidrop_targetsel
Value to select DP in SWD multidrop mode or DP_TARGETSEL_INVALID.
Definition: arm_adi_v5.h:383
uint64_t select
Cache for DP_SELECT register.
Definition: arm_adi_v5.h:345
bool multidrop_dp_id_valid
TPARTNO and TDESIGNER fields of multidrop_targetsel have been configured.
Definition: arm_adi_v5.h:385
struct list_head cmd_pool
Definition: arm_adi_v5.h:327
unsigned int asize
Definition: arm_adi_v5.h:398
bool ignore_syspwrupack
Flag saying whether to ignore the syspwrupack flag in DAP.
Definition: arm_adi_v5.h:380
bool nu_npcx_quirks
Definition: arm_adi_v5.h:364
struct adiv5_dap * dap
Definition: arm_adi_v5.h:750
struct adiv5_dap * dap
Definition: arm_adi_v5.h:743
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
Transport-neutral representation of queued DAP transactions, supporting both JTAG and SWD transports.
Definition: arm_adi_v5.h:408
int(* connect)(struct adiv5_dap *dap)
connect operation for SWD
Definition: arm_adi_v5.h:410
int(* queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack)
AP operation abort.
Definition: arm_adi_v5.h:430
int(* sync)(struct adiv5_dap *dap)
Executes all queued DAP operations but doesn't check sticky error conditions.
Definition: arm_adi_v5.h:437
void(* quit)(struct adiv5_dap *dap)
Optional; called at OpenOCD exit.
Definition: arm_adi_v5.h:440
int(* queue_dp_read)(struct adiv5_dap *dap, unsigned reg, uint32_t *data)
DP register read.
Definition: arm_adi_v5.h:416
int(* send_sequence)(struct adiv5_dap *dap, enum swd_special_seq seq)
send a sequence to the DAP
Definition: arm_adi_v5.h:413
int(* queue_dp_write)(struct adiv5_dap *dap, unsigned reg, uint32_t data)
DP register write.
Definition: arm_adi_v5.h:419
int(* run)(struct adiv5_dap *dap)
Executes all queued DAP operations.
Definition: arm_adi_v5.h:433
int(* queue_ap_write)(struct adiv5_ap *ap, unsigned reg, uint32_t data)
AP register write.
Definition: arm_adi_v5.h:426
int(* queue_ap_read)(struct adiv5_ap *ap, unsigned reg, uint32_t *data)
AP register read.
Definition: arm_adi_v5.h:423
A TCL -ish GetOpt like code.
Definition: jim-nvp.h:135
Definition: jtag.h:100
Definition: list.h:26
Definition: register.h:111
Definition: target.h:120
Definition: psoc6.c:84
uint64_t target_addr_t
Definition: types.h:335
uint8_t cmd
Definition: vdebug.c:1
uint8_t count[4]
Definition: vdebug.c:22