OpenOCD
arm_dpm.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /*
4  * Copyright (C) 2009 by David Brownell
5  */
6 
7 #ifndef OPENOCD_TARGET_ARM_DPM_H
8 #define OPENOCD_TARGET_ARM_DPM_H
9 
21 struct dpm_bpwp {
22  unsigned number;
23  uint32_t address;
24  uint32_t control;
25  /* true if hardware state needs flushing */
26  bool dirty;
27 };
28 
29 struct dpm_bp {
30  struct breakpoint *bp;
31  struct dpm_bpwp bpwp;
32 };
33 
34 struct dpm_wp {
35  struct watchpoint *wp;
36  struct dpm_bpwp bpwp;
37 };
38 
47 struct arm_dpm {
48  struct arm *arm;
49 
51  uint64_t didr;
52 
54  int (*prepare)(struct arm_dpm *dpm);
55 
57  int (*finish)(struct arm_dpm *dpm);
58 
60  int (*instr_execute)(struct arm_dpm *dpm, uint32_t opcode);
61 
62  /* WRITE TO CPU */
63 
65  int (*instr_write_data_dcc)(struct arm_dpm *dpm,
66  uint32_t opcode, uint32_t data);
67 
68  int (*instr_write_data_dcc_64)(struct arm_dpm *dpm,
69  uint32_t opcode, uint64_t data);
70 
72  int (*instr_write_data_r0)(struct arm_dpm *dpm,
73  uint32_t opcode, uint32_t data);
74 
76  int (*instr_write_data_r0_64)(struct arm_dpm *dpm,
77  uint32_t opcode, uint64_t data);
78 
80  int (*instr_cpsr_sync)(struct arm_dpm *dpm);
81 
82  /* READ FROM CPU */
83 
85  int (*instr_read_data_dcc)(struct arm_dpm *dpm,
86  uint32_t opcode, uint32_t *data);
87 
88  int (*instr_read_data_dcc_64)(struct arm_dpm *dpm,
89  uint32_t opcode, uint64_t *data);
90 
92  int (*instr_read_data_r0)(struct arm_dpm *dpm,
93  uint32_t opcode, uint32_t *data);
94 
95  int (*instr_read_data_r0_64)(struct arm_dpm *dpm,
96  uint32_t opcode, uint64_t *data);
97 
98  struct reg *(*arm_reg_current)(struct arm *arm,
99  unsigned regnum);
100 
101  /* BREAKPOINT/WATCHPOINT SUPPORT */
102 
109  int (*bpwp_enable)(struct arm_dpm *dpm, unsigned index_value,
110  uint32_t addr, uint32_t control);
111 
117  int (*bpwp_disable)(struct arm_dpm *dpm, unsigned index_value);
118 
119  /* The breakpoint and watchpoint arrays are private to the
120  * DPM infrastructure. There are nbp indices in the dbp
121  * array. There are nwp indices in the dwp array.
122  */
123 
124  unsigned nbp;
125  unsigned nwp;
126  struct dpm_bp *dbp;
127  struct dpm_wp *dwp;
128 
135 
137  uint32_t dscr;
138 
140  unsigned int last_el;
141 
142  /* FIXME -- read/write DCSR methods and symbols */
143 };
144 
145 int arm_dpm_setup(struct arm_dpm *dpm);
146 int arm_dpm_initialize(struct arm_dpm *dpm);
147 
148 int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum);
149 int arm_dpm_read_current_registers(struct arm_dpm *dpm);
150 int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
151 
152 int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp);
153 
154 void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t wfar);
155 
156 /* DSCR bits; see ARMv7a arch spec section C10.3.1.
157  * Not all v7 bits are valid in v6.
158  */
159 #define DSCR_CORE_HALTED (0x1 << 0)
160 #define DSCR_CORE_RESTARTED (0x1 << 1)
161 #define DSCR_ENTRY_MASK (0xF << 2)
162 #define DSCR_STICKY_ABORT_PRECISE (0x1 << 6)
163 #define DSCR_STICKY_ABORT_IMPRECISE (0x1 << 7)
164 #define DSCR_STICKY_UNDEFINED (0x1 << 8)
165 #define DSCR_DBG_NOPWRDWN (0x1 << 9) /* v6 only */
166 #define DSCR_DBG_ACK (0x1 << 10)
167 #define DSCR_INT_DIS (0x1 << 11)
168 #define DSCR_CP14_USR_COMMS (0x1 << 12)
169 #define DSCR_ITR_EN (0x1 << 13)
170 #define DSCR_HALT_DBG_MODE (0x1 << 14)
171 #define DSCR_MON_DBG_MODE (0x1 << 15)
172 #define DSCR_SEC_PRIV_INVASV_DIS (0x1 << 16)
173 #define DSCR_SEC_PRIV_NINVASV_DIS (0x1 << 17)
174 #define DSCR_NON_SECURE (0x1 << 18)
175 #define DSCR_DSCRD_IMPRECISE_ABORT (0x1 << 19)
176 #define DSCR_EXT_DCC_MASK (0x3 << 20) /* DTR mode */ /* bits 22, 23 are reserved */
177 #define DSCR_INSTR_COMP (0x1 << 24)
178 #define DSCR_PIPE_ADVANCE (0x1 << 25)
179 #define DSCR_DTRTX_FULL_LATCHED (0x1 << 26)
180 #define DSCR_DTRRX_FULL_LATCHED (0x1 << 27) /* bit 28 is reserved */
181 #define DSCR_DTR_TX_FULL (0x1 << 29)
182 #define DSCR_DTR_RX_FULL (0x1 << 30) /* bit 31 is reserved */
183 
184 #define DSCR_ENTRY(dscr) ((dscr) & 0x3f)
185 #define DSCR_RUN_MODE(dscr) ((dscr) & 0x03)
186 
187 
188 /* Methods of entry into debug mode */
189 #define DSCR_ENTRY_HALT_REQ (0x03)
190 #define DSCR_ENTRY_BREAKPOINT (0x07)
191 #define DSCR_ENTRY_IMPRECISE_WATCHPT (0x0B)
192 #define DSCR_ENTRY_BKPT_INSTR (0x0F)
193 #define DSCR_ENTRY_EXT_DBG_REQ (0x13)
194 #define DSCR_ENTRY_VECT_CATCH (0x17)
195 #define DSCR_ENTRY_D_SIDE_ABORT (0x1B) /* v6 only */
196 #define DSCR_ENTRY_I_SIDE_ABORT (0x1F) /* v6 only */
197 #define DSCR_ENTRY_OS_UNLOCK (0x23)
198 #define DSCR_ENTRY_PRECISE_WATCHPT (0x2B)
199 
200 /* DTR modes */
201 #define DSCR_EXT_DCC_NON_BLOCKING (0x0 << 20)
202 #define DSCR_EXT_DCC_STALL_MODE (0x1 << 20)
203 #define DSCR_EXT_DCC_FAST_MODE (0x2 << 20) /* bits 22, 23 are reserved */
204 
205 
206 
207 
208 
209 /* DRCR (debug run control register) bits */
210 #define DRCR_HALT (1 << 0)
211 #define DRCR_RESTART (1 << 1)
212 #define DRCR_CLEAR_EXCEPTIONS (1 << 2)
213 
214 void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
215 
216 /* PRCR (Device Power-down and Reset Control Register) bits */
217 #define PRCR_DEBUG_NO_POWER_DOWN (1 << 0)
218 #define PRCR_WARM_RESET (1 << 1)
219 #define PRCR_HOLD_NON_DEBUG_RESET (1 << 2)
220 
221 /* PRSR (Device Power-down and Reset Status Register) bits */
222 #define PRSR_POWERUP_STATUS (1 << 0)
223 #define PRSR_STICKY_POWERDOWN_STATUS (1 << 1)
224 #define PRSR_RESET_STATUS (1 << 2)
225 #define PRSR_STICKY_RESET_STATUS (1 << 3)
226 #define PRSR_HALTED (1 << 4) /* v7.1 Debug only */
227 #define PRSR_OSLK (1 << 5) /* v7.1 Debug only */
228 #define PRSR_DLK (1 << 6) /* v7.1 Debug only */
229 
230 /* OSLSR (OS Lock Status Register) bits */
231 #define OSLSR_OSLM0 (1 << 0)
232 #define OSLSR_OSLK (1 << 1)
233 #define OSLSR_NTT (1 << 2)
234 #define OSLSR_OSLM1 (1 << 3)
235 #define OSLSR_OSLM (OSLSR_OSLM0|OSLSR_OSLM1)
236 
237 #endif /* OPENOCD_TARGET_ARM_DPM_H */
arm_mode
Represent state of an ARM core.
Definition: arm.h:74
int arm_dpm_read_current_registers(struct arm_dpm *dpm)
Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or ...
Definition: arm_dpm.c:333
int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
Definition: arm_dpm.c:100
int arm_dpm_setup(struct arm_dpm *dpm)
Hooks up this DPM to its associated target; call only once.
Definition: arm_dpm.c:1049
int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
Definition: arm_dpm.c:163
int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
Writes all modified core registers for all processor modes.
Definition: arm_dpm.c:441
void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t wfar)
Definition: arm_dpm.c:987
void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr)
Definition: arm_dpm.c:1011
int arm_dpm_initialize(struct arm_dpm *dpm)
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affec...
Definition: arm_dpm.c:1114
enum arm_mode mode
Definition: armv4_5.c:277
uint32_t addr
Definition: nuttx.c:65
This wraps an implementation of DPM primitives.
Definition: arm_dpm.h:47
target_addr_t wp_addr
Target dependent watchpoint address.
Definition: arm_dpm.h:134
int(* instr_read_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from dcc after execution.
Definition: arm_dpm.h:85
uint64_t didr
Cache of DIDR.
Definition: arm_dpm.h:51
int(* instr_write_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Runs one instruction, writing data to R0 before execution.
Definition: arm_dpm.h:76
int(* instr_read_data_dcc_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Definition: arm_dpm.h:88
int(* instr_execute)(struct arm_dpm *dpm, uint32_t opcode)
Runs one instruction.
Definition: arm_dpm.h:60
int(* instr_write_data_dcc_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Definition: arm_dpm.h:68
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
Definition: arm_dpm.h:72
struct arm * arm
Definition: arm_dpm.h:48
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
Definition: arm_dpm.h:57
int(* bpwp_enable)(struct arm_dpm *dpm, unsigned index_value, uint32_t addr, uint32_t control)
Enables one breakpoint or watchpoint by writing to the hardware registers.
Definition: arm_dpm.h:109
struct dpm_bp * dbp
Definition: arm_dpm.h:126
unsigned int last_el
Recent exception level on armv8.
Definition: arm_dpm.h:140
int(* instr_write_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
Definition: arm_dpm.h:65
int(* bpwp_disable)(struct arm_dpm *dpm, unsigned index_value)
Disables one breakpoint or watchpoint by clearing its hardware control registers.
Definition: arm_dpm.h:117
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
Definition: arm_dpm.h:54
int(* instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
Definition: arm_dpm.h:92
unsigned nbp
Definition: arm_dpm.h:124
int(* instr_read_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Definition: arm_dpm.h:95
unsigned nwp
Definition: arm_dpm.h:125
struct dpm_wp * dwp
Definition: arm_dpm.h:127
int(* instr_cpsr_sync)(struct arm_dpm *dpm)
Optional core-specific operation invoked after CPSR writes.
Definition: arm_dpm.h:80
uint32_t dscr
Recent value of DSCR.
Definition: arm_dpm.h:137
Represents a generic ARM core, with standard application registers.
Definition: arm.h:167
Definition: arm_dpm.h:29
struct dpm_bpwp bpwp
Definition: arm_dpm.h:31
struct breakpoint * bp
Definition: arm_dpm.h:30
uint32_t control
Definition: arm_dpm.h:24
unsigned number
Definition: arm_dpm.h:22
bool dirty
Definition: arm_dpm.h:26
uint32_t address
Definition: arm_dpm.h:23
Definition: arm_dpm.h:34
struct watchpoint * wp
Definition: arm_dpm.h:35
struct dpm_bpwp bpwp
Definition: arm_dpm.h:36
Definition: register.h:111
uint64_t target_addr_t
Definition: types.h:335