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arm_dpm.h File Reference

This is the interface to the Debug Programmers Model for ARMv6 and ARMv7 processors. More...

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Data Structures

struct  arm_dpm
 This wraps an implementation of DPM primitives. More...
 
struct  dpm_bp
 
struct  dpm_bpwp
 
struct  dpm_wp
 

Macros

#define DRCR_CLEAR_EXCEPTIONS   (1 << 2)
 
#define DRCR_HALT   (1 << 0)
 
#define DRCR_RESTART   (1 << 1)
 
#define DSCR_CORE_HALTED   (0x1 << 0)
 
#define DSCR_CORE_RESTARTED   (0x1 << 1)
 
#define DSCR_CP14_USR_COMMS   (0x1 << 12)
 
#define DSCR_DBG_ACK   (0x1 << 10)
 
#define DSCR_DBG_NOPWRDWN   (0x1 << 9) /* v6 only */
 
#define DSCR_DSCRD_IMPRECISE_ABORT   (0x1 << 19)
 
#define DSCR_DTR_RX_FULL   (0x1 << 30) /* bit 31 is reserved */
 
#define DSCR_DTR_TX_FULL   (0x1 << 29)
 
#define DSCR_DTRRX_FULL_LATCHED   (0x1 << 27) /* bit 28 is reserved */
 
#define DSCR_DTRTX_FULL_LATCHED   (0x1 << 26)
 
#define DSCR_ENTRY(dscr)   ((dscr) & 0x3f)
 
#define DSCR_ENTRY_BKPT_INSTR   (0x0F)
 
#define DSCR_ENTRY_BREAKPOINT   (0x07)
 
#define DSCR_ENTRY_D_SIDE_ABORT   (0x1B) /* v6 only */
 
#define DSCR_ENTRY_EXT_DBG_REQ   (0x13)
 
#define DSCR_ENTRY_HALT_REQ   (0x03)
 
#define DSCR_ENTRY_I_SIDE_ABORT   (0x1F) /* v6 only */
 
#define DSCR_ENTRY_IMPRECISE_WATCHPT   (0x0B)
 
#define DSCR_ENTRY_MASK   (0xF << 2)
 
#define DSCR_ENTRY_OS_UNLOCK   (0x23)
 
#define DSCR_ENTRY_PRECISE_WATCHPT   (0x2B)
 
#define DSCR_ENTRY_VECT_CATCH   (0x17)
 
#define DSCR_EXT_DCC_FAST_MODE   (0x2 << 20) /* bits 22, 23 are reserved */
 
#define DSCR_EXT_DCC_MASK   (0x3 << 20) /* DTR mode */ /* bits 22, 23 are reserved */
 
#define DSCR_EXT_DCC_NON_BLOCKING   (0x0 << 20)
 
#define DSCR_EXT_DCC_STALL_MODE   (0x1 << 20)
 
#define DSCR_HALT_DBG_MODE   (0x1 << 14)
 
#define DSCR_INSTR_COMP   (0x1 << 24)
 
#define DSCR_INT_DIS   (0x1 << 11)
 
#define DSCR_ITR_EN   (0x1 << 13)
 
#define DSCR_MON_DBG_MODE   (0x1 << 15)
 
#define DSCR_NON_SECURE   (0x1 << 18)
 
#define DSCR_PIPE_ADVANCE   (0x1 << 25)
 
#define DSCR_RUN_MODE(dscr)   ((dscr) & 0x03)
 
#define DSCR_SEC_PRIV_INVASV_DIS   (0x1 << 16)
 
#define DSCR_SEC_PRIV_NINVASV_DIS   (0x1 << 17)
 
#define DSCR_STICKY_ABORT_IMPRECISE   (0x1 << 7)
 
#define DSCR_STICKY_ABORT_PRECISE   (0x1 << 6)
 
#define DSCR_STICKY_UNDEFINED   (0x1 << 8)
 
#define OSLSR_NTT   (1 << 2)
 
#define OSLSR_OSLK   (1 << 1)
 
#define OSLSR_OSLM   (OSLSR_OSLM0|OSLSR_OSLM1)
 
#define OSLSR_OSLM0   (1 << 0)
 
#define OSLSR_OSLM1   (1 << 3)
 
#define PRCR_DEBUG_NO_POWER_DOWN   (1 << 0)
 
#define PRCR_HOLD_NON_DEBUG_RESET   (1 << 2)
 
#define PRCR_WARM_RESET   (1 << 1)
 
#define PRSR_DLK   (1 << 6) /* v7.1 Debug only */
 
#define PRSR_HALTED   (1 << 4) /* v7.1 Debug only */
 
#define PRSR_OSLK   (1 << 5) /* v7.1 Debug only */
 
#define PRSR_POWERUP_STATUS   (1 << 0)
 
#define PRSR_RESET_STATUS   (1 << 2)
 
#define PRSR_STICKY_POWERDOWN_STATUS   (1 << 1)
 
#define PRSR_STICKY_RESET_STATUS   (1 << 3)
 

Functions

int arm_dpm_initialize (struct arm_dpm *dpm)
 Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affected the debug module. More...
 
int arm_dpm_modeswitch (struct arm_dpm *dpm, enum arm_mode mode)
 
int arm_dpm_read_current_registers (struct arm_dpm *dpm)
 Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb). More...
 
int arm_dpm_read_reg (struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 
void arm_dpm_report_dscr (struct arm_dpm *dpm, uint32_t dcsr)
 
void arm_dpm_report_wfar (struct arm_dpm *dpm, uint32_t wfar)
 
int arm_dpm_setup (struct arm_dpm *dpm)
 Hooks up this DPM to its associated target; call only once. More...
 
int arm_dpm_write_dirty_registers (struct arm_dpm *dpm, bool bpwp)
 Writes all modified core registers for all processor modes. More...
 

Detailed Description

This is the interface to the Debug Programmers Model for ARMv6 and ARMv7 processors.

ARMv6 processors (such as ARM11xx implementations) introduced a model which became part of the ARMv7-AR architecture which is most familiar through the Cortex-A series parts. While specific details differ (like how to write the instruction register), the high level models easily support shared code because those registers are compatible.

Definition in file arm_dpm.h.

Macro Definition Documentation

◆ DRCR_CLEAR_EXCEPTIONS

#define DRCR_CLEAR_EXCEPTIONS   (1 << 2)

Definition at line 212 of file arm_dpm.h.

◆ DRCR_HALT

#define DRCR_HALT   (1 << 0)

Definition at line 210 of file arm_dpm.h.

◆ DRCR_RESTART

#define DRCR_RESTART   (1 << 1)

Definition at line 211 of file arm_dpm.h.

◆ DSCR_CORE_HALTED

#define DSCR_CORE_HALTED   (0x1 << 0)

Definition at line 159 of file arm_dpm.h.

◆ DSCR_CORE_RESTARTED

#define DSCR_CORE_RESTARTED   (0x1 << 1)

Definition at line 160 of file arm_dpm.h.

◆ DSCR_CP14_USR_COMMS

#define DSCR_CP14_USR_COMMS   (0x1 << 12)

Definition at line 168 of file arm_dpm.h.

◆ DSCR_DBG_ACK

#define DSCR_DBG_ACK   (0x1 << 10)

Definition at line 166 of file arm_dpm.h.

◆ DSCR_DBG_NOPWRDWN

#define DSCR_DBG_NOPWRDWN   (0x1 << 9) /* v6 only */

Definition at line 165 of file arm_dpm.h.

◆ DSCR_DSCRD_IMPRECISE_ABORT

#define DSCR_DSCRD_IMPRECISE_ABORT   (0x1 << 19)

Definition at line 175 of file arm_dpm.h.

◆ DSCR_DTR_RX_FULL

#define DSCR_DTR_RX_FULL   (0x1 << 30) /* bit 31 is reserved */

Definition at line 182 of file arm_dpm.h.

◆ DSCR_DTR_TX_FULL

#define DSCR_DTR_TX_FULL   (0x1 << 29)

Definition at line 181 of file arm_dpm.h.

◆ DSCR_DTRRX_FULL_LATCHED

#define DSCR_DTRRX_FULL_LATCHED   (0x1 << 27) /* bit 28 is reserved */

Definition at line 180 of file arm_dpm.h.

◆ DSCR_DTRTX_FULL_LATCHED

#define DSCR_DTRTX_FULL_LATCHED   (0x1 << 26)

Definition at line 179 of file arm_dpm.h.

◆ DSCR_ENTRY

#define DSCR_ENTRY (   dscr)    ((dscr) & 0x3f)

Definition at line 184 of file arm_dpm.h.

◆ DSCR_ENTRY_BKPT_INSTR

#define DSCR_ENTRY_BKPT_INSTR   (0x0F)

Definition at line 192 of file arm_dpm.h.

◆ DSCR_ENTRY_BREAKPOINT

#define DSCR_ENTRY_BREAKPOINT   (0x07)

Definition at line 190 of file arm_dpm.h.

◆ DSCR_ENTRY_D_SIDE_ABORT

#define DSCR_ENTRY_D_SIDE_ABORT   (0x1B) /* v6 only */

Definition at line 195 of file arm_dpm.h.

◆ DSCR_ENTRY_EXT_DBG_REQ

#define DSCR_ENTRY_EXT_DBG_REQ   (0x13)

Definition at line 193 of file arm_dpm.h.

◆ DSCR_ENTRY_HALT_REQ

#define DSCR_ENTRY_HALT_REQ   (0x03)

Definition at line 189 of file arm_dpm.h.

◆ DSCR_ENTRY_I_SIDE_ABORT

#define DSCR_ENTRY_I_SIDE_ABORT   (0x1F) /* v6 only */

Definition at line 196 of file arm_dpm.h.

◆ DSCR_ENTRY_IMPRECISE_WATCHPT

#define DSCR_ENTRY_IMPRECISE_WATCHPT   (0x0B)

Definition at line 191 of file arm_dpm.h.

◆ DSCR_ENTRY_MASK

#define DSCR_ENTRY_MASK   (0xF << 2)

Definition at line 161 of file arm_dpm.h.

◆ DSCR_ENTRY_OS_UNLOCK

#define DSCR_ENTRY_OS_UNLOCK   (0x23)

Definition at line 197 of file arm_dpm.h.

◆ DSCR_ENTRY_PRECISE_WATCHPT

#define DSCR_ENTRY_PRECISE_WATCHPT   (0x2B)

Definition at line 198 of file arm_dpm.h.

◆ DSCR_ENTRY_VECT_CATCH

#define DSCR_ENTRY_VECT_CATCH   (0x17)

Definition at line 194 of file arm_dpm.h.

◆ DSCR_EXT_DCC_FAST_MODE

#define DSCR_EXT_DCC_FAST_MODE   (0x2 << 20) /* bits 22, 23 are reserved */

Definition at line 203 of file arm_dpm.h.

◆ DSCR_EXT_DCC_MASK

#define DSCR_EXT_DCC_MASK   (0x3 << 20) /* DTR mode */ /* bits 22, 23 are reserved */

Definition at line 176 of file arm_dpm.h.

◆ DSCR_EXT_DCC_NON_BLOCKING

#define DSCR_EXT_DCC_NON_BLOCKING   (0x0 << 20)

Definition at line 201 of file arm_dpm.h.

◆ DSCR_EXT_DCC_STALL_MODE

#define DSCR_EXT_DCC_STALL_MODE   (0x1 << 20)

Definition at line 202 of file arm_dpm.h.

◆ DSCR_HALT_DBG_MODE

#define DSCR_HALT_DBG_MODE   (0x1 << 14)

Definition at line 170 of file arm_dpm.h.

◆ DSCR_INSTR_COMP

#define DSCR_INSTR_COMP   (0x1 << 24)

Definition at line 177 of file arm_dpm.h.

◆ DSCR_INT_DIS

#define DSCR_INT_DIS   (0x1 << 11)

Definition at line 167 of file arm_dpm.h.

◆ DSCR_ITR_EN

#define DSCR_ITR_EN   (0x1 << 13)

Definition at line 169 of file arm_dpm.h.

◆ DSCR_MON_DBG_MODE

#define DSCR_MON_DBG_MODE   (0x1 << 15)

Definition at line 171 of file arm_dpm.h.

◆ DSCR_NON_SECURE

#define DSCR_NON_SECURE   (0x1 << 18)

Definition at line 174 of file arm_dpm.h.

◆ DSCR_PIPE_ADVANCE

#define DSCR_PIPE_ADVANCE   (0x1 << 25)

Definition at line 178 of file arm_dpm.h.

◆ DSCR_RUN_MODE

#define DSCR_RUN_MODE (   dscr)    ((dscr) & 0x03)

Definition at line 185 of file arm_dpm.h.

◆ DSCR_SEC_PRIV_INVASV_DIS

#define DSCR_SEC_PRIV_INVASV_DIS   (0x1 << 16)

Definition at line 172 of file arm_dpm.h.

◆ DSCR_SEC_PRIV_NINVASV_DIS

#define DSCR_SEC_PRIV_NINVASV_DIS   (0x1 << 17)

Definition at line 173 of file arm_dpm.h.

◆ DSCR_STICKY_ABORT_IMPRECISE

#define DSCR_STICKY_ABORT_IMPRECISE   (0x1 << 7)

Definition at line 163 of file arm_dpm.h.

◆ DSCR_STICKY_ABORT_PRECISE

#define DSCR_STICKY_ABORT_PRECISE   (0x1 << 6)

Definition at line 162 of file arm_dpm.h.

◆ DSCR_STICKY_UNDEFINED

#define DSCR_STICKY_UNDEFINED   (0x1 << 8)

Definition at line 164 of file arm_dpm.h.

◆ OSLSR_NTT

#define OSLSR_NTT   (1 << 2)

Definition at line 233 of file arm_dpm.h.

◆ OSLSR_OSLK

#define OSLSR_OSLK   (1 << 1)

Definition at line 232 of file arm_dpm.h.

◆ OSLSR_OSLM

#define OSLSR_OSLM   (OSLSR_OSLM0|OSLSR_OSLM1)

Definition at line 235 of file arm_dpm.h.

◆ OSLSR_OSLM0

#define OSLSR_OSLM0   (1 << 0)

Definition at line 231 of file arm_dpm.h.

◆ OSLSR_OSLM1

#define OSLSR_OSLM1   (1 << 3)

Definition at line 234 of file arm_dpm.h.

◆ PRCR_DEBUG_NO_POWER_DOWN

#define PRCR_DEBUG_NO_POWER_DOWN   (1 << 0)

Definition at line 217 of file arm_dpm.h.

◆ PRCR_HOLD_NON_DEBUG_RESET

#define PRCR_HOLD_NON_DEBUG_RESET   (1 << 2)

Definition at line 219 of file arm_dpm.h.

◆ PRCR_WARM_RESET

#define PRCR_WARM_RESET   (1 << 1)

Definition at line 218 of file arm_dpm.h.

◆ PRSR_DLK

#define PRSR_DLK   (1 << 6) /* v7.1 Debug only */

Definition at line 228 of file arm_dpm.h.

◆ PRSR_HALTED

#define PRSR_HALTED   (1 << 4) /* v7.1 Debug only */

Definition at line 226 of file arm_dpm.h.

◆ PRSR_OSLK

#define PRSR_OSLK   (1 << 5) /* v7.1 Debug only */

Definition at line 227 of file arm_dpm.h.

◆ PRSR_POWERUP_STATUS

#define PRSR_POWERUP_STATUS   (1 << 0)

Definition at line 222 of file arm_dpm.h.

◆ PRSR_RESET_STATUS

#define PRSR_RESET_STATUS   (1 << 2)

Definition at line 224 of file arm_dpm.h.

◆ PRSR_STICKY_POWERDOWN_STATUS

#define PRSR_STICKY_POWERDOWN_STATUS   (1 << 1)

Definition at line 223 of file arm_dpm.h.

◆ PRSR_STICKY_RESET_STATUS

#define PRSR_STICKY_RESET_STATUS   (1 << 3)

Definition at line 225 of file arm_dpm.h.

Function Documentation

◆ arm_dpm_initialize()

int arm_dpm_initialize ( struct arm_dpm dpm)

Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affected the debug module.

Definition at line 1114 of file arm_dpm.c.

References arm_dpm::arm, dpm_bp::bpwp, dpm_wp::bpwp, arm_dpm::bpwp_disable, arm_dpm::dbp, arm_dpm::dwp, ERROR_OK, LOG_WARNING, arm_dpm::nbp, dpm_bpwp::number, arm_dpm::nwp, arm::target, and target_name().

Referenced by arm11_dpm_init(), and cortex_a_dpm_setup().

◆ arm_dpm_modeswitch()

◆ arm_dpm_read_current_registers()

int arm_dpm_read_current_registers ( struct arm_dpm dpm)

Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).

In normal operation this is called on entry to halting debug state, possibly after some other operations supporting restore of debug state or making sure the CPU is fully idle (drain write buffer, etc).

Definition at line 333 of file arm_dpm.c.

References arm_dpm::arm, arm_dpm_read_reg(), arm_reg_current(), arm_set_cpsr(), ARMV4_5_MRS, arm::core_cache, arm::cpsr, reg::dirty, arm::dpm, ERROR_OK, arm_dpm::finish, arm_dpm::instr_read_data_r0, arm_dpm::prepare, reg_cache::reg_list, and reg::valid.

Referenced by arm11_debug_entry(), and cortex_a_debug_entry().

◆ arm_dpm_read_reg()

◆ arm_dpm_report_dscr()

◆ arm_dpm_report_wfar()

void arm_dpm_report_wfar ( struct arm_dpm dpm,
uint32_t  wfar 
)

◆ arm_dpm_setup()

◆ arm_dpm_write_dirty_registers()

int arm_dpm_write_dirty_registers ( struct arm_dpm dpm,
bool  bpwp 
)

Writes all modified core registers for all processor modes.

In normal operation this is called on exit from halting debug state.

Parameters
dpmrepresents the processor
bpwptrue ensures breakpoints and watchpoints are set, false ensures they are cleared

Definition at line 441 of file arm_dpm.c.

References target_type::add_breakpoint, reg::arch_info, arm_dpm::arm, arm_dpm_modeswitch(), ARM_MODE_ANY, ARM_MODE_FIQ, ARM_MODE_USR, dpm_bp::bp, dpm_bp::bpwp, dpm_wp::bpwp, arm::core_cache, arm::core_mode, arm::cpsr, arm_dpm::dbp, reg::dirty, arm::dpm, dpm_add_breakpoint(), dpm_maybe_update_bpwp(), dpm_write_pc_core_state(), dpm_write_reg(), arm_dpm::dwp, ERROR_OK, reg::exist, arm_dpm::finish, breakpoint::is_set, watchpoint::is_set, arm_reg::mode, mode, arm_dpm::nbp, NULL, arm_reg::num, reg_cache::num_regs, arm_dpm::nwp, arm::pc, arm_dpm::prepare, reg_cache::reg_list, arm::target, target::type, and dpm_wp::wp.

Referenced by arm11_leave_debug_state(), and cortex_a_restore_context().