29 #define _DEBUG_INSTRUCTION_EXECUTION_
47 LOG_DEBUG(
"Bringing target into debug mode");
139 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) {
144 LOG_DEBUG(
"DRAIN, DSCR %08x (DONE)", dscr);
244 LOG_ERROR(
"wDTR/rDTR inconsistent (DSCR %08x)",
245 (
unsigned) arm11->
dscr);
291 NULL, chain5_fields + 0);
386 LOG_WARNING(
"Timeout (1000ms) waiting for instructions to complete");
418 address &= 0xFFFFFFFC;
440 target_addr_t address,
int handle_breakpoints,
int debug_execution)
463 if (!debug_execution)
467 if (handle_breakpoints) {
482 unsigned brp_num = 0;
494 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
530 LOG_WARNING(
"Timeout (1000ms) waiting for instructions to complete");
538 if (!debug_execution)
567 uint32_t next_instruction;
572 if ((next_instruction & 0xFFF00070) == 0xe1200070) {
578 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) {
583 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
616 brp[1].
value = 0x1 | (3 << 1) | (0x0F << 5)
617 | (0 << 14) | (0 << 16) | (0 << 20)
633 brp[0].
value = next_pc;
634 brp[1].
value = 0x1 | (3 << 1) | (0x0F << 5)
635 | (0 << 14) | (0 << 16) | (0 << 20)
676 "Timeout (1000ms) waiting for instructions to complete");
709 LOG_WARNING(
"Reset is not asserted because the target is not examined.");
710 LOG_WARNING(
"Use a reset button or power cycle the target.");
769 LOG_WARNING(
"%s: ran after reset and before halt ...",
794 bool arm11_config_memrw_no_increment)
805 LOG_DEBUG(
"ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"",
825 for (
size_t i = 0; i <
count; i++) {
829 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000));
844 for (
size_t i = 0; i <
count; i++) {
847 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0));
854 uint16_t svalue = res;
855 memcpy(
buffer + i *
sizeof(uint16_t), &svalue,
sizeof(uint16_t));
863 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
865 uint32_t *words = (uint32_t *)(
void *)
buffer;
892 uint32_t address, uint32_t
size,
903 LOG_DEBUG(
"ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"",
934 for (
size_t i = 0; i <
count; i++) {
945 !no_increment ? 0xe4c01001 : 0xe5c01000);
957 for (
size_t i = 0; i <
count; i++) {
959 memcpy(&value,
buffer + i *
sizeof(uint16_t),
sizeof(uint16_t));
971 !no_increment ? 0xe0c010b2 : 0xe1c010b0);
983 uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
986 uint32_t *words = (uint32_t *)(
void *)
buffer;
994 instr, words,
count);
997 instr, words,
count);
1006 if (!no_increment) {
1015 LOG_ERROR(
"Data transfer failed. Expected end "
1016 "address 0x%08x, got 0x%08x",
1022 "use 'arm11 memwrite burst disable' to disable fast burst mode");
1054 LOG_INFO(
"sw breakpoint requested, but software breakpoints not enabled");
1060 LOG_DEBUG(
"no breakpoint unit available for hardware breakpoint");
1065 LOG_DEBUG(
"only breakpoints of four bytes length supported");
1092 LOG_ERROR(
"'target arm11' expects IR LENGTH = 5");
1096 arm11 = calloc(1,
sizeof(*arm11));
1136 uint32_t didr, device_id;
1137 uint8_t implementor;
1163 chain0_fields), chain0_fields,
TAP_IDLE);
1168 switch ((device_id >> 12) & 0xFFFF) {
1173 type =
"ARM11 MPCore";
1190 switch ((didr >> 16) & 0x0F) {
1195 LOG_ERROR(
"Only ARM v6 and v6.1 debug supported.");
1199 arm11->
brp = ((didr >> 24) & 0x0F) + 1;
1204 LOG_DEBUG(
"IDCODE %08" PRIx32
" IMPLEMENTOR %02x DIDR %08" PRIx32,
1205 device_id, implementor, didr);
1235 #define ARM11_BOOL_WRAPPER(name, print_name) \
1236 COMMAND_HANDLER(arm11_handle_bool_ ## name) \
1238 struct target *target = get_current_target(CMD_CTX); \
1239 struct arm11_common *arm11 = target_to_arm11(target); \
1241 return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1242 &arm11->name, print_name); \
1276 .handler = arm11_handle_bool_memwrite_burst,
1278 .help =
"Display or modify flag controlling potentially "
1279 "risky fast burst mode (default: enabled)",
1280 .usage =
"['enable'|'disable']",
1283 .name =
"error_fatal",
1284 .handler = arm11_handle_bool_memwrite_error_fatal,
1286 .help =
"Display or modify flag controlling transfer "
1287 "termination on transfer errors"
1288 " (default: enabled)",
1289 .usage =
"['enable'|'disable']",
1298 .
name =
"hardware_step",
1299 .handler = arm11_handle_bool_hardware_step,
1301 .help =
"DEBUG ONLY - Hardware single stepping"
1302 " (default: disabled)",
1303 .usage =
"['enable'|'disable']",
1308 .help =
"memwrite command group",
1313 .
name =
"step_irq_enable",
1314 .handler = arm11_handle_bool_step_irq_enable,
1316 .help =
"Display or modify flag controlling interrupt "
1317 "enable while stepping (default: disabled)",
1318 .usage =
"['enable'|'disable']",
1322 .handler = arm11_handle_vcr,
1324 .help =
"Display or modify Vector Catch Register",
1340 .help =
"ARM11 command group",
#define CHECK_RETVAL(action)
static int arm11_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static int arm11_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
static int arm11_examine(struct target *target)
COMMAND_HANDLER(arm11_handle_vcr)
static int arm11_poll(struct target *target)
static int arm11_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
static const struct command_registration arm11_mw_command_handlers[]
static const struct command_registration arm11_command_handlers[]
static void arm11_deinit_target(struct target *target)
static int arm11_halt(struct target *target)
static int arm11_write_memory_inner(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer, bool no_increment)
static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
Restore processor state.
static int arm11_assert_reset(struct target *target)
static int arm11_arch_state(struct target *target)
#define ARM11_BOOL_WRAPPER(name, print_name)
static int arm11_read_memory_inner(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, bool arm11_config_memrw_no_increment)
static int arm11_init_target(struct command_context *cmd_ctx, struct target *target)
static int arm11_deassert_reset(struct target *target)
struct target_type arm11_target
Holds methods for ARM11xx targets.
static int arm11_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
static int arm11_debug_entry(struct arm11_common *arm11)
Save processor state.
static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
static int arm11_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
static const struct command_registration arm11_any_command_handlers[]
static int arm11_target_create(struct target *target, Jim_Interp *interp)
static int arm11_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
static int arm11_check_init(struct arm11_common *arm11)
Check and if necessary take control of the system.
#define ARM11_TAP_DEFAULT
static struct arm11_common * target_to_arm11(struct target *target)
int arm11_run_instr_data_to_core1(struct arm11_common *arm11, uint32_t opcode, uint32_t data)
Execute an instruction via ITR while handing data into the core via DTR.
int arm11_run_instr_data_to_core_noack(struct arm11_common *arm11, uint32_t opcode, uint32_t *data, size_t count)
Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution.
int arm11_run_instr_data_to_core_via_r0(struct arm11_common *arm11, uint32_t opcode, uint32_t data)
Load data into core via DTR then move it to r0 then execute one instruction via ITR.
void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_field *fields, tap_state_t state)
int arm11_bpwp_flush(struct arm11_common *arm11)
Flush any pending breakpoint and watchpoint updates.
int arm11_read_memory_word(struct arm11_common *arm11, uint32_t address, uint32_t *result)
Read word from address.
int arm11_read_dscr(struct arm11_common *arm11)
Read and save the Debug Status and Control Register (DSCR).
int arm11_write_dscr(struct arm11_common *arm11, uint32_t dscr)
Write the Debug Status and Control Register (DSCR)
int arm11_run_instr_data_from_core(struct arm11_common *arm11, uint32_t opcode, uint32_t *data, size_t count)
Execute one instruction via ITR repeatedly while reading data from the core via DTR on each execution...
int arm11_sc7_clear_vbw(struct arm11_common *arm11)
Clear VCR and all breakpoints and watchpoints via scan chain 7.
int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr)
Set up high-level debug module utilities.
void arm11_add_ir(struct arm11_common *arm11, uint8_t instr, tap_state_t state)
Write JTAG instruction register.
void arm11_setup_field(struct arm11_common *arm11, int num_bits, void *out_data, void *in_data, struct scan_field *field)
Code de-clutter: Construct struct scan_field to write out a value.
int arm11_run_instr_data_finish(struct arm11_common *arm11)
Cleanup after ITR/DTR operations from the arm11_run_instr...
int arm11_run_instr_data_prepare(struct arm11_common *arm11)
Prepare the stage for ITR/DTR operations from the arm11_run_instr...
int arm11_run_instr_data_from_core_via_r0(struct arm11_common *arm11, uint32_t opcode, uint32_t *data)
Execute one instruction via ITR then load r0 into DTR and read DTR from core.
int arm11_sc7_set_vcr(struct arm11_common *arm11, uint32_t value)
Write VCR register.
void arm11_dpm_deinit(struct arm11_common *arm11)
int arm11_run_instr_data_to_core(struct arm11_common *arm11, uint32_t opcode, uint32_t *data, size_t count)
Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution.
int arm11_run_instr_no_data1(struct arm11_common *arm11, uint32_t opcode)
Execute one instruction via ITR.
int arm11_add_debug_scan_n(struct arm11_common *arm11, uint8_t chain, tap_state_t state)
Select and write to Scan Chain Register (SCREG)
int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions, size_t count)
Apply reads and writes to scan chain 7.
int arm_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Runs ARM code in the target to check whether a memory block holds all ones.
int arm_arch_state(struct target *target)
int arm_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Runs ARM code in the target to calculate a CRC32 checksum.
int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
const char * arm_get_gdb_arch(struct target *target)
const struct command_registration arm_command_handlers[]
int arm_init_arch_info(struct target *target, struct arm *arm)
void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
int arm_dpm_read_current_registers(struct arm_dpm *dpm)
Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or ...
int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
Writes all modified core registers for all processor modes.
void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
#define DSCR_CORE_RESTARTED
#define DSCR_HALT_DBG_MODE
Macros used to generate various ARM or Thumb opcodes.
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
struct reg_cache * etm_build_reg_cache(struct target *target, struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
int etm_setup(struct target *target)
const struct command_registration etm_command_handlers[]
void jtag_add_reset(int req_tlr_or_trst, int req_srst)
A reset of the TAP state machine can be requested.
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
void jtag_add_tlr(void)
Run a TAP_RESET reset where the end state is TAP_RESET, regardless of the start state.
enum reset_types jtag_get_reset_config(void)
#define LOG_USER(expr ...)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
void register_cache_invalidate(struct reg_cache *cache)
Marks the contents of the register cache as invalid (and clean).
static int step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
size_t size
Size of the control block search area.
uint32_t vcr
Configured Vector Catch Register settings.
bool simulate_reset_on_next_halt
Perform cleanups of the ARM state on next halt.
size_t brp
Number of Breakpoint Register Pairs from DIDR
size_t free_brps
Number of breakpoints allocated.
struct arm_dpm dpm
Debug module state.
uint32_t dscr
Last retrieved DSCR value.
bool memwrite_error_fatal
struct arm_jtag jtag_info
Used with arm11_sc7_run to make a list of read/write commands for scan chain 7.
uint8_t address
Register address mode.
uint32_t value
If write then set this to value to be written.
bool write
Access mode: true for write, false for read.
target_addr_t wp_addr
Target dependent watchpoint address.
struct etm_context * etm
Handle for the Embedded Trace Module, if one is present.
enum arm_core_type core_type
Indicates what registers are in the ARM state core register set.
struct reg * pc
Handle to the PC; valid in all core modes.
struct reg_cache * core_cache
struct arm_dpm * dpm
Handle for the debug module, if one is present.
struct target * target
Backpointer to the target.
enum arm_state core_state
Record the current core state: ARM, Thumb, or otherwise.
enum breakpoint_type type
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
int ir_length
size of instruction register
This structure defines a single scan field in the scan.
This holds methods shared between all instances of a given target type.
const char * name
Name of this type of target.
enum target_debug_reason debug_reason
struct reg_cache * reg_cache
struct breakpoint * breakpoints
int target_call_event_callbacks(struct target *target, enum target_event event)
void target_free_all_working_areas(struct target *target)
const char * target_state_name(struct target *t)
Return the name of this targets current state.
int target_halt(struct target *target)
bool target_has_event_action(struct target *target, enum target_event event)
Returns true only if the target has a handler for the specified event.
struct target * get_current_target(struct command_context *cmd_ctx)
void target_handle_event(struct target *target, enum target_event e)
#define ERROR_TARGET_NOT_HALTED
@ TARGET_EVENT_DEBUG_HALTED
@ TARGET_EVENT_RESET_ASSERT
#define ERROR_TARGET_NOT_EXAMINED
static const char * target_name(struct target *target)
Returns the instance-specific name of the specified target.
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
static void target_set_examined(struct target *target)
Sets the examined flag for the given target.
static bool target_was_examined(struct target *target)
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.