OpenOCD
riscv-011.c File Reference
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Data Structures

struct  bits_t
 
struct  memory_cache_line
 
struct  riscv011_info_t
 
struct  scans_t
 
struct  trigger
 

Macros

#define CACHE_NO_READ   128
 Write cache to the target, and optionally run the program. More...
 
#define CSR_BPCONTROL_BPACTION   (0xff<<11)
 
#define CSR_BPCONTROL_BPMATCH   (0xf<<7)
 
#define CSR_BPCONTROL_H   (1<<5)
 
#define CSR_BPCONTROL_M   (1<<6)
 
#define CSR_BPCONTROL_R   (1<<2)
 
#define CSR_BPCONTROL_S   (1<<4)
 
#define CSR_BPCONTROL_U   (1<<3)
 
#define CSR_BPCONTROL_W   (1<<1)
 
#define CSR_BPCONTROL_X   (1<<0)
 
#define DBUS   0x11
 
#define DBUS_ADDRESS_START   36
 
#define DBUS_ADDRESS_UNKNOWN   0xffff
 
#define DBUS_DATA_SIZE   34
 
#define DBUS_DATA_START   2
 
#define DBUS_OP_SIZE   2
 
#define DBUS_OP_START   0
 
#define DEBUG_LENGTH   264
 
#define DEBUG_RAM_START   0x400
 
#define DEBUG_ROM_EXCEPTION   (DEBUG_ROM_START + 8)
 
#define DEBUG_ROM_RESUME   (DEBUG_ROM_START + 4)
 
#define DEBUG_ROM_START   0x800
 
#define DMAUTHDATA0   0x12
 
#define DMAUTHDATA1   0x13
 
#define DMCONTROL   0x10
 
#define DMCONTROL_ACCESS   (7<<12)
 
#define DMCONTROL_AUTOINCREMENT   (1<<15)
 
#define DMCONTROL_BUSERROR   (7<<19)
 
#define DMCONTROL_FULLRESET   1
 
#define DMCONTROL_HALTNOT   (((uint64_t)1)<<32)
 
#define DMCONTROL_HARTID   (0x3ff<<2)
 
#define DMCONTROL_INTERRUPT   (((uint64_t)1)<<33)
 
#define DMCONTROL_NDRESET   (1<<1)
 
#define DMCONTROL_SERIAL   (3<<16)
 
#define DMINFO   0x11
 
#define DMINFO_ABUSSIZE   (0x7fU<<25)
 
#define DMINFO_ACCESS128   (1<<20)
 
#define DMINFO_ACCESS16   (1<<17)
 
#define DMINFO_ACCESS32   (1<<18)
 
#define DMINFO_ACCESS64   (1<<19)
 
#define DMINFO_ACCESS8   (1<<16)
 
#define DMINFO_AUTHBUSY   (1<<4)
 
#define DMINFO_AUTHENTICATED   (1<<5)
 
#define DMINFO_AUTHTYPE   (3<<2)
 
#define DMINFO_DRAMSIZE   (0x3f<<10)
 
#define DMINFO_SERIALCOUNT   (0xf<<21)
 
#define DMINFO_VERSION   3
 
#define DRAM_CACHE_SIZE   16
 
#define DTMCONTROL   0x10
 
#define DTMCONTROL_ADDRBITS   (0xf<<4)
 
#define DTMCONTROL_DBUS_RESET   (1<<16)
 
#define DTMCONTROL_IDLE   (7<<10)
 
#define DTMCONTROL_VERSION   (0xf)
 
#define get_field(reg, mask)   (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
 Since almost everything can be accomplish by scanning the dbus register, all functions here assume dbus is already selected. More...
 
#define set_field(reg, mask, val)   (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
 
#define SETHALTNOT   0x10c
 

Typedefs

typedef enum slot slot_t
 

Enumerations

enum  dbus_op_t {
  DBUS_OP_NOP = 0 , DBUS_OP_READ = 1 , DBUS_OP_WRITE = 2 , DBUS_OP_NOP = 0 ,
  DBUS_OP_READ = 1 , DBUS_OP_WRITE = 2
}
 
enum  dbus_status_t {
  DBUS_STATUS_SUCCESS = 0 , DBUS_STATUS_FAILED = 2 , DBUS_STATUS_BUSY = 3 , DBUS_STATUS_SUCCESS = 0 ,
  DBUS_STATUS_FAILED = 2 , DBUS_STATUS_BUSY = 3
}
 
enum  riscv_error_t { RE_OK , RE_FAIL , RE_AGAIN }
 
enum  slot {
  SLOT0 , SLOT1 , SLOT_LAST , SLOT0 ,
  SLOT1 , SLOT_LAST , SLOT0 , SLOT1 ,
  SLOT_LAST
}
 

Functions

static void add_dbus_scan (const struct target *target, struct scan_field *field, uint8_t *out_value, uint8_t *in_value, dbus_op_t op, uint16_t address, uint64_t data)
 
static int arch_state (struct target *target)
 
static int assert_reset (struct target *target)
 
static int cache_check (struct target *target)
 
static void cache_clean (struct target *target)
 
static uint64_t cache_get (struct target *target, slot_t slot)
 
static uint32_t cache_get32 (struct target *target, unsigned int address)
 
static void cache_invalidate (struct target *target)
 
static void cache_set (struct target *target, slot_t slot, uint64_t data)
 
static void cache_set32 (struct target *target, unsigned int index, uint32_t data)
 
static void cache_set_jump (struct target *target, unsigned int index)
 
static void cache_set_load (struct target *target, unsigned int index, unsigned int reg, slot_t slot)
 
static void cache_set_store (struct target *target, unsigned int index, unsigned int reg, slot_t slot)
 
static int cache_write (struct target *target, unsigned int address, bool run)
 
static COMMAND_HELPER (riscv011_print_info, struct target *target)
 
static uint64_t dbus_read (struct target *target, uint16_t address)
 
static dbus_status_t dbus_scan (struct target *target, uint16_t *address_in, uint64_t *data_in, dbus_op_t op, uint16_t address_out, uint64_t data_out)
 
static void dbus_write (struct target *target, uint16_t address, uint64_t value)
 
static int deassert_reset (struct target *target)
 
static void deinit_target (struct target *target)
 
static uint16_t dram_address (unsigned int index)
 
static int dram_check32 (struct target *target, unsigned int index, uint32_t expected)
 
static uint32_t dram_read32 (struct target *target, unsigned int index)
 
static void dram_write32 (struct target *target, unsigned int index, uint32_t value, bool set_interrupt)
 
static void dram_write_jump (struct target *target, unsigned int index, bool set_interrupt)
 
static uint32_t dtmcontrol_scan (struct target *target, uint32_t out)
 
static void dump_debug_ram (struct target *target)
 
static void dump_field (const struct scan_field *field)
 
static int examine (struct target *target)
 
static int execute_resume (struct target *target, bool step)
 
static int full_step (struct target *target, bool announce)
 
static riscv011_info_tget_info (const struct target *target)
 
static int get_register (struct target *target, riscv_reg_t *value, int regid)
 
static int halt (struct target *target)
 
static int handle_halt (struct target *target, bool announce)
 
static riscv_error_t handle_halt_routine (struct target *target)
 
static uint32_t idcode_scan (struct target *target)
 
static void increase_dbus_busy_delay (struct target *target)
 
static void increase_interrupt_high_delay (struct target *target)
 
static int init_target (struct command_context *cmd_ctx, struct target *target)
 
static uint32_t load_slot (const struct target *target, unsigned int dest, slot_t slot)
 
static int maybe_read_tselect (struct target *target)
 
static int maybe_write_tselect (struct target *target)
 
static int poll_target (struct target *target, bool announce)
 
static bits_t read_bits (struct target *target)
 Read the haltnot and interrupt bits. More...
 
static int read_memory (struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
 
static int read_remote_csr (struct target *target, uint64_t *value, uint32_t csr)
 
static uint64_t reg_cache_get (struct target *target, unsigned int number)
 
static void reg_cache_set (struct target *target, unsigned int number, uint64_t value)
 
static int register_read (struct target *target, riscv_reg_t *value, int regnum)
 
static int register_write (struct target *target, unsigned int number, uint64_t value)
 
static int resume (struct target *target, int debug_execution, bool step)
 
static int riscv011_authdata_read (struct target *target, uint32_t *value, unsigned int index)
 
static int riscv011_authdata_write (struct target *target, uint32_t value, unsigned int index)
 
static int riscv011_poll (struct target *target)
 
static int riscv011_resume (struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
 
static void scans_add_read (scans_t *scans, slot_t slot, bool set_interrupt)
 Add one or more scans to read the indicated slot. More...
 
static void scans_add_read32 (scans_t *scans, uint16_t address, bool set_interrupt)
 Add a 32-bit dbus read. More...
 
static void scans_add_write32 (scans_t *scans, uint16_t address, uint32_t data, bool set_interrupt)
 Add a 32-bit dbus write to the scans structure. More...
 
static void scans_add_write_jump (scans_t *scans, uint16_t address, bool set_interrupt)
 Add a 32-bit dbus write for an instruction that jumps to the beginning of debug RAM. More...
 
static void scans_add_write_load (scans_t *scans, uint16_t address, unsigned int reg, slot_t slot, bool set_interrupt)
 Add a 32-bit dbus write for an instruction that loads from the indicated slot. More...
 
static void scans_add_write_store (scans_t *scans, uint16_t address, unsigned int reg, slot_t slot, bool set_interrupt)
 Add a 32-bit dbus write for an instruction that stores to the indicated slot. More...
 
static scans_tscans_delete (scans_t *scans)
 
static void scans_dump (scans_t *scans)
 
static int scans_execute (scans_t *scans)
 
static uint32_t scans_get_u32 (scans_t *scans, unsigned int index, unsigned first, unsigned num)
 
static uint64_t scans_get_u64 (scans_t *scans, unsigned int index, unsigned first, unsigned num)
 
static scans_tscans_new (struct target *target, unsigned int scan_count)
 
static void scans_reset (scans_t *scans)
 
static int set_register (struct target *target, int regid, uint64_t value)
 
static int setup_write_memory (struct target *target, uint32_t size)
 
static unsigned int slot_offset (const struct target *target, slot_t slot)
 
static int step (struct target *target, int current, target_addr_t address, int handle_breakpoints)
 
static uint32_t store_slot (const struct target *target, unsigned int src, slot_t slot)
 
static int strict_step (struct target *target, bool announce)
 
static int update_mstatus_actual (struct target *target)
 
static int wait_for_authbusy (struct target *target)
 
static int wait_for_debugint_clear (struct target *target, bool ignore_first)
 
static int wait_for_state (struct target *target, enum target_state state)
 
static int write_gpr (struct target *target, unsigned int gpr, uint64_t value)
 
static int write_memory (struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
 
static int write_remote_csr (struct target *target, uint32_t csr, uint64_t value)
 

Variables

struct target_type riscv011_target
 

Macro Definition Documentation

◆ CACHE_NO_READ

#define CACHE_NO_READ   128

Write cache to the target, and optionally run the program.

Then read the value at address into the cache, assuming address < 128.

Definition at line 861 of file riscv-011.c.

◆ CSR_BPCONTROL_BPACTION

#define CSR_BPCONTROL_BPACTION   (0xff<<11)

Definition at line 82 of file riscv-011.c.

◆ CSR_BPCONTROL_BPMATCH

#define CSR_BPCONTROL_BPMATCH   (0xf<<7)

Definition at line 81 of file riscv-011.c.

◆ CSR_BPCONTROL_H

#define CSR_BPCONTROL_H   (1<<5)

Definition at line 79 of file riscv-011.c.

◆ CSR_BPCONTROL_M

#define CSR_BPCONTROL_M   (1<<6)

Definition at line 80 of file riscv-011.c.

◆ CSR_BPCONTROL_R

#define CSR_BPCONTROL_R   (1<<2)

Definition at line 76 of file riscv-011.c.

◆ CSR_BPCONTROL_S

#define CSR_BPCONTROL_S   (1<<4)

Definition at line 78 of file riscv-011.c.

◆ CSR_BPCONTROL_U

#define CSR_BPCONTROL_U   (1<<3)

Definition at line 77 of file riscv-011.c.

◆ CSR_BPCONTROL_W

#define CSR_BPCONTROL_W   (1<<1)

Definition at line 75 of file riscv-011.c.

◆ CSR_BPCONTROL_X

#define CSR_BPCONTROL_X   (1<<0)

Definition at line 74 of file riscv-011.c.

◆ DBUS

#define DBUS   0x11

Definition at line 99 of file riscv-011.c.

◆ DBUS_ADDRESS_START

#define DBUS_ADDRESS_START   36

Definition at line 114 of file riscv-011.c.

◆ DBUS_ADDRESS_UNKNOWN

#define DBUS_ADDRESS_UNKNOWN   0xffff

Definition at line 160 of file riscv-011.c.

◆ DBUS_DATA_SIZE

#define DBUS_DATA_SIZE   34

Definition at line 113 of file riscv-011.c.

◆ DBUS_DATA_START

#define DBUS_DATA_START   2

Definition at line 112 of file riscv-011.c.

◆ DBUS_OP_SIZE

#define DBUS_OP_SIZE   2

Definition at line 101 of file riscv-011.c.

◆ DBUS_OP_START

#define DBUS_OP_START   0

Definition at line 100 of file riscv-011.c.

◆ DEBUG_LENGTH

#define DEBUG_LENGTH   264

Definition at line 226 of file riscv-011.c.

◆ DEBUG_RAM_START

#define DEBUG_RAM_START   0x400

Definition at line 87 of file riscv-011.c.

◆ DEBUG_ROM_EXCEPTION

#define DEBUG_ROM_EXCEPTION   (DEBUG_ROM_START + 8)

Definition at line 86 of file riscv-011.c.

◆ DEBUG_ROM_RESUME

#define DEBUG_ROM_RESUME   (DEBUG_ROM_START + 4)

Definition at line 85 of file riscv-011.c.

◆ DEBUG_ROM_START

#define DEBUG_ROM_START   0x800

Definition at line 84 of file riscv-011.c.

◆ DMAUTHDATA0

#define DMAUTHDATA0   0x12

Definition at line 155 of file riscv-011.c.

◆ DMAUTHDATA1

#define DMAUTHDATA1   0x13

Definition at line 156 of file riscv-011.c.

◆ DMCONTROL

#define DMCONTROL   0x10

Definition at line 130 of file riscv-011.c.

◆ DMCONTROL_ACCESS

#define DMCONTROL_ACCESS   (7<<12)

Definition at line 136 of file riscv-011.c.

◆ DMCONTROL_AUTOINCREMENT

#define DMCONTROL_AUTOINCREMENT   (1<<15)

Definition at line 135 of file riscv-011.c.

◆ DMCONTROL_BUSERROR

#define DMCONTROL_BUSERROR   (7<<19)

Definition at line 133 of file riscv-011.c.

◆ DMCONTROL_FULLRESET

#define DMCONTROL_FULLRESET   1

Definition at line 139 of file riscv-011.c.

◆ DMCONTROL_HALTNOT

#define DMCONTROL_HALTNOT   (((uint64_t)1)<<32)

Definition at line 132 of file riscv-011.c.

◆ DMCONTROL_HARTID

#define DMCONTROL_HARTID   (0x3ff<<2)

Definition at line 137 of file riscv-011.c.

◆ DMCONTROL_INTERRUPT

#define DMCONTROL_INTERRUPT   (((uint64_t)1)<<33)

Definition at line 131 of file riscv-011.c.

◆ DMCONTROL_NDRESET

#define DMCONTROL_NDRESET   (1<<1)

Definition at line 138 of file riscv-011.c.

◆ DMCONTROL_SERIAL

#define DMCONTROL_SERIAL   (3<<16)

Definition at line 134 of file riscv-011.c.

◆ DMINFO

#define DMINFO   0x11

Definition at line 141 of file riscv-011.c.

◆ DMINFO_ABUSSIZE

#define DMINFO_ABUSSIZE   (0x7fU<<25)

Definition at line 142 of file riscv-011.c.

◆ DMINFO_ACCESS128

#define DMINFO_ACCESS128   (1<<20)

Definition at line 144 of file riscv-011.c.

◆ DMINFO_ACCESS16

#define DMINFO_ACCESS16   (1<<17)

Definition at line 147 of file riscv-011.c.

◆ DMINFO_ACCESS32

#define DMINFO_ACCESS32   (1<<18)

Definition at line 146 of file riscv-011.c.

◆ DMINFO_ACCESS64

#define DMINFO_ACCESS64   (1<<19)

Definition at line 145 of file riscv-011.c.

◆ DMINFO_ACCESS8

#define DMINFO_ACCESS8   (1<<16)

Definition at line 148 of file riscv-011.c.

◆ DMINFO_AUTHBUSY

#define DMINFO_AUTHBUSY   (1<<4)

Definition at line 151 of file riscv-011.c.

◆ DMINFO_AUTHENTICATED

#define DMINFO_AUTHENTICATED   (1<<5)

Definition at line 150 of file riscv-011.c.

◆ DMINFO_AUTHTYPE

#define DMINFO_AUTHTYPE   (3<<2)

Definition at line 152 of file riscv-011.c.

◆ DMINFO_DRAMSIZE

#define DMINFO_DRAMSIZE   (0x3f<<10)

Definition at line 149 of file riscv-011.c.

◆ DMINFO_SERIALCOUNT

#define DMINFO_SERIALCOUNT   (0xf<<21)

Definition at line 143 of file riscv-011.c.

◆ DMINFO_VERSION

#define DMINFO_VERSION   3

Definition at line 153 of file riscv-011.c.

◆ DRAM_CACHE_SIZE

#define DRAM_CACHE_SIZE   16

Definition at line 162 of file riscv-011.c.

◆ DTMCONTROL

#define DTMCONTROL   0x10

Definition at line 93 of file riscv-011.c.

◆ DTMCONTROL_ADDRBITS

#define DTMCONTROL_ADDRBITS   (0xf<<4)

Definition at line 96 of file riscv-011.c.

◆ DTMCONTROL_DBUS_RESET

#define DTMCONTROL_DBUS_RESET   (1<<16)

Definition at line 94 of file riscv-011.c.

◆ DTMCONTROL_IDLE

#define DTMCONTROL_IDLE   (7<<10)

Definition at line 95 of file riscv-011.c.

◆ DTMCONTROL_VERSION

#define DTMCONTROL_VERSION   (0xf)

Definition at line 97 of file riscv-011.c.

◆ get_field

#define get_field (   reg,
  mask 
)    (((reg) & (mask)) / ((mask) & ~((mask) << 1)))

Since almost everything can be accomplish by scanning the dbus register, all functions here assume dbus is already selected.

The exception are functions called directly by OpenOCD, which can't assume anything about what's currently in IR. They should set IR to dbus explicitly. Code structure

At the bottom of the stack are the OpenOCD JTAG functions: jtag_add_[id]r_scan jtag_execute_query jtag_add_runtest

There are a few functions to just instantly shift a register and get its value: dtmcontrol_scan idcode_scan dbus_scan

Because doing one scan and waiting for the result is slow, most functions batch up a bunch of dbus writes and then execute them all at once. They use the scans "class" for this: scans_new scans_delete scans_execute scans_add_... Usually you new(), call a bunch of add functions, then execute() and look at the results by calling scans_get...()

Optimized functions will directly use the scans class above, but slightly lazier code will use the cache functions that in turn use the scans functions: cache_get... cache_set... cache_write cache_set... update a local structure, which is then synced to the target with cache_write(). Only Debug RAM words that are actually changed are sent to the target. Afterwards use cache_get... to read results.

Definition at line 70 of file riscv-011.c.

◆ set_field

#define set_field (   reg,
  mask,
  val 
)    (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))

Definition at line 71 of file riscv-011.c.

◆ SETHALTNOT

#define SETHALTNOT   0x10c

Definition at line 89 of file riscv-011.c.

Typedef Documentation

◆ slot_t

typedef enum slot slot_t

Enumeration Type Documentation

◆ dbus_op_t

enum dbus_op_t
Enumerator
DBUS_OP_NOP 
DBUS_OP_READ 
DBUS_OP_WRITE 
DBUS_OP_NOP 
DBUS_OP_READ 
DBUS_OP_WRITE 

Definition at line 102 of file riscv-011.c.

◆ dbus_status_t

Enumerator
DBUS_STATUS_SUCCESS 
DBUS_STATUS_FAILED 
DBUS_STATUS_BUSY 
DBUS_STATUS_SUCCESS 
DBUS_STATUS_FAILED 
DBUS_STATUS_BUSY 

Definition at line 107 of file riscv-011.c.

◆ riscv_error_t

Enumerator
RE_OK 
RE_FAIL 
RE_AGAIN 

Definition at line 116 of file riscv-011.c.

◆ slot

enum slot
Enumerator
SLOT0 
SLOT1 
SLOT_LAST 
SLOT0 
SLOT1 
SLOT_LAST 
SLOT0 
SLOT1 
SLOT_LAST 

Definition at line 122 of file riscv-011.c.

Function Documentation

◆ add_dbus_scan()

static void add_dbus_scan ( const struct target target,
struct scan_field field,
uint8_t *  out_value,
uint8_t *  in_value,
dbus_op_t  op,
uint16_t  address,
uint64_t  data 
)
static

◆ arch_state()

static int arch_state ( struct target target)
static

Definition at line 2295 of file riscv-011.c.

References ERROR_OK.

◆ assert_reset()

◆ cache_check()

static int cache_check ( struct target target)
static

Definition at line 839 of file riscv-011.c.

References dram_check32(), dump_debug_ram(), ERROR_FAIL, ERROR_OK, get_info(), and info.

Referenced by examine().

◆ cache_clean()

static void cache_clean ( struct target target)
static

Definition at line 829 of file riscv-011.c.

References get_info(), and info.

Referenced by cache_write(), read_memory(), and write_memory().

◆ cache_get()

static uint64_t cache_get ( struct target target,
slot_t  slot 
)
static

Definition at line 1001 of file riscv-011.c.

References cache_get32(), offset, riscv_xlen(), and slot_offset().

Referenced by read_remote_csr(), register_read(), and write_memory().

◆ cache_get32()

static uint32_t cache_get32 ( struct target target,
unsigned int  address 
)
static

Definition at line 991 of file riscv-011.c.

References dram_read32(), get_info(), and info.

Referenced by cache_get(), examine(), read_remote_csr(), register_read(), and register_write().

◆ cache_invalidate()

static void cache_invalidate ( struct target target)
static

Definition at line 818 of file riscv-011.c.

References get_info(), and info.

Referenced by assert_reset(), examine(), execute_resume(), and handle_halt_routine().

◆ cache_set()

static void cache_set ( struct target target,
slot_t  slot,
uint64_t  data 
)
static

◆ cache_set32()

static void cache_set32 ( struct target target,
unsigned int  index,
uint32_t  data 
)
static

◆ cache_set_jump()

static void cache_set_jump ( struct target target,
unsigned int  index 
)
static

◆ cache_set_load()

static void cache_set_load ( struct target target,
unsigned int  index,
unsigned int  reg,
slot_t  slot 
)
static

◆ cache_set_store()

static void cache_set_store ( struct target target,
unsigned int  index,
unsigned int  reg,
slot_t  slot 
)
static

◆ cache_write()

◆ COMMAND_HELPER()

static COMMAND_HELPER ( riscv011_print_info  ,
struct target target 
)
static

Definition at line 2300 of file riscv-011.c.

References CMD, dbus_read(), DMINFO, DMINFO_AUTHENTICATED, and get_field.

◆ dbus_read()

static uint64_t dbus_read ( struct target target,
uint16_t  address 
)
static

◆ dbus_scan()

static dbus_status_t dbus_scan ( struct target target,
uint16_t *  address_in,
uint64_t *  data_in,
dbus_op_t  op,
uint16_t  address_out,
uint64_t  data_out 
)
static

◆ dbus_write()

static void dbus_write ( struct target target,
uint16_t  address,
uint64_t  value 
)
static

◆ deassert_reset()

static int deassert_reset ( struct target target)
static

◆ deinit_target()

static void deinit_target ( struct target target)
static

Definition at line 1408 of file riscv-011.c.

References target::arch_info, info, LOG_DEBUG, and NULL.

◆ dram_address()

static uint16_t dram_address ( unsigned int  index)
static

Definition at line 274 of file riscv-011.c.

Referenced by dram_check32(), dram_read32(), dram_write32(), and execute_resume().

◆ dram_check32()

static int dram_check32 ( struct target target,
unsigned int  index,
uint32_t  expected 
)
static

Definition at line 753 of file riscv-011.c.

References dbus_read(), dram_address(), ERROR_FAIL, ERROR_OK, and LOG_ERROR.

Referenced by cache_check().

◆ dram_read32()

static uint32_t dram_read32 ( struct target target,
unsigned int  index 
)
static

Definition at line 672 of file riscv-011.c.

References dbus_read(), and dram_address().

Referenced by cache_get32(), and dump_debug_ram().

◆ dram_write32()

static void dram_write32 ( struct target target,
unsigned int  index,
uint32_t  value,
bool  set_interrupt 
)
static

◆ dram_write_jump()

static void dram_write_jump ( struct target target,
unsigned int  index,
bool  set_interrupt 
)
static

Definition at line 1012 of file riscv-011.c.

References DEBUG_RAM_START, DEBUG_ROM_RESUME, dram_write32(), and jal().

Referenced by assert_reset(), and execute_resume().

◆ dtmcontrol_scan()

◆ dump_debug_ram()

static void dump_debug_ram ( struct target target)
static

Definition at line 809 of file riscv-011.c.

References DRAM_CACHE_SIZE, dram_read32(), and LOG_ERROR.

Referenced by cache_check(), cache_write(), and examine().

◆ dump_field()

◆ examine()

◆ execute_resume()

◆ full_step()

static int full_step ( struct target target,
bool  announce 
)
static

◆ get_info()

◆ get_register()

◆ halt()

◆ handle_halt()

◆ handle_halt_routine()

◆ idcode_scan()

◆ increase_dbus_busy_delay()

static void increase_dbus_busy_delay ( struct target target)
static

◆ increase_interrupt_high_delay()

static void increase_interrupt_high_delay ( struct target target)
static

Definition at line 350 of file riscv-011.c.

References get_info(), info, and LOG_DEBUG.

Referenced by cache_write(), handle_halt_routine(), read_memory(), and write_memory().

◆ init_target()

static int init_target ( struct command_context cmd_ctx,
struct target target 
)
static

◆ load_slot()

static uint32_t load_slot ( const struct target target,
unsigned int  dest,
slot_t  slot 
)
static

Definition at line 260 of file riscv-011.c.

References DEBUG_RAM_START, load(), offset, slot_offset(), and ZERO.

Referenced by scans_add_write_load().

◆ maybe_read_tselect()

static int maybe_read_tselect ( struct target target)
static

Definition at line 1082 of file riscv-011.c.

References CSR_TSELECT, ERROR_OK, get_info(), info, and read_remote_csr().

Referenced by handle_halt().

◆ maybe_write_tselect()

static int maybe_write_tselect ( struct target target)
static

Definition at line 1096 of file riscv-011.c.

References CSR_TSELECT, ERROR_OK, get_info(), info, and write_remote_csr().

Referenced by execute_resume(), get_register(), and register_write().

◆ poll_target()

static int poll_target ( struct target target,
bool  announce 
)
static

◆ read_bits()

static bits_t read_bits ( struct target target)
static

◆ read_memory()

◆ read_remote_csr()

static int read_remote_csr ( struct target target,
uint64_t *  value,
uint32_t  csr 
)
static

◆ reg_cache_get()

static uint64_t reg_cache_get ( struct target target,
unsigned int  number 
)
static

◆ reg_cache_set()

static void reg_cache_set ( struct target target,
unsigned int  number,
uint64_t  value 
)
static

◆ register_read()

static int register_read ( struct target target,
riscv_reg_t value,
int  regnum 
)
static

◆ register_write()

◆ resume()

static int resume ( struct target target,
int  debug_execution,
bool  step 
)
static

Definition at line 1195 of file riscv-011.c.

References ERROR_FAIL, execute_resume(), LOG_ERROR, and step().

Referenced by riscv011_resume().

◆ riscv011_authdata_read()

static int riscv011_authdata_read ( struct target target,
uint32_t *  value,
unsigned int  index 
)
static

Definition at line 2339 of file riscv-011.c.

References dbus_read(), DMAUTHDATA0, DMAUTHDATA1, ERROR_FAIL, ERROR_OK, LOG_ERROR, and wait_for_authbusy().

Referenced by init_target().

◆ riscv011_authdata_write()

static int riscv011_authdata_write ( struct target target,
uint32_t  value,
unsigned int  index 
)
static

Definition at line 2355 of file riscv-011.c.

References dbus_write(), DMAUTHDATA0, DMAUTHDATA1, ERROR_FAIL, ERROR_OK, LOG_ERROR, and wait_for_authbusy().

Referenced by init_target().

◆ riscv011_poll()

static int riscv011_poll ( struct target target)
static

Definition at line 1927 of file riscv-011.c.

References poll_target().

Referenced by examine(), and wait_for_state().

◆ riscv011_resume()

static int riscv011_resume ( struct target target,
int  current,
target_addr_t  address,
int  handle_breakpoints,
int  debug_execution 
)
static

Definition at line 1932 of file riscv-011.c.

References jtag_add_ir_scan(), resume(), RISCV_INFO, select_dbus, target::tap, and TAP_IDLE.

◆ scans_add_read()

static void scans_add_read ( scans_t scans,
slot_t  slot,
bool  set_interrupt 
)
static

Add one or more scans to read the indicated slot.

Definition at line 644 of file riscv-011.c.

References riscv_xlen(), scans_add_read32(), slot_offset(), and scans_t::target.

Referenced by handle_halt_routine().

◆ scans_add_read32()

static void scans_add_read32 ( scans_t scans,
uint16_t  address,
bool  set_interrupt 
)
static

◆ scans_add_write32()

static void scans_add_write32 ( scans_t scans,
uint16_t  address,
uint32_t  data,
bool  set_interrupt 
)
static

◆ scans_add_write_jump()

static void scans_add_write_jump ( scans_t scans,
uint16_t  address,
bool  set_interrupt 
)
static

Add a 32-bit dbus write for an instruction that jumps to the beginning of debug RAM.

Definition at line 605 of file riscv-011.c.

References DEBUG_RAM_START, DEBUG_ROM_RESUME, jal(), and scans_add_write32().

Referenced by handle_halt_routine().

◆ scans_add_write_load()

static void scans_add_write_load ( scans_t scans,
uint16_t  address,
unsigned int  reg,
slot_t  slot,
bool  set_interrupt 
)
static

Add a 32-bit dbus write for an instruction that loads from the indicated slot.

Definition at line 615 of file riscv-011.c.

References load_slot(), scans_add_write32(), and scans_t::target.

Referenced by handle_halt_routine().

◆ scans_add_write_store()

static void scans_add_write_store ( scans_t scans,
uint16_t  address,
unsigned int  reg,
slot_t  slot,
bool  set_interrupt 
)
static

Add a 32-bit dbus write for an instruction that stores to the indicated slot.

Definition at line 624 of file riscv-011.c.

References scans_add_write32(), store_slot(), and scans_t::target.

Referenced by handle_halt_routine().

◆ scans_delete()

static scans_t* scans_delete ( scans_t scans)
static

Definition at line 556 of file riscv-011.c.

References scans_t::field, scans_t::in, NULL, and scans_t::out.

Referenced by cache_write(), handle_halt_routine(), read_memory(), and write_memory().

◆ scans_dump()

static void scans_dump ( scans_t scans)
static

Definition at line 571 of file riscv-011.c.

References dump_field(), scans_t::field, and scans_t::next_scan.

Referenced by scans_execute().

◆ scans_execute()

static int scans_execute ( scans_t scans)
static

◆ scans_get_u32()

static uint32_t scans_get_u32 ( scans_t scans,
unsigned int  index,
unsigned  first,
unsigned  num 
)
static

Definition at line 658 of file riscv-011.c.

References buf_get_u32(), scans_t::in, and scans_t::scan_size.

Referenced by cache_write(), handle_halt_routine(), read_memory(), and write_memory().

◆ scans_get_u64()

static uint64_t scans_get_u64 ( scans_t scans,
unsigned int  index,
unsigned  first,
unsigned  num 
)
static

Definition at line 664 of file riscv-011.c.

References buf_get_u64(), scans_t::in, and scans_t::scan_size.

Referenced by handle_halt_routine(), and read_memory().

◆ scans_new()

static scans_t* scans_new ( struct target target,
unsigned int  scan_count 
)
static

◆ scans_reset()

static void scans_reset ( scans_t scans)
static

Definition at line 566 of file riscv-011.c.

References scans_t::next_scan.

Referenced by read_memory(), and write_memory().

◆ set_register()

static int set_register ( struct target target,
int  regid,
uint64_t  value 
)
static

Definition at line 1385 of file riscv-011.c.

References register_write(), and reg::value.

Referenced by init_target().

◆ setup_write_memory()

static int setup_write_memory ( struct target target,
uint32_t  size 
)
static

◆ slot_offset()

static unsigned int slot_offset ( const struct target target,
slot_t  slot 
)
static

◆ step()

◆ store_slot()

static uint32_t store_slot ( const struct target target,
unsigned int  src,
slot_t  slot 
)
static

Definition at line 267 of file riscv-011.c.

References DEBUG_RAM_START, offset, slot_offset(), store(), and ZERO.

Referenced by scans_add_write_store().

◆ strict_step()

static int strict_step ( struct target target,
bool  announce 
)
static

◆ update_mstatus_actual()

static int update_mstatus_actual ( struct target target)
static

◆ wait_for_authbusy()

static int wait_for_authbusy ( struct target target)
static

◆ wait_for_debugint_clear()

static int wait_for_debugint_clear ( struct target target,
bool  ignore_first 
)
static

◆ wait_for_state()

static int wait_for_state ( struct target target,
enum target_state  state 
)
static

◆ write_gpr()

static int write_gpr ( struct target target,
unsigned int  gpr,
uint64_t  value 
)
static

Definition at line 1072 of file riscv-011.c.

References cache_set(), cache_set_jump(), cache_set_load(), cache_write(), ERROR_FAIL, ERROR_OK, and SLOT0.

Referenced by write_memory().

◆ write_memory()

◆ write_remote_csr()

static int write_remote_csr ( struct target target,
uint32_t  csr,
uint64_t  value 
)
static

Variable Documentation

◆ riscv011_target

struct target_type riscv011_target
Initial value:
= {
.name = "riscv",
.init_target = init_target,
.deinit_target = deinit_target,
.examine = examine,
.poll = riscv011_poll,
.halt = halt,
.resume = riscv011_resume,
.step = step,
.assert_reset = assert_reset,
.deassert_reset = deassert_reset,
.write_memory = write_memory,
.arch_state = arch_state,
}
static int riscv011_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Definition: riscv-011.c:1932
static int riscv011_poll(struct target *target)
Definition: riscv-011.c:1927
static int examine(struct target *target)
Definition: riscv-011.c:1468
static int deassert_reset(struct target *target)
Definition: riscv-011.c:1978
static int assert_reset(struct target *target)
Definition: riscv-011.c:1942
static int init_target(struct command_context *cmd_ctx, struct target *target)
Definition: riscv-011.c:2371
static int arch_state(struct target *target)
Definition: riscv-011.c:2295
static int halt(struct target *target)
Definition: riscv-011.c:1390
static void deinit_target(struct target *target)
Definition: riscv-011.c:1408
static int step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
Definition: riscv-011.c:1442
static int write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: riscv-011.c:2157

Definition at line 2371 of file riscv-011.c.

Referenced by get_target_type().