36 uint8_t *in, uint8_t ir_len);
37 static int drscan(
struct target *t, uint8_t *out, uint8_t *in, uint8_t len);
49 int reg, uint32_t *regval, uint8_t cache);
51 int reg, uint32_t regval, uint8_t cache);
76 {
EAX,
"eax", 0x000000D01D660000, 0, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.core" },
77 {
ECX,
"ecx", 0x000000501D660000, 1, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.core" },
78 {
EDX,
"edx", 0x000000901D660000, 2, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.core" },
86 {
EIP,
"eip", 0x000000C01D660000, 3, 32,
REG_TYPE_CODE_PTR,
"general",
"org.gnu.gdb.i386.core" },
87 {
EFLAGS,
"eflags", 0x000000401D660000, 4, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.core" },
90 {
CS,
"cs", 0x000000281D660000, 5, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.core" },
116 {
CR0,
"cr0", 0x000000001D660000, 6, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.sys" },
117 {
CR2,
"cr2", 0x000000BC1D660000, 7, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.sys" },
118 {
CR3,
"cr3", 0x000000801D660000, 8, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.sys" },
119 {
CR4,
"cr4", 0x0000002C1D660000, 9, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.sys" },
126 {
DR6,
"dr6", 0x000000301D660000, 10, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.sys" },
127 {
DR7,
"dr7", 0x000000B01D660000, 11, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.sys" },
145 {
CSAR,
"csar", 0x000000741D660000, 12, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.sys" },
146 {
DSB,
"dsbase", 0x000000941D660000, 13, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.sys" },
147 {
DSL,
"dslimit", 0x000000541D660000, 14, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.sys" },
148 {
DSAR,
"dsar", 0x000000141D660000, 15, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.sys" },
160 {
SSAR,
"ssar", 0x000000D41D660000, 16, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.sys" },
165 {
PMCR,
"pmcr", 0x000000421D660000, 17, 32,
REG_TYPE_INT32,
"general",
"org.gnu.gdb.i386.sys" },
168 static const struct {
174 {
MEMRDB32,
"MEMRDB32", 0x0909090909090851 },
175 {
MEMRDB16,
"MEMRDB16", 0x09090909090851E6 },
176 {
MEMRDH32,
"MEMRDH32", 0x090909090908D166 },
177 {
MEMRDH16,
"MEMRDH16", 0x090909090908D1E6 },
178 {
MEMRDW32,
"MEMRDW32", 0x09090909090908D1 },
179 {
MEMRDW16,
"MEMRDW16", 0x0909090908D1E666 },
180 {
MEMWRB32,
"MEMWRB32", 0x0909090909090811 },
181 {
MEMWRB16,
"MEMWRB16", 0x09090909090811E6 },
182 {
MEMWRH32,
"MEMWRH32", 0x0909090909089166 },
183 {
MEMWRH16,
"MEMWRH16", 0x09090909090891E6 },
184 {
MEMWRW32,
"MEMWRW32", 0x0909090909090891 },
185 {
MEMWRW16,
"MEMWRW16", 0x090909090891E666 },
187 {
IORDB32,
"IORDB32", 0x0909090909090937 },
188 {
IORDB16,
"IORDB16", 0x09090909090937E6 },
189 {
IORDH32,
"IORDH32", 0x090909090909B766 },
190 {
IORDH16,
"IORDH16", 0x090909090909B7E6 },
191 {
IORDW32,
"IORDW32", 0x09090909090909B7 },
192 {
IORDW16,
"IORDW16", 0x0909090909B7E666 },
193 {
IOWRB32,
"IOWRB32", 0x0909090909090977 },
194 {
IOWRB16,
"IOWRB16", 0x09090909090977E6 },
195 {
IOWRH32,
"IOWRH32", 0x090909090909F766 },
196 {
IOWRH16,
"IOWRH16", 0x090909090909F7E6 },
197 {
IOWRW32,
"IOWRW32", 0x09090909090909F7 },
198 {
IOWRW16,
"IOWRW16", 0x0909090909F7E666 },
200 {
SRAMACCESS,
"SRAMACCESS", 0x0000000E9D660000 },
201 {
SRAM2PDR,
"SRAM2PDR", 0x4CF0000000000000 },
202 {
PDR2SRAM,
"PDR2SRAM", 0x0CF0000000000000 },
203 {
WBINVD,
"WBINVD", 0x09090909090990F0 },
210 LOG_ERROR(
"target running, halt it first");
215 uint8_t *in, uint8_t ir_len)
221 LOG_ERROR(
"%s invalid target tap", __func__);
227 LOG_ERROR(
"%s tap enabled but tap irlen=%d",
230 LOG_ERROR(
"%s tap not enabled and irlen=%d",
242 LOG_ERROR(
"%s failed to execute queue", __func__);
247 static int drscan(
struct target *t, uint8_t *out, uint8_t *in, uint8_t len)
254 LOG_ERROR(
"%s invalid target tap", __func__);
259 LOG_ERROR(
"%s data len is %d bits, max is %d bits",
271 LOG_ERROR(
"%s drscan failed to execute queue", __func__);
277 for (
int n = (len / 8) - 1 ; n >= 0; n--)
278 data = (data << 8) + *(in+n);
282 LOG_ERROR(
"%s no drscan data", __func__);
294 LOG_ERROR(
"%s error reading regs", __func__);
309 LOG_ERROR(
"%s error writing regs", __func__);
368 struct reg *reg_list = calloc(num_regs,
sizeof(
struct reg));
373 if (!cache || !reg_list || !arch_info) {
382 cache->
name =
"lakemont registers";
387 x86_32->
cache = cache;
389 for (i = 0; i < num_regs; i++) {
392 arch_info[i].
op =
regs[i].op;
395 reg_list[i].
size = 32;
396 reg_list[i].
value = calloc(1, 4);
397 reg_list[i].
dirty =
false;
398 reg_list[i].
valid =
false;
404 reg_list[i].
exist =
true;
412 LOG_ERROR(
"%s unable to allocate feature list", __func__);
418 LOG_ERROR(
"%s unable to allocate reg type list", __func__);
435 uint32_t tapstatus = 0;
439 LOG_DEBUG(
"TS before PM enter = 0x%08" PRIx32, tapstatus);
453 LOG_DEBUG(
"TS after PM enter = 0x%08" PRIx32, tapstatus);
458 LOG_ERROR(
"%s PM enter error, tapstatus = 0x%08" PRIx32
459 , __func__, tapstatus);
466 LOG_DEBUG(
"TS before PM exit = 0x%08" PRIx32, tapstatus);
510 LOG_DEBUG(
"EFLAGS = 0x%08" PRIx32
", VM86 = %d, IF = %d", eflags,
517 LOG_DEBUG(
"EFLAGS now = 0x%08" PRIx32
", VM86 = %d, IF = %d",
539 LOG_DEBUG(
"caching enabled CR0 = 0x%08" PRIx32, cr0);
612 LOG_DEBUG(
"read_all_core_hw_regs read %u registers ok", i);
631 LOG_DEBUG(
"write_all_core_hw_regs wrote %u registers ok", i);
662 LOG_DEBUG(
"reg=%s, op=0x%016" PRIx64
", val=0x%08" PRIx32,
680 LOG_DEBUG(
"reg=%s, op=0x%016" PRIx64
", val=0x%08" PRIx32,
728 LOG_ERROR(
"%s error disabling paging", __func__);
740 LOG_ERROR(
"%s error enabling paging", __func__);
759 LOG_ERROR(
"%s transaction error tapstatus = 0x%08" PRIx32
760 , __func__, tapstatus);
771 LOG_ERROR(
"%s error submitting pir", __func__);
782 LOG_ERROR(
"%s error submitting pir", __func__);
794 LOG_ERROR(
"%s error submitting pir", __func__);
857 LOG_ERROR(
"tapstatus invalid - scan_chain serialization or locked JTAG access issues");
866 LOG_INFO(
"target running for unknown reason");
888 uint32_t hwbreakpoint = (uint32_t)-1;
899 if (hwbreakpoint != (uint32_t)-1) {
903 LOG_USER(
"hit hardware breakpoint (hwreg=%" PRIu32
") at 0x%08" PRIx32, hwbreakpoint, eip);
905 uint32_t address = 0;
906 switch (hwbreakpoint) {
921 LOG_USER(
"hit '%s' watchpoint for 0x%08" PRIx32
" (hwreg=%" PRIu32
") at 0x%08" PRIx32,
941 LOG_USER(
"hit software breakpoint at 0x%08" PRIx32, eip-1);
946 LOG_USER(
"hit unknown breakpoint at 0x%08" PRIx32, eip);
955 LOG_USER(
"unknown break reason at 0x%08" PRIx32, eip);
970 LOG_USER(
"target halted due to %s at 0x%08" PRIx32
" in %s mode",
986 LOG_ERROR(
"%s target not running", __func__);
992 int handle_breakpoints,
int debug_execution)
1008 LOG_ERROR(
"%s stepping over a software breakpoint at 0x%08" PRIx32
" "
1009 "failed to resume the target", __func__, eip);
1016 while (activeswbp && !activeswbp->
is_set)
1017 activeswbp = activeswbp->
next;
1019 while (activehwbp && !activehwbp->
is_set)
1020 activehwbp = activehwbp->
next;
1021 if (activeswbp || activehwbp)
1041 uint32_t tapstatus = 0;
1055 LOG_DEBUG(
"modifying PMCR = 0x%08" PRIx32
" and EFLAGS = 0x%08" PRIx32, pmcr, eflags);
1059 LOG_DEBUG(
"EFLAGS [TF] [RF] bits set=0x%08" PRIx32
", PMCR=0x%08" PRIx32
", EIP=0x%08" PRIx32,
1083 LOG_USER(
"step done from EIP 0x%08" PRIx32
" to 0x%08" PRIx32, eip,
1090 LOG_ERROR(
"%s target didn't stop after executing a single step", __func__);
1123 LOG_ERROR(
"%s could not select quark_x10xx.cltap", __func__);
1137 LOG_ERROR(
"%s irscan failed to execute queue", __func__);
1147 LOG_ERROR(
"%s drscan failed to execute queue", __func__);
1168 uint8_t cf9_reset_val = 0x6;
1174 LOG_DEBUG(
"target must be halted first");
1191 LOG_ERROR(
"could not write to port 0xcf9");
1224 LOG_ERROR(
"could not update state after probemode entry");
1229 LOG_WARNING(
"%s: ran after reset and before halt ...",
static void buf_set_u64(uint8_t *_buffer, unsigned first, unsigned num, uint64_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
struct breakpoint * breakpoint_find(struct target *target, target_addr_t address)
static int halted(struct target *target, const char *label)
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
struct jtag_tap * jtag_tap_by_position(unsigned n)
void jtag_add_sleep(uint32_t us)
void jtag_add_ir_scan(struct jtag_tap *active, struct scan_field *in_fields, tap_state_t state)
Generate an IR SCAN with a list of scan fields with one entry for each enabled TAP.
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cache)
int lakemont_reset_deassert(struct target *t)
static const struct @101 regs[]
static int submit_instruction_pir(struct target *t, int num)
static int save_context(struct target *target)
static struct reg_cache * lakemont_build_reg_cache(struct target *target)
static int halt_prep(struct target *t)
static const struct reg_arch_type lakemont_reg_type
static bool is_paging_enabled(struct target *t)
int lakemont_init_target(struct command_context *cmd_ctx, struct target *t)
static uint8_t get_num_user_regs(struct target *t)
static int exit_probemode(struct target *t)
static int submit_instruction(struct target *t, int num)
int lakemont_arch_state(struct target *t)
int lakemont_init_arch_info(struct target *t, struct x86_32_common *x86_32)
static int enable_paging(struct target *t)
static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf)
static int submit_reg_pir(struct target *t, int num)
int lakemont_poll(struct target *t)
static int write_all_core_hw_regs(struct target *t)
static int do_resume(struct target *t)
int lakemont_step(struct target *t, int current, target_addr_t address, int handle_breakpoints)
int lakemont_update_after_probemode_entry(struct target *t)
int lakemont_reset_assert(struct target *t)
int lakemont_resume(struct target *t, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
bool check_not_halted(const struct target *t)
static int read_all_core_hw_regs(struct target *t)
static int lakemont_reset_break(struct target *t)
static bool sw_bpts_supported(struct target *t)
static int transaction_status(struct target *t)
static const struct @102 instructions[]
static int enter_probemode(struct target *t)
static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cache)
static int restore_context(struct target *target)
static int lakemont_get_core_reg(struct reg *reg)
static uint32_t get_tapstatus(struct target *t)
static int irscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t ir_len)
static int do_halt(struct target *t)
int lakemont_halt(struct target *t)
static int drscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t len)
static int disable_paging(struct target *t)
static int submit_pir(struct target *t, uint64_t op)
static struct scan_blk scan
#define LOG_USER(expr ...)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
enum breakpoint_type type
int ir_length
size of instruction register
bool enabled
Is this TAP currently enabled?
struct x86_32_common * x86_32_common
int(* get)(struct reg *reg)
struct reg_feature * feature
struct reg_data_type * reg_data_type
const struct reg_arch_type * type
uint8_t in[MAX_SCAN_SIZE]
uint8_t out[MAX_SCAN_SIZE]
This structure defines a single scan field in the scan.
int num_bits
The number of bits this field specifies.
uint8_t * in_value
A pointer to a 32-bit memory location for data scanned out.
const uint8_t * out_value
A pointer to value to be scanned into the device.
enum target_debug_reason debug_reason
struct reg_cache * reg_cache
struct breakpoint * breakpoints
struct watchpoint * watchpoints
enum x86_core_type core_type
bool(* sw_bpts_supported)(struct target *t)
int(* disable_paging)(struct target *t)
int(* read_hw_reg)(struct target *t, int reg, uint32_t *regval, uint8_t cache)
bool(* is_paging_enabled)(struct target *t)
uint8_t(* get_num_user_regs)(struct target *t)
int(* write_hw_reg)(struct target *t, int reg, uint32_t regval, uint8_t cache)
int forced_halt_for_reset
int(* enable_paging)(struct target *t)
uint32_t pm_regs[NUM_PM_REGS]
int(* submit_instruction)(struct target *t, int num)
struct jtag_tap * curr_tap
int(* transaction_status)(struct target *t)
int target_call_event_callbacks(struct target *target, enum target_event event)
int target_halt(struct target *target)
const char * debug_reason_name(struct target *t)
#define ERROR_TARGET_NOT_HALTED
static const char * target_name(struct target *target)
Returns the instance-specific name of the specified target.
static bool target_was_examined(struct target *target)
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp)
void x86_32_common_reset_breakpoints_watchpoints(struct target *t)
int x86_32_common_write_io(struct target *t, uint32_t addr, uint32_t size, const uint8_t *buf)
int x86_32_common_remove_breakpoint(struct target *t, struct breakpoint *bp)
static struct x86_32_common * target_to_x86_32(struct target *target)