21 #ifndef OPENOCD_TARGET_X86_32_COMMON_H
22 #define OPENOCD_TARGET_X86_32_COMMON_H
35 #define EFLAGS_TF ((uint32_t)0x00000100)
36 #define EFLAGS_IF ((uint32_t)0x00000200)
37 #define EFLAGS_RF ((uint32_t)0x00010000)
38 #define EFLAGS_VM86 ((uint32_t)0x00020000)
40 #define CSAR_DPL ((uint32_t)0x00006000)
41 #define CSAR_D ((uint32_t)0x00400000)
42 #define SSAR_DPL ((uint32_t)0x00006000)
44 #define CR0_PE ((uint32_t)0x00000001)
45 #define CR0_NW ((uint32_t)0x20000000)
46 #define CR0_CD ((uint32_t)0x40000000)
47 #define CR0_PG ((uint32_t)0x80000000)
50 #define PM_DR6 ((uint32_t)0xFFFF0FF0)
52 #define DR6_BRKDETECT_0 ((uint32_t)0x00000001)
53 #define DR6_BRKDETECT_1 ((uint32_t)0x00000002)
54 #define DR6_BRKDETECT_2 ((uint32_t)0x00000004)
55 #define DR6_BRKDETECT_3 ((uint32_t)0x00000008)
151 #define X86_32_COMMON_MAGIC 0x86328632U
200 #define NUM_PM_REGS 18
233 uint32_t regval, uint8_t
cache);
248 #define MAX_DEBUG_REGS 4
249 #define SW_BP_OPCODE 0xf1
250 #define MAX_SW_BPTS 20
257 #define DR7_G_ENABLE_SHIFT 1
258 #define DR7_ENABLE_SIZE 2
259 #define DR7_RW_SHIFT 16
260 #define DR7_LENGTH_SHIFT 18
261 #define DR7_RW_LEN_SIZE 4
262 #define DR7_BP_EXECUTE 0
263 #define DR7_BP_WRITE 1
265 #define DR7_BP_READWRITE 3
266 #define DR7_BP_LENGTH_1 0
267 #define DR7_BP_LENGTH_2 1
268 #define DR7_BP_LENGTH_4 3
270 #define DR7_GLOBAL_ENABLE(val, regnum) \
271 (val |= (1 << (DR7_G_ENABLE_SHIFT + (DR7_ENABLE_SIZE * (regnum)))))
273 #define DR7_GLOBAL_DISABLE(val, regnum) \
274 (val &= ~(3 << (DR7_ENABLE_SIZE * (regnum))))
276 #define DR7_BP_FREE(val, regnum) \
277 ((val & (3 << (DR7_ENABLE_SIZE * (regnum)))) == 0)
279 #define DR7_RESET_RWLEN_BITS(val, regnum) \
280 (val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
282 #define DR7_SET_EXE(val, regnum) \
283 (val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
285 #define DR7_SET_WRITE(val, regnum) \
286 (val |= (DR7_BP_WRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
288 #define DR7_SET_ACCESS(val, regnum) \
289 (val |= (DR7_BP_READWRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
291 #define DR7_SET_LENGTH(val, regnum, len) \
292 (val |= (len == 1) ? (DR7_BP_LENGTH_1 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
293 (len == 2) ? (DR7_BP_LENGTH_2 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
294 (DR7_BP_LENGTH_4 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
298 struct reg **reg_list[],
int *reg_list_size,
309 uint32_t
size, uint32_t
count, uint8_t *buf);
311 uint32_t
size, uint32_t
count,
const uint8_t *buf);
313 uint32_t
size, uint8_t *buf);
315 uint32_t
size,
const uint8_t *buf);
The JTAG interface can be implemented with a software or hardware fifo.
size_t size
Size of the control block search area.
struct swbp_mem_patch * next
int(* read_hw_reg_to_cache)(struct target *target, int num)
enum x86_core_type core_type
struct swbp_mem_patch * swbbp_mem_patch_list
bool(* sw_bpts_supported)(struct target *t)
int(* disable_paging)(struct target *t)
struct x86_32_dbg_reg * hw_break_list
int(* write_hw_reg_from_cache)(struct target *target, int num)
int(* read_hw_reg)(struct target *t, int reg, uint32_t *regval, uint8_t cache)
bool(* is_paging_enabled)(struct target *t)
uint8_t(* get_num_user_regs)(struct target *t)
int(* write_hw_reg)(struct target *t, int reg, uint32_t regval, uint8_t cache)
int forced_halt_for_reset
int(* enable_paging)(struct target *t)
uint32_t pm_regs[NUM_PM_REGS]
int(* submit_instruction)(struct target *t, int num)
struct jtag_tap * curr_tap
struct working_area * fast_data_area
unsigned int common_magic
int(* transaction_status)(struct target *t)
const struct command_registration x86_32_command_handlers[]
int x86_32_common_add_watchpoint(struct target *t, struct watchpoint *wp)
int x86_32_common_read_io(struct target *t, uint32_t addr, uint32_t size, uint8_t *buf)
int x86_32_common_read_memory(struct target *t, target_addr_t addr, uint32_t size, uint32_t count, uint8_t *buf)
int x86_32_common_init_arch_info(struct target *target, struct x86_32_common *x86_32)
int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp)
int x86_32_common_virt2phys(struct target *t, target_addr_t address, target_addr_t *physical)
int x86_32_common_write_memory(struct target *t, target_addr_t addr, uint32_t size, uint32_t count, const uint8_t *buf)
int x86_32_get_gdb_reg_list(struct target *t, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
int x86_32_common_read_phys_mem(struct target *t, target_addr_t phys_address, uint32_t size, uint32_t count, uint8_t *buffer)
int x86_32_common_remove_watchpoint(struct target *t, struct watchpoint *wp)
int x86_32_common_mmu(struct target *t, int *enabled)
bool check_not_halted(const struct target *t)
static struct x86_32_common * target_to_x86_32(struct target *target)
void x86_32_common_reset_breakpoints_watchpoints(struct target *t)
int x86_32_common_write_phys_mem(struct target *t, target_addr_t phys_address, uint32_t size, uint32_t count, const uint8_t *buffer)
int x86_32_common_write_io(struct target *t, uint32_t addr, uint32_t size, const uint8_t *buf)
int x86_32_common_remove_breakpoint(struct target *t, struct breakpoint *bp)