OpenOCD
reg_ezusb.h
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3
/***************************************************************************
4
* Copyright (C) 2011 by Martin Schmoelzer *
5
* <martin.schmoelzer@student.tuwien.ac.at> *
6
***************************************************************************/
7
8
#ifndef REG_EZUSB_H
9
#define REG_EZUSB_H
10
29
/* Compiler-specific definitions of SBIT, SFR, SFRX, ... macros */
30
#include <mcs51/compiler.h>
31
32
/* Bit vectors */
33
#define bmBit0 0x01
34
#define bmBit1 0x02
35
#define bmBit2 0x04
36
#define bmBit3 0x08
37
#define bmBit4 0x10
38
#define bmBit5 0x20
39
#define bmBit6 0x40
40
#define bmBit7 0x80
41
42
/**************************************************************************
43
************************ Special Function Registers **********************
44
***************************************************************************/
45
46
/* See EZ-USB TRM, pp. A-9 - A-10 */
47
48
SFR
(SP, 0x81);
49
SFR
(DPL0, 0x82);
50
SFR
(DPH0, 0x83);
51
SFR
(DPL1, 0x84);
52
SFR
(DPL2, 0x85);
53
54
SFR
(DPS, 0x86);
55
#define SEL bmBit0
56
/* Bit 1 read-only, always reads '0' */
57
/* Bit 2 read-only, always reads '0' */
58
/* Bit 3 read-only, always reads '0' */
59
/* Bit 4 read-only, always reads '0' */
60
/* Bit 5 read-only, always reads '0' */
61
/* Bit 6 read-only, always reads '0' */
62
/* Bit 7 read-only, always reads '0' */
63
64
SFR
(PCON, 0x87);
65
#define IDLE bmBit0
66
#define STOP bmBit1
67
#define GF0 bmBit2
68
#define GF1 bmBit3
69
/* Bit 4 read-only, always reads '1' */
70
/* Bit 5 read-only, always reads '1' */
71
/* Bit 6 unused */
72
#define SMOD0 bmBit7
73
74
SFR
(TCON, 0x88);
75
SBIT
(IT0, 0x88, 0);
76
SBIT
(IE0, 0x88, 1);
77
SBIT
(IT1, 0x88, 2);
78
SBIT
(IE1, 0x88, 3);
79
SBIT
(TR0, 0x88, 4);
80
SBIT
(TF0, 0x88, 5);
81
SBIT
(TR1, 0x88, 6);
82
SBIT
(TF1, 0x88, 7);
83
84
SFR
(TMOD, 0x89);
85
/* Some bits in this register share the same name in the EZ-USB TRM. Therefore,
86
* we add a '0'/'1' to distinguish them */
87
#define M00 bmBit0
88
#define M01 bmBit1
89
#define CT0 bmBit2
90
#define GATE0 bmBit3
91
#define M10 bmBit4
92
#define M11 bmBit5
93
#define CT1 bmBit6
94
#define GATE1 bmBit7
95
96
SFR
(TL0, 0x8A);
97
SFR
(TL1, 0x8B);
98
SFR
(TH0, 0x8C);
99
SFR
(TH1, 0x8D);
100
101
SFR
(CKCON, 0x8E);
102
#define MD0 bmBit0
103
#define MD1 bmBit1
104
#define MD2 bmBit2
105
#define T0M bmBit3
106
#define T1M bmBit4
107
#define T2M bmBit5
108
/* Bit 6 unused */
109
/* Bit 7 unused */
110
111
SFR
(SPC_FNC, 0x8D);
112
#define bmWRS bmBit0
113
/* Bit 1 read-only, always reads '0' */
114
/* Bit 2 read-only, always reads '0' */
115
/* Bit 3 read-only, always reads '0' */
116
/* Bit 4 read-only, always reads '0' */
117
/* Bit 5 read-only, always reads '0' */
118
/* Bit 6 read-only, always reads '0' */
119
/* Bit 7 read-only, always reads '0' */
120
121
SFR
(EXIF, 0x91);
122
/* Bit 0 read-only, always reads '0' */
123
/* Bit 1 read-only, always reads '0' */
124
/* Bit 2 read-only, always reads '0' */
125
/* Bit 3 read-only, always reads '1' */
126
#define USBINT bmBit4
127
#define I2CINT bmBit5
128
#define IE4 bmBit6
129
#define IE5 bmBit7
130
131
/* Definition of the _XPAGE register, according to SDCC Compiler User Guide,
132
* Version 3.0.1, Chapter 4, p. 61. Also see EZ-USB TRM, p. 2-4. */
133
SFR
(MPAGE, 0x92);
134
SFR
(_XPAGE, 0x92);
135
136
SFR
(SCON0, 0x98);
137
SBIT
(RI_0, 0x98, 0);
138
SBIT
(TI_0, 0x98, 1);
139
SBIT
(RB8_0, 0x98, 2);
140
SBIT
(TB8_0, 0x98, 3);
141
SBIT
(REN_0, 0x98, 4);
142
SBIT
(SM2_0, 0x98, 5);
143
SBIT
(SM1_0, 0x98, 6);
144
SBIT
(SM0_0, 0x98, 7);
145
146
SFR
(SBUF0, 0x99);
147
148
SFR
(IE, 0xA8);
149
SBIT
(EX0, 0xA8, 0);
150
SBIT
(ET0, 0xA8, 1);
151
SBIT
(EX1, 0xA8, 2);
152
SBIT
(ET1, 0xA8, 3);
153
SBIT
(ES0, 0xA8, 4);
154
SBIT
(ET2, 0xA8, 5);
155
SBIT
(ES1, 0xA8, 6);
156
SBIT
(
EA
, 0xA8, 7);
157
158
SFR
(IP, 0xB8);
159
SBIT
(PX0, 0xB8, 0);
160
SBIT
(PT0, 0xB8, 1);
161
SBIT
(PX1, 0xB8, 2);
162
SBIT
(PT1, 0xB8, 3);
163
SBIT
(PS0, 0xB8, 4);
164
SBIT
(PT2, 0xB8, 5);
165
SBIT
(PS1, 0xB8, 6);
166
/* Bit 7 read-only, always reads '1' */
167
168
SFR
(SCON1, 0xC0);
169
SBIT
(RI_1, 0xC0, 0);
170
SBIT
(TI_1, 0xC0, 1);
171
SBIT
(RB8_1, 0xC0, 2);
172
SBIT
(TB8_1, 0xC0, 3);
173
SBIT
(REN_1, 0xC0, 4);
174
SBIT
(SM2_1, 0xC0, 5);
175
SBIT
(SM1_1, 0xC0, 6);
176
SBIT
(SM0_1, 0xC0, 7);
177
178
SFR
(SBUF1, 0xC1);
179
180
SFR
(T2CON, 0xC8);
181
SBIT
(CPRL2, 0xC8, 0);
182
SBIT
(CT2, 0xC8, 1);
183
SBIT
(TR2, 0xC8, 2);
184
SBIT
(EXEN2, 0xC8, 3);
185
SBIT
(TCLK, 0xC8, 4);
186
SBIT
(RCLK, 0xC8, 5);
187
SBIT
(EXF2, 0xC8, 6);
188
SBIT
(TF2, 0xC8, 7);
189
190
SFR
(RCAP2L, 0xCA);
191
SFR
(RCAP2H, 0xCB);
192
SFR
(TL2, 0xCC);
193
SFR
(TH2, 0xCD);
194
195
SFR
(PSW, 0xD0);
196
SBIT
(P, 0xD0, 0);
197
SBIT
(F1, 0xD0, 1);
198
SBIT
(OV, 0xD0, 2);
199
SBIT
(RS0, 0xD0, 3);
200
SBIT
(RS1, 0xD0, 4);
201
SBIT
(F0, 0xD0, 5);
202
SBIT
(AC, 0xD0, 6);
203
SBIT
(CY, 0xD0, 7);
204
205
SFR
(EICON, 0xD8);
206
/* Bit 0 read-only, always reads '0' */
207
/* Bit 1 read-only, always reads '0' */
208
/* Bit 2 read-only, always reads '0' */
209
SBIT
(
INT6
, 0xD8, 3);
210
SBIT
(RESI, 0xD8, 4);
211
SBIT
(ERESI, 0xD8, 5);
212
/* Bit 6 read-only, always reads '1' */
213
SBIT
(SMOD1, 0xD8, 7);
214
215
SFR
(ACC, 0xE0);
216
217
SFR
(EIE, 0xE8);
218
SBIT
(EUSB, 0xE8, 0);
219
SBIT
(EI2C, 0xE8, 1);
220
SBIT
(EX4, 0xE8, 2);
221
SBIT
(EX5, 0xE8, 3);
222
SBIT
(EWDI, 0xE8, 4);
223
/* Bit 5 read-only, always reads '1' */
224
/* Bit 6 read-only, always reads '1' */
225
/* Bit 7 read-only, always reads '1' */
226
227
SFR
(B, 0xF0);
228
229
SFR
(
EIP
, 0xF8);
230
SBIT
(PUSB, 0xF8, 0);
231
SBIT
(PI2C, 0xF8, 1);
232
SBIT
(PX4, 0xF8, 2);
233
SBIT
(PX5, 0xF8, 3);
234
SBIT
(PX6, 0xF8, 4);
235
/* Bit 5 read-only, always reads '1' */
236
/* Bit 6 read-only, always reads '1' */
237
/* Bit 7 read-only, always reads '1' */
238
239
/**************************************************************************
240
***************************** XDATA Registers ****************************
241
***************************************************************************/
242
243
/************************ Endpoint 0-7 Data Buffers ************************/
244
SFRX
(OUT7BUF[64], 0x7B40);
245
SFRX
(IN7BUF[64], 0x7B80);
246
SFRX
(OUT6BUF[64], 0x7BC0);
247
SFRX
(IN6BUF[64], 0x7C00);
248
SFRX
(OUT5BUF[64], 0x7C40);
249
SFRX
(IN5BUF[64], 0x7C80);
250
SFRX
(OUT4BUF[64], 0x7CC0);
251
SFRX
(IN4BUF[64], 0x7D00);
252
SFRX
(OUT3BUF[64], 0x7D40);
253
SFRX
(IN3BUF[64], 0x7D80);
254
SFRX
(OUT2BUF[64], 0x7DC0);
255
SFRX
(IN2BUF[64], 0x7E00);
256
SFRX
(OUT1BUF[64], 0x7E40);
257
SFRX
(IN1BUF[64], 0x7E80);
258
SFRX
(OUT0BUF[64], 0x7EC0);
259
SFRX
(IN0BUF[64], 0x7F00);
260
/* 0x7F40 - 0x7F5F reserved */
261
262
/**************************** Isochronous Data *****************************/
263
SFRX
(OUT8DATA, 0x7F60);
264
SFRX
(OUT9DATA, 0x7F61);
265
SFRX
(OUT10DATA, 0x7F62);
266
SFRX
(OUT11DATA, 0x7F63);
267
SFRX
(OUT12DATA, 0x7F64);
268
SFRX
(OUT13DATA, 0x7F65);
269
SFRX
(OUT14DATA, 0x7F66);
270
SFRX
(OUT15DATA, 0x7F67);
271
272
SFRX
(IN8DATA, 0x7F68);
273
SFRX
(IN9DATA, 0x7F69);
274
SFRX
(IN10DATA, 0x7F6A);
275
SFRX
(IN11DATA, 0x7F6B);
276
SFRX
(IN12DATA, 0x7F6C);
277
SFRX
(IN13DATA, 0x7F6D);
278
SFRX
(IN14DATA, 0x7F6E);
279
SFRX
(IN15DATA, 0x7F6F);
280
281
/************************* Isochronous Byte Counts *************************/
282
SFRX
(OUT8BCH, 0x7F70);
283
SFRX
(OUT8BCL, 0x7F71);
284
SFRX
(OUT9BCH, 0x7F72);
285
SFRX
(OUT9BCL, 0x7F73);
286
SFRX
(OUT10BCH, 0x7F74);
287
SFRX
(OUT10BCL, 0x7F75);
288
SFRX
(OUT11BCH, 0x7F76);
289
SFRX
(OUT11BCL, 0x7F77);
290
SFRX
(OUT12BCH, 0x7F78);
291
SFRX
(OUT12BCL, 0x7F79);
292
SFRX
(OUT13BCH, 0x7F7A);
293
SFRX
(OUT13BCL, 0x7F7B);
294
SFRX
(OUT14BCH, 0x7F7C);
295
SFRX
(OUT14BCL, 0x7F7D);
296
SFRX
(OUT15BCH, 0x7F7E);
297
SFRX
(OUT16BCL, 0x7F7F);
298
299
/****************************** CPU Registers ******************************/
300
SFRX
(CPUCS, 0x7F92);
301
#define RES8051 bmBit0
302
#define CLK24OE bmBit1
303
/* Bit 2 read-only, always reads '0' */
304
/* Bit 3 read-only, always reads '0' */
305
/* Bits 4...7: Chip Revision */
306
307
SFRX
(PORTACFG, 0x7F93);
308
#define T0OUT bmBit0
309
#define T1OUT bmBit1
310
#define OE bmBit2
311
#define CS bmBit3
312
#define FWR bmBit4
313
#define FRD bmBit5
314
#define RXD0OUT bmBit6
315
#define RXD1OUT bmBit7
316
317
SFRX
(PORTBCFG, 0x7F94);
318
#define T2 bmBit0
319
#define T2EX bmBit1
320
#define RXD1 bmBit2
321
#define TXD1 bmBit3
322
#define INT4 bmBit4
323
#define INT5 bmBit5
324
#define INT6 bmBit6
325
#define T2OUT bmBit7
326
327
SFRX
(PORTCCFG, 0x7F95);
328
#define RXD0 bmBit0
329
#define TXD0 bmBit1
330
#define INT0 bmBit2
331
#define INT1 bmBit3
332
#define T0 bmBit4
333
#define T1 bmBit5
334
#define WR bmBit6
335
#define RD bmBit7
336
337
/*********************** Input-Output Port Registers ***********************/
338
SFRX
(OUTA, 0x7F96);
339
#define OUTA0 bmBit0
340
#define OUTA1 bmBit1
341
#define OUTA2 bmBit2
342
#define OUTA3 bmBit3
343
#define OUTA4 bmBit4
344
#define OUTA5 bmBit5
345
#define OUTA6 bmBit6
346
#define OUTA7 bmBit7
347
348
SFRX
(OUTB, 0x7F97);
349
#define OUTB0 bmBit0
350
#define OUTB1 bmBit1
351
#define OUTB2 bmBit2
352
#define OUTB3 bmBit3
353
#define OUTB4 bmBit4
354
#define OUTB5 bmBit5
355
#define OUTB6 bmBit6
356
#define OUTB7 bmBit7
357
358
SFRX
(OUTC, 0x7F98);
359
#define OUTC0 bmBit0
360
#define OUTC1 bmBit1
361
#define OUTC2 bmBit2
362
#define OUTC3 bmBit3
363
#define OUTC4 bmBit4
364
#define OUTC5 bmBit5
365
#define OUTC6 bmBit6
366
#define OUTC7 bmBit7
367
368
SFRX
(PINSA, 0x7F99);
369
#define PINA0 bmBit0
370
#define PINA1 bmBit1
371
#define PINA2 bmBit2
372
#define PINA3 bmBit3
373
#define PINA4 bmBit4
374
#define PINA5 bmBit5
375
#define PINA6 bmBit6
376
#define PINA7 bmBit7
377
378
SFRX
(PINSB, 0x7F9A);
379
#define PINB0 bmBit0
380
#define PINB1 bmBit1
381
#define PINB2 bmBit2
382
#define PINB3 bmBit3
383
#define PINB4 bmBit4
384
#define PINB5 bmBit5
385
#define PINB6 bmBit6
386
#define PINB7 bmBit7
387
388
SFRX
(PINSC, 0x7F9B);
389
#define PINC0 bmBit0
390
#define PINC1 bmBit1
391
#define PINC2 bmBit2
392
#define PINC3 bmBit3
393
#define PINC4 bmBit4
394
#define PINC5 bmBit5
395
#define PINC6 bmBit6
396
#define PINC7 bmBit7
397
398
SFRX
(OEA, 0x7F9C);
399
#define OEA0 bmBit0
400
#define OEA1 bmBit1
401
#define OEA2 bmBit2
402
#define OEA3 bmBit3
403
#define OEA4 bmBit4
404
#define OEA5 bmBit5
405
#define OEA6 bmBit6
406
#define OEA7 bmBit7
407
408
SFRX
(OEB, 0x7F9D);
409
#define OEB0 bmBit0
410
#define OEB1 bmBit1
411
#define OEB2 bmBit2
412
#define OEB3 bmBit3
413
#define OEB4 bmBit4
414
#define OEB5 bmBit5
415
#define OEB6 bmBit6
416
#define OEB7 bmBit7
417
418
SFRX
(OEC, 0x7F9E);
419
#define OEC0 bmBit0
420
#define OEC1 bmBit1
421
#define OEC2 bmBit2
422
#define OEC3 bmBit3
423
#define OEC4 bmBit4
424
#define OEC5 bmBit5
425
#define OEC6 bmBit6
426
#define OEC7 bmBit7
427
428
/* 0x7F9F reserved */
429
430
/****************** Isochronous Control/Status Registers *******************/
431
SFRX
(ISOERR, 0x7FA0);
432
#define ISO8ERR bmBit0
433
#define ISO9ERR bmBit1
434
#define ISO10ERR bmBit2
435
#define ISO11ERR bmBit3
436
#define ISO12ERR bmBit4
437
#define ISO13ERR bmBit5
438
#define ISO14ERR bmBit6
439
#define ISO15ERR bmBit7
440
441
SFRX
(ISOCTL, 0x7FA1);
442
#define ISODISAB bmBit0
443
#define MBZ0 bmBit1
444
#define MBZ1 bmBit2
445
#define PPSTAT bmBit3
446
/* Bit 4 unused */
447
/* Bit 5 unused */
448
/* Bit 6 unused */
449
/* Bit 7 unused */
450
451
SFRX
(ZBCOUT, 0x7FA2);
452
#define EP8 bmBit0
453
#define EP9 bmBit1
454
#define EP10 bmBit2
455
#define EP11 bmBit3
456
#define EP12 bmBit4
457
#define EP13 bmBit5
458
#define EP14 bmBit6
459
#define EP15 bmBit7
460
461
/* 0x7FA3 reserved */
462
/* 0x7FA4 reserved */
463
464
/****************************** I2C Registers ******************************/
465
SFRX
(I2CS, 0x7FA5);
466
#define DONE bmBit0
467
#define ACK bmBit1
468
#define BERR bmBit2
469
#define ID0 bmBit3
470
#define ID1 bmBit4
471
#define LASTRD bmBit5
472
#define I2C_STOP bmBit6
473
#define I2C_START bmBit7
474
475
SFRX
(I2DAT, 0x7FA6);
476
/* 0x7FA7 reserved */
477
478
/******************************* Interrupts ********************************/
479
SFRX
(IVEC, 0x7FA8);
480
/* Bit 0 read-only, always reads '0' */
481
/* Bit 1 read-only, always reads '0' */
482
#define IV0 bmBit2
483
#define IV1 bmBit3
484
#define IV2 bmBit4
485
#define IV3 bmBit5
486
#define IV4 bmBit6
487
/* Bit 7 read-only, always reads '0' */
488
489
SFRX
(IN07IRQ, 0x7FA9);
490
#define IN0IR bmBit0
491
#define IN1IR bmBit1
492
#define IN2IR bmBit2
493
#define IN3IR bmBit3
494
#define IN4IR bmBit4
495
#define IN5IR bmBit5
496
#define IN6IR bmBit6
497
#define IN7IR bmBit7
498
499
SFRX
(OUT07IRQ, 0x7FAA);
500
#define OUT0IR bmBit0
501
#define OUT1IR bmBit1
502
#define OUT2IR bmBit2
503
#define OUT3IR bmBit3
504
#define OUT4IR bmBit4
505
#define OUT5IR bmBit5
506
#define OUT6IR bmBit6
507
#define OUT7IR bmBit7
508
509
SFRX
(USBIRQ, 0x7FAB);
510
#define SUDAVIR bmBit0
511
#define SOFIR bmBit1
512
#define SUTOKIR bmBit2
513
#define SUSPIR bmBit3
514
#define URESIR bmBit4
515
/* Bit 5 unused */
516
/* Bit 6 unused */
517
/* Bit 7 unused */
518
519
SFRX
(IN07IEN, 0x7FAC);
520
#define IN0IEN bmBit0
521
#define IN1IEN bmBit1
522
#define IN2IEN bmBit2
523
#define IN3IEN bmBit3
524
#define IN4IEN bmBit4
525
#define IN5IEN bmBit5
526
#define IN6IEN bmBit6
527
#define IN7IEN bmBit7
528
529
SFRX
(OUT07IEN, 0x7FAD);
530
#define OUT0IEN bmBit0
531
#define OUT1IEN bmBit1
532
#define OUT2IEN bmBit2
533
#define OUT3IEN bmBit3
534
#define OUT4IEN bmBit4
535
#define OUT5IEN bmBit5
536
#define OUT6IEN bmBit6
537
#define OUT7IEN bmBit7
538
539
SFRX
(USBIEN, 0x7FAE);
540
#define SUDAVIE bmBit0
541
#define SOFIE bmBit1
542
#define SUTOKIE bmBit2
543
#define SUSPIE bmBit3
544
#define URESIE bmBit4
545
/* Bit 5 unused */
546
/* Bit 6 unused */
547
/* Bit 7 unused */
548
549
SFRX
(USBBAV, 0x7FAF);
550
#define AVEN bmBit0
551
#define BPEN bmBit1
552
#define BPPULSE bmBit2
553
#define BREAK bmBit3
554
/* Bit 4 unused */
555
/* Bit 5 unused */
556
/* Bit 6 unused */
557
/* Bit 7 unused */
558
559
/* 0x7FB0 reserved */
560
/* 0x7FB1 reserved */
561
SFRX
(BPADDRH, 0x7FB2);
562
SFRX
(BPADDRL, 0x7FB3);
563
564
/****************************** Endpoints 0-7 ******************************/
565
SFRX
(EP0CS, 0x7FB4);
566
#define EP0STALL bmBit0
567
#define HSNAK bmBit1
568
#define IN0BSY bmBit2
569
#define OUT0BSY bmBit3
570
/* Bit 4 unused */
571
/* Bit 5 unused */
572
/* Bit 6 unused */
573
/* Bit 7 unused */
574
575
SFRX
(IN0BC, 0x7FB5);
576
SFRX
(IN1CS, 0x7FB6);
577
SFRX
(IN1BC, 0x7FB7);
578
SFRX
(IN2CS, 0x7FB8);
579
SFRX
(IN2BC, 0x7FB9);
580
SFRX
(IN3CS, 0x7FBA);
581
SFRX
(IN3BC, 0x7FBB);
582
SFRX
(IN4CS, 0x7FBC);
583
SFRX
(IN4BC, 0x7FBD);
584
SFRX
(IN5CS, 0x7FBE);
585
SFRX
(IN5BC, 0x7FBF);
586
SFRX
(IN6CS, 0x7FC0);
587
SFRX
(IN6BC, 0x7FC1);
588
SFRX
(IN7CS, 0x7FC2);
589
SFRX
(IN7BC, 0x7FC3);
590
/* 0x7FC4 reserved */
591
SFRX
(OUT0BC, 0x7FC5);
592
SFRX
(OUT1CS, 0x7FC6);
593
SFRX
(OUT1BC, 0x7FC7);
594
SFRX
(OUT2CS, 0x7FC8);
595
SFRX
(OUT2BC, 0x7FC9);
596
SFRX
(OUT3CS, 0x7FCA);
597
SFRX
(OUT3BC, 0x7FCB);
598
SFRX
(OUT4CS, 0x7FCC);
599
SFRX
(OUT4BC, 0x7FCD);
600
SFRX
(OUT5CS, 0x7FCE);
601
SFRX
(OUT5BC, 0x7FCF);
602
SFRX
(OUT6CS, 0x7FD0);
603
SFRX
(OUT6BC, 0x7FD1);
604
SFRX
(OUT7CS, 0x7FD2);
605
SFRX
(OUT7BC, 0x7FD3);
606
607
/* The INxSTALL, OUTxSTALL, INxBSY and OUTxBSY bits are the same for all
608
* INxCS/OUTxCS registers. For better readability, we define them only once */
609
#define EPSTALL bmBit0
610
#define EPBSY bmBit1
611
612
/************************** Global USB Registers ***************************/
613
SFRX
(SUDPTRH, 0x7FD4);
614
SFRX
(SUDPTRL, 0x7FD5);
615
616
SFRX
(USBCS, 0x7FD6);
617
#define SIGRSUME bmBit0
618
#define RENUM bmBit1
619
#define DISCOE bmBit2
620
#define DISCON bmBit3
621
/* Bit 4 unused */
622
/* Bit 5 unused */
623
/* Bit 6 unused */
624
#define WAKESRC bmBit7
625
626
SFRX
(TOGCTL, 0x7FD7);
627
#define TOG_EP0 bmBit0
628
#define TOG_EP1 bmBit1
629
#define TOG_EP2 bmBit2
630
/* Bit 3 is read-only, always reads '0' */
631
#define TOG_IO bmBit4
632
#define TOG_R bmBit5
633
#define TOG_S bmBit6
634
#define TOG_Q bmBit7
635
636
SFRX
(USBFRAMEL, 0x7FD8);
637
SFRX
(USBFRAMEH, 0x7FD9);
638
/* 0x7FDA reserved */
639
SFRX
(FNADDR, 0x7FDB);
640
/* 0x7FDC reserved */
641
642
SFRX
(USBPAIR, 0x7FDD);
643
#define PR2IN bmBit0
644
#define PR4IN bmBit1
645
#define PR6IN bmBit2
646
#define PR2OUT bmBit3
647
#define PR4OUT bmBit4
648
#define PR6OUT bmBit5
649
/* Bit 6 unused */
650
#define ISOSEND0 bmBit7
651
652
SFRX
(IN07VAL, 0x7FDE);
653
/* Bit 0 is read-only, always reads '1' */
654
#define IN1VAL bmBit1
655
#define IN2VAL bmBit2
656
#define IN3VAL bmBit3
657
#define IN4VAL bmBit4
658
#define IN5VAL bmBit5
659
#define IN6VAL bmBit6
660
#define IN7VAL bmBit7
661
662
SFRX
(OUT07VAL, 0x7FDF);
663
/* Bit 0 is read-only, always reads '1' */
664
#define OUT1VAL bmBit1
665
#define OUT2VAL bmBit2
666
#define OUT3VAL bmBit3
667
#define OUT4VAL bmBit4
668
#define OUT5VAL bmBit5
669
#define OUT6VAL bmBit6
670
#define OUT7VAL bmBit7
671
672
SFRX
(INISOVAL, 0x7FE0);
673
#define IN8VAL bmBit0
674
#define IN9VAL bmBit1
675
#define IN10VAL bmBit2
676
#define IN11VAL bmBit3
677
#define IN12VAL bmBit4
678
#define IN13VAL bmBit5
679
#define IN14VAL bmBit6
680
#define IN15VAL bmBit7
681
682
SFRX
(OUTISOVAL, 0x7FE1);
683
#define OUT8VAL bmBit0
684
#define OUT9VAL bmBit1
685
#define OUT10VAL bmBit2
686
#define OUT11VAL bmBit3
687
#define OUT12VAL bmBit4
688
#define OUT13VAL bmBit5
689
#define OUT14VAL bmBit6
690
#define OUT15VAL bmBit7
691
692
SFRX
(FASTXFR, 0x7FE2);
693
#define WMOD0 bmBit0
694
#define WMOD1 bmBit1
695
#define WPOL bmBit2
696
#define RMOD0 bmBit3
697
#define RMOD1 bmBit4
698
#define RPOL bmBit5
699
#define FBLK bmBit6
700
#define FISO bmBit7
701
702
SFRX
(AUTOPTRH, 0x7FE3);
703
SFRX
(AUTOPTRL, 0x7FE4);
704
SFRX
(AUTODATA, 0x7FE5);
705
/* 0x7FE6 reserved */
706
/* 0x7FE7 reserved */
707
708
/******************************* Setup Data ********************************/
709
SFRX
(SETUPDAT[8], 0x7FE8);
710
711
/************************* Isochronous FIFO sizes **************************/
712
SFRX
(OUT8ADDR, 0x7FF0);
713
SFRX
(OUT9ADDR, 0x7FF1);
714
SFRX
(OUT10ADDR, 0x7FF2);
715
SFRX
(OUT11ADDR, 0x7FF3);
716
SFRX
(OUT12ADDR, 0x7FF4);
717
SFRX
(OUT13ADDR, 0x7FF5);
718
SFRX
(OUT14ADDR, 0x7FF6);
719
SFRX
(OUT15ADDR, 0x7FF7);
720
721
SFRX
(IN8ADDR, 0x7FF8);
722
SFRX
(IN9ADDR, 0x7FF9);
723
SFRX
(IN10ADDR, 0x7FFA);
724
SFRX
(IN11ADDR, 0x7FFB);
725
SFRX
(IN12ADDR, 0x7FFC);
726
SFRX
(IN13ADDR, 0x7FFD);
727
SFRX
(IN14ADDR, 0x7FFE);
728
SFRX
(IN15ADDR, 0x7FFF);
729
730
#endif
EA
#define EA
Definition:
at91sam7.c:59
SFR
SFR(SP, 0x81)
SFRX
SFRX(OUT7BUF[64], 0x7B40)
SBIT
SBIT(IT0, 0x88, 0)
INT6
#define INT6
Definition:
reg_ezusb.h:324
EIP
@ EIP
Definition:
x86_32_common.h:68
src
jtag
drivers
OpenULINK
include
reg_ezusb.h
Generated by
1.9.1