70 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
71 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
74 #define CSR_BPCONTROL_X (1<<0)
75 #define CSR_BPCONTROL_W (1<<1)
76 #define CSR_BPCONTROL_R (1<<2)
77 #define CSR_BPCONTROL_U (1<<3)
78 #define CSR_BPCONTROL_S (1<<4)
79 #define CSR_BPCONTROL_H (1<<5)
80 #define CSR_BPCONTROL_M (1<<6)
81 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
82 #define CSR_BPCONTROL_BPACTION (0xff<<11)
84 #define DEBUG_ROM_START 0x800
85 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
86 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
87 #define DEBUG_RAM_START 0x400
89 #define SETHALTNOT 0x10c
93 #define DTMCONTROL 0x10
94 #define DTMCONTROL_DBUS_RESET (1<<16)
95 #define DTMCONTROL_IDLE (7<<10)
96 #define DTMCONTROL_ADDRBITS (0xf<<4)
97 #define DTMCONTROL_VERSION (0xf)
100 #define DBUS_OP_START 0
101 #define DBUS_OP_SIZE 2
112 #define DBUS_DATA_START 2
113 #define DBUS_DATA_SIZE 34
114 #define DBUS_ADDRESS_START 36
130 #define DMCONTROL 0x10
131 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
132 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
133 #define DMCONTROL_BUSERROR (7<<19)
134 #define DMCONTROL_SERIAL (3<<16)
135 #define DMCONTROL_AUTOINCREMENT (1<<15)
136 #define DMCONTROL_ACCESS (7<<12)
137 #define DMCONTROL_HARTID (0x3ff<<2)
138 #define DMCONTROL_NDRESET (1<<1)
139 #define DMCONTROL_FULLRESET 1
142 #define DMINFO_ABUSSIZE (0x7fU<<25)
143 #define DMINFO_SERIALCOUNT (0xf<<21)
144 #define DMINFO_ACCESS128 (1<<20)
145 #define DMINFO_ACCESS64 (1<<19)
146 #define DMINFO_ACCESS32 (1<<18)
147 #define DMINFO_ACCESS16 (1<<17)
148 #define DMINFO_ACCESS8 (1<<16)
149 #define DMINFO_DRAMSIZE (0x3f<<10)
150 #define DMINFO_AUTHENTICATED (1<<5)
151 #define DMINFO_AUTHBUSY (1<<4)
152 #define DMINFO_AUTHTYPE (3<<2)
153 #define DMINFO_VERSION 3
155 #define DMAUTHDATA0 0x12
156 #define DMAUTHDATA1 0x13
160 #define DBUS_ADDRESS_UNKNOWN 0xffff
162 #define DRAM_CACHE_SIZE 16
191 uint64_t mstatus_actual;
226 #define DEBUG_LENGTH 264
232 assert(
info->version_specific);
233 return info->version_specific;
242 case SLOT0:
return 4;
243 case SLOT1:
return 5;
249 case SLOT0:
return 4;
250 case SLOT1:
return 6;
254 LOG_ERROR(
"slot_offset called with xlen=%d, slot=%d",
279 return 0x40 + index - 0x10;
302 LOG_ERROR(
"failed jtag scan: %d", retval);
307 LOG_DEBUG(
"DTMCONTROL: 0x%x -> 0x%x", out, in);
326 LOG_ERROR(
"failed jtag scan: %d", retval);
342 info->dbus_busy_delay +=
info->dbus_busy_delay / 10 + 1;
343 LOG_DEBUG(
"dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
344 info->dtmcontrol_idle,
info->dbus_busy_delay,
345 info->interrupt_high_delay);
353 info->interrupt_high_delay +=
info->interrupt_high_delay / 10 + 1;
354 LOG_DEBUG(
"dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
355 info->dtmcontrol_idle,
info->dbus_busy_delay,
356 info->interrupt_high_delay);
361 uint16_t address, uint64_t data)
366 if (r->reset_delays_wait >= 0) {
367 r->reset_delays_wait--;
368 if (r->reset_delays_wait < 0) {
369 info->dbus_busy_delay = 0;
370 info->interrupt_high_delay = 0;
384 int idle_count =
info->dtmcontrol_idle +
info->dbus_busy_delay;
386 idle_count +=
info->interrupt_high_delay;
394 static const char *
const op_string[] = {
"nop",
"r",
"w",
"?"};
395 static const char *
const status_string[] = {
"+",
"?",
"F",
"b"};
404 unsigned int out_data = out >> 2;
410 unsigned int in_data = in >> 2;
414 __FILE__, __LINE__,
"scan",
415 "%db %s %c%c:%08x @%02x -> %s %c%c:%08x @%02x",
417 op_string[out_op], out_interrupt, out_haltnot, out_data,
419 status_string[in_op], in_interrupt, in_haltnot, in_data,
424 uint64_t *data_in,
dbus_op_t op, uint16_t address_out, uint64_t data_out)
428 uint8_t out[8] = {0};
435 assert(
info->addrbits != 0);
444 int idle_count =
info->dtmcontrol_idle +
info->dbus_busy_delay;
483 LOG_ERROR(
"dbus_read(0x%x) failed!", address);
490 LOG_ERROR(
"failed read from 0x%x; value=0x%" PRIx64
", status=%d\n", address, value,
status);
505 LOG_ERROR(
"failed to write 0x%" PRIx64
" to 0x%x; status=%d\n", value, address,
status);
573 for (
unsigned int i = 0; i < scans->
next_scan; i++)
581 LOG_ERROR(
"failed jtag scan: %d", retval);
659 unsigned first,
unsigned num)
665 unsigned first,
unsigned num)
706 if (address_in == (1<<
info->addrbits) - 1 &&
708 LOG_ERROR(
"TDO seems to be stuck high.");
722 }
while (address_in > 0x10 && address_in !=
DMCONTROL);
746 LOG_ERROR(
"Timed out waiting for debug int to clear."
747 "Increase timeout with riscv set_command_timeout_sec.");
758 if (expected != actual) {
759 LOG_ERROR(
"Wrote 0x%x to Debug RAM at %d, but read back 0x%x",
760 expected, index, actual);
769 if (
info->dram_cache[index].valid &&
770 info->dram_cache[index].data == data) {
772 LOG_DEBUG(
"cache[0x%x] = 0x%08x: DASM(0x%x) (hit)", index, data, data);
775 LOG_DEBUG(
"cache[0x%x] = 0x%08x: DASM(0x%x)", index, data, data);
776 info->dram_cache[index].data = data;
777 info->dram_cache[index].valid =
true;
778 info->dram_cache[index].dirty =
true;
813 LOG_ERROR(
"Debug RAM 0x%x: 0x%08x", i, value);
821 for (
unsigned int i = 0; i <
info->dramsize; i++) {
822 info->dram_cache[i].valid =
false;
823 info->dram_cache[i].dirty =
false;
832 for (
unsigned int i = 0; i <
info->dramsize; i++) {
834 info->dram_cache[i].valid =
false;
835 info->dram_cache[i].dirty =
false;
844 for (
unsigned int i = 0; i <
info->dramsize; i++) {
845 if (
info->dram_cache[i].valid && !
info->dram_cache[i].dirty) {
861 #define CACHE_NO_READ 128
870 unsigned int last =
info->dramsize;
871 for (
unsigned int i = 0; i <
info->dramsize; i++) {
872 if (
info->dram_cache[i].dirty)
876 if (last ==
info->dramsize) {
881 for (
unsigned int i = 0; i <
info->dramsize; i++) {
882 if (
info->dram_cache[i].dirty) {
883 bool set_interrupt = (i == last && run);
908 for (
unsigned int i = 0; i < scans->
next_scan; i++) {
915 LOG_ERROR(
"Debug RAM write failed. Hardware error?");
933 for (
unsigned int i = 0; i <
info->dramsize; i++) {
934 if (i == last && run)
938 info->dram_cache[i].dirty =
false;
944 LOG_ERROR(
"Debug interrupt didn't clear.");
954 for (
unsigned int i = 0; i <
info->dramsize; i++)
955 info->dram_cache[i].dirty =
false;
965 LOG_ERROR(
"Debug interrupt didn't clear.");
974 if (read_addr != address) {
975 LOG_INFO(
"Got data from 0x%x but expected it from 0x%x",
978 info->dram_cache[read_addr].data =
980 info->dram_cache[read_addr].valid =
true;
994 if (!
info->dram_cache[address].valid) {
996 info->dram_cache[address].valid =
true;
998 return info->dram_cache[address].data;
1030 LOG_ERROR(
"Timed out waiting for state %d. "
1031 "Increase timeout with riscv set_command_timeout_sec.",
state);
1050 LOG_WARNING(
"Got exception 0x%x when reading %s", exception,
1086 if (
info->tselect_dirty) {
1090 info->tselect_dirty =
false;
1100 if (!
info->tselect_dirty) {
1104 info->tselect_dirty =
true;
1128 if (mstatus_reg->
valid) {
1130 if (mstatus_user !=
info->mstatus_actual) {
1163 LOG_ERROR(
"Debug interrupt didn't clear.");
1187 LOG_ERROR(
"Timed out waiting for step to complete."
1188 "Increase timeout with riscv set_command_timeout_sec");
1197 if (debug_execution) {
1198 LOG_ERROR(
"TODO: debug_execution is true");
1229 if (mstatus_reg->
valid) {
1250 LOG_ERROR(
"Don't know how to read register %d", regnum);
1333 LOG_WARNING(
"Got exception 0x%x when writing %s", exception,
1415 free(
info->version_specific);
1443 int handle_breakpoints)
1449 LOG_WARNING(
"Asked to resume at 32-bit PC on %d-bit target.",
1457 if (handle_breakpoints) {
1473 LOG_DEBUG(
"dtmcontrol=0x%x", dtmcontrol);
1477 if (dtmcontrol == 0) {
1478 LOG_ERROR(
"dtmcontrol is 0. Check JTAG connectivity/board power.");
1482 LOG_ERROR(
"Unsupported DTM version %d. (dtmcontrol=0x%x)",
1492 if (
info->dtmcontrol_idle == 0) {
1495 if (idcode == 0x10e31913)
1496 info->dtmcontrol_idle = 1;
1515 LOG_ERROR(
"OpenOCD only supports Debug Module version 1, not %d "
1523 LOG_ERROR(
"Authentication required by RISC-V core but not "
1524 "supported by OpenOCD. dminfo=0x%x", dminfo);
1541 for (
unsigned i = 6; i <
info->dramsize; i++)
1556 if (word0 == 1 && word1 == 0) {
1557 generic_info->
xlen = 32;
1558 }
else if (word0 == 0xffffffff && word1 == 3) {
1559 generic_info->
xlen = 64;
1560 }
else if (word0 == 0xffffffff && word1 == 0xffffffff) {
1561 generic_info->
xlen = 128;
1564 LOG_ERROR(
"Failed to discover xlen; word0=0x%x, word1=0x%x, exception=0x%x",
1565 word0, word1, exception);
1572 const unsigned old_csr_misa = 0xf10;
1578 LOG_ERROR(
"Failed to read misa at 0x%x.", old_csr_misa);
1586 info->never_halted =
true;
1594 for (
size_t i = 0; i < 32; ++i)
1596 LOG_INFO(
"Examined RISCV core; XLEN=%d, misa=0x%" PRIx64,
1648 LOG_ERROR(
"JTAG execute failed: %d", retval);
1652 unsigned int dbus_busy = 0;
1653 unsigned int interrupt_set = 0;
1654 unsigned result = 0;
1659 for (
unsigned int i = 1; i < scans->
next_scan && dbus_busy == 0; i++) {
1669 LOG_ERROR(
"Debug access failed. Hardware error?");
1682 if (address == 4 || address == 5) {
1788 LOG_ERROR(
"Got invalid register result %d", result);
1796 value = data & 0xffffffff;
1797 }
else if (address == 5) {
1812 if (interrupt_set) {
1840 LOG_ERROR(
"handle_halt_routine failed");
1860 LOG_ERROR(
"Invalid halt cause %d in DCSR (0x%" PRIx64
")",
1864 if (
info->never_halted) {
1865 info->never_halted =
false;
1882 const char *cause_string[] = {
1884 "software breakpoint",
1894 LOG_USER(
"halted at 0x%" PRIx64
" due to %s",
info->dpc, cause_string[cause]);
1911 if (
bits.haltnot &&
bits.interrupt) {
1914 }
else if (
bits.haltnot && !
bits.interrupt) {
1917 }
else if (!
bits.haltnot &&
bits.interrupt) {
1920 }
else if (!
bits.haltnot && !
bits.interrupt) {
1933 target_addr_t address,
int handle_breakpoints,
int debug_execution)
1951 LOG_ERROR(
"Debug interrupt didn't clear.");
1990 if (increment !=
size) {
1991 LOG_ERROR(
"read_memory with custom increment not implemented");
2019 const unsigned max_batch_size = 256;
2024 uint32_t result_value = 0x777;
2026 while (i <
count + 3) {
2027 unsigned int batch_size =
MIN(
count + 3 - i, max_batch_size);
2030 for (
unsigned int j = 0; j < batch_size; j++) {
2031 if (i + j ==
count) {
2034 }
else if (i + j >=
count + 1) {
2046 LOG_ERROR(
"JTAG execute failed: %d", retval);
2051 int execute_busy = 0;
2052 for (
unsigned int j = 0; j < batch_size; j++) {
2059 LOG_ERROR(
"Debug RAM write failed. Hardware error?");
2072 if (i + j ==
count + 2) {
2073 result_value = data;
2074 }
else if (i + j > 1) {
2098 if (dbus_busy || execute_busy) {
2103 " with more delays", address +
size * i);
2109 if (result_value != 0) {
2110 LOG_USER(
"Core got an exception (0x%x) while reading from 0x%"
2115 "didn't check then.)",
2177 const unsigned max_batch_size = 256;
2182 uint32_t result_value = 0x777;
2184 while (i <
count + 2) {
2185 unsigned int batch_size =
MIN(
count + 2 - i, max_batch_size);
2188 for (
unsigned int j = 0; j < batch_size; j++) {
2189 if (i + j >=
count) {
2220 LOG_ERROR(
"JTAG execute failed: %d", retval);
2225 int execute_busy = 0;
2226 for (
unsigned int j = 0; j < batch_size; j++) {
2233 LOG_ERROR(
"Debug RAM write failed. Hardware error?");
2245 if (i + j ==
count + 1)
2252 if (dbus_busy || execute_busy) {
2259 " with more delays", address +
size * i);
2273 if (result_value != 0) {
2274 LOG_ERROR(
"Core got an exception (0x%x) while writing to 0x%"
2279 "didn't check then.)",
2303 riscv_print_info_line(
CMD,
"target",
"memory.read_while_running8", 0);
2304 riscv_print_info_line(
CMD,
"target",
"memory.write_while_running8", 0);
2305 riscv_print_info_line(
CMD,
"target",
"memory.read_while_running16", 0);
2306 riscv_print_info_line(
CMD,
"target",
"memory.write_while_running16", 0);
2307 riscv_print_info_line(
CMD,
"target",
"memory.read_while_running32", 0);
2308 riscv_print_info_line(
CMD,
"target",
"memory.write_while_running32", 0);
2309 riscv_print_info_line(
CMD,
"target",
"memory.read_while_running64", 0);
2310 riscv_print_info_line(
CMD,
"target",
"memory.write_while_running64", 0);
2311 riscv_print_info_line(
CMD,
"target",
"memory.read_while_running128", 0);
2312 riscv_print_info_line(
CMD,
"target",
"memory.write_while_running128", 0);
2328 LOG_ERROR(
"Timed out after %ds waiting for authbusy to go low (dminfo=0x%x). "
2329 "Increase the timeout with riscv set_command_timeout_sec.",
2342 LOG_ERROR(
"Spec 0.11 only has a two authdata registers.");
2358 LOG_ERROR(
"Spec 0.11 only has a two authdata registers.");
2381 generic_info->print_info = &riscv011_print_info;
2384 if (!generic_info->version_specific)
2388 generic_info->xlen = 32;
static uint32_t load(const struct target *target, unsigned int rd, unsigned int base, uint16_t offset) __attribute__((unused))
static uint32_t store(const struct target *target, unsigned int src, unsigned int base, uint16_t offset) __attribute__((unused))
static void buf_set_u64(uint8_t *_buffer, unsigned first, unsigned num, uint64_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
static uint64_t buf_get_u64(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 64-bit word.
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define DCSR_CAUSE_DEBUGINT
enum esirisc_reg_num number
const char * gdb_regno_name(enum gdb_regno regno)
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
void jtag_add_ir_scan(struct jtag_tap *active, struct scan_field *in_fields, tap_state_t state)
Generate an IR SCAN with a list of scan fields with one entry for each enabled TAP.
void jtag_add_runtest(int num_cycles, tap_state_t state)
Goes to TAP_IDLE (if we're not already there), cycle precisely num_cycles in the TAP_IDLE state,...
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
The JTAG interface can be implemented with a software or hardware fifo.
void log_printf_lf(enum log_levels level, const char *file, unsigned line, const char *function, const char *format,...)
#define LOG_USER(expr ...)
#define ERROR_NOT_IMPLEMENTED
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset) __attribute__((unused))
static uint32_t csrw(unsigned int source, unsigned int csr) __attribute__((unused))
static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) __attribute__((unused))
static uint32_t fence_i(void) __attribute__((unused))
static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset) __attribute__((unused))
static uint32_t csrr(unsigned int rd, unsigned int csr) __attribute__((unused))
static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset) __attribute__((unused))
static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset) __attribute__((unused))
static uint32_t jal(unsigned int rd, uint32_t imm) __attribute__((unused))
static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset) __attribute__((unused))
static uint32_t csrsi(unsigned int csr, uint16_t imm) __attribute__((unused))
static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset) __attribute__((unused))
static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset) __attribute__((unused))
static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt) __attribute__((unused))
static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset) __attribute__((unused))
static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset) __attribute__((unused))
static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm) __attribute__((unused))
static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm) __attribute__((unused))
void register_cache_invalidate(struct reg_cache *cache)
Marks the contents of the register cache as invalid (and clean).
static void scans_add_write32(scans_t *scans, uint16_t address, uint32_t data, bool set_interrupt)
Add a 32-bit dbus write to the scans structure.
static riscv_error_t handle_halt_routine(struct target *target)
static void scans_add_write_load(scans_t *scans, uint16_t address, unsigned int reg, slot_t slot, bool set_interrupt)
Add a 32-bit dbus write for an instruction that loads from the indicated slot.
static int riscv011_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
static int resume(struct target *target, int debug_execution, bool step)
struct target_type riscv011_target
static uint64_t reg_cache_get(struct target *target, unsigned int number)
static int maybe_read_tselect(struct target *target)
static int riscv011_poll(struct target *target)
static int register_write(struct target *target, unsigned int number, uint64_t value)
static unsigned int slot_offset(const struct target *target, slot_t slot)
static int wait_for_authbusy(struct target *target)
static void scans_add_write_store(scans_t *scans, uint16_t address, unsigned int reg, slot_t slot, bool set_interrupt)
Add a 32-bit dbus write for an instruction that stores to the indicated slot.
static int strict_step(struct target *target, bool announce)
static int read_remote_csr(struct target *target, uint64_t *value, uint32_t csr)
#define DMCONTROL_INTERRUPT
static void dump_field(const struct scan_field *field)
static void increase_dbus_busy_delay(struct target *target)
static uint32_t load_slot(const struct target *target, unsigned int dest, slot_t slot)
static void scans_dump(scans_t *scans)
#define DMCONTROL_HALTNOT
static int dram_check32(struct target *target, unsigned int index, uint32_t expected)
static uint32_t cache_get32(struct target *target, unsigned int address)
static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in, uint64_t *data_in, dbus_op_t op, uint16_t address_out, uint64_t data_out)
static void cache_set(struct target *target, slot_t slot, uint64_t data)
static uint64_t dbus_read(struct target *target, uint16_t address)
#define DTMCONTROL_DBUS_RESET
static void cache_clean(struct target *target)
static uint16_t dram_address(unsigned int index)
#define DBUS_ADDRESS_START
static int examine(struct target *target)
static int maybe_write_tselect(struct target *target)
static int deassert_reset(struct target *target)
static int register_read(struct target *target, riscv_reg_t *value, int regnum)
static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
Add one or more scans to read the indicated slot.
static bits_t read_bits(struct target *target)
Read the haltnot and interrupt bits.
static uint32_t store_slot(const struct target *target, unsigned int src, slot_t slot)
static int full_step(struct target *target, bool announce)
#define DTMCONTROL_ADDRBITS
static int assert_reset(struct target *target)
#define get_field(reg, mask)
Since almost everything can be accomplish by scanning the dbus register, all functions here assume db...
static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
static void cache_invalidate(struct target *target)
#define DTMCONTROL_VERSION
static int poll_target(struct target *target, bool announce)
static int read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
static scans_t * scans_new(struct target *target, unsigned int scan_count)
static int set_register(struct target *target, int regid, uint64_t value)
static void cache_set_load(struct target *target, unsigned int index, unsigned int reg, slot_t slot)
static int cache_write(struct target *target, unsigned int address, bool run)
static int init_target(struct command_context *cmd_ctx, struct target *target)
static int arch_state(struct target *target)
static riscv011_info_t * get_info(const struct target *target)
static uint32_t dram_read32(struct target *target, unsigned int index)
static int setup_write_memory(struct target *target, uint32_t size)
static int write_gpr(struct target *target, unsigned int gpr, uint64_t value)
static int cache_check(struct target *target)
static COMMAND_HELPER(riscv011_print_info, struct target *target)
static uint64_t cache_get(struct target *target, slot_t slot)
static void scans_add_read32(scans_t *scans, uint16_t address, bool set_interrupt)
Add a 32-bit dbus read.
static int update_mstatus_actual(struct target *target)
static int riscv011_authdata_read(struct target *target, uint32_t *value, unsigned int index)
static int get_register(struct target *target, riscv_reg_t *value, int regid)
#define CACHE_NO_READ
Write cache to the target, and optionally run the program.
static int write_remote_csr(struct target *target, uint32_t csr, uint64_t value)
static int halt(struct target *target)
static void add_dbus_scan(const struct target *target, struct scan_field *field, uint8_t *out_value, uint8_t *in_value, dbus_op_t op, uint16_t address, uint64_t data)
static int wait_for_debugint_clear(struct target *target, bool ignore_first)
static void dbus_write(struct target *target, uint16_t address, uint64_t value)
static uint64_t scans_get_u64(scans_t *scans, unsigned int index, unsigned first, unsigned num)
static void dram_write32(struct target *target, unsigned int index, uint32_t value, bool set_interrupt)
static void cache_set32(struct target *target, unsigned int index, uint32_t data)
static void reg_cache_set(struct target *target, unsigned int number, uint64_t value)
static void dump_debug_ram(struct target *target)
static void scans_add_write_jump(scans_t *scans, uint16_t address, bool set_interrupt)
Add a 32-bit dbus write for an instruction that jumps to the beginning of debug RAM.
static uint32_t idcode_scan(struct target *target)
static uint32_t scans_get_u32(scans_t *scans, unsigned int index, unsigned first, unsigned num)
static void cache_set_jump(struct target *target, unsigned int index)
static void increase_interrupt_high_delay(struct target *target)
static int wait_for_state(struct target *target, enum target_state state)
static void deinit_target(struct target *target)
static void cache_set_store(struct target *target, unsigned int index, unsigned int reg, slot_t slot)
static int execute_resume(struct target *target, bool step)
static int step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
static int scans_execute(scans_t *scans)
static int handle_halt(struct target *target, bool announce)
#define DMINFO_AUTHENTICATED
static void scans_reset(scans_t *scans)
static int write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
#define DMINFO_SERIALCOUNT
static void dram_write_jump(struct target *target, unsigned int index, bool set_interrupt)
#define set_field(reg, mask, val)
static scans_t * scans_delete(scans_t *scans)
static int riscv011_authdata_write(struct target *target, uint32_t value, unsigned int index)
struct scan_field select_idcode
struct scan_field select_dbus
int riscv_set_current_hartid(struct target *target, int hartid)
int riscv_init_registers(struct target *target)
unsigned riscv_xlen(const struct target *target)
struct scan_field select_dtmcontrol
int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
int riscv_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
int riscv_enumerate_triggers(struct target *target)
Count triggers, and initialize trigger_count for each hart.
int riscv_command_timeout_sec
static struct riscv_info * riscv_info(const struct target *target) __attribute__((unused))
enum semihosting_result riscv_semihosting(struct target *target, int *retval)
Check for and process a semihosting request using the ARM protocol).
size_t size
Size of the control block search area.
unsigned int dbus_busy_delay
unsigned int interrupt_high_delay
unsigned int dtmcontrol_idle
struct command_context * cmd_ctx
This structure defines a single scan field in the scan.
int num_bits
The number of bits this field specifies.
uint8_t * in_value
A pointer to a 32-bit memory location for data scanned out.
const uint8_t * out_value
A pointer to value to be scanned into the device.
struct scan_field * field
const struct target * target
This holds methods shared between all instances of a given target type.
const char * name
Name of this type of target.
enum target_debug_reason debug_reason
struct reg_cache * reg_cache
struct watchpoint * watchpoints
int target_call_event_callbacks(struct target *target, enum target_event event)
static void target_set_examined(struct target *target)
Sets the examined flag for the given target.
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
static struct ublast_lowlevel_priv info