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| int(* | authdata_read )(struct target *target, uint32_t *value, unsigned int index) |
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| int(* | authdata_write )(struct target *target, uint32_t value, unsigned int index) |
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| struct command_context * | cmd_ctx |
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| unsigned int | common_magic |
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| int | current_hartid |
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| unsigned(* | data_bits )(struct target *target) |
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| int | debug_buffer_size |
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| int(* | dmi_read )(struct target *target, uint32_t *value, uint32_t address) |
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| int(* | dmi_write )(struct target *target, uint32_t address, uint32_t value) |
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| int(* | dmi_write_u64_bits )(struct target *target) |
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| unsigned | dtm_version |
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| int(* | execute_debug_buffer )(struct target *target) |
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| struct list_head | expose_csr |
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| struct list_head | expose_custom |
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| void(* | fill_dmi_nop_u64 )(struct target *target, char *buf) |
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| void(* | fill_dmi_read_u64 )(struct target *target, char *buf, int a) |
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| void(* | fill_dmi_write_u64 )(struct target *target, char *buf, int a, uint64_t d) |
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| int(* | get_register )(struct target *target, riscv_reg_t *value, int regid) |
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| int(* | get_register_buf )(struct target *target, uint8_t *buf, int regno) |
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| int(* | halt_go )(struct target *target) |
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| int(* | halt_prep )(struct target *target) |
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| enum riscv_halt_reason(* | halt_reason )(struct target *target) |
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| int(* | hart_count )(struct target *target) |
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| bool | impebreak |
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| bool(* | is_halted )(struct target *target) |
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| bool | manual_hwbp_set |
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| bool | mem_access_abstract_warn |
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| int | mem_access_methods [RISCV_NUM_MEM_ACCESS_METHODS] |
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| bool | mem_access_progbuf_warn |
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| bool | mem_access_sysbus_warn |
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| riscv_reg_t | misa |
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| int(* | on_halt )(struct target *target) |
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| int(* | on_step )(struct target *target) |
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| bool | prepped |
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| riscv_insn_t(* | read_debug_buffer )(struct target *target, unsigned index) |
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| int(* | read_memory )(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment) |
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| char * | reg_names |
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| int | reset_delays_wait |
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| int(* | resume_go )(struct target *target) |
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| int(* | resume_prep )(struct target *target) |
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| struct riscv_sample_buf | sample_buf |
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| riscv_sample_config_t | sample_config |
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| int(* | sample_memory )(struct target *target, struct riscv_sample_buf *buf, riscv_sample_config_t *config, int64_t until_ms) |
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| int(* | select_current_hart )(struct target *target) |
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| bool | selected |
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| int(* | set_register )(struct target *target, int regid, uint64_t value) |
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| int(* | set_register_buf )(struct target *target, int regno, const uint8_t *buf) |
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| int(* | step_current_hart )(struct target *target) |
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| int(* | test_sba_config_reg )(struct target *target, target_addr_t legal_address, uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test) |
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| unsigned int | trigger_count |
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| int | trigger_unique_id [RISCV_MAX_HWBPS] |
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| bool | triggers_enumerated |
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| struct reg_data_type | type_uint128_vector |
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| struct reg_data_type | type_uint16_vector |
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| struct reg_data_type | type_uint32_vector |
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| struct reg_data_type | type_uint64_vector |
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| struct reg_data_type | type_uint8_vector |
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| struct reg_data_type | type_vector |
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| struct reg_data_type_union_field | vector_fields [5] |
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| struct reg_data_type_vector | vector_uint128 |
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| struct reg_data_type_vector | vector_uint16 |
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| struct reg_data_type_vector | vector_uint32 |
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| struct reg_data_type_vector | vector_uint64 |
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| struct reg_data_type_vector | vector_uint8 |
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| struct reg_data_type_union | vector_union |
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| void * | version_specific |
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| unsigned int | vlenb |
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| int(* | write_debug_buffer )(struct target *target, unsigned index, riscv_insn_t d) |
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| int | xlen |
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Definition at line 90 of file riscv.h.
