OpenOCD
riscv.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef RISCV_H
4 #define RISCV_H
5 
6 struct riscv_program;
7 
8 #include <stdint.h>
9 #include "opcodes.h"
10 #include "gdb_regs.h"
11 #include "jtag/jtag.h"
12 #include "target/register.h"
14 #include <helper/command.h>
15 
16 #define RISCV_COMMON_MAGIC 0x52495356U
17 
18 /* The register cache is statically allocated. */
19 #define RISCV_MAX_HARTS 1024
20 #define RISCV_MAX_REGISTERS 5000
21 #define RISCV_MAX_TRIGGERS 32
22 #define RISCV_MAX_HWBPS 16
23 
24 #define DEFAULT_COMMAND_TIMEOUT_SEC 2
25 #define DEFAULT_RESET_TIMEOUT_SEC 30
26 
27 #define RISCV_SATP_MODE(xlen) ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)
28 #define RISCV_SATP_PPN(xlen) ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)
29 #define RISCV_PGSHIFT 12
30 
31 # define PG_MAX_LEVEL 4
32 
33 #define RISCV_NUM_MEM_ACCESS_METHODS 3
34 
35 extern struct target_type riscv011_target;
36 extern struct target_type riscv013_target;
37 
38 /*
39  * Definitions shared by code supporting all RISC-V versions.
40  */
41 typedef uint64_t riscv_reg_t;
42 typedef uint32_t riscv_insn_t;
43 typedef uint64_t riscv_addr_t;
44 
50 };
51 
60 };
61 
62 typedef struct {
63  struct target *target;
64  unsigned custom_number;
66 
67 #define RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE 0x80
68 #define RISCV_SAMPLE_BUF_TIMESTAMP_AFTER 0x81
70  uint8_t *buf;
71  unsigned int used;
72  unsigned int size;
73 };
74 
75 typedef struct {
76  bool enabled;
77  struct {
78  bool enabled;
80  uint32_t size_bytes;
81  } bucket[16];
83 
84 typedef struct {
85  struct list_head list;
86  uint16_t low, high;
87  char *name;
88 } range_list_t;
89 
90 struct riscv_info {
91  unsigned int common_magic;
92 
93  unsigned dtm_version;
94 
97 
98  /* The hart that is currently being debugged. Note that this is
99  * different than the hartid that the RTOS is expected to use. This
100  * one will change all the time, it's more of a global argument to
101  * every function than an actual */
103 
104  /* Single buffer that contains all register names, instead of calling
105  * malloc for each register. Needs to be freed when reg_list is freed. */
106  char *reg_names;
107 
108  /* It's possible that each core has a different supported ISA set. */
109  int xlen;
111  /* Cached value of vlenb. 0 if vlenb is not readable for some reason. */
112  unsigned int vlenb;
113 
114  /* The number of triggers per hart. */
115  unsigned int trigger_count;
116 
117  /* For each physical trigger, contains -1 if the hwbp is available, or the
118  * unique_id of the breakpoint/watchpoint that is using it.
119  * Note that in RTOS mode the triggers are the same across all harts the
120  * target controls, while otherwise only a single hart is controlled. */
122 
123  /* The number of entries in the debug buffer. */
125 
126  /* This hart contains an implicit ebreak at the end of the program buffer. */
127  bool impebreak;
128 
130 
131  /* Decremented every scan, and when it reaches 0 we clear the learned
132  * delays, causing them to be relearned. Used for testing. */
134 
135  /* This target has been prepped and is ready to step/resume. */
136  bool prepped;
137  /* This target was selected using hasel. */
138  bool selected;
139 
140  /* Helper functions that target the various RISC-V debug spec
141  * implementations. */
142  int (*get_register)(struct target *target, riscv_reg_t *value, int regid);
143  int (*set_register)(struct target *target, int regid, uint64_t value);
144  int (*get_register_buf)(struct target *target, uint8_t *buf, int regno);
145  int (*set_register_buf)(struct target *target, int regno,
146  const uint8_t *buf);
148  bool (*is_halted)(struct target *target);
149  /* Resume this target, as well as every other prepped target that can be
150  * resumed near-simultaneously. Clear the prepped flag on any target that
151  * was resumed. */
152  int (*resume_go)(struct target *target);
153  int (*step_current_hart)(struct target *target);
154  int (*on_halt)(struct target *target);
155  /* Get this target as ready as possible to resume, without actually
156  * resuming. */
157  int (*resume_prep)(struct target *target);
158  int (*halt_prep)(struct target *target);
159  int (*halt_go)(struct target *target);
160  int (*on_step)(struct target *target);
161  enum riscv_halt_reason (*halt_reason)(struct target *target);
162  int (*write_debug_buffer)(struct target *target, unsigned index,
163  riscv_insn_t d);
164  riscv_insn_t (*read_debug_buffer)(struct target *target, unsigned index);
167  void (*fill_dmi_write_u64)(struct target *target, char *buf, int a, uint64_t d);
168  void (*fill_dmi_read_u64)(struct target *target, char *buf, int a);
169  void (*fill_dmi_nop_u64)(struct target *target, char *buf);
170 
171  int (*authdata_read)(struct target *target, uint32_t *value, unsigned int index);
172  int (*authdata_write)(struct target *target, uint32_t value, unsigned int index);
173 
174  int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address);
175  int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
176 
177  int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address,
178  uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
179 
180  int (*sample_memory)(struct target *target,
181  struct riscv_sample_buf *buf,
183  int64_t until_ms);
184 
185  int (*read_memory)(struct target *target, target_addr_t address,
186  uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
187 
188  /* How many harts are attached to the DM that this target is attached to? */
189  int (*hart_count)(struct target *target);
190  unsigned (*data_bits)(struct target *target);
191 
192  COMMAND_HELPER((*print_info), struct target *target);
193 
194  /* Storage for vector register types. */
207  struct reg_data_type type_vector;
208 
209  /* Set when trigger registers are changed by the user. This indicates we eed
210  * to beware that we may hit a trigger that we didn't realize had been set. */
212 
213  /* Memory access methods to use, ordered by priority, highest to lowest. */
215 
216  /* Different memory regions may need different methods but single configuration is applied
217  * for all. Following flags are used to warn only once about failing memory access method. */
221 
222  /* In addition to the ones in the standard spec, we'll also expose additional
223  * CSRs in this list. */
224  struct list_head expose_csr;
225  /* Same, but for custom registers.
226  * Custom registers are for non-standard extensions and use abstract register numbers
227  * from range 0xc000 ... 0xffff. */
228  struct list_head expose_custom;
229 
232 };
233 
234 COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
235  unsigned int value);
236 
237 typedef struct {
238  uint8_t tunneled_dr_width;
239  struct scan_field tunneled_dr[4];
241 
242 typedef struct {
243  const char *name;
244  int level;
245  unsigned va_bits;
246  unsigned pte_shift;
247  unsigned vpn_shift[PG_MAX_LEVEL];
248  unsigned vpn_mask[PG_MAX_LEVEL];
249  unsigned pte_ppn_shift[PG_MAX_LEVEL];
250  unsigned pte_ppn_mask[PG_MAX_LEVEL];
251  unsigned pa_ppn_shift[PG_MAX_LEVEL];
252  unsigned pa_ppn_mask[PG_MAX_LEVEL];
254 
255 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
256 extern int riscv_command_timeout_sec;
257 
258 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
259 extern int riscv_reset_timeout_sec;
260 
261 extern bool riscv_enable_virtual;
262 extern bool riscv_ebreakm;
263 extern bool riscv_ebreaks;
264 extern bool riscv_ebreaku;
265 
266 /* Everything needs the RISC-V specific info structure, so here's a nice macro
267  * that provides that. */
268 static inline struct riscv_info *riscv_info(const struct target *target) __attribute__((unused));
269 static inline struct riscv_info *riscv_info(const struct target *target)
270 {
271  assert(target->arch_info);
272  return target->arch_info;
273 }
274 #define RISCV_INFO(R) struct riscv_info *R = riscv_info(target);
275 
276 static inline bool is_riscv(const struct riscv_info *riscv_info)
277 {
279 }
280 
281 extern struct scan_field select_dtmcontrol;
282 extern struct scan_field select_dbus;
283 extern struct scan_field select_idcode;
284 
288 extern int bscan_tunnel_ir_width;
289 
290 uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out);
291 void select_dmi_via_bscan(struct target *target);
292 
293 /*** OpenOCD Interface */
294 int riscv_openocd_poll(struct target *target);
295 
296 int riscv_halt(struct target *target);
297 
299  struct target *target,
300  int current,
301  target_addr_t address,
302  int handle_breakpoints
303 );
304 
307 
308 /*** RISC-V Interface ***/
309 
310 bool riscv_supports_extension(struct target *target, char letter);
311 
312 /* Returns XLEN for the given (or current) hart. */
313 unsigned riscv_xlen(const struct target *target);
314 int riscv_xlen_of_hart(const struct target *target);
315 
316 /* Sets the current hart, which is the hart that will actually be used when
317  * issuing debug commands. */
318 int riscv_set_current_hartid(struct target *target, int hartid);
320 int riscv_current_hartid(const struct target *target);
321 
322 /*** Support functions for the RISC-V 'RTOS', which provides multihart support
323  * without requiring multiple targets. */
324 
325 /* Lists the number of harts in the system, which are assumed to be
326  * consecutive and start with mhartid=0. */
327 int riscv_count_harts(struct target *target);
328 
330 int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
332 int riscv_get_register(struct target *target, riscv_reg_t *value,
333  enum gdb_regno r);
334 
335 /* Checks the state of the current hart -- "is_halted" checks the actual
336  * on-device register. */
337 bool riscv_is_halted(struct target *target);
338 
339 /* These helper functions let the generic program interface get target-specific
340  * information. */
341 size_t riscv_debug_buffer_size(struct target *target);
342 
344 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn);
346 
347 void riscv_fill_dmi_nop_u64(struct target *target, char *buf);
348 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d);
349 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a);
351 
353 
356  struct watchpoint *watchpoint);
357 
358 int riscv_init_registers(struct target *target);
359 
360 void riscv_semihosting_init(struct target *target);
361 
362 enum semihosting_result riscv_semihosting(struct target *target, int *retval);
363 
364 void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
366 
367 int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer);
368 int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer);
369 
370 #endif
struct esp_usb_jtag __attribute__
Definition: armv8.c:804
gdb_regno
Definition: gdb_regs.h:8
The JTAG interface can be implemented with a software or hardware fifo.
int riscv_reset_timeout_sec
Definition: riscv.c:206
struct scan_field select_idcode
Definition: riscv.c:123
bool riscv_ebreaks
Definition: riscv.c:210
int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v)
Set register, updating the cache.
Definition: riscv.c:3391
struct target_type riscv011_target
Definition: riscv-011.c:2394
uint32_t bscan_tunneled_select_dmi_num_fields
struct scan_field select_dbus
Definition: riscv.c:118
int riscv_set_current_hartid(struct target *target, int hartid)
Definition: riscv.c:3296
int riscv_xlen_of_hart(const struct target *target)
static struct riscv_info * riscv_info(const struct target *target) __attribute__((unused))
Definition: riscv.h:269
static bool is_riscv(const struct riscv_info *riscv_info)
Definition: riscv.h:276
#define PG_MAX_LEVEL
Definition: riscv.h:31
int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn)
Definition: riscv.c:3480
int riscv_openocd_deassert_reset(struct target *target)
bool riscv_is_halted(struct target *target)
Definition: riscv.c:3455
int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
Read one memory item using any memory access size that will work.
Definition: riscv.c:837
int riscv_init_registers(struct target *target)
Definition: riscv.c:3873
void riscv_semihosting_init(struct target *target)
Initialize RISC-V semihosting.
int riscv_halt(struct target *target)
Definition: riscv.c:1226
bool riscv_ebreakm
Definition: riscv.c:209
riscv_mem_access_method
Definition: riscv.h:45
@ RISCV_MEM_ACCESS_UNSPECIFIED
Definition: riscv.h:46
@ RISCV_MEM_ACCESS_SYSBUS
Definition: riscv.h:48
@ RISCV_MEM_ACCESS_PROGBUF
Definition: riscv.h:47
@ RISCV_MEM_ACCESS_ABSTRACT
Definition: riscv.h:49
#define RISCV_NUM_MEM_ACCESS_METHODS
Definition: riscv.h:33
int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
Write one memory item using any memory access size that will work.
Definition: riscv.c:805
void riscv_fill_dmi_nop_u64(struct target *target, char *buf)
Definition: riscv.c:3511
unsigned riscv_xlen(const struct target *target)
Definition: riscv.c:3290
struct target_type riscv013_target
Definition: riscv-013.c:4052
void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field, riscv_bscan_tunneled_scan_context_t *ctxt)
Definition: riscv.c:4501
COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key, unsigned int value)
Definition: riscv.c:2902
#define RISCV_MAX_HWBPS
Definition: riscv.h:22
enum semihosting_result riscv_semihosting(struct target *target, int *retval)
Check for and process a semihosting request using the ARM protocol).
int riscv_current_hartid(const struct target *target)
Definition: riscv.c:3322
int riscv_select_current_hart(struct target *target)
Definition: riscv.c:1161
int riscv_execute_debug_buffer(struct target *target)
Definition: riscv.c:3493
struct scan_field * bscan_tunneled_select_dmi
size_t riscv_debug_buffer_size(struct target *target)
Definition: riscv.c:3474
struct scan_field select_dtmcontrol
Definition: riscv.c:113
uint64_t riscv_reg_t
Definition: riscv.h:41
uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
Definition: riscv.c:293
int riscv_openocd_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
Definition: riscv.c:2305
int riscv_openocd_poll(struct target *target)
Definition: riscv.c:2184
int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: riscv.c:988
#define RISCV_COMMON_MAGIC
Definition: riscv.h:16
int riscv_openocd_assert_reset(struct target *target)
void select_dmi_via_bscan(struct target *target)
Definition: riscv.c:282
bscan_tunnel_type_t
Definition: riscv.h:287
@ BSCAN_TUNNEL_NESTED_TAP
Definition: riscv.h:287
@ BSCAN_TUNNEL_DATA_REGISTER
Definition: riscv.h:287
int riscv_dmi_write_u64_bits(struct target *target)
Definition: riscv.c:3517
bool riscv_enable_virtual
Definition: riscv.c:213
bool riscv_supports_extension(struct target *target, char letter)
Definition: riscv.c:3277
void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
Definition: riscv.c:3499
void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a)
Definition: riscv.c:3505
int riscv_get_register(struct target *target, riscv_reg_t *value, enum gdb_regno r)
Get register, from the cache if it's in there.
Definition: riscv.c:3417
bool riscv_ebreaku
Definition: riscv.c:211
int riscv_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: riscv.c:1001
uint32_t riscv_insn_t
Definition: riscv.h:42
riscv_halt_reason
Definition: riscv.h:52
@ RISCV_HALT_INTERRUPT
Definition: riscv.h:53
@ RISCV_HALT_BREAKPOINT
Definition: riscv.h:54
@ RISCV_HALT_SINGLESTEP
Definition: riscv.h:55
@ RISCV_HALT_UNKNOWN
Definition: riscv.h:57
@ RISCV_HALT_ERROR
Definition: riscv.h:59
@ RISCV_HALT_GROUP
Definition: riscv.h:58
@ RISCV_HALT_TRIGGER
Definition: riscv.h:56
riscv_insn_t riscv_read_debug_buffer(struct target *target, int index)
Definition: riscv.c:3487
int riscv_enumerate_triggers(struct target *target)
Count triggers, and initialize trigger_count for each hart.
Definition: riscv.c:3530
int riscv_command_timeout_sec
Definition: riscv.c:203
uint64_t riscv_addr_t
Definition: riscv.h:43
int riscv_count_harts(struct target *target)
Definition: riscv.c:3328
int bscan_tunnel_ir_width
Definition: riscv.c:129
struct target * target
Definition: rtt/rtt.c:26
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
semihosting_result
Definition: list.h:26
char * name
Definition: riscv.h:87
uint16_t high
Definition: riscv.h:86
int(* on_step)(struct target *target)
Definition: riscv.h:160
void * version_specific
Definition: riscv.h:96
int(* dmi_read)(struct target *target, uint32_t *value, uint32_t address)
Definition: riscv.h:174
struct reg_data_type_vector vector_uint8
Definition: riscv.h:195
struct reg_data_type type_uint64_vector
Definition: riscv.h:203
bool(* is_halted)(struct target *target)
Definition: riscv.h:148
struct reg_data_type type_uint16_vector
Definition: riscv.h:201
unsigned(* data_bits)(struct target *target)
Definition: riscv.h:190
struct list_head expose_custom
Definition: riscv.h:228
struct reg_data_type_vector vector_uint16
Definition: riscv.h:196
int(* set_register_buf)(struct target *target, int regno, const uint8_t *buf)
Definition: riscv.h:145
int(* get_register_buf)(struct target *target, uint8_t *buf, int regno)
Definition: riscv.h:144
int(* halt_go)(struct target *target)
Definition: riscv.h:159
struct reg_data_type type_vector
Definition: riscv.h:207
struct reg_data_type_union_field vector_fields[5]
Definition: riscv.h:205
riscv_insn_t(* read_debug_buffer)(struct target *target, unsigned index)
Definition: riscv.h:164
int(* dmi_write_u64_bits)(struct target *target)
Definition: riscv.h:166
int(* select_current_hart)(struct target *target)
Definition: riscv.h:147
bool selected
Definition: riscv.h:138
bool triggers_enumerated
Definition: riscv.h:129
int mem_access_methods[RISCV_NUM_MEM_ACCESS_METHODS]
Definition: riscv.h:214
int xlen
Definition: riscv.h:109
struct reg_data_type type_uint128_vector
Definition: riscv.h:204
unsigned int vlenb
Definition: riscv.h:112
bool prepped
Definition: riscv.h:136
int(* write_debug_buffer)(struct target *target, unsigned index, riscv_insn_t d)
Definition: riscv.h:162
char * reg_names
Definition: riscv.h:106
int current_hartid
Definition: riscv.h:102
int debug_buffer_size
Definition: riscv.h:124
int(* authdata_write)(struct target *target, uint32_t value, unsigned int index)
Definition: riscv.h:172
bool mem_access_abstract_warn
Definition: riscv.h:220
bool mem_access_sysbus_warn
Definition: riscv.h:219
struct list_head expose_csr
Definition: riscv.h:224
struct reg_data_type type_uint32_vector
Definition: riscv.h:202
int(* resume_prep)(struct target *target)
Definition: riscv.h:157
int(* halt_prep)(struct target *target)
Definition: riscv.h:158
bool manual_hwbp_set
Definition: riscv.h:211
int reset_delays_wait
Definition: riscv.h:133
int(* dmi_write)(struct target *target, uint32_t address, uint32_t value)
Definition: riscv.h:175
riscv_reg_t misa
Definition: riscv.h:110
riscv_sample_config_t sample_config
Definition: riscv.h:230
COMMAND_HELPER((*print_info), struct target *target)
bool mem_access_progbuf_warn
Definition: riscv.h:218
unsigned int common_magic
Definition: riscv.h:91
void(* fill_dmi_write_u64)(struct target *target, char *buf, int a, uint64_t d)
Definition: riscv.h:167
int(* on_halt)(struct target *target)
Definition: riscv.h:154
int(* sample_memory)(struct target *target, struct riscv_sample_buf *buf, riscv_sample_config_t *config, int64_t until_ms)
Definition: riscv.h:180
int(* authdata_read)(struct target *target, uint32_t *value, unsigned int index)
Definition: riscv.h:171
struct reg_data_type type_uint8_vector
Definition: riscv.h:200
struct reg_data_type_vector vector_uint32
Definition: riscv.h:197
int(* hart_count)(struct target *target)
Definition: riscv.h:189
struct riscv_sample_buf sample_buf
Definition: riscv.h:231
struct reg_data_type_union vector_union
Definition: riscv.h:206
unsigned int trigger_count
Definition: riscv.h:115
int(* step_current_hart)(struct target *target)
Definition: riscv.h:153
struct reg_data_type_vector vector_uint64
Definition: riscv.h:198
int(* read_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
Definition: riscv.h:185
struct command_context * cmd_ctx
Definition: riscv.h:95
unsigned dtm_version
Definition: riscv.h:93
enum riscv_halt_reason(* halt_reason)(struct target *target)
Definition: riscv.h:161
void(* fill_dmi_nop_u64)(struct target *target, char *buf)
Definition: riscv.h:169
int(* set_register)(struct target *target, int regid, uint64_t value)
Definition: riscv.h:143
void(* fill_dmi_read_u64)(struct target *target, char *buf, int a)
Definition: riscv.h:168
int(* execute_debug_buffer)(struct target *target)
Definition: riscv.h:165
bool impebreak
Definition: riscv.h:127
int trigger_unique_id[RISCV_MAX_HWBPS]
Definition: riscv.h:121
struct reg_data_type_vector vector_uint128
Definition: riscv.h:199
int(* resume_go)(struct target *target)
Definition: riscv.h:152
int(* get_register)(struct target *target, riscv_reg_t *value, int regid)
Definition: riscv.h:142
int(* test_sba_config_reg)(struct target *target, target_addr_t legal_address, uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test)
Definition: riscv.h:177
unsigned custom_number
Definition: riscv.h:64
struct target * target
Definition: riscv.h:63
unsigned int size
Definition: riscv.h:72
uint8_t * buf
Definition: riscv.h:70
unsigned int used
Definition: riscv.h:71
target_addr_t address
Definition: riscv.h:79
This structure defines a single scan field in the scan.
Definition: jtag.h:86
This holds methods shared between all instances of a given target type.
Definition: target_type.h:26
Definition: target.h:120
void * arch_info
Definition: target.h:169
const char * name
Definition: riscv.h:243
unsigned pte_shift
Definition: riscv.h:246
unsigned va_bits
Definition: riscv.h:245
uint64_t target_addr_t
Definition: types.h:335
static struct ublast_lowlevel low
uint8_t count[4]
Definition: vdebug.c:22