16 #define RISCV_COMMON_MAGIC 0x52495356U
19 #define RISCV_MAX_HARTS 1024
20 #define RISCV_MAX_REGISTERS 5000
21 #define RISCV_MAX_TRIGGERS 32
22 #define RISCV_MAX_HWBPS 16
24 #define DEFAULT_COMMAND_TIMEOUT_SEC 2
25 #define DEFAULT_RESET_TIMEOUT_SEC 30
27 #define RISCV_SATP_MODE(xlen) ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)
28 #define RISCV_SATP_PPN(xlen) ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)
29 #define RISCV_PGSHIFT 12
31 # define PG_MAX_LEVEL 4
33 #define RISCV_NUM_MEM_ACCESS_METHODS 3
67 #define RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE 0x80
68 #define RISCV_SAMPLE_BUF_TIMESTAMP_AFTER 0x81
178 uint32_t num_words,
target_addr_t illegal_address,
bool run_sbbusyerror_test);
234 COMMAND_HELPER(riscv_print_info_line,
const char *section,
const char *key,
238 uint8_t tunneled_dr_width;
274 #define RISCV_INFO(R) struct riscv_info *R = riscv_info(target);
302 int handle_breakpoints
struct esp_usb_jtag __attribute__
static struct device_config config
The JTAG interface can be implemented with a software or hardware fifo.
int riscv_reset_timeout_sec
struct scan_field select_idcode
int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v)
Set register, updating the cache.
struct target_type riscv011_target
uint32_t bscan_tunneled_select_dmi_num_fields
struct scan_field select_dbus
int riscv_set_current_hartid(struct target *target, int hartid)
int riscv_xlen_of_hart(const struct target *target)
static struct riscv_info * riscv_info(const struct target *target) __attribute__((unused))
static bool is_riscv(const struct riscv_info *riscv_info)
int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn)
int riscv_openocd_deassert_reset(struct target *target)
bool riscv_is_halted(struct target *target)
int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
Read one memory item using any memory access size that will work.
int riscv_init_registers(struct target *target)
void riscv_semihosting_init(struct target *target)
Initialize RISC-V semihosting.
int riscv_halt(struct target *target)
@ RISCV_MEM_ACCESS_UNSPECIFIED
@ RISCV_MEM_ACCESS_SYSBUS
@ RISCV_MEM_ACCESS_PROGBUF
@ RISCV_MEM_ACCESS_ABSTRACT
#define RISCV_NUM_MEM_ACCESS_METHODS
int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
Write one memory item using any memory access size that will work.
void riscv_fill_dmi_nop_u64(struct target *target, char *buf)
unsigned riscv_xlen(const struct target *target)
struct target_type riscv013_target
void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field, riscv_bscan_tunneled_scan_context_t *ctxt)
COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key, unsigned int value)
enum semihosting_result riscv_semihosting(struct target *target, int *retval)
Check for and process a semihosting request using the ARM protocol).
int riscv_current_hartid(const struct target *target)
int riscv_select_current_hart(struct target *target)
int riscv_execute_debug_buffer(struct target *target)
struct scan_field * bscan_tunneled_select_dmi
size_t riscv_debug_buffer_size(struct target *target)
struct scan_field select_dtmcontrol
uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
int riscv_openocd_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int riscv_openocd_poll(struct target *target)
int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
#define RISCV_COMMON_MAGIC
int riscv_openocd_assert_reset(struct target *target)
void select_dmi_via_bscan(struct target *target)
@ BSCAN_TUNNEL_NESTED_TAP
@ BSCAN_TUNNEL_DATA_REGISTER
int riscv_dmi_write_u64_bits(struct target *target)
bool riscv_enable_virtual
bool riscv_supports_extension(struct target *target, char letter)
void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a)
int riscv_get_register(struct target *target, riscv_reg_t *value, enum gdb_regno r)
Get register, from the cache if it's in there.
int riscv_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
riscv_insn_t riscv_read_debug_buffer(struct target *target, int index)
int riscv_enumerate_triggers(struct target *target)
Count triggers, and initialize trigger_count for each hart.
int riscv_command_timeout_sec
int riscv_count_harts(struct target *target)
int bscan_tunnel_ir_width
size_t size
Size of the control block search area.
int(* on_step)(struct target *target)
int(* dmi_read)(struct target *target, uint32_t *value, uint32_t address)
struct reg_data_type_vector vector_uint8
struct reg_data_type type_uint64_vector
bool(* is_halted)(struct target *target)
struct reg_data_type type_uint16_vector
unsigned(* data_bits)(struct target *target)
struct list_head expose_custom
struct reg_data_type_vector vector_uint16
int(* set_register_buf)(struct target *target, int regno, const uint8_t *buf)
int(* get_register_buf)(struct target *target, uint8_t *buf, int regno)
int(* halt_go)(struct target *target)
struct reg_data_type type_vector
struct reg_data_type_union_field vector_fields[5]
riscv_insn_t(* read_debug_buffer)(struct target *target, unsigned index)
int(* dmi_write_u64_bits)(struct target *target)
int(* select_current_hart)(struct target *target)
int mem_access_methods[RISCV_NUM_MEM_ACCESS_METHODS]
struct reg_data_type type_uint128_vector
int(* write_debug_buffer)(struct target *target, unsigned index, riscv_insn_t d)
int(* authdata_write)(struct target *target, uint32_t value, unsigned int index)
bool mem_access_abstract_warn
bool mem_access_sysbus_warn
struct list_head expose_csr
struct reg_data_type type_uint32_vector
int(* resume_prep)(struct target *target)
int(* halt_prep)(struct target *target)
int(* dmi_write)(struct target *target, uint32_t address, uint32_t value)
riscv_sample_config_t sample_config
COMMAND_HELPER((*print_info), struct target *target)
bool mem_access_progbuf_warn
unsigned int common_magic
void(* fill_dmi_write_u64)(struct target *target, char *buf, int a, uint64_t d)
int(* on_halt)(struct target *target)
int(* sample_memory)(struct target *target, struct riscv_sample_buf *buf, riscv_sample_config_t *config, int64_t until_ms)
int(* authdata_read)(struct target *target, uint32_t *value, unsigned int index)
struct reg_data_type type_uint8_vector
struct reg_data_type_vector vector_uint32
int(* hart_count)(struct target *target)
struct riscv_sample_buf sample_buf
struct reg_data_type_union vector_union
unsigned int trigger_count
int(* step_current_hart)(struct target *target)
struct reg_data_type_vector vector_uint64
int(* read_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
struct command_context * cmd_ctx
enum riscv_halt_reason(* halt_reason)(struct target *target)
void(* fill_dmi_nop_u64)(struct target *target, char *buf)
int(* set_register)(struct target *target, int regid, uint64_t value)
void(* fill_dmi_read_u64)(struct target *target, char *buf, int a)
int(* execute_debug_buffer)(struct target *target)
int trigger_unique_id[RISCV_MAX_HWBPS]
struct reg_data_type_vector vector_uint128
int(* resume_go)(struct target *target)
int(* get_register)(struct target *target, riscv_reg_t *value, int regid)
int(* test_sba_config_reg)(struct target *target, target_addr_t legal_address, uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test)
This structure defines a single scan field in the scan.
This holds methods shared between all instances of a given target type.
static struct ublast_lowlevel low