3 #ifndef TARGET__RISCV__PROGRAM_H
4 #define TARGET__RISCV__PROGRAM_H
8 #define RISCV_MAX_DEBUG_BUFFER_SIZE 32
9 #define RISCV_REGISTER_COUNT 32
10 #define RISCV_DSCRATCH_COUNT 2
int riscv_program_fence_i(struct riscv_program *p)
int riscv_program_ldr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno a, int o)
int riscv_program_write(struct riscv_program *program)
int riscv_program_lwr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno a, int o)
int riscv_program_fence(struct riscv_program *p)
int riscv_program_sbr(struct riscv_program *p, enum gdb_regno s, enum gdb_regno a, int o)
int riscv_program_csrrsi(struct riscv_program *p, enum gdb_regno d, unsigned int z, enum gdb_regno csr)
int riscv_program_addi(struct riscv_program *p, enum gdb_regno d, enum gdb_regno s, int16_t i)
int riscv_program_sdr(struct riscv_program *p, enum gdb_regno s, enum gdb_regno a, int o)
int riscv_program_init(struct riscv_program *p, struct target *t)
int riscv_program_lbr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno a, int o)
int riscv_program_insert(struct riscv_program *p, riscv_insn_t i)
int riscv_program_csrr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno csr)
int riscv_program_csrw(struct riscv_program *p, enum gdb_regno s, enum gdb_regno csr)
int riscv_program_shr(struct riscv_program *p, enum gdb_regno s, enum gdb_regno a, int o)
int riscv_program_swr(struct riscv_program *p, enum gdb_regno s, enum gdb_regno a, int o)
int riscv_program_ebreak(struct riscv_program *p)
int riscv_program_lhr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno a, int o)
#define RISCV_MAX_DEBUG_BUFFER_SIZE
int riscv_program_exec(struct riscv_program *p, struct target *t)
Add ebreak and execute the program.
int riscv_program_csrrci(struct riscv_program *p, enum gdb_regno d, unsigned int z, enum gdb_regno csr)
#define RISCV_REGISTER_COUNT
uint32_t debug_buffer[RISCV_MAX_DEBUG_BUFFER_SIZE]
bool writes_xreg[RISCV_REGISTER_COUNT]