42 uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
53 LOG_DEBUG(
"MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
55 (
int) crm, (
int) op2);
67 uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
78 LOG_DEBUG(
"MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
80 (
int) crm, (
int) op2);
127 uint32_t value_r0, value_r1;
156 (
unsigned) value_r0, (
unsigned) value_r1);
260 (
unsigned) value_r0, (
unsigned) value_r1);
345 for (
unsigned i = 0; i < 2; i++) {
363 for (
unsigned i = 2; i < 16; i++) {
405 xp->
dirty = disable =
false;
411 xp->
dirty = disable =
true;
423 disable ?
"disable" :
"enable",
425 (xp->
number < 16) ?
"break" :
"watch",
460 for (
unsigned i = 0; i < dpm->
nbp; i++) {
472 for (
unsigned i = 0; i < dpm->
nwp; i++) {
497 for (
unsigned i = 2; i < cache->
num_regs; i++) {
584 for (
unsigned i = 0; i < 2; i++) {
752 for (
unsigned i = 0; i < cache->
num_regs; i++) {
782 (r->
num == 16) ? 17 : r->
num);
827 control |= (1 << (
addr & 3)) << 5;
832 control |= (3 << (
addr & 2)) << 5;
844 LOG_ERROR(
"unsupported {break,watch}point length/alignment");
858 LOG_DEBUG(
"BPWP: addr %8.8" PRIx32
", control %" PRIx32
", number %d",
880 for (
unsigned i = 0; i < dpm->
nbp; i++) {
881 if (!dpm->
dbp[i].
bp) {
899 for (
unsigned i = 0; i < dpm->
nbp; i++) {
900 if (dpm->
dbp[i].
bp == bp) {
922 LOG_DEBUG(
"watchpoint values and masking not supported");
956 for (
unsigned i = 0; i < dpm->
nwp; i++) {
957 if (!dpm->
dwp[i].
wp) {
973 for (
unsigned i = 0; i < dpm->
nwp; i++) {
974 if (dpm->
dwp[i].
wp == wp) {
1088 dpm->
nbp = 1 + ((dpm->
didr >> 24) & 0xf);
1089 dpm->
nwp = 1 + ((dpm->
didr >> 28) & 0xf);
1090 dpm->
dbp = calloc(dpm->
nbp,
sizeof(*dpm->
dbp));
1091 dpm->
dwp = calloc(dpm->
nwp,
sizeof(*dpm->
dwp));
1093 if (!dpm->
dbp || !dpm->
dwp) {
1100 LOG_INFO(
"%s: hardware has %d breakpoints, %d watchpoints",
1120 for (i = 0; i < dpm->
nbp; i++) {
1124 for (i = 0; i < dpm->
nwp; i++) {
1129 LOG_WARNING(
"%s: can't disable breakpoints and watchpoints",
Holds the interface to ARM cores.
struct reg_cache * arm_build_reg_cache(struct target *target, struct arm *arm)
arm_mode
Represent state of an ARM core.
void arm_free_reg_cache(struct arm *arm)
static struct arm * target_to_arm(struct target *target)
Convert target handle to generic ARM target state handle.
void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
Configures host-side ARM records to reflect the specified CPSR.
struct reg * arm_reg_current(struct arm *arm, unsigned regnum)
Returns handle to the register currently mapped to a given number.
void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
int arm_dpm_read_current_registers(struct arm_dpm *dpm)
Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or ...
int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
static int dpm_write_pc_core_state(struct arm_dpm *dpm, struct reg *r)
Write to program counter and switch the core state (arm/thumb) according to the address.
int arm_dpm_setup(struct arm_dpm *dpm)
Hooks up this DPM to its associated target; call only once.
int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
static int arm_dpm_full_context(struct target *target)
static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp, struct dpm_bpwp *xp, bool *set_p)
static enum arm_mode dpm_mapmode(struct arm *arm, unsigned num, enum arm_mode mode)
int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
Writes all modified core registers for all processor modes.
static int dpm_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
static int arm_dpm_write_core_reg(struct target *target, struct reg *r, int regnum, enum arm_mode mode, uint8_t *value)
static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t, struct watchpoint *wp)
static int dpm_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
static int arm_dpm_read_core_reg(struct target *target, struct reg *r, int regnum, enum arm_mode mode)
static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp, uint32_t addr, uint32_t length)
static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp)
int arm_dpm_initialize(struct arm_dpm *dpm)
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affec...
static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp)
static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
This is the interface to the Debug Programmers Model for ARMv6 and ARMv7 processors.
#define DSCR_ENTRY_BKPT_INSTR
#define DSCR_ENTRY_IMPRECISE_WATCHPT
#define DSCR_ENTRY_PRECISE_WATCHPT
#define DSCR_ENTRY_EXT_DBG_REQ
#define DSCR_ENTRY_BREAKPOINT
#define DSCR_ENTRY_HALT_REQ
Macros used to generate various ARM or Thumb opcodes.
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
#define ARMV4_5_MRS(rn, r)
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
#define ARMV4_5_VMOV(op, rt2, rt, m, vm)
#define ARMV4_5_MSR_GP(rm, field, r)
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
#define ERROR_COMMAND_SYNTAX_ERROR
The JTAG interface can be implemented with a software or hardware fifo.
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
This wraps an implementation of DPM primitives.
target_addr_t wp_addr
Target dependent watchpoint address.
int(* instr_read_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from dcc after execution.
uint64_t didr
Cache of DIDR.
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
int(* bpwp_enable)(struct arm_dpm *dpm, unsigned index_value, uint32_t addr, uint32_t control)
Enables one breakpoint or watchpoint by writing to the hardware registers.
int(* instr_write_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
int(* bpwp_disable)(struct arm_dpm *dpm, unsigned index_value)
Disables one breakpoint or watchpoint by clearing its hardware control registers.
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
int(* instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
int(* instr_cpsr_sync)(struct arm_dpm *dpm)
Optional core-specific operation invoked after CPSR writes.
uint32_t dscr
Recent value of DSCR.
Represents a generic ARM core, with standard application registers.
int(* full_context)(struct target *target)
Retrieve all core registers, for display.
int(* mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
Read coprocessor register.
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
struct reg * cpsr
Handle to the CPSR/xPSR; valid in all core modes.
struct reg * pc
Handle to the PC; valid in all core modes.
int(* write_core_reg)(struct target *target, struct reg *reg, int num, enum arm_mode mode, uint8_t *value)
int(* read_core_reg)(struct target *target, struct reg *reg, int num, enum arm_mode mode)
Retrieve a single core register.
struct reg_cache * core_cache
struct arm_dpm * dpm
Handle for the debug module, if one is present.
int(* mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
Write coprocessor register.
struct target * target
Backpointer to the target.
enum arm_state core_state
Record the current core state: ARM, Thumb, or otherwise.
enum breakpoint_type type
int(* add_breakpoint)(struct target *target, struct breakpoint *breakpoint)
int(* add_watchpoint)(struct target *target, struct watchpoint *watchpoint)
int(* remove_breakpoint)(struct target *target, struct breakpoint *breakpoint)
int(* remove_watchpoint)(struct target *target, struct watchpoint *watchpoint)
enum target_debug_reason debug_reason
struct reg_cache * reg_cache
struct target_type * type
static const char * target_name(struct target *target)
Returns the instance-specific name of the specified target.
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE