armv8_dpm.h File Reference

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Macros
#define	DRCR_CBRRQ   (1 << 4)
#define	DRCR_CLEAR_EXCEPTIONS   (1 << 2)
#define	DRCR_CSE   (1 << 2)
#define	DRCR_CSPA   (1 << 3)
#define	DRCR_HALT   (1 << 0)
#define	DRCR_RESTART   (1 << 1)
#define	DSCR_CUR_EL   (0x3 << 8)
#define	DSCR_DEBUG_STATUS_MASK   (0x1F << 0)
#define	DSCR_DTR_RX_FULL   (0x1 << 30) /* bit 31 is reserved */
#define	DSCR_DTR_TX_FULL   (0x1 << 29)
#define	DSCR_EL_STATUS_MASK   (0xF << 10)
#define	DSCR_ERR   (0x1 << 6)
#define	DSCR_EXT_DCC_FAST_MODE   (0x2 << 20) /* bits 22, 23 are reserved */
#define	DSCR_EXT_DCC_NON_BLOCKING   (0x0 << 20)
#define	DSCR_EXT_DCC_STALL_MODE   (0x1 << 20)
#define	DSCR_HDE   (0x1 << 14)
#define	DSCR_INTDIS_MASK   (0x3 << 22)
#define	DSCR_ITE   (0x1 << 24)
#define	DSCR_ITO   (0x1 << 28)
#define	DSCR_MA   (0x1 << 20)
#define	DSCR_NON_SECURE   (0x1 << 18)
#define	DSCR_PIPE_ADVANCE   (0x1 << 25)
#define	DSCR_RTO   (0x1 << 27) /* bit 28 is reserved */
#define	DSCR_SDD   (0x1 << 16)
#define	DSCR_SYS_ERROR_PEND   (0x1 << 7)
#define	DSCR_TDA   (0x1 << 21)
#define	DSCR_TXU   (0x1 << 26)
#define	DSCRV8_ENTRY_BKPT   (0x7)
#define	DSCRV8_ENTRY_EXCEPTION_CATCH   (0x37)
#define	DSCRV8_ENTRY_EXT_DEBUG   (0x13)
#define	DSCRV8_ENTRY_HALT_STEP   (0x3B)
#define	DSCRV8_ENTRY_HALT_STEP_EXECLU   (0x1F)
#define	DSCRV8_ENTRY_HALT_STEP_NORMAL   (0x1B)
#define	DSCRV8_ENTRY_HLT   (0x2F)
#define	DSCRV8_ENTRY_NON_DEBUG   (0x2)
#define	DSCRV8_ENTRY_OS_UNLOCK   (0x23)
#define	DSCRV8_ENTRY_RESET_CATCH   (0x27)
#define	DSCRV8_ENTRY_RESTARTING   (0x1)
#define	DSCRV8_ENTRY_SW_ACCESS_DBG   (0x33)
#define	DSCRV8_ENTRY_WATCHPOINT   (0x2B)
#define	DSCRV8_HALT_MASK   (0x3C)
#define	ECR_RCE   BIT(1)
#define	ESR_RC   BIT(1)
#define	PRCR_CORENPDRQ   (1 << 0)
#define	PRCR_COREPURQ   (1 << 3)
#define	PRCR_CWRR   (1 << 2)
#define	PRSR_DLK   (1 << 6)
#define	PRSR_EDAD   (1 << 7)
#define	PRSR_EPMAD   (1 << 9)
#define	PRSR_HALT   (1 << 4)
#define	PRSR_OSLK   (1 << 5)
#define	PRSR_PU   (1 << 0)
#define	PRSR_RESET   (1 << 2)
#define	PRSR_SDAD   (1 << 8)
#define	PRSR_SDR   (1 << 11)
#define	PRSR_SPD   (1 << 1)
#define	PRSR_SPMAD   (1 << 10)
#define	PRSR_SR   (1 << 3)

Functions
enum arm_state	armv8_dpm_get_core_state (struct arm_dpm *dpm)
	Get core state from EDSCR, without necessity to retrieve CPSR. More...
void	armv8_dpm_handle_exception (struct arm_dpm *dpm, bool do_restore)
int	armv8_dpm_initialize (struct arm_dpm *dpm)
	Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affected the debug module. More...
int	armv8_dpm_modeswitch (struct arm_dpm *dpm, enum arm_mode mode)
int	armv8_dpm_read_current_registers (struct arm_dpm *dpm)
	Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb). More...
void	armv8_dpm_report_dscr (struct arm_dpm *dpm, uint32_t dcsr)
int	armv8_dpm_setup (struct arm_dpm *dpm)
	This wraps an implementation of DPM primitives. More...
int	armv8_dpm_write_dirty_registers (struct arm_dpm *dpm, bool bpwp)
	Writes all modified core registers for all processor modes. More...

Macro Definition Documentation

DRCR_CBRRQ

#define DRCR_CBRRQ   (1 << 4)

Definition at line 76 of file armv8_dpm.h.

DRCR_CLEAR_EXCEPTIONS

#define DRCR_CLEAR_EXCEPTIONS   (1 << 2)

Definition at line 88 of file armv8_dpm.h.

DRCR_CSE

#define DRCR_CSE   (1 << 2)

Definition at line 74 of file armv8_dpm.h.

DRCR_CSPA

#define DRCR_CSPA   (1 << 3)

Definition at line 75 of file armv8_dpm.h.

DRCR_HALT

#define DRCR_HALT   (1 << 0)

Definition at line 86 of file armv8_dpm.h.

DRCR_RESTART

#define DRCR_RESTART   (1 << 1)

Definition at line 87 of file armv8_dpm.h.

DSCR_CUR_EL

#define DSCR_CUR_EL   (0x3 << 8)

Definition at line 39 of file armv8_dpm.h.

DSCR_DEBUG_STATUS_MASK

#define DSCR_DEBUG_STATUS_MASK   (0x1F << 0)

Definition at line 36 of file armv8_dpm.h.

DSCR_DTR_RX_FULL

#define DSCR_DTR_RX_FULL   (0x1 << 30) /* bit 31 is reserved */

Definition at line 53 of file armv8_dpm.h.

DSCR_DTR_TX_FULL

#define DSCR_DTR_TX_FULL   (0x1 << 29)

Definition at line 52 of file armv8_dpm.h.

DSCR_EL_STATUS_MASK

#define DSCR_EL_STATUS_MASK   (0xF << 10)

Definition at line 40 of file armv8_dpm.h.

DSCR_ERR

#define DSCR_ERR   (0x1 << 6)

Definition at line 37 of file armv8_dpm.h.

DSCR_EXT_DCC_FAST_MODE

#define DSCR_EXT_DCC_FAST_MODE   (0x2 << 20) /* bits 22, 23 are reserved */

Definition at line 82 of file armv8_dpm.h.

DSCR_EXT_DCC_NON_BLOCKING

#define DSCR_EXT_DCC_NON_BLOCKING   (0x0 << 20)

Definition at line 80 of file armv8_dpm.h.

DSCR_EXT_DCC_STALL_MODE

#define DSCR_EXT_DCC_STALL_MODE   (0x1 << 20)

Definition at line 81 of file armv8_dpm.h.

DSCR_HDE

#define DSCR_HDE   (0x1 << 14)

Definition at line 41 of file armv8_dpm.h.

DSCR_INTDIS_MASK

#define DSCR_INTDIS_MASK   (0x3 << 22)

Definition at line 46 of file armv8_dpm.h.

DSCR_ITE

#define DSCR_ITE   (0x1 << 24)

Definition at line 47 of file armv8_dpm.h.

DSCR_ITO

#define DSCR_ITO   (0x1 << 28)

Definition at line 51 of file armv8_dpm.h.

DSCR_MA

#define DSCR_MA   (0x1 << 20)

Definition at line 44 of file armv8_dpm.h.

DSCR_NON_SECURE

#define DSCR_NON_SECURE   (0x1 << 18)

Definition at line 43 of file armv8_dpm.h.

DSCR_PIPE_ADVANCE

#define DSCR_PIPE_ADVANCE   (0x1 << 25)

Definition at line 48 of file armv8_dpm.h.

DSCR_RTO

#define DSCR_RTO   (0x1 << 27) /* bit 28 is reserved */

Definition at line 50 of file armv8_dpm.h.

DSCR_SDD

#define DSCR_SDD   (0x1 << 16)

Definition at line 42 of file armv8_dpm.h.

DSCR_SYS_ERROR_PEND

#define DSCR_SYS_ERROR_PEND   (0x1 << 7)

Definition at line 38 of file armv8_dpm.h.

DSCR_TDA

#define DSCR_TDA   (0x1 << 21)

Definition at line 45 of file armv8_dpm.h.

DSCR_TXU

#define DSCR_TXU   (0x1 << 26)

Definition at line 49 of file armv8_dpm.h.

DSCRV8_ENTRY_BKPT

#define DSCRV8_ENTRY_BKPT   (0x7)

Definition at line 60 of file armv8_dpm.h.

DSCRV8_ENTRY_EXCEPTION_CATCH

#define DSCRV8_ENTRY_EXCEPTION_CATCH   (0x37)

Definition at line 69 of file armv8_dpm.h.

DSCRV8_ENTRY_EXT_DEBUG

#define DSCRV8_ENTRY_EXT_DEBUG   (0x13)

Definition at line 61 of file armv8_dpm.h.

DSCRV8_ENTRY_HALT_STEP

#define DSCRV8_ENTRY_HALT_STEP   (0x3B)

Definition at line 70 of file armv8_dpm.h.

DSCRV8_ENTRY_HALT_STEP_EXECLU

#define DSCRV8_ENTRY_HALT_STEP_EXECLU   (0x1F)

Definition at line 63 of file armv8_dpm.h.

DSCRV8_ENTRY_HALT_STEP_NORMAL

#define DSCRV8_ENTRY_HALT_STEP_NORMAL   (0x1B)

Definition at line 62 of file armv8_dpm.h.

DSCRV8_ENTRY_HLT

#define DSCRV8_ENTRY_HLT   (0x2F)

Definition at line 67 of file armv8_dpm.h.

DSCRV8_ENTRY_NON_DEBUG

#define DSCRV8_ENTRY_NON_DEBUG   (0x2)

Definition at line 58 of file armv8_dpm.h.

DSCRV8_ENTRY_OS_UNLOCK

#define DSCRV8_ENTRY_OS_UNLOCK   (0x23)

Definition at line 64 of file armv8_dpm.h.

DSCRV8_ENTRY_RESET_CATCH

#define DSCRV8_ENTRY_RESET_CATCH   (0x27)

Definition at line 65 of file armv8_dpm.h.

DSCRV8_ENTRY_RESTARTING

#define DSCRV8_ENTRY_RESTARTING   (0x1)

Definition at line 59 of file armv8_dpm.h.

DSCRV8_ENTRY_SW_ACCESS_DBG

#define DSCRV8_ENTRY_SW_ACCESS_DBG   (0x33)

Definition at line 68 of file armv8_dpm.h.

DSCRV8_ENTRY_WATCHPOINT

#define DSCRV8_ENTRY_WATCHPOINT   (0x2B)

Definition at line 66 of file armv8_dpm.h.

DSCRV8_HALT_MASK

#define DSCRV8_HALT_MASK   (0x3C)

Definition at line 71 of file armv8_dpm.h.

ECR_RCE

#define ECR_RCE   BIT(1)

Definition at line 91 of file armv8_dpm.h.

ESR_RC

#define ESR_RC   BIT(1)

Definition at line 94 of file armv8_dpm.h.

PRCR_CORENPDRQ

#define PRCR_CORENPDRQ   (1 << 0)

Definition at line 111 of file armv8_dpm.h.

PRCR_COREPURQ

#define PRCR_COREPURQ   (1 << 3)

Definition at line 113 of file armv8_dpm.h.

PRCR_CWRR

#define PRCR_CWRR   (1 << 2)

Definition at line 112 of file armv8_dpm.h.

PRSR_DLK

#define PRSR_DLK   (1 << 6)

Definition at line 103 of file armv8_dpm.h.

PRSR_EDAD

#define PRSR_EDAD   (1 << 7)

Definition at line 104 of file armv8_dpm.h.

PRSR_EPMAD

#define PRSR_EPMAD   (1 << 9)

Definition at line 106 of file armv8_dpm.h.

PRSR_HALT

#define PRSR_HALT   (1 << 4)

Definition at line 101 of file armv8_dpm.h.

PRSR_OSLK

#define PRSR_OSLK   (1 << 5)

Definition at line 102 of file armv8_dpm.h.

PRSR_PU

#define PRSR_PU   (1 << 0)

Definition at line 97 of file armv8_dpm.h.

PRSR_RESET

#define PRSR_RESET   (1 << 2)

Definition at line 99 of file armv8_dpm.h.

PRSR_SDAD

#define PRSR_SDAD   (1 << 8)

Definition at line 105 of file armv8_dpm.h.

PRSR_SDR

#define PRSR_SDR   (1 << 11)

Definition at line 108 of file armv8_dpm.h.

PRSR_SPD

#define PRSR_SPD   (1 << 1)

Definition at line 98 of file armv8_dpm.h.

PRSR_SPMAD

#define PRSR_SPMAD   (1 << 10)

Definition at line 107 of file armv8_dpm.h.

PRSR_SR

#define PRSR_SR   (1 << 3)

Definition at line 100 of file armv8_dpm.h.

Function Documentation

armv8_dpm_get_core_state()

enum arm_state armv8_dpm_get_core_state

(

struct arm_dpm *

dpm

)

Get core state from EDSCR, without necessity to retrieve CPSR.

Definition at line 1 of file armv8_dpm.c.

Referenced by aarch64_debug_entry(), aarch64_set_breakpoint(), armv8_dpm_handle_exception(), armv8_dpm_modeswitch(), and dpmv8_exec_opcode().

armv8_dpm_handle_exception()

void armv8_dpm_handle_exception	(	struct arm_dpm *	dpm,
		bool	do_restore
	)

Definition at line 1286 of file armv8_dpm.c.

References arm::arch_info, arm_dpm::arm, ARM_MODE_ANY, ARM_STATE_AARCH64, armv8_dpm_get_core_state(), armv8_dpm_modeswitch(), ARMV8_ELR_EL1, ARMV8_ELR_EL2, ARMV8_ELR_EL3, ARMV8_ESR_EL1, ARMV8_ESR_EL2, ARMV8_ESR_EL3, ARMV8_PC, armv8_select_opcodes(), armv8_select_reg_access(), ARMV8_SPSR_EL1, ARMV8_SPSR_EL2, ARMV8_SPSR_EL3, ARMV8_XPSR, arm::core_cache, CPUV8_DBG_DRCR, armv8_common::debug_ap, armv8_common::debug_base, reg::dirty, armv8_common::dpm, DRCR_CSE, arm_dpm::dscr, LOG_DEBUG, LOG_ERROR, mem_ap_write_u32(), armv8_common::read_reg_u64, reg_cache::reg_list, and SYSTEM_CUREL_EL3.

Referenced by aarch64_read_cpu_memory(), aarch64_write_cpu_memory(), armv8_dpm_modeswitch(), and dpmv8_exec_opcode().

armv8_dpm_initialize()

int armv8_dpm_initialize

(

struct arm_dpm *

dpm

)

Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affected the debug module.

Definition at line 1474 of file armv8_dpm.c.

References arm_dpm::arm, dpm_bp::bpwp, dpm_wp::bpwp, arm_dpm::bpwp_disable, arm_dpm::dbp, arm_dpm::dwp, ERROR_OK, LOG_WARNING, arm_dpm::nbp, dpm_bpwp::number, arm_dpm::nwp, arm::target, and target_name().

Referenced by aarch64_dpm_setup().

armv8_dpm_modeswitch()

int armv8_dpm_modeswitch	(	struct arm_dpm *	dpm,
		enum arm_mode	mode
	)

Definition at line 539 of file armv8_dpm.c.

References arm::arch_info, arm_dpm::arm, ARM_MODE_ABT, ARM_MODE_ANY, ARM_MODE_FIQ, ARM_MODE_IRQ, ARM_MODE_MON, ARM_MODE_SVC, ARM_MODE_SYS, ARM_MODE_USR, ARM_STATE_AARCH64, armv8_dpm_get_core_state(), armv8_dpm_handle_exception(), ARMV8_MSR_GP_XPSR_T1, ARMV8_OPC_DCPS, ARMV8_OPC_DRPS, armv8_select_opcodes(), armv8_select_reg_access(), buf_get_u32(), arm::cpsr, reg::dirty, armv8_common::dpm, ERROR_FAIL, ERROR_OK, arm_dpm::instr_execute, arm_dpm::instr_write_data_r0, arm_dpm::last_el, LOG_DEBUG, LOG_ERROR, LOG_INFO, mode, arm::pc, SYSTEM_CUREL_EL3, and reg::value.

Referenced by aarch64_mmu_modify(), aarch64_post_debug_entry(), aarch64_restore_system_control_reg(), armv8_dpm_full_context(), armv8_dpm_handle_exception(), armv8_dpm_write_dirty_registers(), armv8_identify_cache(), armv8_mmu_translate_va_pa(), and armv8_read_mpidr().

armv8_dpm_read_current_registers()

int armv8_dpm_read_current_registers

(

struct arm_dpm *

dpm

)

Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).

In normal operation this is called on entry to halting debug state, possibly after some other operations supporting restore of debug state or making sure the CPU is fully idle (drain write buffer, etc).

Definition at line 731 of file armv8_dpm.c.

References arm::arch_info, arm_dpm::arm, ARM_MODE_ANY, ARM_MODE_SYS, armv8_curel_from_core_mode(), ARMV8_FPCR, ARMV8_PC, ARMV8_R0, ARMV8_R1, armv8_reg_current(), armv8_set_cpsr(), ARMV8_SPSR_EL1, ARMV8_V0, arm::core_cache, arm::core_mode, arm::dpm, armv8_common::dpm, dpmv8_read_reg(), ERROR_OK, arm_dpm::finish, arm_dpm::instr_read_data_r0, arm_dpm::last_el, arm_reg::mode, arm_dpm::prepare, READ_REG_DSPSR, and reg_cache::reg_list.

Referenced by aarch64_debug_entry().

armv8_dpm_report_dscr()

void armv8_dpm_report_dscr	(	struct arm_dpm *	dpm,
		uint32_t	dcsr
	)

Definition at line 1342 of file armv8_dpm.c.

References arm_dpm::arm, DBG_REASON_BREAKPOINT, DBG_REASON_DBGRQ, DBG_REASON_EXC_CATCH, DBG_REASON_SINGLESTEP, DBG_REASON_UNDEFINED, DBG_REASON_WATCHPOINT, target::debug_reason, arm_dpm::dscr, DSCR_ENTRY, DSCRV8_ENTRY_BKPT, DSCRV8_ENTRY_EXCEPTION_CATCH, DSCRV8_ENTRY_EXT_DEBUG, DSCRV8_ENTRY_HALT_STEP, DSCRV8_ENTRY_HALT_STEP_EXECLU, DSCRV8_ENTRY_HALT_STEP_NORMAL, DSCRV8_ENTRY_HLT, DSCRV8_ENTRY_OS_UNLOCK, DSCRV8_ENTRY_RESET_CATCH, DSCRV8_ENTRY_SW_ACCESS_DBG, DSCRV8_ENTRY_WATCHPOINT, arm_dpm::last_el, and arm::target.

Referenced by aarch64_debug_entry().

armv8_dpm_setup()

int armv8_dpm_setup

(

struct arm_dpm *

dpm

)

This wraps an implementation of DPM primitives.

Each interface provider supplies a structure like this, which is the glue between upper level code and the lower level hardware access.

It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with support for CPU register access.

This wraps an implementation of DPM primitives.

Initially this only covers the register cache.

Oh, and watchpoints. Yeah.

Definition at line 1392 of file armv8_dpm.c.

References target_type::add_breakpoint, target_type::add_watchpoint, arm_dpm::arm, arm_dpm::arm_reg_current, armv8_build_reg_cache(), armv8_dpm_full_context(), armv8_dpm_read_core_reg(), armv8_dpm_write_core_reg(), armv8_reg_current(), arm_dpm::bpwp_disable, arm::core_cache, arm_dpm::dbp, arm_dpm::didr, arm::dpm, dpmv8_add_breakpoint(), dpmv8_add_watchpoint(), dpmv8_bpwp_disable(), dpmv8_dpm_finish(), dpmv8_dpm_prepare(), dpmv8_instr_cpsr_sync(), dpmv8_instr_execute(), dpmv8_instr_read_data_dcc(), dpmv8_instr_read_data_dcc_64(), dpmv8_instr_read_data_r0(), dpmv8_instr_read_data_r0_64(), dpmv8_instr_write_data_dcc(), dpmv8_instr_write_data_dcc_64(), dpmv8_instr_write_data_r0(), dpmv8_instr_write_data_r0_64(), dpmv8_mcr(), dpmv8_mrc(), dpmv8_remove_breakpoint(), dpmv8_remove_watchpoint(), arm_dpm::dwp, ERROR_FAIL, ERROR_OK, arm_dpm::finish, arm::full_context, arm_dpm::instr_cpsr_sync, arm_dpm::instr_execute, arm_dpm::instr_read_data_dcc, arm_dpm::instr_read_data_dcc_64, arm_dpm::instr_read_data_r0, arm_dpm::instr_read_data_r0_64, arm_dpm::instr_write_data_dcc, arm_dpm::instr_write_data_dcc_64, arm_dpm::instr_write_data_r0, arm_dpm::instr_write_data_r0_64, LOG_INFO, arm::mcr, arm::mrc, arm_dpm::nbp, arm_dpm::nwp, arm_dpm::prepare, arm::read_core_reg, target_type::remove_breakpoint, target_type::remove_watchpoint, arm::target, target_name(), target::type, and arm::write_core_reg.

Referenced by aarch64_dpm_setup().

armv8_dpm_write_dirty_registers()

int armv8_dpm_write_dirty_registers	(	struct arm_dpm *	dpm,
		bool	bpwp
	)

Writes all modified core registers for all processor modes.

In normal operation this is called on exit from halting debug state.

Parameters

dpm	represents the processor
bpwp	true ensures breakpoints and watchpoints are set, false ensures they are cleared

Definition at line 863 of file armv8_dpm.c.

References target_type::add_breakpoint, reg::arch_info, arm_dpm::arm, ARM_MODE_ANY, armv8_curel_from_core_mode(), armv8_dpm_modeswitch(), ARMV8_PC, ARMV8_XPSR, dpm_bp::bp, dpm_bp::bpwp, dpm_wp::bpwp, arm::core_cache, arm_dpm::dbp, reg::dirty, arm::dpm, dpmv8_add_breakpoint(), dpmv8_maybe_update_bpwp(), dpmv8_write_reg(), arm_dpm::dwp, ERROR_OK, reg::exist, arm_dpm::finish, arm_dpm::instr_cpsr_sync, breakpoint::is_set, watchpoint::is_set, arm_dpm::last_el, arm_reg::mode, arm_dpm::nbp, NULL, reg_cache::num_regs, arm_dpm::nwp, arm_dpm::prepare, reg_cache::reg_list, arm::target, target::type, reg::valid, and dpm_wp::wp.

Referenced by aarch64_restore_context().