18 #define CACHE_LEVEL_HAS_UNIFIED_CACHE 0x4
19 #define CACHE_LEVEL_HAS_D_CACHE 0x2
20 #define CACHE_LEVEL_HAS_I_CACHE 0x1
46 int32_t c_way, c_index =
size->index;
52 uint32_t value = (c_index <<
size->index_shift)
53 | (c_way <<
size->way_shift) | (cl << 1);
65 }
while (c_index >= 0);
86 for (cl = 0; cl < cache->
loc; cl++) {
108 uint64_t linelen = armv8_cache->
dminline;
120 va_line = va & (-linelen);
123 while (va_line < va_end) {
147 uint64_t linelen = armv8_cache->
iminline;
159 va_line = va & (-linelen);
162 while (va_line < va_end) {
186 if (armv8_cache->
info == -1) {
191 for (cl = 0; cl < armv8_cache->
loc; cl++) {
194 if (arch->
ctype & 1) {
196 "L%d I-Cache: linelen %" PRIu32
197 ", associativity %" PRIu32
199 ", cachesize %" PRIu32
" KBytes",
207 if (arch->
ctype >= 2) {
209 "L%d D-Cache: linelen %" PRIu32
210 ", associativity %" PRIu32
212 ", cachesize %" PRIu32
" KBytes",
235 LOG_ERROR(
"trying to flush un-identified cache");
263 (cl << 1) | (ct == 1 ? 1 : 0));
279 size.linelen = 16 << (cache_reg & 0x7);
280 size.associativity = ((cache_reg >> 3) & 0x3ff) + 1;
281 size.nsets = ((cache_reg >> 13) & 0x7fff) + 1;
285 size.index_shift = (cache_reg & 0x7) + 4;
286 size.index = (cache_reg >> 13) & 0x7fff;
287 size.way = ((cache_reg >> 3) & 0x3ff);
289 while (((
size.way << i) & 0x80000000) == 0)
302 uint32_t csselr, clidr, ctr;
324 cache->
iminline = 4UL << (ctr & 0xf);
325 cache->
dminline = 4UL << ((ctr & 0xf0000) >> 16);
326 LOG_DEBUG(
"ctr %" PRIx32
" ctr.iminline %" PRIu32
" ctr.dminline %" PRIu32,
335 cache->
loc = (clidr & 0x7000000) >> 24;
336 LOG_DEBUG(
"Number of cache levels to PoC %" PRId32, cache->
loc);
346 for (cl = 0; cl < cache->
loc; clidr >>= 3, cl++) {
363 LOG_DEBUG(
"data/unified cache index %" PRIu32
" << %" PRIu32
", way %" PRIu32
" << %" PRIu32,
369 LOG_DEBUG(
"cacheline %" PRIu32
" bytes %" PRIu32
" KBytes asso %" PRIu32
" ways",
383 LOG_DEBUG(
"instruction cache index %" PRIu32
" << %" PRIu32
", way %" PRIu32
" << %" PRIu32,
389 LOG_DEBUG(
"cacheline %" PRIu32
" bytes %" PRIu32
" KBytes asso %" PRIu32
" ways",
static struct armv8_common * target_to_armv8(struct target *target)
static unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
static int armv8_handle_inner_cache_info_command(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache)
int armv8_identify_cache(struct armv8_common *armv8)
int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va, size_t size)
static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t *cache_reg)
#define CACHE_LEVEL_HAS_UNIFIED_CACHE
#define CACHE_LEVEL_HAS_I_CACHE
static int _armv8_flush_all_data(struct target *target)
static int armv8_d_cache_sanity_check(struct armv8_common *armv8)
static int armv8_cache_d_inner_clean_inval_all(struct armv8_common *armv8)
static int armv8_cache_d_inner_flush_level(struct armv8_common *armv8, struct armv8_cachesize *size, int cl)
int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va, size_t size)
static int armv8_flush_all_data(struct target *target)
static int armv8_i_cache_sanity_check(struct armv8_common *armv8)
#define CACHE_LEVEL_HAS_D_CACHE
static struct armv8_cachesize decode_cache_reg(uint32_t cache_reg)
int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
void command_print(struct command_invocation *cmd, const char *format,...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
size_t size
Size of the control block search area.
#define foreach_smp_target(pos, head)
This wraps an implementation of DPM primitives.
int(* instr_write_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Runs one instruction, writing data to R0 before execution.
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
int(* instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
Represents a generic ARM core, with standard application registers.
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
struct arm_dpm * dpm
Handle for the debug module, if one is present.
struct armv8_cachesize d_u_size
struct armv8_cachesize i_size
struct armv8_arch_cache arch[6]
int(* display_cache_info)(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache)
int(* flush_all_data_cache)(struct target *target)
struct armv8_mmu_common armv8_mmu
struct armv8_cache_common armv8_cache
When run_command is called, a new instance will be created on the stack, filled with the proper value...
struct list_head * smp_targets
#define ERROR_TARGET_INVALID