20 #define JTAG_DEBUG(expr ...) do { if (1) \
21 LOG_DEBUG(expr); } while (0)
23 #define JTAG_DEBUG(expr ...) do { if (0) \
24 LOG_DEBUG(expr); } while (0)
76 void *out_data,
void *in_data,
struct scan_field *field)
85 const char *s =
"unknown";
151 LOG_ERROR(
"'arm11 target' JTAG error SCREG OUT 0x%02x", v);
245 JTAG_DEBUG(
"INST <= 0x%08x", (
unsigned) inst);
284 if (arm11->
dscr != dscr)
287 (
unsigned) arm11->
dscr);
322 (
unsigned) arm11->
dscr);
382 uint32_t *opcode,
size_t count)
407 "Timeout (1000ms) waiting for instructions to complete");
477 chain5_fields), chain5_fields,
TAP_IDLE);
481 JTAG_DEBUG(
"DTR ready %d n_retry %d", ready, n_retry);
490 "Timeout (1000ms) waiting for instructions to complete");
512 JTAG_DEBUG(
"DTR _data %08x ready %d n_retry %d",
513 (
unsigned) _data, ready, n_retry);
521 LOG_WARNING(
"Timeout (1000ms) waiting for instructions to complete");
574 unsigned readies_num =
count;
575 unsigned bytes =
sizeof(*readies)*readies_num;
577 readies = malloc(bytes);
579 LOG_ERROR(
"Out of memory allocating %u bytes", bytes);
583 uint8_t *ready_pos = readies;
585 chain5_fields[0].
out_value = (uint8_t *)(data++);
586 chain5_fields[1].
in_value = ready_pos++;
599 unsigned error_count = 0;
601 for (
size_t i = 0; i < readies_num; i++) {
606 if (error_count > 0) {
607 LOG_ERROR(
"%u words out of %u not transferred",
608 error_count, readies_num);
676 chain5_fields[1].
in_value = &ready_flag;
683 if (ready_flag != 1) {
752 chain5_fields), chain5_fields,
757 JTAG_DEBUG(
"DTR _data %08x ready %d n_retry %d",
758 (
unsigned) _data, ready, n_retry);
767 "Timeout (1000ms) waiting for instructions to complete");
867 for (
size_t i = 0; i <
count + 1; i++) {
869 n_rw = actions[i].
write ? 1 : 0;
870 data_out = actions[i].
value;
871 address_out = actions[i].
address;
882 (
unsigned) address_out,
884 n_rw ?
"write" :
"read");
902 "Timeout (1000ms) waiting for instructions to complete");
911 JTAG_DEBUG(
"SC7 => Data %08x", (
unsigned) data_in);
914 if (actions[i - 1].address != address_in)
915 LOG_WARNING(
"Scan chain 7 shifted out unexpected address");
917 if (!actions[i - 1].write)
918 actions[i - 1].
value = data_in;
920 if (actions[i - 1].value != data_in)
921 LOG_WARNING(
"Scan chain 7 shifted out unexpected data");
935 size_t clear_bw_size = arm11->
brp + 1;
939 for (
size_t i = 0; i < clear_bw_size; i++) {
940 clear_bw[i].
write =
true;
941 clear_bw[i].
value = 0;
944 for (
size_t i = 0; i < arm11->
brp; i++)
966 set_vcr.
write =
true;
1019 uint32_t opcode, uint32_t data)
1026 uint32_t opcode, uint32_t data)
1033 uint32_t opcode, uint32_t *data)
1040 uint32_t opcode, uint32_t *data)
1051 uint32_t
addr, uint32_t control)
1066 action[1].
value = control;
1094 action[0].
write =
true;
1095 action[0].
value = 0;
#define CHECK_RETVAL(action)
#define ARM11_TAP_DEFAULT
int arm11_run_instr_data_to_core1(struct arm11_common *arm11, uint32_t opcode, uint32_t data)
Execute an instruction via ITR while handing data into the core via DTR.
int arm11_run_instr_data_to_core_noack(struct arm11_common *arm11, uint32_t opcode, uint32_t *data, size_t count)
Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution.
int arm11_run_instr_data_to_core_via_r0(struct arm11_common *arm11, uint32_t opcode, uint32_t data)
Load data into core via DTR then move it to r0 then execute one instruction via ITR.
void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_field *fields, tap_state_t state)
int arm11_bpwp_flush(struct arm11_common *arm11)
Flush any pending breakpoint and watchpoint updates.
static const char * arm11_ir_to_string(uint8_t ir)
int arm11_read_memory_word(struct arm11_common *arm11, uint32_t address, uint32_t *result)
Read word from address.
int arm11_read_dscr(struct arm11_common *arm11)
Read and save the Debug Status and Control Register (DSCR).
static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap, uint32_t opcode, uint32_t *data, size_t count)
int arm11_write_dscr(struct arm11_common *arm11, uint32_t dscr)
Write the Debug Status and Control Register (DSCR)
static void arm11_add_ir_scan_vc(struct jtag_tap *tap, struct scan_field *fields, tap_state_t state)
int arm11_run_instr_data_from_core(struct arm11_common *arm11, uint32_t opcode, uint32_t *data, size_t count)
Execute one instruction via ITR repeatedly while reading data from the core via DTR on each execution...
static void arm11_add_debug_inst(struct arm11_common *arm11, uint32_t inst, uint8_t *flag, tap_state_t state)
Queue a DR scan of the ITR register.
int arm11_sc7_clear_vbw(struct arm11_common *arm11)
Clear VCR and all breakpoints and watchpoints via scan chain 7.
static const tap_state_t arm11_move_pi_to_si_via_ci[]
int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr)
Set up high-level debug module utilities.
void arm11_add_ir(struct arm11_common *arm11, uint8_t instr, tap_state_t state)
Write JTAG instruction register.
static int arm11_dpm_instr_write_data_r0(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
void arm11_setup_field(struct arm11_common *arm11, int num_bits, void *out_data, void *in_data, struct scan_field *field)
Code de-clutter: Construct struct scan_field to write out a value.
static struct arm11_common * dpm_to_arm11(struct arm_dpm *dpm)
int arm11_run_instr_data_finish(struct arm11_common *arm11)
Cleanup after ITR/DTR operations from the arm11_run_instr...
static int arm11_dpm_instr_write_data_dcc(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
int arm11_run_instr_data_prepare(struct arm11_common *arm11)
Prepare the stage for ITR/DTR operations from the arm11_run_instr...
#define JTAG_DEBUG(expr ...)
int arm11_run_instr_data_from_core_via_r0(struct arm11_common *arm11, uint32_t opcode, uint32_t *data)
Execute one instruction via ITR then load r0 into DTR and read DTR from core.
static int arm11_dpm_finish(struct arm_dpm *dpm)
int arm11_sc7_set_vcr(struct arm11_common *arm11, uint32_t value)
Write VCR register.
static void arm11_in_handler_scan_n(uint8_t *in_value)
Verify data shifted out from Scan Chain Register (SCREG).
static int arm11_dpm_instr_read_data_dcc(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
static const tap_state_t arm11_move_pd_to_sd_via_cd[]
static const tap_state_t arm11_move_drpause_idle_drpause_with_delay[]
JTAG path for arm11_run_instr_data_to_core_noack.
void arm11_dpm_deinit(struct arm11_common *arm11)
static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
int arm11_run_instr_data_to_core(struct arm11_common *arm11, uint32_t opcode, uint32_t *data, size_t count)
Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution.
static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
static int arm11_dpm_prepare(struct arm_dpm *dpm)
static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, uint32_t addr, uint32_t control)
int arm11_run_instr_no_data1(struct arm11_common *arm11, uint32_t opcode)
Execute one instruction via ITR.
int arm11_add_debug_scan_n(struct arm11_common *arm11, uint8_t chain, tap_state_t state)
Select and write to Scan Chain Register (SCREG)
int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions, size_t count)
Apply reads and writes to scan chain 7.
static int arm11_run_instr_no_data(struct arm11_common *arm11, uint32_t *opcode, size_t count)
Execute one or more instructions via ITR.
void arm_free_reg_cache(struct arm *arm)
int arm_dpm_setup(struct arm_dpm *dpm)
Hooks up this DPM to its associated target; call only once.
int arm_dpm_initialize(struct arm_dpm *dpm)
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affec...
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
void jtag_set_error(int error)
Set the current JTAG core execution error, unless one was set by a previous call previously.
void jtag_execute_queue_noclear(void)
same as jtag_execute_queue() but does not clear the error flag
void jtag_add_pathmove(int num_states, const tap_state_t *path)
Application code must assume that interfaces will implement transitions between states with different...
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
tap_state_t cmd_queue_cur_state
The current TAP state of the pending JTAG command queue.
int jtag_add_statemove(tap_state_t goal_state)
jtag_add_statemove() moves from the current state to goal_state.
void jtag_add_ir_scan(struct jtag_tap *active, struct scan_field *in_fields, tap_state_t state)
Generate an IR SCAN with a list of scan fields with one entry for each enabled TAP.
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
enum tap_state tap_state_t
Defines JTAG Test Access Port states.
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
struct arm11_sc7_action * bpwp_actions
size_t brp
Number of Breakpoint Register Pairs from DIDR
struct arm_dpm dpm
Debug module state.
uint32_t dscr
Last retrieved DSCR value.
struct arm_jtag jtag_info
Used with arm11_sc7_run to make a list of read/write commands for scan chain 7.
uint8_t address
Register address mode.
uint32_t value
If write then set this to value to be written.
bool write
Access mode: true for write, false for read.
This wraps an implementation of DPM primitives.
int(* instr_read_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from dcc after execution.
uint64_t didr
Cache of DIDR.
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
int(* bpwp_enable)(struct arm_dpm *dpm, unsigned index_value, uint32_t addr, uint32_t control)
Enables one breakpoint or watchpoint by writing to the hardware registers.
int(* instr_write_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
int(* bpwp_disable)(struct arm_dpm *dpm, unsigned index_value)
Disables one breakpoint or watchpoint by clearing its hardware control registers.
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
int(* instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
struct target * target
Backpointer to the target.
uint8_t * cur_instr
current instruction
This structure defines a single scan field in the scan.
int num_bits
The number of bits this field specifies.
uint8_t * in_value
A pointer to a 32-bit memory location for data scanned out.
const uint8_t * out_value
A pointer to value to be scanned into the device.
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
#define container_of(ptr, type, member)
Cast a member of a structure out to the containing structure.