OpenOCD
arm11_dbgtap.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2008 digenius technology GmbH. *
5  * Michael Bruck *
6  * *
7  * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
8  ***************************************************************************/
9 
10 #ifdef HAVE_CONFIG_H
11 #include "config.h"
12 #endif
13 
14 #include "arm_jtag.h"
15 #include "arm11_dbgtap.h"
16 
17 #include <helper/time_support.h>
18 
19 #if 0
20 #define JTAG_DEBUG(expr ...) do { if (1) \
21  LOG_DEBUG(expr); } while (0)
22 #else
23 #define JTAG_DEBUG(expr ...) do { if (0) \
24  LOG_DEBUG(expr); } while (0)
25 #endif
26 
27 /*
28 This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The
29 behavior of the FTDI driver IIRC was to go via RTI.
30 
31 Conversely there may be other places in this code where the ARM11 code relies
32 on the driver to hit through RTI when coming from Update-?R.
33 */
36 };
37 
38 /* REVISIT no error handling here! */
39 static void arm11_add_ir_scan_vc(struct jtag_tap *tap, struct scan_field *fields,
41 {
45 
46  jtag_add_ir_scan(tap, fields, state);
47 }
48 
51 };
52 
53 /* REVISIT no error handling here! */
54 void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_field *fields,
56 {
60 
61  jtag_add_dr_scan(tap, num_fields, fields, state);
62 }
63 
64 
75 void arm11_setup_field(struct arm11_common *arm11, int num_bits,
76  void *out_data, void *in_data, struct scan_field *field)
77 {
78  field->num_bits = num_bits;
79  field->out_value = out_data;
80  field->in_value = in_data;
81 }
82 
83 static const char *arm11_ir_to_string(uint8_t ir)
84 {
85  const char *s = "unknown";
86 
87  switch (ir) {
88  case ARM11_EXTEST:
89  s = "EXTEST";
90  break;
91  case ARM11_SCAN_N:
92  s = "SCAN_N";
93  break;
94  case ARM11_RESTART:
95  s = "RESTART";
96  break;
97  case ARM11_HALT:
98  s = "HALT";
99  break;
100  case ARM11_INTEST:
101  s = "INTEST";
102  break;
103  case ARM11_ITRSEL:
104  s = "ITRSEL";
105  break;
106  case ARM11_IDCODE:
107  s = "IDCODE";
108  break;
109  case ARM11_BYPASS:
110  s = "BYPASS";
111  break;
112  }
113  return s;
114 }
115 
124 void arm11_add_ir(struct arm11_common *arm11, uint8_t instr, tap_state_t state)
125 {
126  struct jtag_tap *tap = arm11->arm.target->tap;
127 
128  if (buf_get_u32(tap->cur_instr, 0, 5) == instr) {
129  JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
130  return;
131  }
132 
133  JTAG_DEBUG("IR <= %s (0x%02x)", arm11_ir_to_string(instr), instr);
134 
135  struct scan_field field;
136 
137  arm11_setup_field(arm11, 5, &instr, NULL, &field);
138 
140  &field,
142 }
143 
145 static void arm11_in_handler_scan_n(uint8_t *in_value)
146 {
147  /* Don't expect JTAG layer to modify bits we didn't ask it to read */
148  uint8_t v = *in_value & 0x1F;
149 
150  if (v != 0x10) {
151  LOG_ERROR("'arm11 target' JTAG error SCREG OUT 0x%02x", v);
153  }
154 }
155 
184  uint8_t chain, tap_state_t state)
185 {
186  /* Don't needlessly switch the scan chain.
187  * NOTE: the ITRSEL instruction fakes SCREG changing;
188  * but leaves its actual value unchanged.
189  */
190 #if 0
191  /* FIX!!! the optimization below is broken because we do not */
192  /* invalidate the cur_scan_chain upon a TRST/TMS. See arm_jtag.c */
193  /* for example on how to invalidate cur_scan_chain. Tested patches gladly */
194  /* accepted! */
195  if (arm11->jtag_info.cur_scan_chain == chain) {
196  JTAG_DEBUG("SCREG <= %d SKIPPED", chain);
198  ? TAP_DRPAUSE : state);
199  }
200 #endif
201  JTAG_DEBUG("SCREG <= %d", chain);
202 
204 
205  struct scan_field field;
206 
207  uint8_t tmp[1];
208  arm11_setup_field(arm11, 5, &chain, &tmp, &field);
209 
211  1,
212  &field,
214 
216 
218 
219  arm11->jtag_info.cur_scan_chain = chain;
220 
221  return jtag_execute_queue();
222 }
223 
242 static void arm11_add_debug_inst(struct arm11_common *arm11,
243  uint32_t inst, uint8_t *flag, tap_state_t state)
244 {
245  JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst);
246 
247  struct scan_field itr[2];
248 
249  arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
250  arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
251 
252  arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(itr), itr, state);
253 }
254 
265 int arm11_read_dscr(struct arm11_common *arm11)
266 {
267  int retval;
268 
269  retval = arm11_add_debug_scan_n(arm11, 0x01, ARM11_TAP_DEFAULT);
270  if (retval != ERROR_OK)
271  return retval;
272 
274 
275  uint32_t dscr;
276  struct scan_field chain1_field;
277 
278  arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
279 
280  arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &chain1_field, TAP_DRPAUSE);
281 
283 
284  if (arm11->dscr != dscr)
285  JTAG_DEBUG("DSCR = %08x (OLD %08x)",
286  (unsigned) dscr,
287  (unsigned) arm11->dscr);
288 
289  arm11->dscr = dscr;
290 
291  return ERROR_OK;
292 }
293 
303 int arm11_write_dscr(struct arm11_common *arm11, uint32_t dscr)
304 {
305  int retval;
306  retval = arm11_add_debug_scan_n(arm11, 0x01, ARM11_TAP_DEFAULT);
307  if (retval != ERROR_OK)
308  return retval;
309 
311 
312  struct scan_field chain1_field;
313 
314  arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
315 
316  arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &chain1_field, TAP_DRPAUSE);
317 
319 
320  JTAG_DEBUG("DSCR <= %08x (OLD %08x)",
321  (unsigned) dscr,
322  (unsigned) arm11->dscr);
323 
324  arm11->dscr = dscr;
325 
326  return ERROR_OK;
327 }
328 
344 {
345  return arm11_add_debug_scan_n(arm11, 0x05, ARM11_TAP_DEFAULT);
346 }
347 
363 {
364  return arm11_add_debug_scan_n(arm11, 0x00, ARM11_TAP_DEFAULT);
365 }
366 
380 static
382  uint32_t *opcode, size_t count)
383 {
385 
386  while (count--) {
387  arm11_add_debug_inst(arm11, *opcode++, NULL, TAP_IDLE);
388 
389  int i = 0;
390  while (1) {
391  uint8_t flag;
392 
394 
396 
397  if (flag)
398  break;
399 
400  int64_t then = 0;
401 
402  if (i == 1000)
403  then = timeval_ms();
404  if (i >= 1000) {
405  if ((timeval_ms()-then) > 1000) {
406  LOG_WARNING(
407  "Timeout (1000ms) waiting for instructions to complete");
408  return ERROR_FAIL;
409  }
410  }
411 
412  i++;
413  }
414  }
415 
416  return ERROR_OK;
417 }
418 
427 int arm11_run_instr_no_data1(struct arm11_common *arm11, uint32_t opcode)
428 {
429  return arm11_run_instr_no_data(arm11, &opcode, 1);
430 }
431 
432 
451  uint32_t opcode,
452  uint32_t *data,
453  size_t count)
454 {
456 
457  arm11_add_debug_inst(arm11, opcode, NULL, TAP_DRPAUSE);
458 
460 
461  struct scan_field chain5_fields[3];
462 
463  uint32_t _data;
464  uint8_t ready;
465  uint8_t n_retry;
466 
467  arm11_setup_field(arm11, 32, &_data, NULL, chain5_fields + 0);
468  arm11_setup_field(arm11, 1, NULL, &ready, chain5_fields + 1);
469  arm11_setup_field(arm11, 1, NULL, &n_retry, chain5_fields + 2);
470 
471  while (count--) {
472  int i = 0;
473  do {
474  _data = *data;
475 
477  chain5_fields), chain5_fields, TAP_IDLE);
478 
480 
481  JTAG_DEBUG("DTR ready %d n_retry %d", ready, n_retry);
482 
483  int64_t then = 0;
484 
485  if (i == 1000)
486  then = timeval_ms();
487  if (i >= 1000) {
488  if ((timeval_ms()-then) > 1000) {
489  LOG_WARNING(
490  "Timeout (1000ms) waiting for instructions to complete");
491  return ERROR_FAIL;
492  }
493  }
494 
495  i++;
496  } while (!ready);
497 
498  data++;
499  }
500 
502 
503  int i = 0;
504  do {
505  _data = 0;
506 
508  chain5_fields), chain5_fields, TAP_DRPAUSE);
509 
511 
512  JTAG_DEBUG("DTR _data %08x ready %d n_retry %d",
513  (unsigned) _data, ready, n_retry);
514 
515  int64_t then = 0;
516 
517  if (i == 1000)
518  then = timeval_ms();
519  if (i >= 1000) {
520  if ((timeval_ms()-then) > 1000) {
521  LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
522  return ERROR_FAIL;
523  }
524  }
525 
526  i++;
527  } while (!ready);
528 
529  return ERROR_OK;
530 }
531 
552 };
553 
555  uint32_t opcode,
556  uint32_t *data,
557  size_t count)
558 {
559  struct scan_field chain5_fields[3];
560 
561  chain5_fields[0].num_bits = 32;
562  chain5_fields[0].out_value = NULL; /*&Data*/
563  chain5_fields[0].in_value = NULL;
564 
565  chain5_fields[1].num_bits = 1;
566  chain5_fields[1].out_value = NULL;
567  chain5_fields[1].in_value = NULL; /*&Ready*/
568 
569  chain5_fields[2].num_bits = 1;
570  chain5_fields[2].out_value = NULL;
571  chain5_fields[2].in_value = NULL;
572 
573  uint8_t *readies;
574  unsigned readies_num = count;
575  unsigned bytes = sizeof(*readies)*readies_num;
576 
577  readies = malloc(bytes);
578  if (!readies) {
579  LOG_ERROR("Out of memory allocating %u bytes", bytes);
580  return ERROR_FAIL;
581  }
582 
583  uint8_t *ready_pos = readies;
584  while (count--) {
585  chain5_fields[0].out_value = (uint8_t *)(data++);
586  chain5_fields[1].in_value = ready_pos++;
587 
588  if (count > 0) {
589  jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields,
590  TAP_DRPAUSE);
593  } else
594  jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_IDLE);
595  }
596 
597  int retval = jtag_execute_queue();
598  if (retval == ERROR_OK) {
599  unsigned error_count = 0;
600 
601  for (size_t i = 0; i < readies_num; i++) {
602  if (readies[i] != 1)
603  error_count++;
604  }
605 
606  if (error_count > 0) {
607  LOG_ERROR("%u words out of %u not transferred",
608  error_count, readies_num);
609  retval = ERROR_FAIL;
610  }
611  }
612  free(readies);
613 
614  return retval;
615 }
616 
637  uint32_t opcode,
638  uint32_t *data,
639  size_t count)
640 {
642 
643  arm11_add_debug_inst(arm11, opcode, NULL, TAP_DRPAUSE);
644 
646 
648  opcode,
649  data,
650  count);
651 
652  if (retval != ERROR_OK)
653  return retval;
654 
656 
657  struct scan_field chain5_fields[3];
658 
659  arm11_setup_field(arm11,
660  32,
661  NULL /*&Data*/,
662  NULL,
663  chain5_fields + 0);
664  arm11_setup_field(arm11,
665  1,
666  NULL,
667  NULL /*&Ready*/,
668  chain5_fields + 1);
669  arm11_setup_field(arm11,
670  1,
671  NULL,
672  NULL,
673  chain5_fields + 2);
674 
675  uint8_t ready_flag;
676  chain5_fields[1].in_value = &ready_flag;
677 
679  chain5_fields), chain5_fields, TAP_DRPAUSE);
680 
681  retval = jtag_execute_queue();
682  if (retval == ERROR_OK) {
683  if (ready_flag != 1) {
684  LOG_ERROR("last word not transferred");
685  retval = ERROR_FAIL;
686  }
687  }
688 
689  return retval;
690 }
691 
692 
704 int arm11_run_instr_data_to_core1(struct arm11_common *arm11, uint32_t opcode, uint32_t data)
705 {
706  return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
707 }
708 
709 
728  uint32_t opcode,
729  uint32_t *data,
730  size_t count)
731 {
733 
734  arm11_add_debug_inst(arm11, opcode, NULL, TAP_IDLE);
735 
737 
738  struct scan_field chain5_fields[3];
739 
740  uint32_t _data;
741  uint8_t ready;
742  uint8_t n_retry;
743 
744  arm11_setup_field(arm11, 32, NULL, &_data, chain5_fields + 0);
745  arm11_setup_field(arm11, 1, NULL, &ready, chain5_fields + 1);
746  arm11_setup_field(arm11, 1, NULL, &n_retry, chain5_fields + 2);
747 
748  while (count--) {
749  int i = 0;
750  do {
752  chain5_fields), chain5_fields,
754 
756 
757  JTAG_DEBUG("DTR _data %08x ready %d n_retry %d",
758  (unsigned) _data, ready, n_retry);
759 
760  int64_t then = 0;
761 
762  if (i == 1000)
763  then = timeval_ms();
764  if (i >= 1000) {
765  if ((timeval_ms()-then) > 1000) {
766  LOG_WARNING(
767  "Timeout (1000ms) waiting for instructions to complete");
768  return ERROR_FAIL;
769  }
770  }
771 
772  i++;
773  } while (!ready);
774 
775  *data++ = _data;
776  }
777 
778  return ERROR_OK;
779 }
780 
794  uint32_t opcode,
795  uint32_t *data)
796 {
797  int retval;
798  retval = arm11_run_instr_no_data1(arm11, opcode);
799  if (retval != ERROR_OK)
800  return retval;
801 
802  /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
803  arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1);
804 
805  return ERROR_OK;
806 }
807 
820 int arm11_run_instr_data_to_core_via_r0(struct arm11_common *arm11, uint32_t opcode, uint32_t data)
821 {
822  int retval;
823  /* MRC p14,0,r0,c0,c5,0 */
824  retval = arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
825  if (retval != ERROR_OK)
826  return retval;
827 
828  retval = arm11_run_instr_no_data1(arm11, opcode);
829  if (retval != ERROR_OK)
830  return retval;
831 
832  return ERROR_OK;
833 }
834 
844 int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions, size_t count)
845 {
846  int retval;
847 
848  retval = arm11_add_debug_scan_n(arm11, 0x07, ARM11_TAP_DEFAULT);
849  if (retval != ERROR_OK)
850  return retval;
851 
853 
854  struct scan_field chain7_fields[3];
855 
856  uint8_t n_rw;
857  uint32_t data_out;
858  uint8_t address_out;
859  uint8_t ready;
860  uint32_t data_in;
861  uint8_t address_in;
862 
863  arm11_setup_field(arm11, 1, &n_rw, &ready, chain7_fields + 0);
864  arm11_setup_field(arm11, 32, &data_out, &data_in, chain7_fields + 1);
865  arm11_setup_field(arm11, 7, &address_out, &address_in, chain7_fields + 2);
866 
867  for (size_t i = 0; i < count + 1; i++) {
868  if (i < count) {
869  n_rw = actions[i].write ? 1 : 0;
870  data_out = actions[i].value;
871  address_out = actions[i].address;
872  } else {
873  n_rw = 1;
874  data_out = 0;
875  address_out = 0;
876  }
877 
878  /* Timeout here so we don't get stuck. */
879  int i_n = 0;
880  while (1) {
881  JTAG_DEBUG("SC7 <= c%-3d Data %08x %s",
882  (unsigned) address_out,
883  (unsigned) data_out,
884  n_rw ? "write" : "read");
885 
886  arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain7_fields),
887  chain7_fields, TAP_DRPAUSE);
888 
890 
891  /* 'n_rw' is 'ready' on read out */
892  if (ready)
893  break;
894 
895  int64_t then = 0;
896 
897  if (i_n == 1000)
898  then = timeval_ms();
899  if (i_n >= 1000) {
900  if ((timeval_ms()-then) > 1000) {
901  LOG_WARNING(
902  "Timeout (1000ms) waiting for instructions to complete");
903  return ERROR_FAIL;
904  }
905  }
906 
907  i_n++;
908  }
909 
910  if (!n_rw)
911  JTAG_DEBUG("SC7 => Data %08x", (unsigned) data_in);
912 
913  if (i > 0) {
914  if (actions[i - 1].address != address_in)
915  LOG_WARNING("Scan chain 7 shifted out unexpected address");
916 
917  if (!actions[i - 1].write)
918  actions[i - 1].value = data_in;
919  else {
920  if (actions[i - 1].value != data_in)
921  LOG_WARNING("Scan chain 7 shifted out unexpected data");
922  }
923  }
924  }
925  return ERROR_OK;
926 }
927 
934 {
935  size_t clear_bw_size = arm11->brp + 1;
936  struct arm11_sc7_action *clear_bw = malloc(sizeof(struct arm11_sc7_action) * clear_bw_size);
937  struct arm11_sc7_action *pos = clear_bw;
938 
939  for (size_t i = 0; i < clear_bw_size; i++) {
940  clear_bw[i].write = true;
941  clear_bw[i].value = 0;
942  }
943 
944  for (size_t i = 0; i < arm11->brp; i++)
945  (pos++)->address = ARM11_SC7_BCR0 + i;
946 
947  (pos++)->address = ARM11_SC7_VCR;
948 
949  int retval;
950  retval = arm11_sc7_run(arm11, clear_bw, clear_bw_size);
951 
952  free(clear_bw);
953 
954  return retval;
955 }
956 
962 int arm11_sc7_set_vcr(struct arm11_common *arm11, uint32_t value)
963 {
964  struct arm11_sc7_action set_vcr;
965 
966  set_vcr.write = true;
967  set_vcr.address = ARM11_SC7_VCR;
968  set_vcr.value = value;
969 
970  return arm11_sc7_run(arm11, &set_vcr, 1);
971 }
972 
980 int arm11_read_memory_word(struct arm11_common *arm11, uint32_t address, uint32_t *result)
981 {
982  int retval;
983  retval = arm11_run_instr_data_prepare(arm11);
984  if (retval != ERROR_OK)
985  return retval;
986 
987  /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
989 
990  /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
991  CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
992 
993  return arm11_run_instr_data_finish(arm11);
994 }
995 
996 /************************************************************************/
997 
998 /*
999  * ARM11 provider for the OpenOCD implementation of the standard
1000  * architectural ARM v6/v7 "Debug Programmer's Model" (DPM).
1001  */
1002 
1003 static inline struct arm11_common *dpm_to_arm11(struct arm_dpm *dpm)
1004 {
1005  return container_of(dpm, struct arm11_common, dpm);
1006 }
1007 
1008 static int arm11_dpm_prepare(struct arm_dpm *dpm)
1009 {
1011 }
1012 
1013 static int arm11_dpm_finish(struct arm_dpm *dpm)
1014 {
1016 }
1017 
1019  uint32_t opcode, uint32_t data)
1020 {
1022  opcode, &data, 1);
1023 }
1024 
1026  uint32_t opcode, uint32_t data)
1027 {
1029  opcode, data);
1030 }
1031 
1033  uint32_t opcode, uint32_t *data)
1034 {
1036  opcode, data, 1);
1037 }
1038 
1040  uint32_t opcode, uint32_t *data)
1041 {
1043  opcode, data);
1044 }
1045 
1046 /* Because arm11_sc7_run() takes a vector of actions, we batch breakpoint
1047  * and watchpoint operations instead of running them right away. Since we
1048  * pre-allocated our vector, we don't need to worry about space.
1049  */
1050 static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
1051  uint32_t addr, uint32_t control)
1052 {
1053  struct arm11_common *arm11 = dpm_to_arm11(dpm);
1054  struct arm11_sc7_action *action;
1055 
1056  action = arm11->bpwp_actions + arm11->bpwp_n;
1057 
1058  /* Invariant: this bp/wp is disabled.
1059  * It also happens that the core is halted here, but for
1060  * DPM-based cores we don't actually care about that.
1061  */
1062 
1063  action[0].write = action[1].write = true;
1064 
1065  action[0].value = addr;
1066  action[1].value = control;
1067 
1068  switch (index_t) {
1069  case 0 ... 15:
1070  action[0].address = ARM11_SC7_BVR0 + index_t;
1071  action[1].address = ARM11_SC7_BCR0 + index_t;
1072  break;
1073  case 16 ... 32:
1074  index_t -= 16;
1075  action[0].address = ARM11_SC7_WVR0 + index_t;
1076  action[1].address = ARM11_SC7_WCR0 + index_t;
1077  break;
1078  default:
1079  return ERROR_FAIL;
1080  }
1081 
1082  arm11->bpwp_n += 2;
1083 
1084  return ERROR_OK;
1085 }
1086 
1087 static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
1088 {
1089  struct arm11_common *arm11 = dpm_to_arm11(dpm);
1090  struct arm11_sc7_action *action;
1091 
1092  action = arm11->bpwp_actions + arm11->bpwp_n;
1093 
1094  action[0].write = true;
1095  action[0].value = 0;
1096 
1097  switch (index_t) {
1098  case 0 ... 15:
1099  action[0].address = ARM11_SC7_BCR0 + index_t;
1100  break;
1101  case 16 ... 32:
1102  index_t -= 16;
1103  action[0].address = ARM11_SC7_WCR0 + index_t;
1104  break;
1105  default:
1106  return ERROR_FAIL;
1107  }
1108 
1109  arm11->bpwp_n += 1;
1110 
1111  return ERROR_OK;
1112 }
1113 
1115 int arm11_bpwp_flush(struct arm11_common *arm11)
1116 {
1117  int retval;
1118 
1119  if (!arm11->bpwp_n)
1120  return ERROR_OK;
1121 
1122  retval = arm11_sc7_run(arm11, arm11->bpwp_actions, arm11->bpwp_n);
1123  arm11->bpwp_n = 0;
1124 
1125  return retval;
1126 }
1127 
1129 int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr)
1130 {
1131  struct arm_dpm *dpm = &arm11->dpm;
1132  int retval;
1133 
1134  dpm->arm = &arm11->arm;
1135 
1136  dpm->didr = didr;
1137 
1138  dpm->prepare = arm11_dpm_prepare;
1139  dpm->finish = arm11_dpm_finish;
1140 
1143 
1146 
1149 
1150  retval = arm_dpm_setup(dpm);
1151  if (retval != ERROR_OK)
1152  return retval;
1153 
1154  /* alloc enough to enable all breakpoints and watchpoints at once */
1155  arm11->bpwp_actions = calloc(2 * (dpm->nbp + dpm->nwp),
1156  sizeof(*arm11->bpwp_actions));
1157  if (!arm11->bpwp_actions)
1158  return ERROR_FAIL;
1159 
1160  retval = arm_dpm_initialize(dpm);
1161  if (retval != ERROR_OK)
1162  return retval;
1163 
1164  return arm11_bpwp_flush(arm11);
1165 }
1166 
1167 void arm11_dpm_deinit(struct arm11_common *arm11)
1168 {
1169  struct arm_dpm *dpm = &arm11->dpm;
1170 
1171  free(arm11->bpwp_actions);
1172  arm_free_reg_cache(dpm->arm);
1173  free(dpm->dbp);
1174  free(dpm->dwp);
1175 }
#define CHECK_RETVAL(action)
Definition: arc.h:246
#define ARM11_TAP_DEFAULT
Definition: arm11.h:16
@ ARM11_SC7_WCR0
Definition: arm11.h:100
@ ARM11_SC7_BVR0
Definition: arm11.h:97
@ ARM11_SC7_WVR0
Definition: arm11.h:99
@ ARM11_SC7_BCR0
Definition: arm11.h:98
@ ARM11_SC7_VCR
Definition: arm11.h:95
@ ARM11_RESTART
Definition: arm11.h:85
@ ARM11_SCAN_N
Definition: arm11.h:84
@ ARM11_INTEST
Definition: arm11.h:87
@ ARM11_ITRSEL
Definition: arm11.h:88
@ ARM11_BYPASS
Definition: arm11.h:90
@ ARM11_IDCODE
Definition: arm11.h:89
@ ARM11_EXTEST
Definition: arm11.h:83
@ ARM11_HALT
Definition: arm11.h:86
int arm11_run_instr_data_to_core1(struct arm11_common *arm11, uint32_t opcode, uint32_t data)
Execute an instruction via ITR while handing data into the core via DTR.
Definition: arm11_dbgtap.c:704
int arm11_run_instr_data_to_core_noack(struct arm11_common *arm11, uint32_t opcode, uint32_t *data, size_t count)
Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution.
Definition: arm11_dbgtap.c:636
int arm11_run_instr_data_to_core_via_r0(struct arm11_common *arm11, uint32_t opcode, uint32_t data)
Load data into core via DTR then move it to r0 then execute one instruction via ITR.
Definition: arm11_dbgtap.c:820
void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_field *fields, tap_state_t state)
Definition: arm11_dbgtap.c:54
int arm11_bpwp_flush(struct arm11_common *arm11)
Flush any pending breakpoint and watchpoint updates.
static const char * arm11_ir_to_string(uint8_t ir)
Definition: arm11_dbgtap.c:83
int arm11_read_memory_word(struct arm11_common *arm11, uint32_t address, uint32_t *result)
Read word from address.
Definition: arm11_dbgtap.c:980
int arm11_read_dscr(struct arm11_common *arm11)
Read and save the Debug Status and Control Register (DSCR).
Definition: arm11_dbgtap.c:265
static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap, uint32_t opcode, uint32_t *data, size_t count)
Definition: arm11_dbgtap.c:554
int arm11_write_dscr(struct arm11_common *arm11, uint32_t dscr)
Write the Debug Status and Control Register (DSCR)
Definition: arm11_dbgtap.c:303
static void arm11_add_ir_scan_vc(struct jtag_tap *tap, struct scan_field *fields, tap_state_t state)
Definition: arm11_dbgtap.c:39
int arm11_run_instr_data_from_core(struct arm11_common *arm11, uint32_t opcode, uint32_t *data, size_t count)
Execute one instruction via ITR repeatedly while reading data from the core via DTR on each execution...
Definition: arm11_dbgtap.c:727
static void arm11_add_debug_inst(struct arm11_common *arm11, uint32_t inst, uint8_t *flag, tap_state_t state)
Queue a DR scan of the ITR register.
Definition: arm11_dbgtap.c:242
int arm11_sc7_clear_vbw(struct arm11_common *arm11)
Clear VCR and all breakpoints and watchpoints via scan chain 7.
Definition: arm11_dbgtap.c:933
static const tap_state_t arm11_move_pi_to_si_via_ci[]
Definition: arm11_dbgtap.c:34
int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr)
Set up high-level debug module utilities.
void arm11_add_ir(struct arm11_common *arm11, uint8_t instr, tap_state_t state)
Write JTAG instruction register.
Definition: arm11_dbgtap.c:124
static int arm11_dpm_instr_write_data_r0(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
void arm11_setup_field(struct arm11_common *arm11, int num_bits, void *out_data, void *in_data, struct scan_field *field)
Code de-clutter: Construct struct scan_field to write out a value.
Definition: arm11_dbgtap.c:75
static struct arm11_common * dpm_to_arm11(struct arm_dpm *dpm)
int arm11_run_instr_data_finish(struct arm11_common *arm11)
Cleanup after ITR/DTR operations from the arm11_run_instr...
Definition: arm11_dbgtap.c:362
static int arm11_dpm_instr_write_data_dcc(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
int arm11_run_instr_data_prepare(struct arm11_common *arm11)
Prepare the stage for ITR/DTR operations from the arm11_run_instr...
Definition: arm11_dbgtap.c:343
#define JTAG_DEBUG(expr ...)
Definition: arm11_dbgtap.c:23
int arm11_run_instr_data_from_core_via_r0(struct arm11_common *arm11, uint32_t opcode, uint32_t *data)
Execute one instruction via ITR then load r0 into DTR and read DTR from core.
Definition: arm11_dbgtap.c:793
static int arm11_dpm_finish(struct arm_dpm *dpm)
int arm11_sc7_set_vcr(struct arm11_common *arm11, uint32_t value)
Write VCR register.
Definition: arm11_dbgtap.c:962
static void arm11_in_handler_scan_n(uint8_t *in_value)
Verify data shifted out from Scan Chain Register (SCREG).
Definition: arm11_dbgtap.c:145
static int arm11_dpm_instr_read_data_dcc(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
static const tap_state_t arm11_move_pd_to_sd_via_cd[]
Definition: arm11_dbgtap.c:49
static const tap_state_t arm11_move_drpause_idle_drpause_with_delay[]
JTAG path for arm11_run_instr_data_to_core_noack.
Definition: arm11_dbgtap.c:549
void arm11_dpm_deinit(struct arm11_common *arm11)
static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
int arm11_run_instr_data_to_core(struct arm11_common *arm11, uint32_t opcode, uint32_t *data, size_t count)
Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution.
Definition: arm11_dbgtap.c:450
static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
static int arm11_dpm_prepare(struct arm_dpm *dpm)
static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, uint32_t addr, uint32_t control)
int arm11_run_instr_no_data1(struct arm11_common *arm11, uint32_t opcode)
Execute one instruction via ITR.
Definition: arm11_dbgtap.c:427
int arm11_add_debug_scan_n(struct arm11_common *arm11, uint8_t chain, tap_state_t state)
Select and write to Scan Chain Register (SCREG)
Definition: arm11_dbgtap.c:183
int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions, size_t count)
Apply reads and writes to scan chain 7.
Definition: arm11_dbgtap.c:844
static int arm11_run_instr_no_data(struct arm11_common *arm11, uint32_t *opcode, size_t count)
Execute one or more instructions via ITR.
Definition: arm11_dbgtap.c:381
void arm_free_reg_cache(struct arm *arm)
Definition: armv4_5.c:761
int arm_dpm_setup(struct arm_dpm *dpm)
Hooks up this DPM to its associated target; call only once.
Definition: arm_dpm.c:1049
int arm_dpm_initialize(struct arm_dpm *dpm)
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affec...
Definition: arm_dpm.c:1114
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:98
void jtag_set_error(int error)
Set the current JTAG core execution error, unless one was set by a previous call previously.
Definition: jtag/core.c:123
void jtag_execute_queue_noclear(void)
same as jtag_execute_queue() but does not clear the error flag
Definition: jtag/core.c:1018
void jtag_add_pathmove(int num_states, const tap_state_t *path)
Application code must assume that interfaces will implement transitions between states with different...
Definition: jtag/core.c:517
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
Definition: jtag/core.c:1037
tap_state_t cmd_queue_cur_state
The current TAP state of the pending JTAG command queue.
Definition: jtag/core.c:88
int jtag_add_statemove(tap_state_t goal_state)
jtag_add_statemove() moves from the current state to goal_state.
Definition: jtag/core.c:551
void jtag_add_ir_scan(struct jtag_tap *active, struct scan_field *in_fields, tap_state_t state)
Generate an IR SCAN with a list of scan fields with one entry for each enabled TAP.
Definition: jtag/core.c:374
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
Definition: jtag/core.c:451
@ TAP_IRCAPTURE
Definition: jtag.h:54
@ TAP_DRCAPTURE
Definition: jtag.h:46
@ TAP_DRSELECT
Definition: jtag.h:47
@ TAP_DRPAUSE
Definition: jtag.h:43
@ TAP_IRSELECT
Definition: jtag.h:44
@ TAP_IRUPDATE
Definition: jtag.h:53
@ TAP_IREXIT2
Definition: jtag.h:48
@ TAP_IRSHIFT
Definition: jtag.h:50
@ TAP_DREXIT2
Definition: jtag.h:40
@ TAP_IDLE
Definition: jtag.h:52
@ TAP_DRSHIFT
Definition: jtag.h:42
@ TAP_IRPAUSE
Definition: jtag.h:51
@ TAP_DRUPDATE
Definition: jtag.h:45
enum tap_state tap_state_t
Defines JTAG Test Access Port states.
#define LOG_WARNING(expr ...)
Definition: log.h:120
#define ERROR_FAIL
Definition: log.h:161
#define LOG_ERROR(expr ...)
Definition: log.h:123
#define ERROR_OK
Definition: log.h:155
int flag
Definition: mips32.c:41
uint32_t addr
Definition: nuttx.c:65
unsigned bpwp_n
Definition: arm11.h:42
struct arm11_sc7_action * bpwp_actions
Definition: arm11.h:41
size_t brp
Number of Breakpoint Register Pairs from DIDR
Definition: arm11.h:44
struct arm_dpm dpm
Debug module state.
Definition: arm11.h:40
struct arm arm
Definition: arm11.h:37
uint32_t dscr
Last retrieved DSCR value.
Definition: arm11.h:47
struct arm_jtag jtag_info
Definition: arm11.h:69
Used with arm11_sc7_run to make a list of read/write commands for scan chain 7.
Definition: arm11_dbgtap.h:49
uint8_t address
Register address mode.
Definition: arm11_dbgtap.h:51
uint32_t value
If write then set this to value to be written.
Definition: arm11_dbgtap.h:56
bool write
Access mode: true for write, false for read.
Definition: arm11_dbgtap.h:50
This wraps an implementation of DPM primitives.
Definition: arm_dpm.h:47
int(* instr_read_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from dcc after execution.
Definition: arm_dpm.h:85
uint64_t didr
Cache of DIDR.
Definition: arm_dpm.h:51
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
Definition: arm_dpm.h:72
struct arm * arm
Definition: arm_dpm.h:48
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
Definition: arm_dpm.h:57
int(* bpwp_enable)(struct arm_dpm *dpm, unsigned index_value, uint32_t addr, uint32_t control)
Enables one breakpoint or watchpoint by writing to the hardware registers.
Definition: arm_dpm.h:109
struct dpm_bp * dbp
Definition: arm_dpm.h:126
int(* instr_write_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
Definition: arm_dpm.h:65
int(* bpwp_disable)(struct arm_dpm *dpm, unsigned index_value)
Disables one breakpoint or watchpoint by clearing its hardware control registers.
Definition: arm_dpm.h:117
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
Definition: arm_dpm.h:54
int(* instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
Definition: arm_dpm.h:92
unsigned nbp
Definition: arm_dpm.h:124
unsigned nwp
Definition: arm_dpm.h:125
struct dpm_wp * dwp
Definition: arm_dpm.h:127
uint32_t cur_scan_chain
Definition: arm_jtag.h:22
struct target * target
Backpointer to the target.
Definition: arm.h:202
Definition: jtag.h:100
uint8_t * cur_instr
current instruction
Definition: jtag.h:131
This structure defines a single scan field in the scan.
Definition: jtag.h:86
int num_bits
The number of bits this field specifies.
Definition: jtag.h:88
uint8_t * in_value
A pointer to a 32-bit memory location for data scanned out.
Definition: jtag.h:92
const uint8_t * out_value
A pointer to value to be scanned into the device.
Definition: jtag.h:90
struct jtag_tap * tap
Definition: target.h:124
int64_t timeval_ms(void)
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57
#define container_of(ptr, type, member)
Cast a member of a structure out to the containing structure.
Definition: types.h:68
#define NULL
Definition: usb.h:16
uint8_t state[4]
Definition: vdebug.c:21
uint8_t count[4]
Definition: vdebug.c:22