Include dependency graph for arm11_dbgtap.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	arm11_sc7_action
	Used with arm11_sc7_run to make a list of read/write commands for scan chain 7. More...

Functions
int	arm11_add_debug_scan_n (struct arm11_common *arm11, uint8_t chain, tap_state_t state)
	Select and write to Scan Chain Register (SCREG) More...

void	arm11_add_dr_scan_vc (struct jtag_tap tap, int num_fields, struct scan_field fields, tap_state_t state)

void	arm11_add_ir (struct arm11_common *arm11, uint8_t instr, tap_state_t state)
	Write JTAG instruction register. More...

int	arm11_bpwp_flush (struct arm11_common *arm11)
	Flush any pending breakpoint and watchpoint updates. More...

void	arm11_dpm_deinit (struct arm11_common *arm11)

int	arm11_dpm_init (struct arm11_common *arm11, uint32_t didr)
	Set up high-level debug module utilities. More...

int	arm11_read_dscr (struct arm11_common *arm11)
	Read and save the Debug Status and Control Register (DSCR). More...

int	arm11_read_memory_word (struct arm11_common arm11, uint32_t address, uint32_t result)
	Read word from address. More...

int	arm11_run_instr_data_finish (struct arm11_common *arm11)
	Cleanup after ITR/DTR operations from the arm11_run_instr... More...

int	arm11_run_instr_data_from_core (struct arm11_common arm11, uint32_t opcode, uint32_t data, size_t count)
	Execute one instruction via ITR repeatedly while reading data from the core via DTR on each execution. More...

int	arm11_run_instr_data_from_core_via_r0 (struct arm11_common arm11, uint32_t opcode, uint32_t data)
	Execute one instruction via ITR then load r0 into DTR and read DTR from core. More...

int	arm11_run_instr_data_prepare (struct arm11_common *arm11)
	Prepare the stage for ITR/DTR operations from the arm11_run_instr... More...

int	arm11_run_instr_data_to_core (struct arm11_common arm11, uint32_t opcode, uint32_t data, size_t count)
	Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution. More...

int	arm11_run_instr_data_to_core1 (struct arm11_common *arm11, uint32_t opcode, uint32_t data)
	Execute an instruction via ITR while handing data into the core via DTR. More...

int	arm11_run_instr_data_to_core_noack (struct arm11_common arm11, uint32_t opcode, uint32_t data, size_t count)
	Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution. More...

int	arm11_run_instr_data_to_core_via_r0 (struct arm11_common *arm11, uint32_t opcode, uint32_t data)
	Load data into core via DTR then move it to r0 then execute one instruction via ITR. More...

int	arm11_run_instr_no_data1 (struct arm11_common *arm11, uint32_t opcode)
	Execute one instruction via ITR. More...

int	arm11_sc7_clear_vbw (struct arm11_common *arm11)
	Clear VCR and all breakpoints and watchpoints via scan chain 7. More...

int	arm11_sc7_run (struct arm11_common arm11, struct arm11_sc7_action actions, size_t count)
	Apply reads and writes to scan chain 7. More...

int	arm11_sc7_set_vcr (struct arm11_common *arm11, uint32_t value)
	Write VCR register. More...

void	arm11_setup_field (struct arm11_common arm11, int num_bits, void in_data, void out_data, struct scan_field field)
	Code de-clutter: Construct struct scan_field to write out a value. More...

int	arm11_write_dscr (struct arm11_common *arm11, uint32_t dscr)
	Write the Debug Status and Control Register (DSCR) More...

Function Documentation

◆ arm11_add_debug_scan_n()

int arm11_add_debug_scan_n	(	struct arm11_common *	arm11,
		uint8_t	chain,
		tap_state_t	state
	)

Select and write to Scan Chain Register (SCREG)

This function sets the instruction register to SCAN_N and writes the data register with the selected chain number.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html

Parameters

arm11	Target state variable.
chain	Scan chain that will be selected.
state	Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-DR).

Changes the current scan chain if needed, transitions to the specified TAP state, and leaves the IR undefined.

The chain takes effect when Update-DR is passed (usually when subsequently the INTEXT/EXTEST instructions are written).

Warning: (Obsolete) Using this twice in a row will fail. The first call will end in Pause-DR. The second call, due to the IR caching, will not go through Capture-DR when shifting in the new scan chain number. As a result the verification in arm11_in_handler_scan_n() must fail.

Remarks: This adds to the JTAG command queue but does not execute it.

Definition at line 183 of file arm11_dbgtap.c.

References arm11_common::arm, arm11_add_dr_scan_vc(), arm11_add_ir(), arm11_in_handler_scan_n(), ARM11_SCAN_N, arm11_setup_field(), ARM11_TAP_DEFAULT, arm_jtag::cur_scan_chain, jtag_add_statemove(), JTAG_DEBUG, jtag_execute_queue(), jtag_execute_queue_noclear(), arm11_common::jtag_info, state, target::tap, TAP_DRPAUSE, and arm::target.

Referenced by arm11_debug_entry(), arm11_examine(), arm11_leave_debug_state(), arm11_read_dscr(), arm11_run_instr_data_finish(), arm11_run_instr_data_prepare(), arm11_sc7_run(), and arm11_write_dscr().

◆ arm11_add_dr_scan_vc()

void arm11_add_dr_scan_vc	(	struct jtag_tap *	tap,
		int	num_fields,
		struct scan_field *	fields,
		tap_state_t	state
	)

Definition at line 54 of file arm11_dbgtap.c.

References arm11_move_pd_to_sd_via_cd, ARRAY_SIZE, cmd_queue_cur_state, jtag_add_dr_scan(), jtag_add_pathmove(), state, and TAP_DRPAUSE.

Referenced by arm11_add_debug_inst(), arm11_add_debug_scan_n(), arm11_debug_entry(), arm11_examine(), arm11_leave_debug_state(), arm11_read_dscr(), arm11_run_instr_data_from_core(), arm11_run_instr_data_to_core(), arm11_run_instr_data_to_core_noack(), arm11_sc7_run(), and arm11_write_dscr().

◆ arm11_add_ir()

void arm11_add_ir	(	struct arm11_common *	arm11,
		uint8_t	instr,
		tap_state_t	state
	)

Write JTAG instruction register.

Parameters

arm11	Target state variable.
instr	An ARM11 DBGTAP instruction. Use enum arm11_instructions.
state	Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-IR).

Remarks: This adds to the JTAG command queue but does not execute it.

Definition at line 124 of file arm11_dbgtap.c.

References arm11_common::arm, arm11_add_ir_scan_vc(), arm11_ir_to_string(), arm11_setup_field(), ARM11_TAP_DEFAULT, buf_get_u32(), jtag_tap::cur_instr, JTAG_DEBUG, NULL, state, target::tap, TAP_IRPAUSE, and arm::target.

Referenced by arm11_add_debug_scan_n(), arm11_debug_entry(), arm11_examine(), arm11_halt(), arm11_leave_debug_state(), arm11_read_dscr(), arm11_resume(), arm11_run_instr_data_from_core(), arm11_run_instr_data_to_core(), arm11_run_instr_data_to_core_noack(), arm11_run_instr_no_data(), arm11_sc7_run(), arm11_step(), and arm11_write_dscr().

◆ arm11_bpwp_flush()

int arm11_bpwp_flush ( struct arm11_common * arm11 )

Flush any pending breakpoint and watchpoint updates.

Definition at line 1115 of file arm11_dbgtap.c.

References arm11_sc7_run(), arm11_common::bpwp_actions, arm11_common::bpwp_n, and ERROR_OK.

Referenced by arm11_dpm_init(), and arm11_leave_debug_state().

◆ arm11_dpm_deinit()

void arm11_dpm_deinit ( struct arm11_common * arm11 )

Definition at line 1167 of file arm11_dbgtap.c.

References arm_dpm::arm, arm_free_reg_cache(), arm11_common::bpwp_actions, arm_dpm::dbp, arm11_common::dpm, and arm_dpm::dwp.

Referenced by arm11_deinit_target().

◆ arm11_dpm_init()

int arm11_dpm_init	(	struct arm11_common *	arm11,
		uint32_t	didr
	)

Set up high-level debug module utilities.

Definition at line 1129 of file arm11_dbgtap.c.

References arm11_common::arm, arm_dpm::arm, arm11_bpwp_disable(), arm11_bpwp_enable(), arm11_bpwp_flush(), arm11_dpm_finish(), arm11_dpm_instr_read_data_dcc(), arm11_dpm_instr_read_data_r0(), arm11_dpm_instr_write_data_dcc(), arm11_dpm_instr_write_data_r0(), arm11_dpm_prepare(), arm_dpm_initialize(), arm_dpm_setup(), arm11_common::bpwp_actions, arm_dpm::bpwp_disable, arm_dpm::bpwp_enable, arm_dpm::didr, arm11_common::dpm, ERROR_FAIL, ERROR_OK, arm_dpm::finish, arm_dpm::instr_read_data_dcc, arm_dpm::instr_read_data_r0, arm_dpm::instr_write_data_dcc, arm_dpm::instr_write_data_r0, arm_dpm::nbp, arm_dpm::nwp, and arm_dpm::prepare.

Referenced by arm11_examine().

◆ arm11_read_dscr()

int arm11_read_dscr ( struct arm11_common * arm11 )

Read and save the Debug Status and Control Register (DSCR).

Parameters

arm11 Target state variable.

Returns: Error status; arm11->dscr is updated on success.

Remarks: This is a stand-alone function that executes the JTAG command queue. It does not require the ARM11 debug TAP to be in any particular state.

Definition at line 265 of file arm11_dbgtap.c.

References arm11_common::arm, arm11_add_debug_scan_n(), arm11_add_dr_scan_vc(), arm11_add_ir(), ARM11_INTEST, arm11_setup_field(), ARM11_TAP_DEFAULT, CHECK_RETVAL, arm11_common::dscr, ERROR_OK, JTAG_DEBUG, jtag_execute_queue(), NULL, target::tap, TAP_DRPAUSE, and arm::target.

Referenced by arm11_check_init(), arm11_debug_entry(), arm11_halt(), arm11_leave_debug_state(), arm11_resume(), and arm11_step().

◆ arm11_read_memory_word()

int arm11_read_memory_word	(	struct arm11_common *	arm11,
		uint32_t	address,
		uint32_t *	result
	)

Read word from address.

Parameters

arm11	Target state variable.
address	Memory address to be read
result	Pointer where to store result

Definition at line 980 of file arm11_dbgtap.c.

References arm11_sc7_action::address, arm11_run_instr_data_finish(), arm11_run_instr_data_from_core(), arm11_run_instr_data_prepare(), arm11_run_instr_data_to_core1(), CHECK_RETVAL, and ERROR_OK.

Referenced by arm11_step().

◆ arm11_run_instr_data_finish()

int arm11_run_instr_data_finish ( struct arm11_common * arm11 )

Cleanup after ITR/DTR operations from the arm11_run_instr...

group of functions

Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish() around a block of arm11_run_instr_... calls.

Any IDLE can lead to an instruction execution when scan chains 4 or 5 are selected and the IR holds INTEST or EXTEST. So we must disable that before any following activities lead to an IDLE.

Parameters

arm11 Target state variable.

Definition at line 362 of file arm11_dbgtap.c.

References arm11_add_debug_scan_n(), and ARM11_TAP_DEFAULT.

Referenced by arm11_debug_entry(), arm11_dpm_finish(), arm11_leave_debug_state(), arm11_read_memory_inner(), arm11_read_memory_word(), and arm11_write_memory_inner().

◆ arm11_run_instr_data_from_core()

int arm11_run_instr_data_from_core	(	struct arm11_common *	arm11,
		uint32_t	opcode,
		uint32_t *	data,
		size_t	count
	)

Execute one instruction via ITR repeatedly while reading data from the core via DTR on each execution.

Caller guarantees that processor is in debug state, that DSCR_ITR_EN is set, the ITR Ready flag is set (as seen on the previous entry to TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.

The executed instruction must write data to DTR.

Precondition: arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Parameters

arm11	Target state variable.
opcode	ARM opcode
data	Pointer to an array that receives the data words from the core
count	Number of data words and instruction repetitions

Definition at line 727 of file arm11_dbgtap.c.

References arm11_common::arm, arm11_add_debug_inst(), arm11_add_dr_scan_vc(), arm11_add_ir(), ARM11_INTEST, ARM11_ITRSEL, arm11_setup_field(), ARM11_TAP_DEFAULT, ARRAY_SIZE, CHECK_RETVAL, count, ERROR_FAIL, ERROR_OK, JTAG_DEBUG, jtag_execute_queue(), LOG_WARNING, NULL, target::tap, TAP_DRPAUSE, TAP_IDLE, arm::target, and timeval_ms().

Referenced by arm11_dpm_instr_read_data_dcc(), arm11_read_memory_inner(), arm11_read_memory_word(), arm11_run_instr_data_from_core_via_r0(), and arm11_write_memory_inner().

◆ arm11_run_instr_data_from_core_via_r0()

int arm11_run_instr_data_from_core_via_r0	(	struct arm11_common *	arm11,
		uint32_t	opcode,
		uint32_t *	data
	)

Execute one instruction via ITR then load r0 into DTR and read DTR from core.

The first executed instruction (opcode) should write data to r0.

Precondition: arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Parameters

arm11	Target state variable.
opcode	ARM opcode to write r0 with the value of interest
data	Pointer to a data word that receives the value from r0 after `opcode` was executed.

Definition at line 793 of file arm11_dbgtap.c.

References arm11_run_instr_data_from_core(), arm11_run_instr_no_data1(), and ERROR_OK.

Referenced by arm11_debug_entry(), and arm11_dpm_instr_read_data_r0().

◆ arm11_run_instr_data_prepare()

int arm11_run_instr_data_prepare ( struct arm11_common * arm11 )

Prepare the stage for ITR/DTR operations from the arm11_run_instr...

group of functions.

Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish() around a block of arm11_run_instr_... calls.

Select scan chain 5 to allow quick access to DTR. When scan chain 4 is needed to put in a register the ITRSel instruction shortcut is used instead of actually changing the Scan_N register.

Parameters

arm11 Target state variable.

Definition at line 343 of file arm11_dbgtap.c.

References arm11_add_debug_scan_n(), and ARM11_TAP_DEFAULT.

Referenced by arm11_debug_entry(), arm11_dpm_prepare(), arm11_leave_debug_state(), arm11_read_memory_inner(), arm11_read_memory_word(), and arm11_write_memory_inner().

◆ arm11_run_instr_data_to_core()

int arm11_run_instr_data_to_core	(	struct arm11_common *	arm11,
		uint32_t	opcode,
		uint32_t *	data,
		size_t	count
	)

Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution.

Caller guarantees that processor is in debug state, that DSCR_ITR_EN is set, the ITR Ready flag is set (as seen on the previous entry to TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.

The executed instruction must read data from DTR.

Precondition: arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Parameters

arm11	Target state variable.
opcode	ARM opcode
data	Pointer to the data words to be passed to the core
count	Number of data words and instruction repetitions

Definition at line 450 of file arm11_dbgtap.c.

References arm11_common::arm, arm11_add_debug_inst(), arm11_add_dr_scan_vc(), arm11_add_ir(), ARM11_EXTEST, ARM11_INTEST, ARM11_ITRSEL, arm11_setup_field(), ARM11_TAP_DEFAULT, ARRAY_SIZE, CHECK_RETVAL, count, ERROR_FAIL, ERROR_OK, JTAG_DEBUG, jtag_execute_queue(), LOG_WARNING, NULL, target::tap, TAP_DRPAUSE, TAP_IDLE, arm::target, and timeval_ms().

Referenced by arm11_dpm_instr_write_data_dcc(), arm11_run_instr_data_to_core1(), and arm11_write_memory_inner().

◆ arm11_run_instr_data_to_core1()

int arm11_run_instr_data_to_core1	(	struct arm11_common *	arm11,
		uint32_t	opcode,
		uint32_t	data
	)

Execute an instruction via ITR while handing data into the core via DTR.

The executed instruction must read data from DTR.

Precondition: arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Parameters

arm11	Target state variable.
opcode	ARM opcode
data	Data word to be passed to the core via DTR

Definition at line 704 of file arm11_dbgtap.c.

References arm11_run_instr_data_to_core().

Referenced by arm11_read_memory_inner(), arm11_read_memory_word(), arm11_run_instr_data_to_core_via_r0(), and arm11_write_memory_inner().

◆ arm11_run_instr_data_to_core_noack()

int arm11_run_instr_data_to_core_noack	(	struct arm11_common *	arm11,
		uint32_t	opcode,
		uint32_t *	data,
		size_t	count
	)

Execute one instruction via ITR repeatedly while passing data to the core via DTR on each execution.

Caller guarantees that processor is in debug state, that DSCR_ITR_EN is set, the ITR Ready flag is set (as seen on the previous entry to TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.

No Ready check during transmission.

The executed instruction must read data from DTR.

Precondition: arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Parameters

arm11	Target state variable.
opcode	ARM opcode
data	Pointer to the data words to be passed to the core
count	Number of data words and instruction repetitions

Definition at line 636 of file arm11_dbgtap.c.

References arm11_common::arm, arm11_add_debug_inst(), arm11_add_dr_scan_vc(), arm11_add_ir(), ARM11_EXTEST, ARM11_INTEST, ARM11_ITRSEL, arm11_run_instr_data_to_core_noack_inner(), arm11_setup_field(), ARM11_TAP_DEFAULT, ARRAY_SIZE, count, ERROR_FAIL, ERROR_OK, scan_field::in_value, jtag_execute_queue(), LOG_ERROR, NULL, target::tap, TAP_DRPAUSE, and arm::target.

Referenced by arm11_write_memory_inner().

◆ arm11_run_instr_data_to_core_via_r0()

int arm11_run_instr_data_to_core_via_r0	(	struct arm11_common *	arm11,
		uint32_t	opcode,
		uint32_t	data
	)

Load data into core via DTR then move it to r0 then execute one instruction via ITR.

The final executed instruction (opcode) should read data from r0.

Precondition: arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Parameters

arm11	Target state variable.
opcode	ARM opcode to read r0 act upon it
data	Data word that will be written to r0 before `opcode` is executed

Definition at line 820 of file arm11_dbgtap.c.

References arm11_run_instr_data_to_core1(), arm11_run_instr_no_data1(), and ERROR_OK.

Referenced by arm11_debug_entry(), arm11_dpm_instr_write_data_r0(), and arm11_leave_debug_state().

◆ arm11_run_instr_no_data1()

int arm11_run_instr_no_data1	(	struct arm11_common *	arm11,
		uint32_t	opcode
	)

Execute one instruction via ITR.

Precondition: arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block

Parameters

arm11	Target state variable.
opcode	ARM opcode

Definition at line 427 of file arm11_dbgtap.c.

References arm11_run_instr_no_data().

Referenced by arm11_debug_entry(), arm11_read_memory_inner(), arm11_run_instr_data_from_core_via_r0(), arm11_run_instr_data_to_core_via_r0(), and arm11_write_memory_inner().

◆ arm11_sc7_clear_vbw()

int arm11_sc7_clear_vbw ( struct arm11_common * arm11 )

Clear VCR and all breakpoints and watchpoints via scan chain 7.

Parameters

arm11 Target state variable.

Definition at line 933 of file arm11_dbgtap.c.

References arm11_sc7_action::address, ARM11_SC7_BCR0, arm11_sc7_run(), ARM11_SC7_VCR, arm11_common::brp, arm11_sc7_action::value, and arm11_sc7_action::write.

Referenced by arm11_check_init(), arm11_resume(), and arm11_step().

◆ arm11_sc7_run()

int arm11_sc7_run	(	struct arm11_common *	arm11,
		struct arm11_sc7_action *	actions,
		size_t	count
	)

Apply reads and writes to scan chain 7.

See also: struct arm11_sc7_action

Parameters

arm11	Target state variable.
actions	A list of read and/or write instructions
count	Number of instructions in the list.

Definition at line 844 of file arm11_dbgtap.c.

References arm11_sc7_action::address, arm11_common::arm, arm11_add_debug_scan_n(), arm11_add_dr_scan_vc(), arm11_add_ir(), ARM11_EXTEST, arm11_setup_field(), ARM11_TAP_DEFAULT, ARRAY_SIZE, CHECK_RETVAL, count, ERROR_FAIL, ERROR_OK, JTAG_DEBUG, jtag_execute_queue(), LOG_WARNING, target::tap, TAP_DRPAUSE, arm::target, timeval_ms(), arm11_sc7_action::value, and arm11_sc7_action::write.

Referenced by arm11_bpwp_flush(), arm11_resume(), arm11_sc7_clear_vbw(), arm11_sc7_set_vcr(), and arm11_step().

◆ arm11_sc7_set_vcr()

int arm11_sc7_set_vcr	(	struct arm11_common *	arm11,
		uint32_t	value
	)

Write VCR register.

Parameters

arm11	Target state variable.
value	Value to be written

Definition at line 962 of file arm11_dbgtap.c.

References arm11_sc7_action::address, arm11_sc7_run(), ARM11_SC7_VCR, arm11_sc7_action::value, and arm11_sc7_action::write.

Referenced by arm11_assert_reset(), arm11_deassert_reset(), and arm11_resume().

◆ arm11_setup_field()

void arm11_setup_field	(	struct arm11_common *	arm11,
		int	num_bits,
		void *	out_data,
		void *	in_data,
		struct scan_field *	field
	)

Code de-clutter: Construct struct scan_field to write out a value.

Parameters

arm11	Target state variable.
num_bits	Length of the data field
out_data	pointer to the data that will be sent out (data is read when it is added to the JTAG queue)
in_data	pointer to the memory that will receive data that was clocked in (data is written when the JTAG queue is executed)
field	target data structure that will be initialized

Definition at line 75 of file arm11_dbgtap.c.

References scan_field::in_value, scan_field::num_bits, and scan_field::out_value.

Referenced by arm11_add_debug_inst(), arm11_add_debug_scan_n(), arm11_add_ir(), arm11_debug_entry(), arm11_examine(), arm11_leave_debug_state(), arm11_read_dscr(), arm11_run_instr_data_from_core(), arm11_run_instr_data_to_core(), arm11_run_instr_data_to_core_noack(), arm11_sc7_run(), and arm11_write_dscr().

◆ arm11_write_dscr()

int arm11_write_dscr	(	struct arm11_common *	arm11,
		uint32_t	dscr
	)

Write the Debug Status and Control Register (DSCR)

same as CP14 c1

Parameters

arm11	Target state variable.
dscr	DSCR content

Remarks: This is a stand-alone function that executes the JTAG command queue.

Definition at line 303 of file arm11_dbgtap.c.

References arm11_common::arm, arm11_add_debug_scan_n(), arm11_add_dr_scan_vc(), arm11_add_ir(), ARM11_EXTEST, arm11_setup_field(), ARM11_TAP_DEFAULT, CHECK_RETVAL, arm11_common::dscr, ERROR_OK, JTAG_DEBUG, jtag_execute_queue(), NULL, target::tap, TAP_DRPAUSE, and arm::target.

Referenced by arm11_check_init(), arm11_debug_entry(), and arm11_leave_debug_state().

Data Structures

Functions

Function Documentation

◆ arm11_add_debug_scan_n()

◆ arm11_add_dr_scan_vc()

◆ arm11_add_ir()

◆ arm11_bpwp_flush()

◆ arm11_dpm_deinit()

◆ arm11_dpm_init()

◆ arm11_read_dscr()

◆ arm11_read_memory_word()

◆ arm11_run_instr_data_finish()

◆ arm11_run_instr_data_from_core()

◆ arm11_run_instr_data_from_core_via_r0()

◆ arm11_run_instr_data_prepare()

◆ arm11_run_instr_data_to_core()

◆ arm11_run_instr_data_to_core1()

◆ arm11_run_instr_data_to_core_noack()

◆ arm11_run_instr_data_to_core_via_r0()

◆ arm11_run_instr_no_data1()

◆ arm11_sc7_clear_vbw()

◆ arm11_sc7_run()

◆ arm11_sc7_set_vcr()

◆ arm11_setup_field()

◆ arm11_write_dscr()