25 LOG_ERROR(
"%s: target not halted", __func__);
43 LOG_ERROR(
"%s: target not halted", __func__);
49 LOG_DEBUG(
"instruction cache is not enabled");
59 int32_t c_way, c_index =
size->index;
66 uint32_t value = (c_index <<
size->index_shift)
67 | (c_way <<
size->way_shift) | (cl << 1);
80 }
while (c_index >= 0);
103 for (cl = 0; cl < cache->
loc; cl++) {
111 retval = dpm->
finish(dpm);
153 uint32_t linelen = armv7a_cache->
dminline;
154 uint32_t va_line, va_end;
165 va_line = virt & (-linelen);
166 va_end = virt +
size;
169 if (virt != va_line) {
179 if ((va_end & (linelen-1)) != 0) {
180 va_end &= (-linelen);
188 while (va_line < va_end) {
189 if ((i++ & 0x3f) == 0)
217 uint32_t linelen = armv7a_cache->
dminline;
218 uint32_t va_line, va_end;
229 va_line = virt & (-linelen);
230 va_end = virt +
size;
232 while (va_line < va_end) {
233 if ((i++ & 0x3f) == 0)
261 uint32_t linelen = armv7a_cache->
dminline;
262 uint32_t va_line, va_end;
273 va_line = virt & (-linelen);
274 va_end = virt +
size;
276 while (va_line < va_end) {
277 if ((i++ & 0x3f) == 0)
343 uint32_t linelen = armv7a_cache->
iminline;
344 uint32_t va_line, va_end;
355 va_line = virt & (-linelen);
356 va_end = virt +
size;
358 while (va_line < va_end) {
359 if ((i++ & 0x3f) == 0)
521 .handler = armv7a_l1_d_cache_clean_inval_all_cmd,
523 .help =
"flush (clean and invalidate) complete l1 d-cache",
528 .handler = arm7a_l1_d_cache_inval_virt_cmd,
530 .help =
"invalidate l1 d-cache by virtual address offset and range size",
531 .usage =
"<virt_addr> [size]",
535 .handler = arm7a_l1_d_cache_clean_virt_cmd,
537 .help =
"clean l1 d-cache by virtual address address offset and range size",
538 .usage =
"<virt_addr> [size]",
546 .handler = armv7a_i_cache_clean_inval_all_cmd,
548 .help =
"invalidate complete l1 i-cache",
553 .handler = arm7a_l1_i_cache_inval_virt_cmd,
555 .help =
"invalidate l1 i-cache by virtual address offset and range size",
556 .usage =
"<virt_addr> [size]",
564 .handler = arm7a_l1_cache_info_cmd,
566 .help =
"print cache related information",
572 .help =
"l1 d-cache command group",
579 .help =
"l1 i-cache command group",
589 .handler = arm7a_cache_disable_auto_cmd,
591 .help =
"disable or enable automatic cache handling.",
597 .help =
"l1 cache command group",
611 .help =
"cache command group",
Holds the interface to ARM cores.
Macros used to generate various ARM or Thumb opcodes.
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
int armv7a_handle_cache_info_command(struct command_invocation *cmd, struct armv7a_cache_common *armv7a_cache)
static struct armv7a_common * target_to_armv7a(struct target *target)
static int armv7a_l1_d_cache_sanity_check(struct target *target)
int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt, unsigned int size)
int armv7a_cache_auto_flush_all_data(struct target *target)
int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt, uint32_t size)
int armv7a_l1_i_cache_inval_all(struct target *target)
static const struct command_registration arm7a_l1_i_cache_commands[]
static int armv7a_l1_i_cache_sanity_check(struct target *target)
static int armv7a_l1_d_cache_clean_inval_all(struct target *target)
int armv7a_cache_auto_flush_on_write(struct target *target, uint32_t virt, uint32_t size)
static int armv7a_l1_d_cache_flush_level(struct arm_dpm *dpm, struct armv7a_cachesize *size, int cl)
int armv7a_l1_d_cache_clean_virt(struct target *target, uint32_t virt, unsigned int size)
static const struct command_registration arm7a_l1_di_cache_group_handlers[]
int armv7a_cache_flush_virt(struct target *target, uint32_t virt, uint32_t size)
static const struct command_registration arm7a_cache_group_handlers[]
const struct command_registration arm7a_cache_command_handlers[]
COMMAND_HANDLER(arm7a_l1_cache_info_cmd)
static const struct command_registration arm7a_l1_d_cache_commands[]
int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt, uint32_t size)
#define CACHE_LEVEL_HAS_D_CACHE
int arm7a_l2x_flush_all_data(struct target *target)
int armv7a_l2x_cache_flush_virt(struct target *target, target_addr_t virt, uint32_t size)
const struct command_registration arm7a_l2x_cache_command_handler[]
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_PARSE_ENABLE(in, out)
parses an enable/disable command argument
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
#define LOG_ERROR(expr ...)
#define LOG_DEBUG(expr ...)
size_t size
Size of the control block search area.
#define foreach_smp_target(pos, head)
This wraps an implementation of DPM primitives.
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
struct arm_dpm * dpm
Handle for the debug module, if one is present.
struct armv7a_cachesize d_u_size
struct armv7a_arch_cache arch[6]
struct armv7a_mmu_common armv7a_mmu
struct armv7a_cache_common armv7a_cache
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
struct list_head * smp_targets
struct target * get_current_target(struct command_context *cmd_ctx)
#define ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_INVALID