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armv7a.h File Reference
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Data Structures

struct  armv7a_arch_cache
 
struct  armv7a_cache_common
 
struct  armv7a_cachesize
 
struct  armv7a_common
 
struct  armv7a_l2x_cache
 
struct  armv7a_mmu_common
 

Macros

#define ARMV7_COMMON_MAGIC   0x0A450999U
 
#define CPUDBG_AUTHSTATUS   0xFB8
 
#define CPUDBG_BCR_BASE   0x140
 
#define CPUDBG_BVR_BASE   0x100
 
#define CPUDBG_DIDR   0x000
 
#define CPUDBG_DRCR   0x090
 
#define CPUDBG_DSCCR   0x028
 
#define CPUDBG_DSCR   0x088
 
#define CPUDBG_DSMCR   0x02C
 
#define CPUDBG_DTRRX   0x080
 
#define CPUDBG_DTRTX   0x08c
 
#define CPUDBG_ECR   0x024
 
#define CPUDBG_ID_PFR1   0xD24
 
#define CPUDBG_ITR   0x084
 
#define CPUDBG_OSLAR   0x300
 
#define CPUDBG_OSLSR   0x304
 
#define CPUDBG_OSSRR   0x308
 
#define CPUDBG_PRCR   0x310
 
#define CPUDBG_PRSR   0x314
 
#define CPUDBG_VCR   0x01C
 
#define CPUDBG_WCR_BASE   0x1C0
 
#define CPUDBG_WFAR   0x018
 
#define CPUDBG_WVR_BASE   0x180
 
#define DBG_VCR_DATA_ABORT_MASK   ((1 << 28) | (1 << 4))
 
#define DBG_VCR_FIQ_MASK   ((1 << 31) | (1 << 7))
 
#define DBG_VCR_IRQ_MASK   ((1 << 30) | (1 << 6))
 
#define DBG_VCR_PREF_ABORT_MASK   ((1 << 27) | (1 << 3))
 
#define DBG_VCR_SVC_MASK   ((1 << 26) | (1 << 2))
 
#define MPIDR_MP_EXT   (1UL << 31)
 
#define V2PCWPR   0
 
#define V2PCWPW   1
 
#define V2PCWUR   2
 
#define V2PCWUW   3
 
#define V2POWPR   4
 
#define V2POWPW   5
 
#define V2POWUR   6
 
#define V2POWUW   7
 

Enumerations

enum  { ARM_PC = 15 , ARM_CPSR = 16 }
 

Functions

int armv7a_arch_state (struct target *target)
 
int armv7a_handle_cache_info_command (struct command_invocation *cmd, struct armv7a_cache_common *armv7a_cache)
 
int armv7a_identify_cache (struct target *target)
 
int armv7a_init_arch_info (struct target *target, struct armv7a_common *armv7a)
 
int armv7a_read_ttbcr (struct target *target)
 
static bool is_armv7a (struct armv7a_common *armv7a)
 
static struct armv7a_commontarget_to_armv7a (struct target *target)
 

Variables

const struct command_registration armv7a_command_handlers []
 

Macro Definition Documentation

◆ ARMV7_COMMON_MAGIC

#define ARMV7_COMMON_MAGIC   0x0A450999U

Definition at line 22 of file armv7a.h.

◆ CPUDBG_AUTHSTATUS

#define CPUDBG_AUTHSTATUS   0xFB8

Definition at line 169 of file armv7a.h.

◆ CPUDBG_BCR_BASE

#define CPUDBG_BCR_BASE   0x140

Definition at line 153 of file armv7a.h.

◆ CPUDBG_BVR_BASE

#define CPUDBG_BVR_BASE   0x100

Definition at line 152 of file armv7a.h.

◆ CPUDBG_DIDR

#define CPUDBG_DIDR   0x000

Definition at line 136 of file armv7a.h.

◆ CPUDBG_DRCR

#define CPUDBG_DRCR   0x090

Definition at line 142 of file armv7a.h.

◆ CPUDBG_DSCCR

#define CPUDBG_DSCCR   0x028

Definition at line 165 of file armv7a.h.

◆ CPUDBG_DSCR

#define CPUDBG_DSCR   0x088

Definition at line 141 of file armv7a.h.

◆ CPUDBG_DSMCR

#define CPUDBG_DSMCR   0x02C

Definition at line 166 of file armv7a.h.

◆ CPUDBG_DTRRX

#define CPUDBG_DTRRX   0x080

Definition at line 147 of file armv7a.h.

◆ CPUDBG_DTRTX

#define CPUDBG_DTRTX   0x08c

Definition at line 149 of file armv7a.h.

◆ CPUDBG_ECR

#define CPUDBG_ECR   0x024

Definition at line 162 of file armv7a.h.

◆ CPUDBG_ID_PFR1

#define CPUDBG_ID_PFR1   0xD24

Definition at line 172 of file armv7a.h.

◆ CPUDBG_ITR

#define CPUDBG_ITR   0x084

Definition at line 148 of file armv7a.h.

◆ CPUDBG_OSLAR

#define CPUDBG_OSLAR   0x300

Definition at line 159 of file armv7a.h.

◆ CPUDBG_OSLSR

#define CPUDBG_OSLSR   0x304

Definition at line 160 of file armv7a.h.

◆ CPUDBG_OSSRR

#define CPUDBG_OSSRR   0x308

Definition at line 161 of file armv7a.h.

◆ CPUDBG_PRCR

#define CPUDBG_PRCR   0x310

Definition at line 143 of file armv7a.h.

◆ CPUDBG_PRSR

#define CPUDBG_PRSR   0x314

Definition at line 144 of file armv7a.h.

◆ CPUDBG_VCR

#define CPUDBG_VCR   0x01C

Definition at line 156 of file armv7a.h.

◆ CPUDBG_WCR_BASE

#define CPUDBG_WCR_BASE   0x1C0

Definition at line 155 of file armv7a.h.

◆ CPUDBG_WFAR

#define CPUDBG_WFAR   0x018

Definition at line 139 of file armv7a.h.

◆ CPUDBG_WVR_BASE

#define CPUDBG_WVR_BASE   0x180

Definition at line 154 of file armv7a.h.

◆ DBG_VCR_DATA_ABORT_MASK

#define DBG_VCR_DATA_ABORT_MASK   ((1 << 28) | (1 << 4))

Definition at line 177 of file armv7a.h.

◆ DBG_VCR_FIQ_MASK

#define DBG_VCR_FIQ_MASK   ((1 << 31) | (1 << 7))

Definition at line 175 of file armv7a.h.

◆ DBG_VCR_IRQ_MASK

#define DBG_VCR_IRQ_MASK   ((1 << 30) | (1 << 6))

Definition at line 176 of file armv7a.h.

◆ DBG_VCR_PREF_ABORT_MASK

#define DBG_VCR_PREF_ABORT_MASK   ((1 << 27) | (1 << 3))

Definition at line 178 of file armv7a.h.

◆ DBG_VCR_SVC_MASK

#define DBG_VCR_SVC_MASK   ((1 << 26) | (1 << 2))

Definition at line 179 of file armv7a.h.

◆ MPIDR_MP_EXT

#define MPIDR_MP_EXT   (1UL << 31)

Definition at line 182 of file armv7a.h.

◆ V2PCWPR

#define V2PCWPR   0

Definition at line 25 of file armv7a.h.

◆ V2PCWPW

#define V2PCWPW   1

Definition at line 26 of file armv7a.h.

◆ V2PCWUR

#define V2PCWUR   2

Definition at line 27 of file armv7a.h.

◆ V2PCWUW

#define V2PCWUW   3

Definition at line 28 of file armv7a.h.

◆ V2POWPR

#define V2POWPR   4

Definition at line 29 of file armv7a.h.

◆ V2POWPW

#define V2POWPW   5

Definition at line 30 of file armv7a.h.

◆ V2POWUR

#define V2POWUR   6

Definition at line 31 of file armv7a.h.

◆ V2POWUW

#define V2POWUW   7

Definition at line 32 of file armv7a.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
ARM_PC 
ARM_CPSR 

Definition at line 17 of file armv7a.h.

Function Documentation

◆ armv7a_arch_state()

◆ armv7a_handle_cache_info_command()

◆ armv7a_identify_cache()

◆ armv7a_init_arch_info()

◆ armv7a_read_ttbcr()

◆ is_armv7a()

static bool is_armv7a ( struct armv7a_common armv7a)
inlinestatic

Definition at line 127 of file armv7a.h.

References ARMV7_COMMON_MAGIC, and armv7a_common::common_magic.

Referenced by arm_semihosting(), and post_result().

◆ target_to_armv7a()

static struct armv7a_common* target_to_armv7a ( struct target target)
inlinestatic

Definition at line 122 of file armv7a.h.

References target::arch_info, and container_of.

Referenced by arm7a_l2x_flush_all_data(), arm7a_l2x_sanity_check(), arm_semihosting(), armv7a_arch_state(), armv7a_cache_auto_flush_all_data(), armv7a_cache_auto_flush_on_write(), armv7a_identify_cache(), armv7a_l1_d_cache_clean_inval_all(), armv7a_l1_d_cache_clean_virt(), armv7a_l1_d_cache_flush_virt(), armv7a_l1_d_cache_inval_virt(), armv7a_l1_d_cache_sanity_check(), armv7a_l1_i_cache_inval_all(), armv7a_l1_i_cache_inval_virt(), armv7a_l1_i_cache_sanity_check(), armv7a_l2x_cache_clean_virt(), armv7a_l2x_cache_flush_virt(), armv7a_l2x_cache_init(), armv7a_l2x_cache_inval_virt(), armv7a_mmu_translate_va_pa(), armv7a_read_midr(), armv7a_read_mpidr(), armv7a_read_ttbcr(), armv7a_setup_semihosting(), armv7a_show_fault_registers(), COMMAND_HANDLER(), cortex_a_assert_reset(), cortex_a_dap_write_memap_register_u32(), cortex_a_deassert_reset(), cortex_a_debug_entry(), cortex_a_exec_opcode(), cortex_a_halt(), cortex_a_handle_target_request(), cortex_a_init_debug_access(), cortex_a_internal_restart(), cortex_a_internal_restore(), cortex_a_mmu(), cortex_a_mmu_modify(), cortex_a_post_memaccess(), cortex_a_prep_memaccess(), cortex_a_read_copro(), cortex_a_read_cpu_memory(), cortex_a_read_cpu_memory_fast(), cortex_a_read_cpu_memory_slow(), cortex_a_restore_context(), cortex_a_restore_cp15_control_reg(), cortex_a_set_dcc_mode(), cortex_a_set_dscr_bits(), cortex_a_step(), cortex_a_wait_dscr_bits(), cortex_a_wait_instrcmpl(), cortex_a_write_copro(), cortex_a_write_cpu_memory(), cortex_a_write_cpu_memory_fast(), cortex_a_write_cpu_memory_slow(), and post_result().

Variable Documentation

◆ armv7a_command_handlers

const struct command_registration armv7a_command_handlers[]
extern

Definition at line 532 of file armv7a.c.