OpenOCD
arm_disassembler.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2006 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  ***************************************************************************/
7 
8 #ifndef OPENOCD_TARGET_ARM_DISASSEMBLER_H
9 #define OPENOCD_TARGET_ARM_DISASSEMBLER_H
10 
13 
14  /* Branch instructions */
19 
20  /* Data processing instructions */
37 
38  /* Load/store instructions */
43 
47 
49 
54 
56 
58 
59  /* Status register access instructions */
62 
63  /* Multiply instructions */
70 
71  /* Miscellaneous instructions */
73 
74  /* Exception return instructions */
76 
77  /* Exception generating instructions */
82 
83  /* Coprocessor instructions */
89 
90  /* Semaphore instructions */
93 
94  /* Enhanced DSP extensions */
111 
113 };
114 
117  uint32_t target_address;
118 };
119 
121  struct {
122  uint32_t immediate;
124  struct {
125  uint8_t rm;
126  uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
127  uint8_t shift_imm;
129  struct {
130  uint8_t rm;
131  uint8_t shift;
132  uint8_t rs;
134 };
135 
137  int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
138  uint8_t s;
139  uint8_t rn;
140  uint8_t rd;
142 };
143 
145  uint8_t rd;
146  uint8_t rn;
147  uint8_t u;
148  int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
149  int offset_mode; /* 0: immediate, 1: (scaled) register */
150  union {
151  uint32_t offset;
152  struct {
153  uint8_t rm;
154  uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
155  uint8_t shift_imm;
156  } reg;
158 };
159 
161  uint8_t rn;
162  uint32_t register_list;
163  uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
164  uint8_t s;
165  uint8_t w;
166 };
167 
170  char text[128];
171  uint32_t opcode;
172 
173  /* return value ... Thumb-2 sizes vary */
175 
176  union {
181  } info;
182 
183 };
184 
185 int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
186  struct arm_instruction *instruction);
187 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
188  struct arm_instruction *instruction);
189 int arm_access_size(struct arm_instruction *instruction);
190 #if HAVE_CAPSTONE
191 int arm_disassemble(struct command_invocation *cmd, struct target *target,
192  target_addr_t address, size_t count, bool thumb_mode);
193 #endif
194 
195 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
196 
197 #endif /* OPENOCD_TARGET_ARM_DISASSEMBLER_H */
int arm_evaluate_opcode(uint32_t opcode, uint32_t address, struct arm_instruction *instruction)
arm_instruction_type
@ ARM_SMULWY
@ ARM_LDRSB
@ ARM_QDADD
@ ARM_RSB
@ ARM_MSR
@ ARM_UMLAL
@ ARM_CDP
@ ARM_BIC
@ ARM_ADD
@ ARM_DSB
@ ARM_SMULL
@ ARM_UNKNOWN_INSTRUCTION
@ ARM_STM
@ ARM_SMLAXY
@ ARM_QDSUB
@ ARM_SBC
@ ARM_SMC
@ ARM_SWP
@ ARM_SMULXY
@ ARM_RSC
@ ARM_BX
@ ARM_BL
@ ARM_MCRR
@ ARM_MRRC
@ ARM_UMULL
@ ARM_B
@ ARM_MOV
@ ARM_ERET
@ ARM_UNDEFINED_INSTRUCTION
@ ARM_STRD
@ ARM_BKPT
@ ARM_MRC
@ ARM_STC
@ ARM_HVC
@ ARM_LDC
@ ARM_CMP
@ ARM_MRS
@ ARM_ISB
@ ARM_STRH
@ ARM_TST
@ ARM_MUL
@ ARM_LDR
@ ARM_STRT
@ ARM_SMLALXY
@ ARM_LDRB
@ ARM_AND
@ ARM_STRBT
@ ARM_MCR
@ ARM_BLX
@ ARM_ADC
@ ARM_STR
@ ARM_LDM
@ ARM_EOR
@ ARM_LDRSH
@ ARM_SWI
@ ARM_LDRH
@ ARM_LDRBT
@ ARM_STRB
@ ARM_LDRT
@ ARM_SMLAWY
@ ARM_LDRD
@ ARM_SWPB
@ ARM_MLA
@ ARM_PLD
@ ARM_SUB
@ ARM_MVN
@ ARM_ORR
@ ARM_QADD
@ ARM_CLZ
@ ARM_CMN
@ ARM_QSUB
@ ARM_SMLAL
@ ARM_TEQ
int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, struct arm_instruction *instruction)
int arm_access_size(struct arm_instruction *instruction)
union arm_shifter_operand shifter_operand
struct arm_load_store_multiple_instr load_store_multiple
enum arm_instruction_type type
union arm_instruction::@65 info
unsigned instruction_size
struct arm_b_bl_bx_blx_instr b_bl_bx_blx
struct arm_load_store_instr load_store
struct arm_data_proc_instr data_proc
struct arm_load_store_instr::@63::@64 reg
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
Definition: target.h:120
uint64_t target_addr_t
Definition: types.h:335
struct arm_shifter_operand::@62 register_shift
struct arm_shifter_operand::@61 immediate_shift
uint8_t cmd
Definition: vdebug.c:1
uint8_t count[4]
Definition: vdebug.c:22