24 #define XT_NIBSWAP8(V) \
25 ((((V) & 0x0F) << 4) \
26 | (((V) & 0xF0) >> 4))
28 #define XT_NIBSWAP16(V) \
29 ((((V) & 0x000F) << 12) \
30 | (((V) & 0x00F0) << 4) \
31 | (((V) & 0x0F00) >> 4) \
32 | (((V) & 0xF000) >> 12))
34 #define XT_NIBSWAP24(V) \
35 ((((V) & 0x00000F) << 20) \
36 | (((V) & 0x0000F0) << 12) \
37 | (((V) & 0x000F00) << 4) \
38 | (((V) & 0x00F000) >> 4) \
39 | (((V) & 0x0F0000) >> 12) \
40 | (((V) & 0xF00000) >> 20))
46 #define _XT_INS_FORMAT_RSR(X, OPCODE, SR, T) \
47 (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
48 | (((T) & 0x0F) << 16) \
49 | (((SR) & 0xFF) << 8)) << 8 \
51 | (((SR) & 0xFF) << 8) \
52 | (((T) & 0x0F) << 4))
54 #define _XT_INS_FORMAT_RRR(X, OPCODE, ST, R) \
55 (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
56 | ((XT_NIBSWAP8((ST) & 0xFF)) << 12) \
57 | (((R) & 0x0F) << 8)) << 8 \
59 | (((ST) & 0xFF) << 4) \
60 | (((R) & 0x0F) << 12))
62 #define _XT_INS_FORMAT_RRRN(X, OPCODE, S, T, IMM4) \
63 (XT_ISBE(X) ? (XT_NIBSWAP16(OPCODE) \
64 | (((T) & 0x0F) << 8) \
65 | (((S) & 0x0F) << 4) \
66 | ((IMM4) & 0x0F)) << 16 \
68 | (((T) & 0x0F) << 4) \
69 | (((S) & 0x0F) << 8) \
70 | (((IMM4) & 0x0F) << 12))
72 #define _XT_INS_FORMAT_RRI8(X, OPCODE, R, S, T, IMM8) \
73 (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
74 | (((T) & 0x0F) << 16) \
75 | (((S) & 0x0F) << 12) \
76 | (((R) & 0x0F) << 8) \
77 | ((IMM8) & 0xFF)) << 8 \
79 | (((IMM8) & 0xFF) << 16) \
80 | (((R) & 0x0F) << 12) \
81 | (((S) & 0x0F) << 8) \
82 | (((T) & 0x0F) << 4))
84 #define _XT_INS_FORMAT_RRI4(X, OPCODE, IMM4, R, S, T) \
85 (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
86 | (((T) & 0x0F) << 16) \
87 | (((S) & 0x0F) << 12) \
88 | (((R) & 0x0F) << 8)) << 8 \
91 | (((IMM4) & 0x0F) << 20) \
92 | (((R) & 0x0F) << 12) \
93 | (((S) & 0x0F) << 8) \
94 | (((T) & 0x0F) << 4))
99 #define XT_INS_RFDO(X) (XT_ISBE(X) ? 0x000e1f << 8 : 0xf1e000)
101 #define XT_INS_RFDD(X) (XT_ISBE(X) ? 0x010e1f << 8 : 0xf1e010)
104 #define XT_INS_LDDR32P(X, S) (XT_ISBE(X) ? (0x0E0700 | ((S) << 12)) << 8 : (0x0070E0 | ((S) << 8)))
106 #define XT_INS_SDDR32P(X, S) (XT_ISBE(X) ? (0x0F0700 | ((S) << 12)) << 8 : (0x0070F0 | ((S) << 8)))
109 #define XT_INS_L32I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x002002, 0, S, T, IMM8)
111 #define XT_INS_L16UI(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x001002, 0, S, T, IMM8)
113 #define XT_INS_L8UI(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x000002, 0, S, T, IMM8)
116 #define XT_INS_S32I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x006002, 0, S, T, IMM8)
118 #define XT_INS_S16I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x005002, 0, S, T, IMM8)
120 #define XT_INS_S8I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x004002, 0, S, T, IMM8)
123 #define XT_INS_IHI(X, S, IMM8) _XT_INS_FORMAT_RRI8(X, 0x0070E2, 0, S, 0, IMM8)
124 #define XT_INS_DHWBI(X, S, IMM8) _XT_INS_FORMAT_RRI8(X, 0x007052, 0, S, 0, IMM8)
125 #define XT_INS_DHWB(X, S, IMM8) _XT_INS_FORMAT_RRI8(X, 0x007042, 0, S, 0, IMM8)
126 #define XT_INS_ISYNC(X) (XT_ISBE(X) ? 0x000200 << 8 : 0x002000)
129 #define XT_INS_JX(X, S) (XT_ISBE(X) ? (0x050000 | ((S) << 12)) : (0x0000a0 | ((S) << 8)))
130 #define XT_INS_CALL0(X, IMM18) (XT_ISBE(X) ? (0x500000 | ((IMM18) & 0x3ffff)) : (0x000005 | (((IMM18) & 0x3ffff) << 6)))
133 #define XT_INS_RSR(X, SR, T) _XT_INS_FORMAT_RSR(X, 0x030000, SR, T)
135 #define XT_INS_WSR(X, SR, T) _XT_INS_FORMAT_RSR(X, 0x130000, SR, T)
137 #define XT_INS_XSR(X, SR, T) _XT_INS_FORMAT_RSR(X, 0x610000, SR, T)
140 #define XT_INS_ROTW(X, N) (XT_ISBE(X) ? ((0x000804) | (((N) & 15) << 16)) << 8 : ((0x408000) | (((N) & 15) << 4)))
143 #define XT_INS_RUR(X, UR, T) _XT_INS_FORMAT_RRR(X, 0xE30000, UR, T)
145 #define XT_INS_WUR(X, UR, T) _XT_INS_FORMAT_RSR(X, 0xF30000, UR, T)
148 #define XT_INS_RFR(X, FR, T) _XT_INS_FORMAT_RRR(X, 0xFA0000, ((FR << 4) | 0x4), T)
150 #define XT_INS_WFR(X, FR, T) _XT_INS_FORMAT_RRR(X, 0xFA0000, ((T << 4) | 0x5), FR)
152 #define XT_INS_L32E(X, R, S, T) _XT_INS_FORMAT_RRI4(X, 0x090000, 0, R, S, T)
153 #define XT_INS_S32E(X, R, S, T) _XT_INS_FORMAT_RRI4(X, 0x490000, 0, R, S, T)
154 #define XT_INS_L32E_S32E_MASK(X) (XT_ISBE(X) ? 0xF000FF << 8 : 0xFF000F)
156 #define XT_INS_RFWO(X) (XT_ISBE(X) ? 0x004300 << 8 : 0x003400)
157 #define XT_INS_RFWU(X) (XT_ISBE(X) ? 0x005300 << 8 : 0x003500)
158 #define XT_INS_RFWO_RFWU_MASK(X) (XT_ISBE(X) ? 0xFFFFFF << 8 : 0xFFFFFF)
160 #define XT_WATCHPOINTS_NUM_MAX 2
165 #define XT_SR_DDR (xtensa_regs[XT_REG_IDX_DDR].reg_num)
166 #define XT_SR_PS (xtensa_regs[XT_REG_IDX_PS].reg_num)
167 #define XT_SR_WB (xtensa_regs[XT_REG_IDX_WINDOWBASE].reg_num)
168 #define XT_REG_A3 (xtensa_regs[XT_REG_IDX_AR3].reg_num)
169 #define XT_REG_A4 (xtensa_regs[XT_REG_IDX_AR4].reg_num)
171 #define XT_PS_REG_NUM (0xe6U)
172 #define XT_EPS_REG_NUM_BASE (0xc0U)
173 #define XT_EPC_REG_NUM_BASE (0xb0U)
174 #define XT_PC_REG_NUM_VIRTUAL (0xffU)
175 #define XT_PC_DBREG_NUM_BASE (0x20U)
177 #define XT_SW_BREAKPOINTS_MAX_NUM 32
178 #define XT_HW_IBREAK_MAX_NUM 2
179 #define XT_HW_DBREAK_MAX_NUM 2
348 for (
unsigned int i = 0; i < mem->
count; i++) {
350 if (address >= region->
base && address < (region->
base + region->
size))
410 if (strncmp(
reg->
name,
"?0x", 3) == 0) {
411 unsigned int regnum = strtoul(
reg->
name + 1, 0, 0);
412 LOG_WARNING(
"Read unknown register 0x%04x ignored", regnum);
425 assert(
reg->
size <= 64 &&
"up to 64-bit regs are supported only!");
430 if (strncmp(
reg->
name,
"?0x", 3) == 0) {
431 unsigned int regnum = strtoul(
reg->
name + 1, 0, 0);
432 LOG_WARNING(
"Write unknown register 0x%04x ignored", regnum);
446 LOG_DEBUG(
"scratch_ars mapping: a3/%s, a4/%s",
476 LOG_ERROR(
"Error: can't convert register %d to non-windowbased register!", reg_idx);
492 reg_list[reg_idx].
dirty =
true;
502 const int max_oplen = 64;
503 if ((oplen > 0) && (oplen <= max_oplen)) {
504 uint8_t ops_padded[max_oplen];
505 memcpy(ops_padded, ops, oplen);
506 memset(ops_padded + oplen, 0, max_oplen - oplen);
507 unsigned int oplenw =
DIV_ROUND_UP(oplen,
sizeof(uint32_t));
508 for (int32_t i = oplenw - 1; i > 0; i--)
539 LOG_ERROR(
"Failed to read PS (%d)!", res);
545 LOG_DEBUG(
"Clearing PS.WOE (0x%08" PRIx32
" -> 0x%08" PRIx32
")", *woe, woe_dis);
562 LOG_DEBUG(
"Restored PS.WOE (0x%08" PRIx32
")", woe);
593 bool scratch_reg_dirty =
false, delay_cpenable =
false;
596 bool preserve_a3 =
false;
604 for (
unsigned int i = 0; i < reg_list_size; i++) {
607 if (reg_list[i].dirty) {
611 scratch_reg_dirty =
true;
613 delay_cpenable =
true;
623 if (reg_list[i].
exist) {
639 reg_list[i].
dirty =
false;
643 if (scratch_reg_dirty)
645 if (delay_cpenable) {
681 if (reg_list[i].dirty && reg_list[j].dirty) {
682 if (memcmp(reg_list[i].value, reg_list[j].value,
sizeof(
xtensa_reg_val_t)) != 0) {
683 bool show_warning =
true;
692 "Warning: Both A%d [0x%08" PRIx32
693 "] as well as its underlying physical register "
694 "(AR%d) [0x%08" PRIx32
"] are dirty and differ in value",
705 for (
unsigned int i = 0; i < 16; i++) {
726 for (
unsigned int i = 0; i < 16; i++) {
727 if (i + j < xtensa->core_config->aregs_num) {
732 if (reg_list[realadr].dirty) {
736 "Writing back reg %s value %08" PRIX32
", num =%i",
744 reg_list[realadr].
dirty =
false;
788 LOG_ERROR(
"XTensa core not configured; is xtensa-core-openocd.cfg missing?");
826 uint32_t dsr_data = 0x00110000;
853 uint8_t dcr_buf[
sizeof(uint32_t)];
884 int res, needclear = 0;
897 "DSR (%08" PRIX32
") indicates DIR instruction generated an exception!",
904 "DSR (%08" PRIX32
") indicates DIR instruction generated an overrun!",
1036 goto xtensa_fetch_all_regs_done;
1045 for (
unsigned int i = 0; i < 16; i++) {
1046 if (i + j < xtensa->core_config->aregs_num) {
1072 LOG_ERROR(
"Failed to read ARs (%d)!", res);
1073 goto xtensa_fetch_all_regs_done;
1093 for (
unsigned int i = 0; i < reg_list_size; i++) {
1097 bool reg_fetched =
true;
1099 switch (rlist[ridx].
type) {
1115 reg_fetched =
false;
1121 reg_fetched =
false;
1135 goto xtensa_fetch_all_regs_done;
1141 for (
unsigned int i = 0; i < reg_list_size; i++) {
1152 goto xtensa_fetch_all_regs_done;
1162 for (
unsigned int i = 0; i < reg_list_size; i++) {
1172 buf_cpy(regvals[realadr].buf, reg_list[i].value, reg_list[i].
size);
1183 LOG_INFO(
"Register %s: 0x%X", reg_list[i].
name, regval);
1185 reg_list[i].
dirty = is_dirty;
1187 reg_list[i].
valid =
true;
1191 reg_list[i].
valid =
true;
1194 reg_list[i].
valid =
false;
1219 xtensa_fetch_all_regs_done:
1226 struct reg **reg_list[],
1231 unsigned int num_regs;
1235 LOG_ERROR(
"reg_class %d unhandled; 'xtgregs' not found", reg_class);
1244 LOG_DEBUG(
"reg_class=%i, num_regs=%d", (
int)reg_class, num_regs);
1246 *reg_list = calloc(num_regs,
sizeof(
struct reg *));
1250 *reg_list_size = num_regs;
1252 assert((num_regs <= xtensa->
total_regs_num) &&
"contiguous regmap size internal error!");
1253 for (
unsigned int i = 0; i < num_regs; i++)
1258 for (
unsigned int i = 0; i < num_regs; i++)
1268 LOG_ERROR(
"eps_dbglevel_idx not set\n");
1273 LOG_DEBUG(
"SPARSE GDB reg 0x%x getting EPS%d 0x%x",
1289 LOG_ERROR(
"SPARSE GDB reg list full (size %d)", k);
1332 int handle_breakpoints,
1333 int debug_execution)
1339 "current=%d address=" TARGET_ADDR_FMT ", handle_breakpoints=%i, debug_execution=%i)",
1350 if (address && !current) {
1407 int handle_breakpoints,
1408 int debug_execution)
1423 if (!debug_execution)
1457 const uint32_t icount_val = -2;
1461 bool ps_lowered =
false;
1464 current, address, handle_breakpoints);
1472 LOG_ERROR(
"eps_dbglevel_idx not set\n");
1481 LOG_TARGET_DEBUG(
target,
"oldps=%" PRIx32
", oldpc=%" PRIx32
" dbg_cause=%" PRIx32
" exc_cause=%" PRIx32,
1519 "disabling IRQs while stepping is not implemented w/o high prio IRQs option!");
1534 "Single-stepping to get past instruction that triggered the watchpoint...");
1546 if ((oldps & 0xf) >= icountlvl) {
1549 uint32_t newps = (oldps & ~0xf) | (icountlvl - 1);
1552 "Lowering PS.INTLEVEL to allow stepping: %s <- 0x%08" PRIx32
" (was 0x%08" PRIx32
")",
1593 "Timed out waiting for target to finish stepping. dsr=0x%08" PRIx32,
1604 "cur_ps=%" PRIx32
", cur_pc=%" PRIx32
" dbg_cause=%" PRIx32
" exc_cause=%" PRIx32,
1617 LOG_DEBUG(
"Stepping out of window exception, PC=%" PRIX32, cur_pc);
1619 address = oldpc + 3;
1623 if (oldpc == cur_pc)
1627 LOG_DEBUG(
"Stepped from %" PRIX32
" to %" PRIX32, oldpc, cur_pc);
1633 LOG_DEBUG(
"Done stepping, PC=%" PRIX32, cur_pc);
1644 LOG_DEBUG(
"Restoring %s after stepping: 0x%08" PRIx32,
1676 if ((r2_start >= r1_start) && (r2_start < r1_end))
1678 if ((r2_end > r1_start) && (r2_end <= r1_end))
1692 target_addr_t ov_start = r1_start < r2_start ? r2_start : r1_start;
1694 return ov_end - ov_start;
1709 while (adr_pos < adr_end) {
1716 assert(overlap_size != 0);
1717 adr_pos += overlap_size;
1746 unsigned int alloc_bytes =
ALIGN_UP(addrend_al - addrstart_al,
sizeof(uint32_t));
1747 albuff = calloc(alloc_bytes, 1);
1750 addrend_al - addrstart_al);
1762 for (
unsigned int i = 0; adr != addrend_al; i +=
sizeof(uint32_t), adr +=
sizeof(uint32_t))
1768 for (
unsigned int i = 0; adr != addrend_al; i +=
sizeof(uint32_t), adr +=
sizeof(uint32_t)) {
1799 buf_bswap32(albuff, albuff, addrend_al - addrstart_al);
1827 bool fill_head_tail =
false;
1845 if (addrstart_al == address && addrend_al == address + (
size *
count)) {
1848 albuff = malloc(addrend_al - addrstart_al);
1851 albuff = (uint8_t *)
buffer;
1853 fill_head_tail =
true;
1854 albuff = malloc(addrend_al - addrstart_al);
1858 addrend_al - addrstart_al);
1866 if (fill_head_tail) {
1889 &albuff[addrend_al - addrstart_al - 4]);
1894 LOG_ERROR(
"Error issuing unaligned memory write context instruction(s): %d", res);
1901 bool swapped_w0 =
false;
1907 if ((addrend_al - addrstart_al - 4 == 0) && swapped_w0) {
1910 buf_bswap32(&albuff[addrend_al - addrstart_al - 4],
1911 &albuff[addrend_al - addrstart_al - 4], 4);
1921 buf_bswap32(albuff, fill_head_tail ? albuff :
buffer, addrend_al - addrstart_al);
1928 for (
unsigned int i = 0; adr != addrend_al; i +=
sizeof(uint32_t), adr +=
sizeof(uint32_t)) {
1938 for (
unsigned int i = 0; adr != addrend_al; i +=
sizeof(uint32_t), adr +=
sizeof(uint32_t)) {
1970 if (issue_ihi || issue_dhwb) {
1973 uint32_t linesize =
MIN(ilinesize, dlinesize);
1977 while ((adr + off) < addrend_al) {
2000 "Error issuing cache writeback/invaldate instruction(s): %d",
2060 "DSR has changed: was 0x%08" PRIx32
" now 0x%08" PRIx32,
2099 ", debug_reason=%08" PRIx32
", oldstate=%08" PRIx32,
2126 LOG_INFO(
"Detected end of trace.");
2147 unsigned int same_ic_line = ((address & (icache_line_size - 1)) +
size) <= icache_line_size;
2148 unsigned int same_dc_line = ((address & (dcache_line_size - 1)) +
size) <= dcache_line_size;
2151 if (
size > icache_line_size)
2154 if (issue_ihi || issue_dhwbi) {
2164 if (!same_dc_line) {
2173 if (!same_ic_line) {
2185 LOG_ERROR(
"Error issuing cache invaldate instruction(s): %d", ret);
2203 if (!same_dc_line) {
2367 " not supported by hardware.",
2375 dbreakcval |=
BIT(30);
2377 dbreakcval |=
BIT(31);
2379 dbreakcval |=
BIT(30) |
BIT(31);
2414 unsigned int last_dbreg_num = 0;
2423 LOG_ERROR(
"Failed to alloc reg cache!");
2430 struct reg *reg_list = calloc(reg_list_size,
sizeof(
struct reg));
2436 unsigned int didx = 0;
2437 for (
unsigned int whichlist = 0; whichlist < 2; whichlist++) {
2440 for (
unsigned int i = 0; i < listsize; i++, didx++) {
2442 reg_list[didx].
name = rlist[i].
name;
2443 reg_list[didx].
size = 32;
2444 reg_list[didx].
value = calloc(1, 4 );
2445 if (!reg_list[didx].value) {
2446 LOG_ERROR(
"Failed to alloc reg list value!");
2449 reg_list[didx].
dirty =
false;
2450 reg_list[didx].
valid =
false;
2458 "POPULATE %-16s list %d exist %d, idx %d, type %d, dbreg_num 0x%04x",
2459 reg_list[didx].
name,
2461 reg_list[didx].
exist,
2493 LOG_ERROR(
"Failed to alloc empty reg list value!");
2518 "POPULATE contiguous regs list: %-16s, dbreg_num 0x%04x",
2532 LOG_ERROR(
"Failed to alloc mem for algorithm context backup!");
2539 LOG_ERROR(
"Failed to alloc mem for algorithm context!");
2550 for (
unsigned int i = 0; i < reg_list_size; i++)
2551 free(reg_list[i].
value);
2576 while (opstr && (*opstr ==
':')) {
2578 unsigned int oplen = strtoul(opstr + 1, &opstr, 16);
2584 while ((i < oplen) && opstr && (*opstr ==
':'))
2585 ops[i++] = strtoul(opstr + 1, &opstr, 16);
2592 sprintf(insn_buf,
"Exec %d-byte TIE sequence: ", oplen);
2593 for (i = 0; i < oplen; i++)
2594 sprintf(insn_buf + strlen(insn_buf),
"%02x:", ops[i]);
2605 bool iswrite = (packet[0] ==
'Q');
2613 LOG_ERROR(
"Spill location not specified. Try 'target remote <host>:3333 &spill_location0'");
2615 goto xtensa_gdbqc_qxtreg_fail;
2619 uint32_t regnum = strtoul(packet + 6, &delim, 16);
2620 if (*delim !=
':') {
2623 goto xtensa_gdbqc_qxtreg_fail;
2625 uint32_t reglen = strtoul(delim + 1, &delim, 16);
2626 if (*delim !=
':') {
2629 goto xtensa_gdbqc_qxtreg_fail;
2633 LOG_DEBUG(
"TIE reg 0x%08" PRIx32
" %s (%d bytes)", regnum, iswrite ?
"write" :
"read", reglen);
2637 goto xtensa_gdbqc_qxtreg_fail;
2650 goto xtensa_gdbqc_qxtreg_fail;
2655 char *valbuf = strchr(delim,
'=');
2656 if (!(valbuf && (*valbuf ==
'='))) {
2659 goto xtensa_gdbqc_qxtreg_fail;
2662 while (*valbuf && *(valbuf + 1)) {
2663 char bytestr[3] = { 0, 0, 0 };
2664 strncpy(bytestr, valbuf, 2);
2665 regbuf[b++] = strtoul(bytestr,
NULL, 16);
2671 goto xtensa_gdbqc_qxtreg_fail;
2674 reglen / memop_size, regbuf);
2678 goto xtensa_gdbqc_qxtreg_fail;
2704 strcpy(*response_p,
"OK");
2713 for (i = 0; i < reglen; i++)
2714 sprintf(*response_p + 2 * i,
"%02x", regbuf[i]);
2715 *(*response_p + 2 * i) =
'\0';
2726 goto xtensa_gdbqc_qxtreg_fail;
2731 goto xtensa_gdbqc_qxtreg_fail;
2735 xtensa_gdbqc_qxtreg_fail:
2736 strcpy(*response_p,
xt_qerr[error].chrval);
2744 if (!packet || !response_p) {
2750 if (strncmp(packet,
"qxtn", 4) == 0) {
2751 strcpy(*response_p,
"OpenOCD");
2753 }
else if (strncasecmp(packet,
"qxtgdbversion=", 14) == 0) {
2755 }
else if ((strncmp(packet,
"Qxtsis=", 7) == 0) || (strncmp(packet,
"Qxtsds=", 7) == 0)) {
2767 strcpy(*response_p,
"OK");
2769 }
else if ((strncmp(packet,
"Qxtiram=", 8) == 0) || (strncmp(packet,
"Qxtirom=", 8) == 0)) {
2773 unsigned int base = 0,
size = 0, i;
2774 char *pkt = (
char *)&packet[7];
2777 size = strtoul(pkt, &pkt, 16);
2779 base = strtoul(pkt, &pkt, 16);
2781 for (i = 0; i < memp->
count; i++) {
2785 if (i == memp->
count) {
2790 for (i = 0; i < 11; i++) {
2792 strtoul(pkt, &pkt, 16);
2794 }
while (pkt && (pkt[0] ==
','));
2795 strcpy(*response_p,
"OK");
2797 }
else if (strncmp(packet,
"Qxtexcmlvl=", 11) == 0) {
2799 unsigned int excm_level = strtoul(&packet[11],
NULL, 0);
2803 strcpy(*response_p,
"OK");
2805 }
else if ((strncmp(packet,
"Qxtl2cs=", 8) == 0) ||
2806 (strncmp(packet,
"Qxtl2ca=", 8) == 0) ||
2807 (strncmp(packet,
"Qxtdensity=", 11) == 0)) {
2808 strcpy(*response_p,
"OK");
2810 }
else if (strncmp(packet,
"Qxtspill=", 9) == 0) {
2812 uint32_t spill_loc = strtoul(packet + 9, &delim, 16);
2813 if (*delim !=
':') {
2816 goto xtensa_gdb_query_custom_fail;
2826 goto xtensa_gdb_query_custom_fail;
2829 strcpy(*response_p,
"OK");
2831 }
else if (strncasecmp(packet,
"qxtreg", 6) == 0) {
2833 }
else if ((strncmp(packet,
"qTStatus", 8) == 0) ||
2834 (strncmp(packet,
"qxtftie", 7) == 0) ||
2835 (strncmp(packet,
"qxtstie", 7) == 0)) {
2837 strcpy(*response_p,
"");
2843 strcpy(*response_p,
"");
2846 xtensa_gdb_query_custom_fail:
2847 strcpy(*response_p,
xt_qerr[error].chrval);
2861 LOG_ERROR(
"Xtensa configuration alloc failed\n");
2878 LOG_ERROR(
"Xtensa scratch AR alloc failed\n");
2902 LOG_ERROR(
"Failed to alloc memory for HW breakpoints!");
2908 LOG_ERROR(
"Failed to alloc memory for HW watchpoints!");
2915 LOG_ERROR(
"Failed to alloc memory for SW breakpoints!");
2934 for (
unsigned int i = 0; i < cache->
num_regs; i++) {
2970 LOG_ERROR(
"Failed to queue OCDDCR_ENABLEOCD clear operation!");
2976 LOG_ERROR(
"Failed to clear OCDDCR_ENABLEOCD!");
3009 unsigned int parm_len = strlen(parm);
3010 if ((parm_len >= 64) || (parm_len & 1)) {
3011 LOG_ERROR(
"Invalid parameter length (%d): must be even, < 64 characters", parm_len);
3017 unsigned int oplen = parm_len / 2;
3018 char encoded_byte[3] = { 0, 0, 0 };
3019 for (
unsigned int i = 0; i < oplen; i++) {
3020 encoded_byte[0] = *parm++;
3021 encoded_byte[1] = *parm++;
3022 ops[i] = strtoul(encoded_byte,
NULL, 16);
3074 const char *core_name =
CMD_ARGV[0];
3075 if (strcasecmp(core_name,
"LX") == 0) {
3092 if ((val < min) || (val > max)) {
3093 LOG_ERROR(
"xtopt %s (%d) out of range [%d..%d]\n", opt, val, min, max);
3105 const char *opt_name =
CMD_ARGV[0];
3107 if (strcasecmp(opt_name,
"arnum") == 0) {
3111 }
else if (strcasecmp(opt_name,
"windowed") == 0) {
3115 }
else if (strcasecmp(opt_name,
"cpenable") == 0) {
3119 }
else if (strcasecmp(opt_name,
"exceptions") == 0) {
3123 }
else if (strcasecmp(opt_name,
"intnum") == 0) {
3128 }
else if (strcasecmp(opt_name,
"hipriints") == 0) {
3132 }
else if (strcasecmp(opt_name,
"excmlevel") == 0) {
3136 LOG_ERROR(
"xtopt excmlevel requires hipriints\n");
3140 }
else if (strcasecmp(opt_name,
"intlevels") == 0) {
3149 LOG_ERROR(
"xtopt intlevels requires hipriints\n");
3153 }
else if (strcasecmp(opt_name,
"debuglevel") == 0) {
3163 }
else if (strcasecmp(opt_name,
"ibreaknum") == 0) {
3167 }
else if (strcasecmp(opt_name,
"dbreaknum") == 0) {
3171 }
else if (strcasecmp(opt_name,
"tracemem") == 0) {
3176 }
else if (strcasecmp(opt_name,
"tracememrev") == 0) {
3180 }
else if (strcasecmp(opt_name,
"perfcount") == 0) {
3204 bool is_dcache =
false;
3207 LOG_ERROR(
"xtmem <type> [parameters]\n");
3211 const char *mem_name =
CMD_ARGV[0];
3212 if (strcasecmp(mem_name,
"icache") == 0) {
3214 }
else if (strcasecmp(mem_name,
"dcache") == 0) {
3217 }
else if (strcasecmp(mem_name,
"l2cache") == 0) {
3219 }
else if (strcasecmp(mem_name,
"l2addr") == 0) {
3221 }
else if (strcasecmp(mem_name,
"iram") == 0) {
3224 }
else if (strcasecmp(mem_name,
"dram") == 0) {
3227 }
else if (strcasecmp(mem_name,
"sram") == 0) {
3230 }
else if (strcasecmp(mem_name,
"irom") == 0) {
3233 }
else if (strcasecmp(mem_name,
"drom") == 0) {
3236 }
else if (strcasecmp(mem_name,
"srom") == 0) {
3240 LOG_ERROR(
"xtmem types: <icache|dcache|l2cache|l2addr|iram|irom|dram|drom|sram|srom>\n");
3246 LOG_ERROR(
"xtmem <cachetype> <linebytes> <cachebytes> <ways> [writeback]\n");
3256 LOG_ERROR(
"xtmem <memtype> <baseaddr> <bytes>\n");
3262 memcfgp->
access = mem_access;
3279 LOG_ERROR(
"xtmpu <num FG seg> <min seg size> <lockable> <executeonly>\n");
3284 unsigned int minsegsize = strtoul(
CMD_ARGV[1],
NULL, 0);
3288 if ((nfgseg > 32)) {
3289 LOG_ERROR(
"<nfgseg> must be within [0..32]\n");
3291 }
else if (minsegsize & (minsegsize - 1)) {
3292 LOG_ERROR(
"<minsegsize> must be a power of 2 >= 32\n");
3294 }
else if (lockable > 1) {
3295 LOG_ERROR(
"<lockable> must be 0 or 1\n");
3297 }
else if (execonly > 1) {
3298 LOG_ERROR(
"<execonly> must be 0 or 1\n");
3320 LOG_ERROR(
"xtmmu <NIREFILLENTRIES> <NDREFILLENTRIES>\n");
3324 unsigned int nirefillentries = strtoul(
CMD_ARGV[0],
NULL, 0);
3325 unsigned int ndrefillentries = strtoul(
CMD_ARGV[1],
NULL, 0);
3326 if ((nirefillentries != 16) && (nirefillentries != 32)) {
3327 LOG_ERROR(
"<nirefillentries> must be 16 or 32\n");
3329 }
else if ((ndrefillentries != 16) && (ndrefillentries != 32)) {
3330 LOG_ERROR(
"<ndrefillentries> must be 16 or 32\n");
3352 if ((numregs <= 0) || (numregs > UINT16_MAX)) {
3353 LOG_ERROR(
"xtreg <numregs>: Invalid 'numregs' (%d)", numregs);
3357 LOG_ERROR(
"xtregs (%d) must be larger than numgenregs (%d) (if xtregfmt specified)",
3367 LOG_ERROR(
"Failed to allocate xtensa->optregs!");
3380 LOG_ERROR(
"Failed to allocate xtensa->contiguous_regs_desc!");
3387 if (regnum > UINT16_MAX) {
3388 LOG_ERROR(
"<regnum> must be a 16-bit number");
3394 LOG_ERROR(
"'xtreg %s 0x%04x': Too many registers (%d expected, %d core %d extended)",
3398 LOG_ERROR(
"'xtreg %s 0x%04x': Number of registers unspecified",
3405 bool is_extended_reg =
true;
3412 is_extended_reg =
false;
3418 if (is_extended_reg) {
3448 if ((strcmp(rptr->
name,
"mmid") == 0) || (strcmp(rptr->
name,
"eraccess") == 0) ||
3449 (strcmp(rptr->
name,
"ddr") == 0) || (strcmp(rptr->
name,
"intset") == 0) ||
3450 (strcmp(rptr->
name,
"intclear") == 0))
3460 }
else if (strcmp(rptr->
name,
"cpenable") == 0) {
3467 assert((running_reg_count <= xtensa->total_regs_num) &&
"contiguous register address internal error!");
3471 LOG_DEBUG(
"Added %s register %-16s: 0x%04x/0x%02x t%d (%d of %d)",
3472 is_extended_reg ?
"config-specific" :
"core",
3489 if (!strcasecmp(
CMD_ARGV[0],
"sparse")) {
3491 }
else if (!strcasecmp(
CMD_ARGV[0],
"contiguous")) {
3495 if ((numgregs <= 0) ||
3498 LOG_ERROR(
"xtregfmt: if specified, numgregs (%d) must be <= numregs (%d)",
3537 if (CMD_ARGC < 2 || CMD_ARGC > 6)
3540 unsigned int counter_id = strtoul(
CMD_ARGV[0],
NULL, 0);
3562 if (
config.kernelcnt > 1) {
3570 if (
config.tracelevel > 7) {
3576 if (
config.tracelevel == -1)
3594 int counter_id = -1;
3603 unsigned int counter_start = (counter_id < 0) ? 0 : counter_id;
3605 for (
unsigned int counter = counter_start; counter < counter_end; ++counter) {
3606 char result_buf[128] = { 0 };
3607 size_t result_pos = snprintf(result_buf,
sizeof(result_buf),
"Counter %d: ", counter);
3612 snprintf(result_buf + result_pos,
sizeof(result_buf) - result_pos,
3615 result.
overflow ?
" (overflow)" :
"");
3645 if (!strcasecmp(
CMD_ARGV[0],
"off"))
3647 else if (!strcasecmp(
CMD_ARGV[0],
"on"))
3670 for (
unsigned int i = 0; i <
CMD_ARGC; i++) {
3671 if (!strcasecmp(
CMD_ARGV[0],
"none")) {
3673 }
else if (!strcasecmp(
CMD_ARGV[i],
"BreakIn")) {
3675 }
else if (!strcasecmp(
CMD_ARGV[i],
"BreakOut")) {
3677 }
else if (!strcasecmp(
CMD_ARGV[i],
"RunStallIn")) {
3679 }
else if (!strcasecmp(
CMD_ARGV[i],
"DebugModeOut")) {
3681 }
else if (!strcasecmp(
CMD_ARGV[i],
"BreakInOut")) {
3683 }
else if (!strcasecmp(
CMD_ARGV[i],
"RunStall")) {
3689 "use either BreakInOut, None or RunStall as arguments, or any combination of BreakIn, BreakOut, RunStallIn and DebugModeOut.");
3725 .after_is_words =
false
3729 for (
unsigned int i = 0; i <
CMD_ARGC; i++) {
3740 }
else if (!strcasecmp(
CMD_ARGV[i],
"ins")) {
3742 }
else if (!strcasecmp(
CMD_ARGV[i],
"words")) {
3807 uint32_t memsz, wmem;
3828 LOG_INFO(
"Total trace memory: %d words", memsz);
3829 if ((trace_config.
addr &
3833 LOG_INFO(
"...but trace is only %d words", wmem);
3838 LOG_INFO(
"Real trace is many times longer than that (overflow)");
3842 LOG_INFO(
"Real trace is %d words, but the start has been truncated.", trc_sz);
3846 uint8_t *tracemem = malloc(memsz * 4);
3857 int f = open(fname, O_WRONLY | O_CREAT | O_TRUNC, 0666);
3863 if (write(f, tracemem, memsz * 4) != (
int)memsz * 4)
3866 command_print(
CMD,
"Written %d bytes of trace data to %s", memsz * 4, fname);
3869 bool is_all_zeroes =
true;
3870 for (
unsigned int i = 0; i < memsz * 4; i++) {
3871 if (tracemem[i] != 0) {
3872 is_all_zeroes =
false;
3880 "WARNING: File written is all zeroes. Are you sure you enabled trace memory?");
3888 command_print(
CMD,
"Command takes exactly 1 parameter.Need filename to dump to as output!");
3899 .handler = xtensa_cmd_xtdef,
3901 .help =
"Configure Xtensa core type",
3906 .handler = xtensa_cmd_xtopt,
3908 .help =
"Configure Xtensa core option",
3909 .usage =
"<name> <value>",
3913 .handler = xtensa_cmd_xtmem,
3915 .help =
"Configure Xtensa memory/cache option",
3916 .usage =
"<type> [parameters]",
3920 .handler = xtensa_cmd_xtmmu,
3922 .help =
"Configure Xtensa MMU option",
3923 .usage =
"<NIREFILLENTRIES> <NDREFILLENTRIES> <IVARWAY56> <DVARWAY56>",
3927 .handler = xtensa_cmd_xtmpu,
3929 .help =
"Configure Xtensa MPU option",
3930 .usage =
"<num FG seg> <min seg size> <lockable> <executeonly>",
3934 .handler = xtensa_cmd_xtreg,
3936 .help =
"Configure Xtensa register",
3937 .usage =
"<regname> <regnum>",
3941 .handler = xtensa_cmd_xtreg,
3943 .help =
"Configure number of Xtensa registers",
3944 .usage =
"<numregs>",
3948 .handler = xtensa_cmd_xtregfmt,
3950 .help =
"Configure format of Xtensa register map",
3951 .usage =
"<contiguous|sparse> [numgregs]",
3954 .name =
"set_permissive",
3955 .handler = xtensa_cmd_permissive_mode,
3957 .help =
"When set to 1, enable Xtensa permissive mode (fewer client-side checks)",
3962 .handler = xtensa_cmd_mask_interrupts,
3964 .help =
"mask Xtensa interrupts at step",
3965 .usage =
"['on'|'off']",
3969 .handler = xtensa_cmd_smpbreak,
3971 .help =
"Set the way the CPU chains OCD breaks",
3972 .usage =
"[none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]",
3975 .name =
"perfmon_enable",
3976 .handler = xtensa_cmd_perfmon_enable,
3978 .help =
"Enable and start performance counter",
3979 .usage =
"<counter_id> <select> [mask] [kernelcnt] [tracelevel]",
3982 .name =
"perfmon_dump",
3983 .handler = xtensa_cmd_perfmon_dump,
3985 .help =
"Dump performance counter value. If no argument specified, dumps all counters.",
3986 .usage =
"[counter_id]",
3989 .name =
"tracestart",
3990 .handler = xtensa_cmd_tracestart,
3993 "Tracing: Set up and start a trace. Optionally set stop trigger address and amount of data captured after.",
3994 .usage =
"[pc <pcval>/[maskbitcount]] [after <n> [ins|words]]",
3997 .name =
"tracestop",
3998 .handler = xtensa_cmd_tracestop,
4000 .help =
"Tracing: Stop current trace as started by the tracestart command",
4004 .name =
"tracedump",
4005 .handler = xtensa_cmd_tracedump,
4007 .help =
"Tracing: Dump trace memory to a files. One file per core.",
4008 .usage =
"<outfile>",
4012 .handler = xtensa_cmd_exe,
4014 .help =
"Xtensa stub execution",
4015 .usage =
"<ascii-encoded hexadecimal instruction bytes>",
4024 .help =
"Xtensa command group",
void * buf_cpy(const void *from, void *_to, unsigned size)
Copies size bits out of from and into to.
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
#define ERROR_COMMAND_ARGUMENT_INVALID
static struct device_config config
#define LOG_TARGET_INFO(target, fmt_str,...)
#define LOG_TARGET_WARNING(target, fmt_str,...)
#define LOG_WARNING(expr ...)
#define LOG_TARGET_ERROR(target, fmt_str,...)
#define LOG_TARGET_DEBUG(target, fmt_str,...)
#define LOG_ERROR(expr ...)
#define LOG_LEVEL_IS(FOO)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
void register_unlink_cache(struct reg_cache **cache_p, const struct reg_cache *cache)
void register_cache_invalidate(struct reg_cache *cache)
Marks the contents of the register cache as invalid (and clean).
size_t size
Size of the control block search area.
enum breakpoint_type type
int(* get)(struct reg *reg)
const struct reg_arch_type * type
enum target_debug_reason debug_reason
enum target_endianness endianness
struct reg_cache * reg_cache
bool examined
Indicates whether this target has been examined.
struct xtensa_cache_config dcache
struct xtensa_debug_config debug
struct xtensa_tracing_config trace
struct xtensa_local_mem_config irom
struct xtensa_local_mem_config drom
struct xtensa_mpu_config mpu
enum xtensa_type core_type
struct xtensa_cache_config icache
struct xtensa_local_mem_config iram
struct xtensa_high_prio_irq_config high_irq
struct xtensa_mmu_config mmu
struct xtensa_irq_config irq
struct xtensa_local_mem_config dram
struct xtensa_local_mem_config sram
struct xtensa_local_mem_config srom
struct xtensa_power_status power_status
const struct xtensa_power_ops * pwr_ops
struct xtensa_core_status core_status
struct xtensa_local_mem_region_config regions[XT_LOCAL_MEM_REGIONS_NUM_MAX]
uint8_t itlb_entries_count
uint8_t dtlb_entries_count
int(* queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
register write.
enum xtensa_reg_flags flags
enum xtensa_reg_type type
uint8_t insn[XT_ISNS_SZ_MAX]
struct breakpoint * oocd_bp
Represents a generic Xtensa core.
struct watchpoint ** hw_wps
uint8_t come_online_probes_num
struct xtensa_reg_desc ** contiguous_regs_desc
unsigned int total_regs_num
struct xtensa_debug_module dbg_mod
char qpkt_resp[XT_QUERYPKT_RESP_MAX]
struct reg ** contiguous_regs_list
struct xtensa_keyval_info_s scratch_ars[XT_AR_SCRATCH_NUM]
unsigned int eps_dbglevel_idx
void ** algo_context_backup
struct xtensa_sw_breakpoint * sw_brps
unsigned int genpkt_regs_num
enum xtensa_stepping_isr_mode stepping_isr_mode
struct reg_cache * core_cache
unsigned int core_regs_num
struct xtensa_reg_desc * optregs
struct breakpoint ** hw_brps
unsigned int common_magic
struct xtensa_config * core_config
int target_call_event_callbacks(struct target *target, enum target_event event)
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
struct target * get_current_target(struct command_context *cmd_ctx)
uint32_t target_buffer_get_u32(struct target *target, const uint8_t *buffer)
#define ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_EXAMINED
static const char * target_name(struct target *target)
Returns the instance-specific name of the specified target.
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
static void target_set_examined(struct target *target)
Sets the examined flag for the given target.
static bool target_was_examined(struct target *target)
#define ERROR_TARGET_FAILURE
#define DIV_ROUND_UP(m, n)
Rounds m up to the nearest multiple of n using division.
static void buf_bswap32(uint8_t *dst, const uint8_t *src, size_t len)
Byte-swap buffer 32-bit.
int xtensa_gdb_query_custom(struct target *target, const char *packet, char **response_p)
static const struct xtensa_keyval_info_s xt_qerr[XT_QERR_NUM]
#define XT_INS_RSR(X, SR, T)
static int xtensa_core_reg_set(struct reg *reg, uint8_t *buf)
static bool xtensa_memory_op_validate_range(struct xtensa *xtensa, target_addr_t address, size_t size, int access)
Check if the address gets to memory regions, and its access mode.
void xtensa_reg_set_deep_relgen(struct target *target, enum xtensa_reg_id a_idx, xtensa_reg_val_t value)
static COMMAND_HELPER(xtensa_cmd_exe_do, struct target *target)
#define XT_INS_L32E(X, R, S, T)
static void xtensa_mark_register_dirty(struct xtensa *xtensa, enum xtensa_reg_id reg_idx)
#define XT_INS_SDDR32P(X, S)
static bool xtensa_reg_is_readable(int flags, int cpenable)
static enum xtensa_reg_id xtensa_canonical_to_windowbase_offset(struct xtensa *xtensa, enum xtensa_reg_id reg_idx, int windowbase)
#define XT_INS_IHI(X, S, IMM8)
int xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint)
#define XT_HW_DBREAK_MAX_NUM
#define XT_WATCHPOINTS_NUM_MAX
void xtensa_target_deinit(struct target *target)
static const bool xtensa_extra_debug_log
int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint)
static int xtensa_queue_pwr_reg_write(struct xtensa *xtensa, unsigned int reg, uint32_t data)
static enum xtensa_reg_id xtensa_windowbase_offset_to_canonical(struct xtensa *xtensa, enum xtensa_reg_id reg_idx, int windowbase)
static bool xtensa_cmd_xtopt_legal_val(char *opt, int val, int min, int max)
#define XT_INS_WFR(X, FR, T)
uint32_t xtensa_cause_get(struct target *target)
const char * xtensa_get_gdb_arch(struct target *target)
#define XT_INS_RUR(X, UR, T)
xtensa_mem_region_type
Types of memory used at xtensa target.
int xtensa_do_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
#define XT_INS_ROTW(X, N)
static bool xtensa_pc_in_winexc(struct target *target, target_addr_t pc)
int xtensa_smpbreak_read(struct xtensa *xtensa, uint32_t *val)
int xtensa_poll(struct target *target)
int xtensa_prepare_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
#define XT_HW_IBREAK_MAX_NUM
int xtensa_halt(struct target *target)
static const struct command_registration xtensa_any_command_handlers[]
static void xtensa_reg_set_value(struct reg *reg, xtensa_reg_val_t value)
int xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint)
static bool xtensa_scratch_regs_fixup(struct xtensa *xtensa, struct reg *reg_list, int i, int j, int a_idx, int ar_idx)
int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer)
int xtensa_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int xtensa_target_init(struct command_context *cmd_ctx, struct target *target)
int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
#define XT_SW_BREAKPOINTS_MAX_NUM
const struct command_registration xtensa_command_handlers[]
int xtensa_smpbreak_set(struct target *target, uint32_t set)
static bool xtensa_memory_regions_overlap(target_addr_t r1_start, target_addr_t r1_end, target_addr_t r2_start, target_addr_t r2_end)
Returns true if two ranges are overlapping.
int xtensa_examine(struct target *target)
static void xtensa_free_reg_cache(struct target *target)
int xtensa_init_arch_info(struct target *target, struct xtensa *xtensa, const struct xtensa_debug_module_config *dm_cfg)
int xtensa_fetch_all_regs(struct target *target)
int xtensa_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
#define XT_INS_L32E_S32E_MASK(X)
int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoint)
int xtensa_write_buffer(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer)
static void xtensa_window_state_restore(struct target *target, uint32_t woe)
static void xtensa_queue_exec_ins(struct xtensa *xtensa, uint32_t ins)
static bool xtensa_is_icacheable(struct xtensa *xtensa, target_addr_t address)
static int xtensa_window_state_save(struct target *target, uint32_t *woe)
static bool xtensa_is_cacheable(const struct xtensa_cache_config *cache, const struct xtensa_local_mem_config *mem, target_addr_t address)
int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set)
int xtensa_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
void xtensa_reg_set(struct target *target, enum xtensa_reg_id reg_id, xtensa_reg_val_t value)
void xtensa_cause_clear(struct target *target)
#define XT_INS_L32I(X, S, T, IMM8)
COMMAND_HANDLER(xtensa_cmd_exe)
int xtensa_smpbreak_get(struct target *target, uint32_t *val)
struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS]
static int xtensa_core_reg_get(struct reg *reg)
int xtensa_core_status_check(struct target *target)
#define XT_INS_RFR(X, FR, T)
static int xtensa_update_instruction(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
static int32_t xtensa_gdbqc_parse_exec_tie_ops(struct target *target, char *opstr)
#define XT_INS_S32E(X, R, S, T)
int xtensa_do_resume(struct target *target)
#define XT_PC_REG_NUM_VIRTUAL
int xtensa_wakeup(struct target *target)
static xtensa_reg_val_t xtensa_reg_get_value(struct reg *reg)
int xtensa_mmu_is_enabled(struct target *target, int *enabled)
#define XT_INS_DHWBI(X, S, IMM8)
static const struct reg_arch_type xtensa_reg_type
static bool xtensa_is_stopped(struct target *target)
static int xtensa_gdbqc_qxtreg(struct target *target, const char *packet, char **response_p)
static int xtensa_write_dirty_registers(struct target *target)
void xtensa_set_permissive_mode(struct target *target, bool state)
#define XT_PC_DBREG_NUM_BASE
#define XT_INS_WUR(X, UR, T)
int xtensa_deassert_reset(struct target *target)
int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static const struct xtensa_local_mem_config * xtensa_get_mem_config(struct xtensa *xtensa, enum xtensa_mem_region_type type)
Gets a config for the specific mem type.
static int xtensa_sw_breakpoint_add(struct target *target, struct breakpoint *breakpoint, struct xtensa_sw_breakpoint *sw_bp)
static int xtensa_sw_breakpoint_remove(struct target *target, struct xtensa_sw_breakpoint *sw_bp)
static const struct xtensa_local_mem_region_config * xtensa_target_memory_region_find(struct xtensa *xtensa, target_addr_t address)
Returns a corresponding xtensa_local_mem_region_config from the xtensa target for a given address Ret...
int xtensa_soft_reset_halt(struct target *target)
#define XT_EPS_REG_NUM_BASE
static bool xtensa_is_dcacheable(struct xtensa *xtensa, target_addr_t address)
int xtensa_assert_reset(struct target *target)
#define XT_INS_S32I(X, S, T, IMM8)
#define XT_INS_LDDR32P(X, S)
#define XT_EPC_REG_NUM_BASE
static void xtensa_queue_exec_ins_wide(struct xtensa *xtensa, uint8_t *ops, uint8_t oplen)
static target_addr_t xtensa_get_overlap_size(target_addr_t r1_start, target_addr_t r1_end, target_addr_t r2_start, target_addr_t r2_end)
Returns a size of overlapped region of two ranges.
#define XT_INS_DHWB(X, S, IMM8)
static const struct xtensa_local_mem_region_config * xtensa_memory_region_find(const struct xtensa_local_mem_config *mem, target_addr_t address)
Extracts an exact xtensa_local_mem_region_config from xtensa_local_mem_config for a given address Ret...
static int xtensa_build_reg_cache(struct target *target)
#define XT_INS_WSR(X, SR, T)
#define XT_INS_RFWO_RFWU_MASK(X)
xtensa_reg_val_t xtensa_reg_get(struct target *target, enum xtensa_reg_id reg_id)
Holds the interface to Xtensa cores.
#define XT_MEM_ACCESS_READ
static struct xtensa * target_to_xtensa(struct target *target)
static int xtensa_queue_dbg_reg_write(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint32_t data)
#define XT_MEM_ACCESS_WRITE
#define XT_INS_BREAK(X, S, T)
#define XT_INS_BREAKN(X, IMM4)
#define XT_QUERYPKT_RESP_MAX
#define XTENSA_COMMON_MAGIC
static int xtensa_queue_dbg_reg_read(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint8_t *data)
int xtensa_dm_trace_status_read(struct xtensa_debug_module *dm, struct xtensa_trace_status *status)
int xtensa_dm_trace_start(struct xtensa_debug_module *dm, struct xtensa_trace_start_config *cfg)
int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable)
int xtensa_dm_power_status_read(struct xtensa_debug_module *dm, uint32_t clear)
int xtensa_dm_poll(struct xtensa_debug_module *dm)
int xtensa_dm_perfmon_enable(struct xtensa_debug_module *dm, int counter_id, const struct xtensa_perfmon_config *config)
void xtensa_dm_deinit(struct xtensa_debug_module *dm)
int xtensa_dm_trace_config_read(struct xtensa_debug_module *dm, struct xtensa_trace_config *config)
int xtensa_dm_trace_data_read(struct xtensa_debug_module *dm, uint8_t *dest, uint32_t size)
int xtensa_dm_core_status_clear(struct xtensa_debug_module *dm, xtensa_dsr_t bits)
int xtensa_dm_core_status_read(struct xtensa_debug_module *dm)
int xtensa_dm_queue_enable(struct xtensa_debug_module *dm)
int xtensa_dm_init(struct xtensa_debug_module *dm, const struct xtensa_debug_module_config *cfg)
int xtensa_dm_perfmon_dump(struct xtensa_debug_module *dm, int counter_id, struct xtensa_perfmon_result *out_result)
#define PWRSTAT_DEBUGWASRESET(x)
#define TRAXADDR_TWRAP_SHIFT
#define OCDDCR_DEBUGMODEOUTEN
static void xtensa_dm_power_status_cache(struct xtensa_debug_module *dm)
#define XTENSA_MAX_PERF_COUNTERS
#define OCDDSR_DEBUGPENDTRAX
#define OCDDCR_BREAKOUTEN
#define OCDDSR_DEBUGPENDHOST
static void xtensa_dm_queue_tdi_idle(struct xtensa_debug_module *dm)
static bool xtensa_dm_core_was_reset(struct xtensa_debug_module *dm)
#define OCDDSR_DEBUGINTTRAX
static xtensa_dsr_t xtensa_dm_core_status_get(struct xtensa_debug_module *dm)
#define OCDDSR_EXECEXCEPTION
static bool xtensa_dm_is_powered(struct xtensa_debug_module *dm)
#define PWRCTL_CORERESET(x)
#define TRAXADDR_TWRAP_MASK
#define XTENSA_MAX_PERF_SELECT
#define OCDDSR_DEBUGINTBREAK
static bool xtensa_dm_tap_was_reset(struct xtensa_debug_module *dm)
#define PWRCTL_MEMWAKEUP(x)
#define PWRCTL_JTAGDEBUGUSE(x)
static int xtensa_dm_queue_execute(struct xtensa_debug_module *dm)
#define PWRCTL_COREWAKEUP(x)
#define OCDDSR_DEBUGPENDBREAK
static bool xtensa_dm_is_online(struct xtensa_debug_module *dm)
#define OCDDSR_DEBUGINTHOST
#define PWRSTAT_COREWASRESET(x)
#define OCDDCR_DEBUGINTERRUPT
#define PWRCTL_DEBUGWAKEUP(x)
#define OCDDSR_EXECOVERRUN
#define XTENSA_STOPMASK_DISABLED
#define OCDDCR_RUNSTALLINEN
#define XTENSA_MAX_PERF_MASK
#define TRAXADDR_TADDR_MASK
@ XT_REG_IDX_IBREAKENABLE
uint32_t xtensa_reg_val_t
#define XT_MK_REG_DESC(n, r, t, f)