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xtensa_debug_module.h File Reference
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Data Structures

struct  xtensa_core_status
 
struct  xtensa_debug_module
 
struct  xtensa_debug_module_config
 
struct  xtensa_debug_ops
 
struct  xtensa_dm_pwr_reg_offsets
 
struct  xtensa_dm_reg_offsets
 
struct  xtensa_perfmon_config
 
struct  xtensa_perfmon_result
 
struct  xtensa_power_ops
 
struct  xtensa_power_status
 
struct  xtensa_trace_config
 
struct  xtensa_trace_start_config
 
struct  xtensa_trace_status
 

Macros

#define DEBUGCAUSE_BI   BIT(3) /* BREAK instruction encountered */
 
#define DEBUGCAUSE_BN   BIT(4) /* BREAK.N instruction encountered */
 
#define DEBUGCAUSE_DB   BIT(2) /* DBREAK exception */
 
#define DEBUGCAUSE_DI   BIT(5) /* Debug Interrupt */
 
#define DEBUGCAUSE_IB   BIT(1) /* IBREAK exception */
 
#define DEBUGCAUSE_IC   BIT(0) /* ICOUNT exception */
 
#define OCDDCR_BREAKACKITO   BIT(25)
 
#define OCDDCR_BREAKINEN   BIT(16)
 
#define OCDDCR_BREAKOUTEN   BIT(17)
 
#define OCDDCR_BREAKOUTITO   BIT(24)
 
#define OCDDCR_DEBUGINTERRUPT   BIT(1)
 
#define OCDDCR_DEBUGMODEOUTEN   BIT(22)
 
#define OCDDCR_DEBUGSWACTIVE   BIT(20)
 
#define OCDDCR_ENABLEOCD   BIT(0)
 
#define OCDDCR_INTERRUPTALLCONDS   BIT(2)
 
#define OCDDCR_RUNSTALLINEN   BIT(21)
 
#define OCDDSR_BREACKOUTACKITI   BIT(25)
 
#define OCDDSR_BREAKINITI   BIT(26)
 
#define OCDDSR_COREREADDDR   BIT(11)
 
#define OCDDSR_COREWROTEDDR   BIT(10)
 
#define OCDDSR_DBGMODPOWERON   BIT(31)
 
#define OCDDSR_DEBUGINTBREAK   BIT(20)
 
#define OCDDSR_DEBUGINTHOST   BIT(21)
 
#define OCDDSR_DEBUGINTTRAX   BIT(22)
 
#define OCDDSR_DEBUGPENDBREAK   BIT(16)
 
#define OCDDSR_DEBUGPENDHOST   BIT(17)
 
#define OCDDSR_DEBUGPENDTRAX   BIT(18)
 
#define OCDDSR_EXECBUSY   BIT(2)
 
#define OCDDSR_EXECDONE   BIT(0)
 
#define OCDDSR_EXECEXCEPTION   BIT(1)
 
#define OCDDSR_EXECOVERRUN   BIT(3)
 
#define OCDDSR_HOSTREADDDR   BIT(15)
 
#define OCDDSR_HOSTWROTEDDR   BIT(14)
 
#define OCDDSR_RUNSTALLSAMPLE   BIT(24)
 
#define OCDDSR_RUNSTALLTOGGLE   BIT(23)
 
#define OCDDSR_STOPPED   BIT(4)
 
#define PCMATCHCTRL_PCML_MASK   0x1F
 
#define PCMATCHCTRL_PCML_SHIFT   0 /* Amount of lower bits to ignore in pc trigger register */
 
#define PCMATCHCTRL_PCMS
 
#define PWRCTL_CORERESET(x)   (((x)->dbg_mod.dap) ? BIT(16) : BIT(4))
 
#define PWRCTL_COREWAKEUP(x)   (((x)->dbg_mod.dap) ? BIT(0) : BIT(0))
 
#define PWRCTL_DEBUGRESET(x)   (((x)->dbg_mod.dap) ? BIT(28) : BIT(6))
 
#define PWRCTL_DEBUGWAKEUP(x)   (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))
 
#define PWRCTL_JTAGDEBUGUSE(x)   (((x)->dbg_mod.dap) ? (0) : BIT(7))
 
#define PWRCTL_MEMWAKEUP(x)   (((x)->dbg_mod.dap) ? BIT(8) : BIT(1))
 
#define PWRSTAT_COREDOMAINON(x)   (((x)->dbg_mod.dap) ? BIT(0) : BIT(0))
 
#define PWRSTAT_CORESTILLNEEDED(x)   (((x)->dbg_mod.dap) ? BIT(4) : BIT(3))
 
#define PWRSTAT_COREWASRESET(x)   (PWRSTAT_COREWASRESET_DM(&((x)->dbg_mod)))
 
#define PWRSTAT_COREWASRESET_DM(d)   (((d)->dap) ? BIT(16) : BIT(4))
 
#define PWRSTAT_DEBUGDOMAINON(x)   (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))
 
#define PWRSTAT_DEBUGWASRESET(x)   (PWRSTAT_DEBUGWASRESET_DM(&((x)->dbg_mod)))
 
#define PWRSTAT_DEBUGWASRESET_DM(d)   (((d)->dap) ? BIT(28) : BIT(6))
 
#define PWRSTAT_MEMDOMAINON(x)   (((x)->dbg_mod.dap) ? BIT(8) : BIT(1))
 
#define TRAXADDR_TADDR_MASK   0x1FFFFF /* Actually is only as big as the trace buffer size max addr. */
 
#define TRAXADDR_TADDR_SHIFT   0 /* Trax memory address, in 32-bit words. */
 
#define TRAXADDR_TWRAP_MASK   0x3FF
 
#define TRAXADDR_TWRAP_SHIFT   21 /* Amount of times TADDR has overflown */
 
#define TRAXADDR_TWSAT   BIT(31) /* 1 if TWRAP has overflown, clear by disabling tren.*/
 
#define TRAXCTRL_ATEN   BIT(31) /* ATB interface enable */
 
#define TRAXCTRL_ATID_MASK   0x7F /* ARB source ID */
 
#define TRAXCTRL_ATID_SHIFT   24
 
#define TRAXCTRL_CNTU
 
#define TRAXCTRL_CTIEN   BIT(5) /* Cross-trigger enable */
 
#define TRAXCTRL_CTOWS   BIT(21) /* Cross-trigger Out enabled when trace stop completes */
 
#define TRAXCTRL_CTOWT   BIT(20) /* Cross-trigger Out enabled when stop triggered */
 
#define TRAXCTRL_ITATV   BIT(24) /* replaces ATID when in integration mode: ATVALID output */
 
#define TRAXCTRL_ITCTIA   BIT(23) /* Integration mode: cross-trigger ack */
 
#define TRAXCTRL_ITCTO   BIT(22) /* Integration mode: cross-trigger output */
 
#define TRAXCTRL_PCMEN   BIT(2) /* PC match enable */
 
#define TRAXCTRL_PTIEN   BIT(4) /* Processor-trigger enable */
 
#define TRAXCTRL_PTOWS   BIT(17) /* Processor Trigger Out (OCD halt) enabled when trace stop completes */
 
#define TRAXCTRL_PTOWT   BIT(16) /* Processor Trigger Out (OCD halt) enabled when stop triggered */
 
#define TRAXCTRL_SMPER_MASK   0x07 /* Synchronization message period */
 
#define TRAXCTRL_SMPER_SHIFT   12 /* Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg */
 
#define TRAXCTRL_TMEN   BIT(7) /* Tracemem Enable. Always set. */
 
#define TRAXCTRL_TREN   BIT(0) /* Trace enable. Tracing starts on 0->1 */
 
#define TRAXCTRL_TRSTP   BIT(1) /* Trace Stop. Make 1 to stop trace. */
 
#define TRAXCTRL_TSEN   BIT(11) /* Undocumented/deprecated? */
 
#define TRAXSTAT_CTITG   BIT(5) /* Stop trigger caused by Cross-Trigger Input. Clears on TREN 1->0 */
 
#define TRAXSTAT_CTO   BIT(17) /* Cross-Trigger Output: current value */
 
#define TRAXSTAT_ITATR   BIT(24) /* ATREADY Input: current value */
 
#define TRAXSTAT_ITCTI   BIT(23) /* Cross-Trigger Input: current value */
 
#define TRAXSTAT_ITCTOA   BIT(22) /* Cross-Trigger Out Ack: current value */
 
#define TRAXSTAT_MEMSZ_MASK   0x1F
 
#define TRAXSTAT_MEMSZ_SHIFT   8 /* Traceram size inducator. Usable trace ram is 2^MEMSZ bytes. */
 
#define TRAXSTAT_PCMTG   BIT(2) /* Stop trigger caused by PC match. Clears on TREN 1->0 */
 
#define TRAXSTAT_PJTR   BIT(3) /* JTAG transaction result. 1=err in preceding jtag transaction. */
 
#define TRAXSTAT_PTITG   BIT(4) /* Stop trigger caused by Processor Trigger Input.Clears on TREN 1->0 */
 
#define TRAXSTAT_PTO   BIT(16) /* Processor Trigger Output: current value */
 
#define TRAXSTAT_TRACT   BIT(0) /* Trace active flag. */
 
#define TRAXSTAT_TRIG   BIT(1) /* Trace stop trigger. Clears on TREN 1->0 */
 
#define XTENSA_DM_APB_ALIGN   0x4000
 
#define XTENSA_DM_PWR_REG_OFFSETS
 
#define XTENSA_DM_REG_OFFSETS
 
#define XTENSA_MAX_PERF_COUNTERS   2
 
#define XTENSA_MAX_PERF_MASK   0xffff
 
#define XTENSA_MAX_PERF_SELECT   32
 
#define XTENSA_STOPMASK_DISABLED   UINT32_MAX
 

Typedefs

typedef uint32_t xtensa_dsr_t
 
typedef uint32_t xtensa_ocdid_t
 
typedef uint32_t xtensa_pwrstat_t
 
typedef uint32_t xtensa_traxstat_t
 

Enumerations

enum  xtensa_dm_pwr_reg { XDMREG_PWRCTL = 0x00 , XDMREG_PWRSTAT , XDMREG_PWRNUM }
 
enum  xtensa_dm_reg {
  XDMREG_TRAXID = 0x00 , XDMREG_TRAXCTRL , XDMREG_TRAXSTAT , XDMREG_TRAXDATA ,
  XDMREG_TRAXADDR , XDMREG_TRIGGERPC , XDMREG_PCMATCHCTRL , XDMREG_DELAYCNT ,
  XDMREG_MEMADDRSTART , XDMREG_MEMADDREND , XDMREG_PMG , XDMREG_INTPC ,
  XDMREG_PM0 , XDMREG_PM1 , XDMREG_PM2 , XDMREG_PM3 ,
  XDMREG_PM4 , XDMREG_PM5 , XDMREG_PM6 , XDMREG_PM7 ,
  XDMREG_PMCTRL0 , XDMREG_PMCTRL1 , XDMREG_PMCTRL2 , XDMREG_PMCTRL3 ,
  XDMREG_PMCTRL4 , XDMREG_PMCTRL5 , XDMREG_PMCTRL6 , XDMREG_PMCTRL7 ,
  XDMREG_PMSTAT0 , XDMREG_PMSTAT1 , XDMREG_PMSTAT2 , XDMREG_PMSTAT3 ,
  XDMREG_PMSTAT4 , XDMREG_PMSTAT5 , XDMREG_PMSTAT6 , XDMREG_PMSTAT7 ,
  XDMREG_OCDID , XDMREG_DCRCLR , XDMREG_DCRSET , XDMREG_DSR ,
  XDMREG_DDR , XDMREG_DDREXEC , XDMREG_DIR0EXEC , XDMREG_DIR0 ,
  XDMREG_DIR1 , XDMREG_DIR2 , XDMREG_DIR3 , XDMREG_DIR4 ,
  XDMREG_DIR5 , XDMREG_DIR6 , XDMREG_DIR7 , XDMREG_ERISTAT ,
  XDMREG_ITCTRL , XDMREG_CLAIMSET , XDMREG_CLAIMCLR , XDMREG_LOCKACCESS ,
  XDMREG_LOCKSTATUS , XDMREG_AUTHSTATUS , XDMREG_DEVID , XDMREG_DEVTYPE ,
  XDMREG_PERID4 , XDMREG_PERID5 , XDMREG_PERID6 , XDMREG_PERID7 ,
  XDMREG_PERID0 , XDMREG_PERID1 , XDMREG_PERID2 , XDMREG_PERID3 ,
  XDMREG_COMPID0 , XDMREG_COMPID1 , XDMREG_COMPID2 , XDMREG_COMPID3 ,
  XDMREG_NUM
}
 

Functions

static bool xtensa_dm_core_is_stalled (struct xtensa_debug_module *dm)
 
int xtensa_dm_core_status_check (struct xtensa_debug_module *dm)
 
int xtensa_dm_core_status_clear (struct xtensa_debug_module *dm, xtensa_dsr_t bits)
 
static xtensa_dsr_t xtensa_dm_core_status_get (struct xtensa_debug_module *dm)
 
int xtensa_dm_core_status_read (struct xtensa_debug_module *dm)
 
static bool xtensa_dm_core_was_reset (struct xtensa_debug_module *dm)
 
void xtensa_dm_deinit (struct xtensa_debug_module *dm)
 
static xtensa_ocdid_t xtensa_dm_device_id_get (struct xtensa_debug_module *dm)
 
int xtensa_dm_device_id_read (struct xtensa_debug_module *dm)
 
int xtensa_dm_examine (struct xtensa_debug_module *dm)
 
int xtensa_dm_init (struct xtensa_debug_module *dm, const struct xtensa_debug_module_config *cfg)
 
static bool xtensa_dm_is_online (struct xtensa_debug_module *dm)
 
static bool xtensa_dm_is_powered (struct xtensa_debug_module *dm)
 
int xtensa_dm_perfmon_dump (struct xtensa_debug_module *dm, int counter_id, struct xtensa_perfmon_result *out_result)
 
int xtensa_dm_perfmon_enable (struct xtensa_debug_module *dm, int counter_id, const struct xtensa_perfmon_config *config)
 
int xtensa_dm_poll (struct xtensa_debug_module *dm)
 
static void xtensa_dm_power_status_cache (struct xtensa_debug_module *dm)
 
static void xtensa_dm_power_status_cache_reset (struct xtensa_debug_module *dm)
 
static xtensa_pwrstat_t xtensa_dm_power_status_get (struct xtensa_debug_module *dm)
 
int xtensa_dm_power_status_read (struct xtensa_debug_module *dm, uint32_t clear)
 
int xtensa_dm_queue_enable (struct xtensa_debug_module *dm)
 
static int xtensa_dm_queue_execute (struct xtensa_debug_module *dm)
 
int xtensa_dm_queue_pwr_reg_read (struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
 
int xtensa_dm_queue_pwr_reg_write (struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
 
int xtensa_dm_queue_reg_read (struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value)
 
int xtensa_dm_queue_reg_write (struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value)
 
static void xtensa_dm_queue_tdi_idle (struct xtensa_debug_module *dm)
 
static bool xtensa_dm_tap_was_reset (struct xtensa_debug_module *dm)
 
int xtensa_dm_trace_config_read (struct xtensa_debug_module *dm, struct xtensa_trace_config *config)
 
int xtensa_dm_trace_data_read (struct xtensa_debug_module *dm, uint8_t *dest, uint32_t size)
 
int xtensa_dm_trace_start (struct xtensa_debug_module *dm, struct xtensa_trace_start_config *cfg)
 
int xtensa_dm_trace_status_read (struct xtensa_debug_module *dm, struct xtensa_trace_status *status)
 
int xtensa_dm_trace_stop (struct xtensa_debug_module *dm, bool pto_enable)
 

Macro Definition Documentation

◆ DEBUGCAUSE_BI

#define DEBUGCAUSE_BI   BIT(3) /* BREAK instruction encountered */

Definition at line 281 of file xtensa_debug_module.h.

◆ DEBUGCAUSE_BN

#define DEBUGCAUSE_BN   BIT(4) /* BREAK.N instruction encountered */

Definition at line 282 of file xtensa_debug_module.h.

◆ DEBUGCAUSE_DB

#define DEBUGCAUSE_DB   BIT(2) /* DBREAK exception */

Definition at line 280 of file xtensa_debug_module.h.

◆ DEBUGCAUSE_DI

#define DEBUGCAUSE_DI   BIT(5) /* Debug Interrupt */

Definition at line 283 of file xtensa_debug_module.h.

◆ DEBUGCAUSE_IB

#define DEBUGCAUSE_IB   BIT(1) /* IBREAK exception */

Definition at line 279 of file xtensa_debug_module.h.

◆ DEBUGCAUSE_IC

#define DEBUGCAUSE_IC   BIT(0) /* ICOUNT exception */

Definition at line 278 of file xtensa_debug_module.h.

◆ OCDDCR_BREAKACKITO

#define OCDDCR_BREAKACKITO   BIT(25)

Definition at line 255 of file xtensa_debug_module.h.

◆ OCDDCR_BREAKINEN

#define OCDDCR_BREAKINEN   BIT(16)

Definition at line 249 of file xtensa_debug_module.h.

◆ OCDDCR_BREAKOUTEN

#define OCDDCR_BREAKOUTEN   BIT(17)

Definition at line 250 of file xtensa_debug_module.h.

◆ OCDDCR_BREAKOUTITO

#define OCDDCR_BREAKOUTITO   BIT(24)

Definition at line 254 of file xtensa_debug_module.h.

◆ OCDDCR_DEBUGINTERRUPT

#define OCDDCR_DEBUGINTERRUPT   BIT(1)

Definition at line 247 of file xtensa_debug_module.h.

◆ OCDDCR_DEBUGMODEOUTEN

#define OCDDCR_DEBUGMODEOUTEN   BIT(22)

Definition at line 253 of file xtensa_debug_module.h.

◆ OCDDCR_DEBUGSWACTIVE

#define OCDDCR_DEBUGSWACTIVE   BIT(20)

Definition at line 251 of file xtensa_debug_module.h.

◆ OCDDCR_ENABLEOCD

#define OCDDCR_ENABLEOCD   BIT(0)

Definition at line 246 of file xtensa_debug_module.h.

◆ OCDDCR_INTERRUPTALLCONDS

#define OCDDCR_INTERRUPTALLCONDS   BIT(2)

Definition at line 248 of file xtensa_debug_module.h.

◆ OCDDCR_RUNSTALLINEN

#define OCDDCR_RUNSTALLINEN   BIT(21)

Definition at line 252 of file xtensa_debug_module.h.

◆ OCDDSR_BREACKOUTACKITI

#define OCDDSR_BREACKOUTACKITI   BIT(25)

Definition at line 274 of file xtensa_debug_module.h.

◆ OCDDSR_BREAKINITI

#define OCDDSR_BREAKINITI   BIT(26)

Definition at line 275 of file xtensa_debug_module.h.

◆ OCDDSR_COREREADDDR

#define OCDDSR_COREREADDDR   BIT(11)

Definition at line 263 of file xtensa_debug_module.h.

◆ OCDDSR_COREWROTEDDR

#define OCDDSR_COREWROTEDDR   BIT(10)

Definition at line 262 of file xtensa_debug_module.h.

◆ OCDDSR_DBGMODPOWERON

#define OCDDSR_DBGMODPOWERON   BIT(31)

Definition at line 276 of file xtensa_debug_module.h.

◆ OCDDSR_DEBUGINTBREAK

#define OCDDSR_DEBUGINTBREAK   BIT(20)

Definition at line 269 of file xtensa_debug_module.h.

◆ OCDDSR_DEBUGINTHOST

#define OCDDSR_DEBUGINTHOST   BIT(21)

Definition at line 270 of file xtensa_debug_module.h.

◆ OCDDSR_DEBUGINTTRAX

#define OCDDSR_DEBUGINTTRAX   BIT(22)

Definition at line 271 of file xtensa_debug_module.h.

◆ OCDDSR_DEBUGPENDBREAK

#define OCDDSR_DEBUGPENDBREAK   BIT(16)

Definition at line 266 of file xtensa_debug_module.h.

◆ OCDDSR_DEBUGPENDHOST

#define OCDDSR_DEBUGPENDHOST   BIT(17)

Definition at line 267 of file xtensa_debug_module.h.

◆ OCDDSR_DEBUGPENDTRAX

#define OCDDSR_DEBUGPENDTRAX   BIT(18)

Definition at line 268 of file xtensa_debug_module.h.

◆ OCDDSR_EXECBUSY

#define OCDDSR_EXECBUSY   BIT(2)

Definition at line 259 of file xtensa_debug_module.h.

◆ OCDDSR_EXECDONE

#define OCDDSR_EXECDONE   BIT(0)

Definition at line 257 of file xtensa_debug_module.h.

◆ OCDDSR_EXECEXCEPTION

#define OCDDSR_EXECEXCEPTION   BIT(1)

Definition at line 258 of file xtensa_debug_module.h.

◆ OCDDSR_EXECOVERRUN

#define OCDDSR_EXECOVERRUN   BIT(3)

Definition at line 260 of file xtensa_debug_module.h.

◆ OCDDSR_HOSTREADDDR

#define OCDDSR_HOSTREADDDR   BIT(15)

Definition at line 265 of file xtensa_debug_module.h.

◆ OCDDSR_HOSTWROTEDDR

#define OCDDSR_HOSTWROTEDDR   BIT(14)

Definition at line 264 of file xtensa_debug_module.h.

◆ OCDDSR_RUNSTALLSAMPLE

#define OCDDSR_RUNSTALLSAMPLE   BIT(24)

Definition at line 273 of file xtensa_debug_module.h.

◆ OCDDSR_RUNSTALLTOGGLE

#define OCDDSR_RUNSTALLTOGGLE   BIT(23)

Definition at line 272 of file xtensa_debug_module.h.

◆ OCDDSR_STOPPED

#define OCDDSR_STOPPED   BIT(4)

Definition at line 261 of file xtensa_debug_module.h.

◆ PCMATCHCTRL_PCML_MASK

#define PCMATCHCTRL_PCML_MASK   0x1F

Definition at line 327 of file xtensa_debug_module.h.

◆ PCMATCHCTRL_PCML_SHIFT

#define PCMATCHCTRL_PCML_SHIFT   0 /* Amount of lower bits to ignore in pc trigger register */

Definition at line 326 of file xtensa_debug_module.h.

◆ PCMATCHCTRL_PCMS

#define PCMATCHCTRL_PCMS
Value:
BIT(31) /* PC Match Sense, 0-match when procs PC is in-range, 1-match when
* out-of-range */
#define BIT(nr)
Definition: stm32l4x.h:18

Definition at line 328 of file xtensa_debug_module.h.

◆ PWRCTL_CORERESET

#define PWRCTL_CORERESET (   x)    (((x)->dbg_mod.dap) ? BIT(16) : BIT(4))

Definition at line 51 of file xtensa_debug_module.h.

◆ PWRCTL_COREWAKEUP

#define PWRCTL_COREWAKEUP (   x)    (((x)->dbg_mod.dap) ? BIT(0) : BIT(0))

Definition at line 54 of file xtensa_debug_module.h.

◆ PWRCTL_DEBUGRESET

#define PWRCTL_DEBUGRESET (   x)    (((x)->dbg_mod.dap) ? BIT(28) : BIT(6))

Definition at line 50 of file xtensa_debug_module.h.

◆ PWRCTL_DEBUGWAKEUP

#define PWRCTL_DEBUGWAKEUP (   x)    (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))

Definition at line 52 of file xtensa_debug_module.h.

◆ PWRCTL_JTAGDEBUGUSE

#define PWRCTL_JTAGDEBUGUSE (   x)    (((x)->dbg_mod.dap) ? (0) : BIT(7))

Definition at line 49 of file xtensa_debug_module.h.

◆ PWRCTL_MEMWAKEUP

#define PWRCTL_MEMWAKEUP (   x)    (((x)->dbg_mod.dap) ? BIT(8) : BIT(1))

Definition at line 53 of file xtensa_debug_module.h.

◆ PWRSTAT_COREDOMAINON

#define PWRSTAT_COREDOMAINON (   x)    (((x)->dbg_mod.dap) ? BIT(0) : BIT(0))

Definition at line 63 of file xtensa_debug_module.h.

◆ PWRSTAT_CORESTILLNEEDED

#define PWRSTAT_CORESTILLNEEDED (   x)    (((x)->dbg_mod.dap) ? BIT(4) : BIT(3))

Definition at line 60 of file xtensa_debug_module.h.

◆ PWRSTAT_COREWASRESET

#define PWRSTAT_COREWASRESET (   x)    (PWRSTAT_COREWASRESET_DM(&((x)->dbg_mod)))

Definition at line 59 of file xtensa_debug_module.h.

◆ PWRSTAT_COREWASRESET_DM

#define PWRSTAT_COREWASRESET_DM (   d)    (((d)->dap) ? BIT(16) : BIT(4))

Definition at line 57 of file xtensa_debug_module.h.

◆ PWRSTAT_DEBUGDOMAINON

#define PWRSTAT_DEBUGDOMAINON (   x)    (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))

Definition at line 61 of file xtensa_debug_module.h.

◆ PWRSTAT_DEBUGWASRESET

#define PWRSTAT_DEBUGWASRESET (   x)    (PWRSTAT_DEBUGWASRESET_DM(&((x)->dbg_mod)))

Definition at line 58 of file xtensa_debug_module.h.

◆ PWRSTAT_DEBUGWASRESET_DM

#define PWRSTAT_DEBUGWASRESET_DM (   d)    (((d)->dap) ? BIT(28) : BIT(6))

Definition at line 56 of file xtensa_debug_module.h.

◆ PWRSTAT_MEMDOMAINON

#define PWRSTAT_MEMDOMAINON (   x)    (((x)->dbg_mod.dap) ? BIT(8) : BIT(1))

Definition at line 62 of file xtensa_debug_module.h.

◆ TRAXADDR_TADDR_MASK

#define TRAXADDR_TADDR_MASK   0x1FFFFF /* Actually is only as big as the trace buffer size max addr. */

Definition at line 321 of file xtensa_debug_module.h.

◆ TRAXADDR_TADDR_SHIFT

#define TRAXADDR_TADDR_SHIFT   0 /* Trax memory address, in 32-bit words. */

Definition at line 320 of file xtensa_debug_module.h.

◆ TRAXADDR_TWRAP_MASK

#define TRAXADDR_TWRAP_MASK   0x3FF

Definition at line 323 of file xtensa_debug_module.h.

◆ TRAXADDR_TWRAP_SHIFT

#define TRAXADDR_TWRAP_SHIFT   21 /* Amount of times TADDR has overflown */

Definition at line 322 of file xtensa_debug_module.h.

◆ TRAXADDR_TWSAT

#define TRAXADDR_TWSAT   BIT(31) /* 1 if TWRAP has overflown, clear by disabling tren.*/

Definition at line 324 of file xtensa_debug_module.h.

◆ TRAXCTRL_ATEN

#define TRAXCTRL_ATEN   BIT(31) /* ATB interface enable */

Definition at line 304 of file xtensa_debug_module.h.

◆ TRAXCTRL_ATID_MASK

#define TRAXCTRL_ATID_MASK   0x7F /* ARB source ID */

Definition at line 302 of file xtensa_debug_module.h.

◆ TRAXCTRL_ATID_SHIFT

#define TRAXCTRL_ATID_SHIFT   24

Definition at line 303 of file xtensa_debug_module.h.

◆ TRAXCTRL_CNTU

#define TRAXCTRL_CNTU
Value:
BIT(9) /* Post-stop-trigger countdown units; selects when DelayCount-- happens.
* 0 - every 32-bit word written to tracemem, 1 - every cpu instruction */

Definition at line 291 of file xtensa_debug_module.h.

◆ TRAXCTRL_CTIEN

#define TRAXCTRL_CTIEN   BIT(5) /* Cross-trigger enable */

Definition at line 289 of file xtensa_debug_module.h.

◆ TRAXCTRL_CTOWS

#define TRAXCTRL_CTOWS   BIT(21) /* Cross-trigger Out enabled when trace stop completes */

Definition at line 298 of file xtensa_debug_module.h.

◆ TRAXCTRL_CTOWT

#define TRAXCTRL_CTOWT   BIT(20) /* Cross-trigger Out enabled when stop triggered */

Definition at line 297 of file xtensa_debug_module.h.

◆ TRAXCTRL_ITATV

#define TRAXCTRL_ITATV   BIT(24) /* replaces ATID when in integration mode: ATVALID output */

Definition at line 301 of file xtensa_debug_module.h.

◆ TRAXCTRL_ITCTIA

#define TRAXCTRL_ITCTIA   BIT(23) /* Integration mode: cross-trigger ack */

Definition at line 300 of file xtensa_debug_module.h.

◆ TRAXCTRL_ITCTO

#define TRAXCTRL_ITCTO   BIT(22) /* Integration mode: cross-trigger output */

Definition at line 299 of file xtensa_debug_module.h.

◆ TRAXCTRL_PCMEN

#define TRAXCTRL_PCMEN   BIT(2) /* PC match enable */

Definition at line 287 of file xtensa_debug_module.h.

◆ TRAXCTRL_PTIEN

#define TRAXCTRL_PTIEN   BIT(4) /* Processor-trigger enable */

Definition at line 288 of file xtensa_debug_module.h.

◆ TRAXCTRL_PTOWS

#define TRAXCTRL_PTOWS   BIT(17) /* Processor Trigger Out (OCD halt) enabled when trace stop completes */

Definition at line 296 of file xtensa_debug_module.h.

◆ TRAXCTRL_PTOWT

#define TRAXCTRL_PTOWT   BIT(16) /* Processor Trigger Out (OCD halt) enabled when stop triggered */

Definition at line 295 of file xtensa_debug_module.h.

◆ TRAXCTRL_SMPER_MASK

#define TRAXCTRL_SMPER_MASK   0x07 /* Synchronization message period */

Definition at line 294 of file xtensa_debug_module.h.

◆ TRAXCTRL_SMPER_SHIFT

#define TRAXCTRL_SMPER_SHIFT   12 /* Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg */

Definition at line 293 of file xtensa_debug_module.h.

◆ TRAXCTRL_TMEN

#define TRAXCTRL_TMEN   BIT(7) /* Tracemem Enable. Always set. */

Definition at line 290 of file xtensa_debug_module.h.

◆ TRAXCTRL_TREN

#define TRAXCTRL_TREN   BIT(0) /* Trace enable. Tracing starts on 0->1 */

Definition at line 285 of file xtensa_debug_module.h.

◆ TRAXCTRL_TRSTP

#define TRAXCTRL_TRSTP   BIT(1) /* Trace Stop. Make 1 to stop trace. */

Definition at line 286 of file xtensa_debug_module.h.

◆ TRAXCTRL_TSEN

#define TRAXCTRL_TSEN   BIT(11) /* Undocumented/deprecated? */

Definition at line 292 of file xtensa_debug_module.h.

◆ TRAXSTAT_CTITG

#define TRAXSTAT_CTITG   BIT(5) /* Stop trigger caused by Cross-Trigger Input. Clears on TREN 1->0 */

Definition at line 311 of file xtensa_debug_module.h.

◆ TRAXSTAT_CTO

#define TRAXSTAT_CTO   BIT(17) /* Cross-Trigger Output: current value */

Definition at line 315 of file xtensa_debug_module.h.

◆ TRAXSTAT_ITATR

#define TRAXSTAT_ITATR   BIT(24) /* ATREADY Input: current value */

Definition at line 318 of file xtensa_debug_module.h.

◆ TRAXSTAT_ITCTI

#define TRAXSTAT_ITCTI   BIT(23) /* Cross-Trigger Input: current value */

Definition at line 317 of file xtensa_debug_module.h.

◆ TRAXSTAT_ITCTOA

#define TRAXSTAT_ITCTOA   BIT(22) /* Cross-Trigger Out Ack: current value */

Definition at line 316 of file xtensa_debug_module.h.

◆ TRAXSTAT_MEMSZ_MASK

#define TRAXSTAT_MEMSZ_MASK   0x1F

Definition at line 313 of file xtensa_debug_module.h.

◆ TRAXSTAT_MEMSZ_SHIFT

#define TRAXSTAT_MEMSZ_SHIFT   8 /* Traceram size inducator. Usable trace ram is 2^MEMSZ bytes. */

Definition at line 312 of file xtensa_debug_module.h.

◆ TRAXSTAT_PCMTG

#define TRAXSTAT_PCMTG   BIT(2) /* Stop trigger caused by PC match. Clears on TREN 1->0 */

Definition at line 308 of file xtensa_debug_module.h.

◆ TRAXSTAT_PJTR

#define TRAXSTAT_PJTR   BIT(3) /* JTAG transaction result. 1=err in preceding jtag transaction. */

Definition at line 309 of file xtensa_debug_module.h.

◆ TRAXSTAT_PTITG

#define TRAXSTAT_PTITG   BIT(4) /* Stop trigger caused by Processor Trigger Input.Clears on TREN 1->0 */

Definition at line 310 of file xtensa_debug_module.h.

◆ TRAXSTAT_PTO

#define TRAXSTAT_PTO   BIT(16) /* Processor Trigger Output: current value */

Definition at line 314 of file xtensa_debug_module.h.

◆ TRAXSTAT_TRACT

#define TRAXSTAT_TRACT   BIT(0) /* Trace active flag. */

Definition at line 306 of file xtensa_debug_module.h.

◆ TRAXSTAT_TRIG

#define TRAXSTAT_TRIG   BIT(1) /* Trace stop trigger. Clears on TREN 1->0 */

Definition at line 307 of file xtensa_debug_module.h.

◆ XTENSA_DM_APB_ALIGN

#define XTENSA_DM_APB_ALIGN   0x4000

Definition at line 243 of file xtensa_debug_module.h.

◆ XTENSA_DM_PWR_REG_OFFSETS

#define XTENSA_DM_PWR_REG_OFFSETS
Value:
{ \
/* Power/Reset Registers */ \
{ .apb = 0x3020 }, /* XDMREG_PWRCTL */ \
{ .apb = 0x3024 }, /* XDMREG_PWRSTAT */ \
}

Definition at line 32 of file xtensa_debug_module.h.

◆ XTENSA_DM_REG_OFFSETS

#define XTENSA_DM_REG_OFFSETS

Definition at line 159 of file xtensa_debug_module.h.

◆ XTENSA_MAX_PERF_COUNTERS

#define XTENSA_MAX_PERF_COUNTERS   2

Definition at line 330 of file xtensa_debug_module.h.

◆ XTENSA_MAX_PERF_MASK

#define XTENSA_MAX_PERF_MASK   0xffff

Definition at line 332 of file xtensa_debug_module.h.

◆ XTENSA_MAX_PERF_SELECT

#define XTENSA_MAX_PERF_SELECT   32

Definition at line 331 of file xtensa_debug_module.h.

◆ XTENSA_STOPMASK_DISABLED

#define XTENSA_STOPMASK_DISABLED   UINT32_MAX

Definition at line 334 of file xtensa_debug_module.h.

Typedef Documentation

◆ xtensa_dsr_t

typedef uint32_t xtensa_dsr_t

Definition at line 361 of file xtensa_debug_module.h.

◆ xtensa_ocdid_t

typedef uint32_t xtensa_ocdid_t

Definition at line 360 of file xtensa_debug_module.h.

◆ xtensa_pwrstat_t

typedef uint32_t xtensa_pwrstat_t

Definition at line 359 of file xtensa_debug_module.h.

◆ xtensa_traxstat_t

typedef uint32_t xtensa_traxstat_t

Definition at line 362 of file xtensa_debug_module.h.

Enumeration Type Documentation

◆ xtensa_dm_pwr_reg

Enumerator
XDMREG_PWRCTL 
XDMREG_PWRSTAT 
XDMREG_PWRNUM 

Definition at line 20 of file xtensa_debug_module.h.

◆ xtensa_dm_reg

Enumerator
XDMREG_TRAXID 
XDMREG_TRAXCTRL 
XDMREG_TRAXSTAT 
XDMREG_TRAXDATA 
XDMREG_TRAXADDR 
XDMREG_TRIGGERPC 
XDMREG_PCMATCHCTRL 
XDMREG_DELAYCNT 
XDMREG_MEMADDRSTART 
XDMREG_MEMADDREND 
XDMREG_PMG 
XDMREG_INTPC 
XDMREG_PM0 
XDMREG_PM1 
XDMREG_PM2 
XDMREG_PM3 
XDMREG_PM4 
XDMREG_PM5 
XDMREG_PM6 
XDMREG_PM7 
XDMREG_PMCTRL0 
XDMREG_PMCTRL1 
XDMREG_PMCTRL2 
XDMREG_PMCTRL3 
XDMREG_PMCTRL4 
XDMREG_PMCTRL5 
XDMREG_PMCTRL6 
XDMREG_PMCTRL7 
XDMREG_PMSTAT0 
XDMREG_PMSTAT1 
XDMREG_PMSTAT2 
XDMREG_PMSTAT3 
XDMREG_PMSTAT4 
XDMREG_PMSTAT5 
XDMREG_PMSTAT6 
XDMREG_PMSTAT7 
XDMREG_OCDID 
XDMREG_DCRCLR 
XDMREG_DCRSET 
XDMREG_DSR 
XDMREG_DDR 
XDMREG_DDREXEC 
XDMREG_DIR0EXEC 
XDMREG_DIR0 
XDMREG_DIR1 
XDMREG_DIR2 
XDMREG_DIR3 
XDMREG_DIR4 
XDMREG_DIR5 
XDMREG_DIR6 
XDMREG_DIR7 
XDMREG_ERISTAT 
XDMREG_ITCTRL 
XDMREG_CLAIMSET 
XDMREG_CLAIMCLR 
XDMREG_LOCKACCESS 
XDMREG_LOCKSTATUS 
XDMREG_AUTHSTATUS 
XDMREG_DEVID 
XDMREG_DEVTYPE 
XDMREG_PERID4 
XDMREG_PERID5 
XDMREG_PERID6 
XDMREG_PERID7 
XDMREG_PERID0 
XDMREG_PERID1 
XDMREG_PERID2 
XDMREG_PERID3 
XDMREG_COMPID0 
XDMREG_COMPID1 
XDMREG_COMPID2 
XDMREG_COMPID3 
XDMREG_NUM 

Definition at line 66 of file xtensa_debug_module.h.

Function Documentation

◆ xtensa_dm_core_is_stalled()

static bool xtensa_dm_core_is_stalled ( struct xtensa_debug_module dm)
inlinestatic

Definition at line 530 of file xtensa_debug_module.h.

Referenced by esp32_soc_reset(), and esp32s3_soc_reset().

◆ xtensa_dm_core_status_check()

int xtensa_dm_core_status_check ( struct xtensa_debug_module dm)

◆ xtensa_dm_core_status_clear()

◆ xtensa_dm_core_status_get()

static xtensa_dsr_t xtensa_dm_core_status_get ( struct xtensa_debug_module dm)
inlinestatic

Definition at line 493 of file xtensa_debug_module.h.

Referenced by xtensa_core_status_check(), xtensa_do_step(), and xtensa_halt().

◆ xtensa_dm_core_status_read()

◆ xtensa_dm_core_was_reset()

static bool xtensa_dm_core_was_reset ( struct xtensa_debug_module dm)
inlinestatic

Definition at line 524 of file xtensa_debug_module.h.

Referenced by xtensa_poll().

◆ xtensa_dm_deinit()

void xtensa_dm_deinit ( struct xtensa_debug_module dm)

Definition at line 86 of file xtensa_debug_module.c.

References dap_put_ap(), xtensa_debug_module::debug_ap, and NULL.

Referenced by xtensa_target_deinit().

◆ xtensa_dm_device_id_get()

static xtensa_ocdid_t xtensa_dm_device_id_get ( struct xtensa_debug_module dm)
inlinestatic

Definition at line 499 of file xtensa_debug_module.h.

◆ xtensa_dm_device_id_read()

◆ xtensa_dm_examine()

◆ xtensa_dm_init()

◆ xtensa_dm_is_online()

static bool xtensa_dm_is_online ( struct xtensa_debug_module dm)
inlinestatic

Definition at line 510 of file xtensa_debug_module.h.

Referenced by xtensa_examine().

◆ xtensa_dm_is_powered()

static bool xtensa_dm_is_powered ( struct xtensa_debug_module dm)
inlinestatic

Definition at line 535 of file xtensa_debug_module.h.

Referenced by xtensa_poll().

◆ xtensa_dm_perfmon_dump()

◆ xtensa_dm_perfmon_enable()

◆ xtensa_dm_poll()

int xtensa_dm_poll ( struct xtensa_debug_module dm)

◆ xtensa_dm_power_status_cache()

static void xtensa_dm_power_status_cache ( struct xtensa_debug_module dm)
inlinestatic

Definition at line 481 of file xtensa_debug_module.h.

Referenced by xtensa_poll().

◆ xtensa_dm_power_status_cache_reset()

static void xtensa_dm_power_status_cache_reset ( struct xtensa_debug_module dm)
inlinestatic

Definition at line 477 of file xtensa_debug_module.h.

◆ xtensa_dm_power_status_get()

static xtensa_pwrstat_t xtensa_dm_power_status_get ( struct xtensa_debug_module dm)
inlinestatic

Definition at line 485 of file xtensa_debug_module.h.

◆ xtensa_dm_power_status_read()

◆ xtensa_dm_queue_enable()

int xtensa_dm_queue_enable ( struct xtensa_debug_module dm)

◆ xtensa_dm_queue_execute()

◆ xtensa_dm_queue_pwr_reg_read()

◆ xtensa_dm_queue_pwr_reg_write()

◆ xtensa_dm_queue_reg_read()

◆ xtensa_dm_queue_reg_write()

◆ xtensa_dm_queue_tdi_idle()

◆ xtensa_dm_tap_was_reset()

static bool xtensa_dm_tap_was_reset ( struct xtensa_debug_module dm)
inlinestatic

Definition at line 518 of file xtensa_debug_module.h.

Referenced by xtensa_poll().

◆ xtensa_dm_trace_config_read()

◆ xtensa_dm_trace_data_read()

int xtensa_dm_trace_data_read ( struct xtensa_debug_module dm,
uint8_t *  dest,
uint32_t  size 
)

◆ xtensa_dm_trace_start()

◆ xtensa_dm_trace_status_read()

◆ xtensa_dm_trace_stop()