11 #ifndef OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H
12 #define OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H
32 #define XTENSA_DM_PWR_REG_OFFSETS { \
49 #define PWRCTL_JTAGDEBUGUSE(x) (((x)->dbg_mod.dap) ? (0) : BIT(7))
50 #define PWRCTL_DEBUGRESET(x) (((x)->dbg_mod.dap) ? BIT(28) : BIT(6))
51 #define PWRCTL_CORERESET(x) (((x)->dbg_mod.dap) ? BIT(16) : BIT(4))
52 #define PWRCTL_DEBUGWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))
53 #define PWRCTL_MEMWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(8) : BIT(1))
54 #define PWRCTL_COREWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(0) : BIT(0))
56 #define PWRSTAT_DEBUGWASRESET_DM(d) (((d)->dap) ? BIT(28) : BIT(6))
57 #define PWRSTAT_COREWASRESET_DM(d) (((d)->dap) ? BIT(16) : BIT(4))
58 #define PWRSTAT_DEBUGWASRESET(x) (PWRSTAT_DEBUGWASRESET_DM(&((x)->dbg_mod)))
59 #define PWRSTAT_COREWASRESET(x) (PWRSTAT_COREWASRESET_DM(&((x)->dbg_mod)))
60 #define PWRSTAT_CORESTILLNEEDED(x) (((x)->dbg_mod.dap) ? BIT(4) : BIT(3))
61 #define PWRSTAT_DEBUGDOMAINON(x) (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))
62 #define PWRSTAT_MEMDOMAINON(x) (((x)->dbg_mod.dap) ? BIT(8) : BIT(1))
63 #define PWRSTAT_COREDOMAINON(x) (((x)->dbg_mod.dap) ? BIT(0) : BIT(0))
159 #define XTENSA_DM_REG_OFFSETS { \
161 { .nar = 0x00, .apb = 0x0000 }, \
162 { .nar = 0x01, .apb = 0x0004 }, \
163 { .nar = 0x02, .apb = 0x0008 }, \
164 { .nar = 0x03, .apb = 0x000c }, \
165 { .nar = 0x04, .apb = 0x0010 }, \
166 { .nar = 0x05, .apb = 0x0014 }, \
167 { .nar = 0x06, .apb = 0x0018 }, \
168 { .nar = 0x07, .apb = 0x001c }, \
169 { .nar = 0x08, .apb = 0x0020 }, \
170 { .nar = 0x09, .apb = 0x0024 }, \
173 { .nar = 0x20, .apb = 0x1000 }, \
174 { .nar = 0x24, .apb = 0x1010 }, \
175 { .nar = 0x28, .apb = 0x1080 }, \
176 { .nar = 0x29, .apb = 0x1084 }, \
177 { .nar = 0x2a, .apb = 0x1088 }, \
178 { .nar = 0x2b, .apb = 0x108c }, \
179 { .nar = 0x2c, .apb = 0x1090 }, \
180 { .nar = 0x2d, .apb = 0x1094 }, \
181 { .nar = 0x2e, .apb = 0x1098 }, \
182 { .nar = 0x2f, .apb = 0x109c }, \
183 { .nar = 0x30, .apb = 0x1100 }, \
184 { .nar = 0x31, .apb = 0x1104 }, \
185 { .nar = 0x32, .apb = 0x1108 }, \
186 { .nar = 0x33, .apb = 0x110c }, \
187 { .nar = 0x34, .apb = 0x1110 }, \
188 { .nar = 0x35, .apb = 0x1114 }, \
189 { .nar = 0x36, .apb = 0x1118 }, \
190 { .nar = 0x37, .apb = 0x111c }, \
191 { .nar = 0x38, .apb = 0x1180 }, \
192 { .nar = 0x39, .apb = 0x1184 }, \
193 { .nar = 0x3a, .apb = 0x1188 }, \
194 { .nar = 0x3b, .apb = 0x118c }, \
195 { .nar = 0x3c, .apb = 0x1190 }, \
196 { .nar = 0x3d, .apb = 0x1194 }, \
197 { .nar = 0x3e, .apb = 0x1198 }, \
198 { .nar = 0x3f, .apb = 0x119c }, \
201 { .nar = 0x40, .apb = 0x2000 }, \
202 { .nar = 0x42, .apb = 0x2008 }, \
203 { .nar = 0x43, .apb = 0x200c }, \
204 { .nar = 0x44, .apb = 0x2010 }, \
205 { .nar = 0x45, .apb = 0x2014 }, \
206 { .nar = 0x46, .apb = 0x2018 }, \
207 { .nar = 0x47, .apb = 0x201c }, \
208 { .nar = 0x48, .apb = 0x2020 }, \
209 { .nar = 0x49, .apb = 0x2024 }, \
210 { .nar = 0x4a, .apb = 0x2028 }, \
211 { .nar = 0x4b, .apb = 0x202c }, \
212 { .nar = 0x4c, .apb = 0x2030 }, \
213 { .nar = 0x4d, .apb = 0x2034 }, \
214 { .nar = 0x4e, .apb = 0x2038 }, \
215 { .nar = 0x4f, .apb = 0x203c }, \
218 { .nar = 0x5a, .apb = 0x3028 }, \
221 { .nar = 0x60, .apb = 0x3f00 }, \
222 { .nar = 0x68, .apb = 0x3fa0 }, \
223 { .nar = 0x69, .apb = 0x3fa4 }, \
224 { .nar = 0x6c, .apb = 0x3fb0 }, \
225 { .nar = 0x6d, .apb = 0x3fb4 }, \
226 { .nar = 0x6e, .apb = 0x3fb8 }, \
227 { .nar = 0x72, .apb = 0x3fc8 }, \
228 { .nar = 0x73, .apb = 0x3fcc }, \
229 { .nar = 0x74, .apb = 0x3fd0 }, \
230 { .nar = 0x75, .apb = 0x3fd4 }, \
231 { .nar = 0x76, .apb = 0x3fd8 }, \
232 { .nar = 0x77, .apb = 0x3fdc }, \
233 { .nar = 0x78, .apb = 0x3fe0 }, \
234 { .nar = 0x79, .apb = 0x3fe4 }, \
235 { .nar = 0x7a, .apb = 0x3fe8 }, \
236 { .nar = 0x7b, .apb = 0x3fec }, \
237 { .nar = 0x7c, .apb = 0x3ff0 }, \
238 { .nar = 0x7d, .apb = 0x3ff4 }, \
239 { .nar = 0x7e, .apb = 0x3ff8 }, \
240 { .nar = 0x7f, .apb = 0x3ffc }, \
243 #define XTENSA_DM_APB_ALIGN 0x4000
246 #define OCDDCR_ENABLEOCD BIT(0)
247 #define OCDDCR_DEBUGINTERRUPT BIT(1)
248 #define OCDDCR_INTERRUPTALLCONDS BIT(2)
249 #define OCDDCR_BREAKINEN BIT(16)
250 #define OCDDCR_BREAKOUTEN BIT(17)
251 #define OCDDCR_DEBUGSWACTIVE BIT(20)
252 #define OCDDCR_RUNSTALLINEN BIT(21)
253 #define OCDDCR_DEBUGMODEOUTEN BIT(22)
254 #define OCDDCR_BREAKOUTITO BIT(24)
255 #define OCDDCR_BREAKACKITO BIT(25)
257 #define OCDDSR_EXECDONE BIT(0)
258 #define OCDDSR_EXECEXCEPTION BIT(1)
259 #define OCDDSR_EXECBUSY BIT(2)
260 #define OCDDSR_EXECOVERRUN BIT(3)
261 #define OCDDSR_STOPPED BIT(4)
262 #define OCDDSR_COREWROTEDDR BIT(10)
263 #define OCDDSR_COREREADDDR BIT(11)
264 #define OCDDSR_HOSTWROTEDDR BIT(14)
265 #define OCDDSR_HOSTREADDDR BIT(15)
266 #define OCDDSR_DEBUGPENDBREAK BIT(16)
267 #define OCDDSR_DEBUGPENDHOST BIT(17)
268 #define OCDDSR_DEBUGPENDTRAX BIT(18)
269 #define OCDDSR_DEBUGINTBREAK BIT(20)
270 #define OCDDSR_DEBUGINTHOST BIT(21)
271 #define OCDDSR_DEBUGINTTRAX BIT(22)
272 #define OCDDSR_RUNSTALLTOGGLE BIT(23)
273 #define OCDDSR_RUNSTALLSAMPLE BIT(24)
274 #define OCDDSR_BREACKOUTACKITI BIT(25)
275 #define OCDDSR_BREAKINITI BIT(26)
276 #define OCDDSR_DBGMODPOWERON BIT(31)
278 #define DEBUGCAUSE_IC BIT(0)
279 #define DEBUGCAUSE_IB BIT(1)
280 #define DEBUGCAUSE_DB BIT(2)
281 #define DEBUGCAUSE_BI BIT(3)
282 #define DEBUGCAUSE_BN BIT(4)
283 #define DEBUGCAUSE_DI BIT(5)
285 #define TRAXCTRL_TREN BIT(0)
286 #define TRAXCTRL_TRSTP BIT(1)
287 #define TRAXCTRL_PCMEN BIT(2)
288 #define TRAXCTRL_PTIEN BIT(4)
289 #define TRAXCTRL_CTIEN BIT(5)
290 #define TRAXCTRL_TMEN BIT(7)
291 #define TRAXCTRL_CNTU BIT(9)
293 #define TRAXCTRL_TSEN BIT(11)
294 #define TRAXCTRL_SMPER_SHIFT 12
295 #define TRAXCTRL_SMPER_MASK 0x07
296 #define TRAXCTRL_PTOWT BIT(16)
297 #define TRAXCTRL_PTOWS BIT(17)
298 #define TRAXCTRL_CTOWT BIT(20)
299 #define TRAXCTRL_CTOWS BIT(21)
300 #define TRAXCTRL_ITCTO BIT(22)
301 #define TRAXCTRL_ITCTIA BIT(23)
302 #define TRAXCTRL_ITATV BIT(24)
303 #define TRAXCTRL_ATID_MASK 0x7F
304 #define TRAXCTRL_ATID_SHIFT 24
305 #define TRAXCTRL_ATEN BIT(31)
307 #define TRAXSTAT_TRACT BIT(0)
308 #define TRAXSTAT_TRIG BIT(1)
309 #define TRAXSTAT_PCMTG BIT(2)
310 #define TRAXSTAT_PJTR BIT(3)
311 #define TRAXSTAT_PTITG BIT(4)
312 #define TRAXSTAT_CTITG BIT(5)
313 #define TRAXSTAT_MEMSZ_SHIFT 8
314 #define TRAXSTAT_MEMSZ_MASK 0x1F
315 #define TRAXSTAT_PTO BIT(16)
316 #define TRAXSTAT_CTO BIT(17)
317 #define TRAXSTAT_ITCTOA BIT(22)
318 #define TRAXSTAT_ITCTI BIT(23)
319 #define TRAXSTAT_ITATR BIT(24)
321 #define TRAXADDR_TADDR_SHIFT 0
322 #define TRAXADDR_TADDR_MASK 0x1FFFFF
323 #define TRAXADDR_TWRAP_SHIFT 21
324 #define TRAXADDR_TWRAP_MASK 0x3FF
325 #define TRAXADDR_TWSAT BIT(31)
327 #define PCMATCHCTRL_PCML_SHIFT 0
328 #define PCMATCHCTRL_PCML_MASK 0x1F
329 #define PCMATCHCTRL_PCMS BIT(31)
332 #define XTENSA_MAX_PERF_COUNTERS 2
333 #define XTENSA_MAX_PERF_SELECT 32
334 #define XTENSA_MAX_PERF_MASK 0xffff
336 #define XTENSA_STOPMASK_DISABLED UINT32_MAX
This defines formats and data structures used to talk to ADIv5 entities.
static int dap_run(struct adiv5_dap *dap)
Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they ar...
static struct device_config config
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
The JTAG interface can be implemented with a software or hardware fifo.
size_t size
Size of the control block search area.
This represents an ARM Debug Interface (v5) Access Port (AP).
This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
struct adiv5_ap * debug_ap
void(* queue_tdi_idle)(struct target *target)
const struct xtensa_debug_ops * dbg_ops
const struct xtensa_power_ops * pwr_ops
void * queue_tdi_idle_arg
struct xtensa_power_status power_status
void(* queue_tdi_idle)(struct target *target)
const struct xtensa_power_ops * pwr_ops
struct xtensa_core_status core_status
void * queue_tdi_idle_arg
const struct xtensa_debug_ops * dbg_ops
struct adiv5_ap * debug_ap
int(* queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t data)
register write.
int(* queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *data)
register read.
int(* queue_enable)(struct xtensa_debug_module *dm)
enable operation
int(* queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
register read.
int(* queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
register write.
xtensa_pwrstat_t prev_stat
static void xtensa_dm_power_status_cache(struct xtensa_debug_module *dm)
int xtensa_dm_trace_status_read(struct xtensa_debug_module *dm, struct xtensa_trace_status *status)
int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value)
int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
static xtensa_ocdid_t xtensa_dm_device_id_get(struct xtensa_debug_module *dm)
int xtensa_dm_trace_start(struct xtensa_debug_module *dm, struct xtensa_trace_start_config *cfg)
int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable)
int xtensa_dm_device_id_read(struct xtensa_debug_module *dm)
int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value)
#define OCDDSR_DBGMODPOWERON
static void xtensa_dm_power_status_cache_reset(struct xtensa_debug_module *dm)
uint32_t xtensa_pwrstat_t
static void xtensa_dm_queue_tdi_idle(struct xtensa_debug_module *dm)
static bool xtensa_dm_core_was_reset(struct xtensa_debug_module *dm)
#define PWRSTAT_COREWASRESET_DM(d)
static xtensa_dsr_t xtensa_dm_core_status_get(struct xtensa_debug_module *dm)
static bool xtensa_dm_is_powered(struct xtensa_debug_module *dm)
int xtensa_dm_power_status_read(struct xtensa_debug_module *dm, uint32_t clear)
int xtensa_dm_poll(struct xtensa_debug_module *dm)
static bool xtensa_dm_tap_was_reset(struct xtensa_debug_module *dm)
int xtensa_dm_perfmon_enable(struct xtensa_debug_module *dm, int counter_id, const struct xtensa_perfmon_config *config)
int xtensa_dm_core_status_check(struct xtensa_debug_module *dm)
void xtensa_dm_deinit(struct xtensa_debug_module *dm)
static int xtensa_dm_queue_execute(struct xtensa_debug_module *dm)
static bool xtensa_dm_core_is_stalled(struct xtensa_debug_module *dm)
int xtensa_dm_trace_config_read(struct xtensa_debug_module *dm, struct xtensa_trace_config *config)
#define OCDDSR_RUNSTALLSAMPLE
int xtensa_dm_trace_data_read(struct xtensa_debug_module *dm, uint8_t *dest, uint32_t size)
int xtensa_dm_core_status_clear(struct xtensa_debug_module *dm, xtensa_dsr_t bits)
#define PWRSTAT_DEBUGWASRESET_DM(d)
int xtensa_dm_core_status_read(struct xtensa_debug_module *dm)
static bool xtensa_dm_is_online(struct xtensa_debug_module *dm)
static xtensa_pwrstat_t xtensa_dm_power_status_get(struct xtensa_debug_module *dm)
int xtensa_dm_queue_enable(struct xtensa_debug_module *dm)
int xtensa_dm_init(struct xtensa_debug_module *dm, const struct xtensa_debug_module_config *cfg)
int xtensa_dm_examine(struct xtensa_debug_module *dm)
uint32_t xtensa_traxstat_t
int xtensa_dm_perfmon_dump(struct xtensa_debug_module *dm, int counter_id, struct xtensa_perfmon_result *out_result)