OpenOCD
xtensa_debug_module.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Xtensa Debug Module (XDM) Support for OpenOCD *
5  * Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
6  * Copyright (C) 2019 Espressif Systems Ltd. *
7  * Derived from original ESP8266 target. *
8  * Author: Angus Gratton gus@projectgus.com *
9  ***************************************************************************/
10 
11 #ifndef OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H
12 #define OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H
13 
14 #include <jtag/jtag.h>
15 #include <target/arm_adi_v5.h>
16 #include <helper/bits.h>
17 #include <target/target.h>
18 
19 /* Virtual IDs for using with xtensa_power_ops API */
21  XDMREG_PWRCTL = 0x00,
24 };
25 
26 /* Debug Module Power Register offsets within APB */
28  uint16_t apb;
29 };
30 
31 /* Debug Module Power Register offset structure; must include XDMREG_PWRNUM entries */
32 #define XTENSA_DM_PWR_REG_OFFSETS { \
33  /* Power/Reset Registers */ \
34  { .apb = 0x3020 }, /* XDMREG_PWRCTL */ \
35  { .apb = 0x3024 }, /* XDMREG_PWRSTAT */ \
36 }
37 
38 /*
39  From the manual:
40  To properly use Debug registers through JTAG, software must ensure that:
41  - Tap is out of reset
42  - Xtensa Debug Module is out of reset
43  - Other bits of PWRCTL are set to their desired values, and finally
44  - JtagDebugUse transitions from 0 to 1
45  The bit must continue to be 1 in order for JTAG accesses to the Debug
46  Module to happen correctly. When it is set, any write to this bit clears it.
47  Either don't access it, or re-write it to 1 so JTAG accesses continue.
48 */
49 #define PWRCTL_JTAGDEBUGUSE(x) (((x)->dbg_mod.dap) ? (0) : BIT(7))
50 #define PWRCTL_DEBUGRESET(x) (((x)->dbg_mod.dap) ? BIT(28) : BIT(6))
51 #define PWRCTL_CORERESET(x) (((x)->dbg_mod.dap) ? BIT(16) : BIT(4))
52 #define PWRCTL_DEBUGWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))
53 #define PWRCTL_MEMWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(8) : BIT(1))
54 #define PWRCTL_COREWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(0) : BIT(0))
55 
56 #define PWRSTAT_DEBUGWASRESET_DM(d) (((d)->dap) ? BIT(28) : BIT(6))
57 #define PWRSTAT_COREWASRESET_DM(d) (((d)->dap) ? BIT(16) : BIT(4))
58 #define PWRSTAT_DEBUGWASRESET(x) (PWRSTAT_DEBUGWASRESET_DM(&((x)->dbg_mod)))
59 #define PWRSTAT_COREWASRESET(x) (PWRSTAT_COREWASRESET_DM(&((x)->dbg_mod)))
60 #define PWRSTAT_CORESTILLNEEDED(x) (((x)->dbg_mod.dap) ? BIT(4) : BIT(3))
61 #define PWRSTAT_DEBUGDOMAINON(x) (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))
62 #define PWRSTAT_MEMDOMAINON(x) (((x)->dbg_mod.dap) ? BIT(8) : BIT(1))
63 #define PWRSTAT_COREDOMAINON(x) (((x)->dbg_mod.dap) ? BIT(0) : BIT(0))
64 
65 /* Virtual IDs for using with xtensa_debug_ops API */
67  /* TRAX Registers */
68  XDMREG_TRAXID = 0x00,
78 
79  /* Performance Monitor Registers */
106 
107  /* OCD Registers */
123 
124  /* Misc Registers */
126 
127  /* CoreSight Registers */
148 
149  XDMREG_NUM
150 };
151 
152 /* Debug Module Register offsets within Nexus (NAR) or APB */
154  uint8_t nar;
155  uint16_t apb;
156 };
157 
158 /* Debug Module Register offset structure; must include XDMREG_NUM entries */
159 #define XTENSA_DM_REG_OFFSETS { \
160  /* TRAX Registers */ \
161  { .nar = 0x00, .apb = 0x0000 }, /* XDMREG_TRAXID */ \
162  { .nar = 0x01, .apb = 0x0004 }, /* XDMREG_TRAXCTRL */ \
163  { .nar = 0x02, .apb = 0x0008 }, /* XDMREG_TRAXSTAT */ \
164  { .nar = 0x03, .apb = 0x000c }, /* XDMREG_TRAXDATA */ \
165  { .nar = 0x04, .apb = 0x0010 }, /* XDMREG_TRAXADDR */ \
166  { .nar = 0x05, .apb = 0x0014 }, /* XDMREG_TRIGGERPC */ \
167  { .nar = 0x06, .apb = 0x0018 }, /* XDMREG_PCMATCHCTRL */ \
168  { .nar = 0x07, .apb = 0x001c }, /* XDMREG_DELAYCNT */ \
169  { .nar = 0x08, .apb = 0x0020 }, /* XDMREG_MEMADDRSTART */ \
170  { .nar = 0x09, .apb = 0x0024 }, /* XDMREG_MEMADDREND */ \
171  \
172  /* Performance Monitor Registers */ \
173  { .nar = 0x20, .apb = 0x1000 }, /* XDMREG_PMG */ \
174  { .nar = 0x24, .apb = 0x1010 }, /* XDMREG_INTPC */ \
175  { .nar = 0x28, .apb = 0x1080 }, /* XDMREG_PM0 */ \
176  { .nar = 0x29, .apb = 0x1084 }, /* XDMREG_PM1 */ \
177  { .nar = 0x2a, .apb = 0x1088 }, /* XDMREG_PM2 */ \
178  { .nar = 0x2b, .apb = 0x108c }, /* XDMREG_PM3 */ \
179  { .nar = 0x2c, .apb = 0x1090 }, /* XDMREG_PM4 */ \
180  { .nar = 0x2d, .apb = 0x1094 }, /* XDMREG_PM5 */ \
181  { .nar = 0x2e, .apb = 0x1098 }, /* XDMREG_PM6 */ \
182  { .nar = 0x2f, .apb = 0x109c }, /* XDMREG_PM7 */ \
183  { .nar = 0x30, .apb = 0x1100 }, /* XDMREG_PMCTRL0 */ \
184  { .nar = 0x31, .apb = 0x1104 }, /* XDMREG_PMCTRL1 */ \
185  { .nar = 0x32, .apb = 0x1108 }, /* XDMREG_PMCTRL2 */ \
186  { .nar = 0x33, .apb = 0x110c }, /* XDMREG_PMCTRL3 */ \
187  { .nar = 0x34, .apb = 0x1110 }, /* XDMREG_PMCTRL4 */ \
188  { .nar = 0x35, .apb = 0x1114 }, /* XDMREG_PMCTRL5 */ \
189  { .nar = 0x36, .apb = 0x1118 }, /* XDMREG_PMCTRL6 */ \
190  { .nar = 0x37, .apb = 0x111c }, /* XDMREG_PMCTRL7 */ \
191  { .nar = 0x38, .apb = 0x1180 }, /* XDMREG_PMSTAT0 */ \
192  { .nar = 0x39, .apb = 0x1184 }, /* XDMREG_PMSTAT1 */ \
193  { .nar = 0x3a, .apb = 0x1188 }, /* XDMREG_PMSTAT2 */ \
194  { .nar = 0x3b, .apb = 0x118c }, /* XDMREG_PMSTAT3 */ \
195  { .nar = 0x3c, .apb = 0x1190 }, /* XDMREG_PMSTAT4 */ \
196  { .nar = 0x3d, .apb = 0x1194 }, /* XDMREG_PMSTAT5 */ \
197  { .nar = 0x3e, .apb = 0x1198 }, /* XDMREG_PMSTAT6 */ \
198  { .nar = 0x3f, .apb = 0x119c }, /* XDMREG_PMSTAT7 */ \
199  \
200  /* OCD Registers */ \
201  { .nar = 0x40, .apb = 0x2000 }, /* XDMREG_OCDID */ \
202  { .nar = 0x42, .apb = 0x2008 }, /* XDMREG_DCRCLR */ \
203  { .nar = 0x43, .apb = 0x200c }, /* XDMREG_DCRSET */ \
204  { .nar = 0x44, .apb = 0x2010 }, /* XDMREG_DSR */ \
205  { .nar = 0x45, .apb = 0x2014 }, /* XDMREG_DDR */ \
206  { .nar = 0x46, .apb = 0x2018 }, /* XDMREG_DDREXEC */ \
207  { .nar = 0x47, .apb = 0x201c }, /* XDMREG_DIR0EXEC */ \
208  { .nar = 0x48, .apb = 0x2020 }, /* XDMREG_DIR0 */ \
209  { .nar = 0x49, .apb = 0x2024 }, /* XDMREG_DIR1 */ \
210  { .nar = 0x4a, .apb = 0x2028 }, /* XDMREG_DIR2 */ \
211  { .nar = 0x4b, .apb = 0x202c }, /* XDMREG_DIR3 */ \
212  { .nar = 0x4c, .apb = 0x2030 }, /* XDMREG_DIR4 */ \
213  { .nar = 0x4d, .apb = 0x2034 }, /* XDMREG_DIR5 */ \
214  { .nar = 0x4e, .apb = 0x2038 }, /* XDMREG_DIR6 */ \
215  { .nar = 0x4f, .apb = 0x203c }, /* XDMREG_DIR7 */ \
216  \
217  /* Misc Registers */ \
218  { .nar = 0x5a, .apb = 0x3028 }, /* XDMREG_ERISTAT */ \
219  \
220  /* CoreSight Registers */ \
221  { .nar = 0x60, .apb = 0x3f00 }, /* XDMREG_ITCTRL */ \
222  { .nar = 0x68, .apb = 0x3fa0 }, /* XDMREG_CLAIMSET */ \
223  { .nar = 0x69, .apb = 0x3fa4 }, /* XDMREG_CLAIMCLR */ \
224  { .nar = 0x6c, .apb = 0x3fb0 }, /* XDMREG_LOCKACCESS */ \
225  { .nar = 0x6d, .apb = 0x3fb4 }, /* XDMREG_LOCKSTATUS */ \
226  { .nar = 0x6e, .apb = 0x3fb8 }, /* XDMREG_AUTHSTATUS */ \
227  { .nar = 0x72, .apb = 0x3fc8 }, /* XDMREG_DEVID */ \
228  { .nar = 0x73, .apb = 0x3fcc }, /* XDMREG_DEVTYPE */ \
229  { .nar = 0x74, .apb = 0x3fd0 }, /* XDMREG_PERID4 */ \
230  { .nar = 0x75, .apb = 0x3fd4 }, /* XDMREG_PERID5 */ \
231  { .nar = 0x76, .apb = 0x3fd8 }, /* XDMREG_PERID6 */ \
232  { .nar = 0x77, .apb = 0x3fdc }, /* XDMREG_PERID7 */ \
233  { .nar = 0x78, .apb = 0x3fe0 }, /* XDMREG_PERID0 */ \
234  { .nar = 0x79, .apb = 0x3fe4 }, /* XDMREG_PERID1 */ \
235  { .nar = 0x7a, .apb = 0x3fe8 }, /* XDMREG_PERID2 */ \
236  { .nar = 0x7b, .apb = 0x3fec }, /* XDMREG_PERID3 */ \
237  { .nar = 0x7c, .apb = 0x3ff0 }, /* XDMREG_COMPID0 */ \
238  { .nar = 0x7d, .apb = 0x3ff4 }, /* XDMREG_COMPID1 */ \
239  { .nar = 0x7e, .apb = 0x3ff8 }, /* XDMREG_COMPID2 */ \
240  { .nar = 0x7f, .apb = 0x3ffc }, /* XDMREG_COMPID3 */ \
241 }
242 
243 #define XTENSA_DM_APB_ALIGN 0x4000
244 
245 /* OCD registers, bit definitions */
246 #define OCDDCR_ENABLEOCD BIT(0)
247 #define OCDDCR_DEBUGINTERRUPT BIT(1)
248 #define OCDDCR_INTERRUPTALLCONDS BIT(2)
249 #define OCDDCR_BREAKINEN BIT(16)
250 #define OCDDCR_BREAKOUTEN BIT(17)
251 #define OCDDCR_DEBUGSWACTIVE BIT(20)
252 #define OCDDCR_RUNSTALLINEN BIT(21)
253 #define OCDDCR_DEBUGMODEOUTEN BIT(22)
254 #define OCDDCR_BREAKOUTITO BIT(24)
255 #define OCDDCR_BREAKACKITO BIT(25)
256 
257 #define OCDDSR_EXECDONE BIT(0)
258 #define OCDDSR_EXECEXCEPTION BIT(1)
259 #define OCDDSR_EXECBUSY BIT(2)
260 #define OCDDSR_EXECOVERRUN BIT(3)
261 #define OCDDSR_STOPPED BIT(4)
262 #define OCDDSR_COREWROTEDDR BIT(10)
263 #define OCDDSR_COREREADDDR BIT(11)
264 #define OCDDSR_HOSTWROTEDDR BIT(14)
265 #define OCDDSR_HOSTREADDDR BIT(15)
266 #define OCDDSR_DEBUGPENDBREAK BIT(16)
267 #define OCDDSR_DEBUGPENDHOST BIT(17)
268 #define OCDDSR_DEBUGPENDTRAX BIT(18)
269 #define OCDDSR_DEBUGINTBREAK BIT(20)
270 #define OCDDSR_DEBUGINTHOST BIT(21)
271 #define OCDDSR_DEBUGINTTRAX BIT(22)
272 #define OCDDSR_RUNSTALLTOGGLE BIT(23)
273 #define OCDDSR_RUNSTALLSAMPLE BIT(24)
274 #define OCDDSR_BREACKOUTACKITI BIT(25)
275 #define OCDDSR_BREAKINITI BIT(26)
276 #define OCDDSR_DBGMODPOWERON BIT(31)
277 
278 #define DEBUGCAUSE_IC BIT(0) /* ICOUNT exception */
279 #define DEBUGCAUSE_IB BIT(1) /* IBREAK exception */
280 #define DEBUGCAUSE_DB BIT(2) /* DBREAK exception */
281 #define DEBUGCAUSE_BI BIT(3) /* BREAK instruction encountered */
282 #define DEBUGCAUSE_BN BIT(4) /* BREAK.N instruction encountered */
283 #define DEBUGCAUSE_DI BIT(5) /* Debug Interrupt */
284 
285 #define TRAXCTRL_TREN BIT(0) /* Trace enable. Tracing starts on 0->1 */
286 #define TRAXCTRL_TRSTP BIT(1) /* Trace Stop. Make 1 to stop trace. */
287 #define TRAXCTRL_PCMEN BIT(2) /* PC match enable */
288 #define TRAXCTRL_PTIEN BIT(4) /* Processor-trigger enable */
289 #define TRAXCTRL_CTIEN BIT(5) /* Cross-trigger enable */
290 #define TRAXCTRL_TMEN BIT(7) /* Tracemem Enable. Always set. */
291 #define TRAXCTRL_CNTU BIT(9) /* Post-stop-trigger countdown units; selects when DelayCount-- happens.
292  * 0 - every 32-bit word written to tracemem, 1 - every cpu instruction */
293 #define TRAXCTRL_TSEN BIT(11) /* Undocumented/deprecated? */
294 #define TRAXCTRL_SMPER_SHIFT 12 /* Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg */
295 #define TRAXCTRL_SMPER_MASK 0x07 /* Synchronization message period */
296 #define TRAXCTRL_PTOWT BIT(16) /* Processor Trigger Out (OCD halt) enabled when stop triggered */
297 #define TRAXCTRL_PTOWS BIT(17) /* Processor Trigger Out (OCD halt) enabled when trace stop completes */
298 #define TRAXCTRL_CTOWT BIT(20) /* Cross-trigger Out enabled when stop triggered */
299 #define TRAXCTRL_CTOWS BIT(21) /* Cross-trigger Out enabled when trace stop completes */
300 #define TRAXCTRL_ITCTO BIT(22) /* Integration mode: cross-trigger output */
301 #define TRAXCTRL_ITCTIA BIT(23) /* Integration mode: cross-trigger ack */
302 #define TRAXCTRL_ITATV BIT(24) /* replaces ATID when in integration mode: ATVALID output */
303 #define TRAXCTRL_ATID_MASK 0x7F /* ARB source ID */
304 #define TRAXCTRL_ATID_SHIFT 24
305 #define TRAXCTRL_ATEN BIT(31) /* ATB interface enable */
306 
307 #define TRAXSTAT_TRACT BIT(0) /* Trace active flag. */
308 #define TRAXSTAT_TRIG BIT(1) /* Trace stop trigger. Clears on TREN 1->0 */
309 #define TRAXSTAT_PCMTG BIT(2) /* Stop trigger caused by PC match. Clears on TREN 1->0 */
310 #define TRAXSTAT_PJTR BIT(3) /* JTAG transaction result. 1=err in preceding jtag transaction. */
311 #define TRAXSTAT_PTITG BIT(4) /* Stop trigger caused by Processor Trigger Input.Clears on TREN 1->0 */
312 #define TRAXSTAT_CTITG BIT(5) /* Stop trigger caused by Cross-Trigger Input. Clears on TREN 1->0 */
313 #define TRAXSTAT_MEMSZ_SHIFT 8 /* Traceram size inducator. Usable trace ram is 2^MEMSZ bytes. */
314 #define TRAXSTAT_MEMSZ_MASK 0x1F
315 #define TRAXSTAT_PTO BIT(16) /* Processor Trigger Output: current value */
316 #define TRAXSTAT_CTO BIT(17) /* Cross-Trigger Output: current value */
317 #define TRAXSTAT_ITCTOA BIT(22) /* Cross-Trigger Out Ack: current value */
318 #define TRAXSTAT_ITCTI BIT(23) /* Cross-Trigger Input: current value */
319 #define TRAXSTAT_ITATR BIT(24) /* ATREADY Input: current value */
320 
321 #define TRAXADDR_TADDR_SHIFT 0 /* Trax memory address, in 32-bit words. */
322 #define TRAXADDR_TADDR_MASK 0x1FFFFF /* Actually is only as big as the trace buffer size max addr. */
323 #define TRAXADDR_TWRAP_SHIFT 21 /* Amount of times TADDR has overflown */
324 #define TRAXADDR_TWRAP_MASK 0x3FF
325 #define TRAXADDR_TWSAT BIT(31) /* 1 if TWRAP has overflown, clear by disabling tren.*/
326 
327 #define PCMATCHCTRL_PCML_SHIFT 0 /* Amount of lower bits to ignore in pc trigger register */
328 #define PCMATCHCTRL_PCML_MASK 0x1F
329 #define PCMATCHCTRL_PCMS BIT(31) /* PC Match Sense, 0-match when procs PC is in-range, 1-match when
330  * out-of-range */
331 
332 #define XTENSA_MAX_PERF_COUNTERS 2
333 #define XTENSA_MAX_PERF_SELECT 32
334 #define XTENSA_MAX_PERF_MASK 0xffff
335 
336 #define XTENSA_STOPMASK_DISABLED UINT32_MAX
337 
339 
342  int (*queue_enable)(struct xtensa_debug_module *dm);
344  int (*queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *data);
346  int (*queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t data);
347 };
348 
349 /* Xtensa power registers are 8 bits wide on JTAG interfaces but 32 bits wide
350  * when accessed via APB/DAP. In order to use DAP queuing APIs (for optimal
351  * performance), the XDM power register APIs take 32-bit register params.
352  */
355  int (*queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data,
356  uint32_t clear);
358  int (*queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data);
359 };
360 
361 typedef uint32_t xtensa_pwrstat_t;
362 typedef uint32_t xtensa_ocdid_t;
363 typedef uint32_t xtensa_dsr_t;
364 typedef uint32_t xtensa_traxstat_t;
365 
369  /* TODO: do not need to keep previous status to detect that core or debug module has been
370  * reset, */
371  /* we can clear PWRSTAT_DEBUGWASRESET and PWRSTAT_COREWASRESET after reading will do
372  * the job; */
373  /* upon next reet those bits will be set again. So we can get rid of
374  * xtensa_dm_power_status_cache_reset() and xtensa_dm_power_status_cache(). */
376 };
377 
378 struct xtensa_core_status {
380 };
381 
383  uint32_t ctrl;
384  uint32_t memaddr_start;
385  uint32_t memaddr_end;
386  uint32_t addr;
387 };
388 
389 struct xtensa_trace_status {
391 };
392 
394  uint32_t stoppc;
396  uint32_t after;
397  uint32_t stopmask; /* UINT32_MAX: disable PC match option */
398 };
399 
401  int select;
402  uint32_t mask;
403  int kernelcnt;
404  int tracelevel;
405 };
406 
408  uint64_t value;
409  bool overflow;
410 };
411 
413  const struct xtensa_power_ops *pwr_ops;
414  const struct xtensa_debug_ops *dbg_ops;
415 
416  /* Either JTAG or DAP structures will be populated */
417  struct jtag_tap *tap;
418  void (*queue_tdi_idle)(struct target *target);
419  void *queue_tdi_idle_arg;
420 
421  /* For targets conforming to ARM Debug Interface v5,
422  * "dap" references the Debug Access Port (DAP)
423  * used to make requests to the target;
424  * "debug_ap" is AP instance connected to processor
425  */
426  struct adiv5_dap *dap;
428  int debug_apsel;
429  uint32_t ap_offset;
430 };
431 
433  const struct xtensa_power_ops *pwr_ops;
434  const struct xtensa_debug_ops *dbg_ops;
435 
436  /* Either JTAG or DAP structures will be populated */
437  struct jtag_tap *tap;
438  void (*queue_tdi_idle)(struct target *target);
439  void *queue_tdi_idle_arg;
440 
441  /* DAP struct; AP instance connected to processor */
442  struct adiv5_dap *dap;
443  struct adiv5_ap *debug_ap;
444  int debug_apsel;
445 
449  uint32_t ap_offset;
450 };
451 
452 int xtensa_dm_init(struct xtensa_debug_module *dm, const struct xtensa_debug_module_config *cfg);
453 void xtensa_dm_deinit(struct xtensa_debug_module *dm);
454 int xtensa_dm_poll(struct xtensa_debug_module *dm);
455 int xtensa_dm_examine(struct xtensa_debug_module *dm);
457 int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value);
458 int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value);
460  enum xtensa_dm_pwr_reg reg,
461  uint8_t *data,
462  uint32_t clear);
464  enum xtensa_dm_pwr_reg reg,
465  uint32_t data);
466 
467 static inline int xtensa_dm_queue_execute(struct xtensa_debug_module *dm)
468 {
469  return dm->dap ? dap_run(dm->dap) : jtag_execute_queue();
470 }
471 
472 static inline void xtensa_dm_queue_tdi_idle(struct xtensa_debug_module *dm)
473 {
474  if (dm->queue_tdi_idle)
476 }
477 
478 int xtensa_dm_power_status_read(struct xtensa_debug_module *dm, uint32_t clear);
479 static inline void xtensa_dm_power_status_cache_reset(struct xtensa_debug_module *dm)
480 {
482 }
483 static inline void xtensa_dm_power_status_cache(struct xtensa_debug_module *dm)
484 {
486 }
488 {
489  return dm->power_status.stat;
490 }
491 
496 {
497  return dm->core_status.dsr;
498 }
499 
502 {
503  return dm->device_id;
504 }
505 
507 int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable);
510 int xtensa_dm_trace_data_read(struct xtensa_debug_module *dm, uint8_t *dest, uint32_t size);
511 
512 static inline bool xtensa_dm_is_online(struct xtensa_debug_module *dm)
513 {
514  int res = xtensa_dm_device_id_read(dm);
515  if (res != ERROR_OK)
516  return false;
517  return dm->device_id != 0xffffffff && dm->device_id != 0;
518 }
519 
520 static inline bool xtensa_dm_tap_was_reset(struct xtensa_debug_module *dm)
521 {
522  return !(dm->power_status.prev_stat & PWRSTAT_DEBUGWASRESET_DM(dm)) &&
524 }
525 
526 static inline bool xtensa_dm_core_was_reset(struct xtensa_debug_module *dm)
527 {
528  return !(dm->power_status.prev_stat & PWRSTAT_COREWASRESET_DM(dm)) &&
530 }
531 
532 static inline bool xtensa_dm_core_is_stalled(struct xtensa_debug_module *dm)
533 {
535 }
536 
537 static inline bool xtensa_dm_is_powered(struct xtensa_debug_module *dm)
538 {
539  return dm->core_status.dsr & OCDDSR_DBGMODPOWERON;
540 }
541 
542 int xtensa_dm_perfmon_enable(struct xtensa_debug_module *dm, int counter_id,
543  const struct xtensa_perfmon_config *config);
544 int xtensa_dm_perfmon_dump(struct xtensa_debug_module *dm, int counter_id,
545  struct xtensa_perfmon_result *out_result);
546 
547 #endif /* OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H */
This defines formats and data structures used to talk to ADIv5 entities.
static int dap_run(struct adiv5_dap *dap)
Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they ar...
Definition: arm_adi_v5.h:604
uint32_t bits
Definition: armv4_5.c:359
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
Definition: jtag/core.c:1037
The JTAG interface can be implemented with a software or hardware fifo.
#define ERROR_OK
Definition: log.h:155
struct target * target
Definition: rtt/rtt.c:26
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
This represents an ARM Debug Interface (v5) Access Port (AP).
Definition: arm_adi_v5.h:243
This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
Definition: arm_adi_v5.h:320
Definition: jtag.h:100
Definition: register.h:111
Definition: target.h:120
void(* queue_tdi_idle)(struct target *target)
const struct xtensa_debug_ops * dbg_ops
const struct xtensa_power_ops * pwr_ops
struct xtensa_power_status power_status
void(* queue_tdi_idle)(struct target *target)
const struct xtensa_power_ops * pwr_ops
struct jtag_tap * tap
struct xtensa_core_status core_status
struct adiv5_dap * dap
const struct xtensa_debug_ops * dbg_ops
struct adiv5_ap * debug_ap
int(* queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t data)
register write.
int(* queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *data)
register read.
int(* queue_enable)(struct xtensa_debug_module *dm)
enable operation
int(* queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
register read.
int(* queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
register write.
xtensa_pwrstat_t stath
xtensa_pwrstat_t prev_stat
xtensa_traxstat_t stat
uint8_t status[4]
Definition: vdebug.c:17
static void xtensa_dm_power_status_cache(struct xtensa_debug_module *dm)
int xtensa_dm_trace_status_read(struct xtensa_debug_module *dm, struct xtensa_trace_status *status)
int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value)
int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
static xtensa_ocdid_t xtensa_dm_device_id_get(struct xtensa_debug_module *dm)
int xtensa_dm_trace_start(struct xtensa_debug_module *dm, struct xtensa_trace_start_config *cfg)
int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable)
int xtensa_dm_device_id_read(struct xtensa_debug_module *dm)
int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value)
#define OCDDSR_DBGMODPOWERON
static void xtensa_dm_power_status_cache_reset(struct xtensa_debug_module *dm)
uint32_t xtensa_dsr_t
uint32_t xtensa_pwrstat_t
static void xtensa_dm_queue_tdi_idle(struct xtensa_debug_module *dm)
static bool xtensa_dm_core_was_reset(struct xtensa_debug_module *dm)
#define PWRSTAT_COREWASRESET_DM(d)
static xtensa_dsr_t xtensa_dm_core_status_get(struct xtensa_debug_module *dm)
xtensa_dm_pwr_reg
@ XDMREG_PWRNUM
@ XDMREG_PWRSTAT
@ XDMREG_PWRCTL
static bool xtensa_dm_is_powered(struct xtensa_debug_module *dm)
int xtensa_dm_power_status_read(struct xtensa_debug_module *dm, uint32_t clear)
int xtensa_dm_poll(struct xtensa_debug_module *dm)
static bool xtensa_dm_tap_was_reset(struct xtensa_debug_module *dm)
int xtensa_dm_perfmon_enable(struct xtensa_debug_module *dm, int counter_id, const struct xtensa_perfmon_config *config)
int xtensa_dm_core_status_check(struct xtensa_debug_module *dm)
void xtensa_dm_deinit(struct xtensa_debug_module *dm)
static int xtensa_dm_queue_execute(struct xtensa_debug_module *dm)
static bool xtensa_dm_core_is_stalled(struct xtensa_debug_module *dm)
int xtensa_dm_trace_config_read(struct xtensa_debug_module *dm, struct xtensa_trace_config *config)
#define OCDDSR_RUNSTALLSAMPLE
int xtensa_dm_trace_data_read(struct xtensa_debug_module *dm, uint8_t *dest, uint32_t size)
int xtensa_dm_core_status_clear(struct xtensa_debug_module *dm, xtensa_dsr_t bits)
#define PWRSTAT_DEBUGWASRESET_DM(d)
xtensa_dm_reg
@ XDMREG_LOCKSTATUS
@ XDMREG_DCRSET
@ XDMREG_DIR7
@ XDMREG_PERID5
@ XDMREG_PMCTRL5
@ XDMREG_PMSTAT6
@ XDMREG_PMSTAT1
@ XDMREG_PCMATCHCTRL
@ XDMREG_TRAXDATA
@ XDMREG_PM4
@ XDMREG_CLAIMCLR
@ XDMREG_DIR1
@ XDMREG_TRAXADDR
@ XDMREG_PMSTAT3
@ XDMREG_TRAXSTAT
@ XDMREG_COMPID1
@ XDMREG_DIR4
@ XDMREG_DELAYCNT
@ XDMREG_INTPC
@ XDMREG_PERID0
@ XDMREG_MEMADDREND
@ XDMREG_DDREXEC
@ XDMREG_PMCTRL4
@ XDMREG_PMSTAT5
@ XDMREG_DIR5
@ XDMREG_PMCTRL0
@ XDMREG_DSR
@ XDMREG_ITCTRL
@ XDMREG_PMSTAT2
@ XDMREG_TRAXID
@ XDMREG_LOCKACCESS
@ XDMREG_PM1
@ XDMREG_PERID6
@ XDMREG_PM3
@ XDMREG_PM5
@ XDMREG_PMSTAT4
@ XDMREG_NUM
@ XDMREG_PERID7
@ XDMREG_PM6
@ XDMREG_PERID1
@ XDMREG_DIR2
@ XDMREG_DIR6
@ XDMREG_PM2
@ XDMREG_PM0
@ XDMREG_DIR3
@ XDMREG_CLAIMSET
@ XDMREG_PMCTRL2
@ XDMREG_PM7
@ XDMREG_PMCTRL1
@ XDMREG_PERID4
@ XDMREG_TRIGGERPC
@ XDMREG_TRAXCTRL
@ XDMREG_DEVID
@ XDMREG_DEVTYPE
@ XDMREG_DIR0
@ XDMREG_PMSTAT0
@ XDMREG_COMPID2
@ XDMREG_OCDID
@ XDMREG_PMCTRL7
@ XDMREG_PMCTRL6
@ XDMREG_MEMADDRSTART
@ XDMREG_DDR
@ XDMREG_COMPID3
@ XDMREG_PERID2
@ XDMREG_DCRCLR
@ XDMREG_DIR0EXEC
@ XDMREG_AUTHSTATUS
@ XDMREG_PMSTAT7
@ XDMREG_COMPID0
@ XDMREG_PMCTRL3
@ XDMREG_ERISTAT
@ XDMREG_PERID3
@ XDMREG_PMG
int xtensa_dm_core_status_read(struct xtensa_debug_module *dm)
static bool xtensa_dm_is_online(struct xtensa_debug_module *dm)
static xtensa_pwrstat_t xtensa_dm_power_status_get(struct xtensa_debug_module *dm)
int xtensa_dm_queue_enable(struct xtensa_debug_module *dm)
int xtensa_dm_init(struct xtensa_debug_module *dm, const struct xtensa_debug_module_config *cfg)
int xtensa_dm_examine(struct xtensa_debug_module *dm)
uint32_t xtensa_traxstat_t
int xtensa_dm_perfmon_dump(struct xtensa_debug_module *dm, int counter_id, struct xtensa_perfmon_result *out_result)
uint32_t xtensa_ocdid_t