9 #ifndef OPENOCD_TARGET_XTENSA_H
10 #define OPENOCD_TARGET_XTENSA_H
24 #define XT_ISBE(X) ((X)->target->endianness == TARGET_BIG_ENDIAN)
27 #define XT_INS_BREAK_LE(S, T) (0x004000 | (((S) & 0xF) << 8) | (((T) & 0xF) << 4))
28 #define XT_INS_BREAK_BE(S, T) (0x000400 | (((S) & 0xF) << 12) | ((T) & 0xF))
29 #define XT_INS_BREAK(X, S, T) (XT_ISBE(X) ? XT_INS_BREAK_BE(S, T) : XT_INS_BREAK_LE(S, T))
32 #define XT_INS_BREAKN_LE(IMM4) (0xF02D | (((IMM4) & 0xF) << 8))
33 #define XT_INS_BREAKN_BE(IMM4) (0x0FD2 | (((IMM4) & 0xF) << 12))
34 #define XT_INS_BREAKN(X, IMM4) (XT_ISBE(X) ? XT_INS_BREAKN_BE(IMM4) : XT_INS_BREAKN_LE(IMM4))
36 #define XT_ISNS_SZ_MAX 3
38 #define XT_PS_RING(_v_) ((uint32_t)((_v_) & 0x3) << 6)
39 #define XT_PS_RING_MSK (0x3 << 6)
40 #define XT_PS_RING_GET(_v_) (((_v_) >> 6) & 0x3)
41 #define XT_PS_CALLINC_MSK (0x3 << 16)
42 #define XT_PS_OWB_MSK (0xF << 8)
43 #define XT_PS_WOE_MSK BIT(18)
45 #define XT_LOCAL_MEM_REGIONS_NUM_MAX 8
47 #define XT_AREGS_NUM_MAX 64
48 #define XT_USER_REGS_NUM_MAX 256
50 #define XT_MEM_ACCESS_NONE 0x0
51 #define XT_MEM_ACCESS_READ 0x1
52 #define XT_MEM_ACCESS_WRITE 0x2
54 #define XT_MAX_TIE_REG_WIDTH (512)
55 #define XT_QUERYPKT_RESP_MAX (XT_MAX_TIE_REG_WIDTH * 2 + 1)
187 #define XTENSA_COMMON_MAGIC 0x54E4E555U
255 for (
unsigned int i = 0; i < mem->
count; i++) {
257 addr < mem->regions[i].base + mem->
regions[i].
size)
282 LOG_ERROR(
"Can not access %u reg when Trace Port option disabled!",
reg);
294 LOG_ERROR(
"Can not access %u reg when Trace Port option disabled!",
reg);
319 struct reg **reg_list[],
331 int handle_breakpoints,
332 int debug_execution);
336 int handle_breakpoints,
337 int debug_execution);
#define LOG_ERROR(expr ...)
size_t size
Size of the control block search area.
struct xtensa_cache_config dcache
struct xtensa_debug_config debug
struct xtensa_tracing_config trace
struct xtensa_local_mem_config irom
struct xtensa_local_mem_config drom
struct xtensa_mpu_config mpu
enum xtensa_type core_type
struct xtensa_cache_config icache
struct xtensa_local_mem_config iram
struct xtensa_high_prio_irq_config high_irq
struct xtensa_mmu_config mmu
struct xtensa_irq_config irq
struct xtensa_local_mem_config dram
struct xtensa_local_mem_config sram
struct xtensa_local_mem_config srom
const struct xtensa_debug_ops * dbg_ops
int(* queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t data)
register write.
int(* queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *data)
register read.
struct xtensa_local_mem_region_config regions[XT_LOCAL_MEM_REGIONS_NUM_MAX]
uint8_t itlb_entries_count
uint8_t dtlb_entries_count
uint8_t insn[XT_ISNS_SZ_MAX]
struct breakpoint * oocd_bp
Represents a generic Xtensa core.
struct watchpoint ** hw_wps
uint8_t come_online_probes_num
struct xtensa_reg_desc ** contiguous_regs_desc
unsigned int total_regs_num
struct xtensa_debug_module dbg_mod
char qpkt_resp[XT_QUERYPKT_RESP_MAX]
struct xtensa_chip_common * xtensa_chip
struct reg ** contiguous_regs_list
struct xtensa_keyval_info_s scratch_ars[XT_AR_SCRATCH_NUM]
unsigned int eps_dbglevel_idx
void ** algo_context_backup
struct xtensa_sw_breakpoint * sw_brps
unsigned int genpkt_regs_num
enum xtensa_stepping_isr_mode stepping_isr_mode
struct reg_cache * core_cache
unsigned int core_regs_num
struct xtensa_reg_desc * optregs
struct breakpoint ** hw_brps
unsigned int common_magic
struct xtensa_config * core_config
int xtensa_gdb_query_custom(struct target *target, const char *packet, char **response_p)
void xtensa_reg_set_deep_relgen(struct target *target, enum xtensa_reg_id a_idx, xtensa_reg_val_t value)
static struct xtensa * target_to_xtensa(struct target *target)
static int xtensa_queue_dbg_reg_write(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint32_t data)
int xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint)
void xtensa_target_deinit(struct target *target)
int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint)
static bool xtensa_data_addr_valid(struct target *target, uint32_t addr)
static bool xtensa_addr_in_mem(const struct xtensa_local_mem_config *mem, uint32_t addr)
uint32_t xtensa_cause_get(struct target *target)
const char * xtensa_get_gdb_arch(struct target *target)
int xtensa_do_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int xtensa_smpbreak_read(struct xtensa *xtensa, uint32_t *val)
int xtensa_poll(struct target *target)
int xtensa_prepare_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
int xtensa_halt(struct target *target)
int xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint)
int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer)
int xtensa_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int xtensa_target_init(struct command_context *cmd_ctx, struct target *target)
int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
void xtensa_on_poll(struct target *target)
const struct command_registration xtensa_command_handlers[]
int xtensa_smpbreak_set(struct target *target, uint32_t set)
int xtensa_examine(struct target *target)
int xtensa_init_arch_info(struct target *target, struct xtensa *xtensa, const struct xtensa_debug_module_config *dm_cfg)
int xtensa_fetch_all_regs(struct target *target)
int xtensa_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoint)
void xtensa_cause_reset(struct target *target)
int xtensa_write_buffer(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer)
int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set)
int xtensa_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
void xtensa_reg_set(struct target *target, enum xtensa_reg_id reg_id, xtensa_reg_val_t value)
void xtensa_cause_clear(struct target *target)
int xtensa_smpbreak_get(struct target *target, uint32_t *val)
int xtensa_core_status_check(struct target *target)
int xtensa_do_resume(struct target *target)
#define XT_LOCAL_MEM_REGIONS_NUM_MAX
int xtensa_wakeup(struct target *target)
int xtensa_mmu_is_enabled(struct target *target, int *enabled)
#define XT_QUERYPKT_RESP_MAX
#define XTENSA_COMMON_MAGIC
void xtensa_set_permissive_mode(struct target *target, bool state)
int xtensa_deassert_reset(struct target *target)
COMMAND_HELPER(xtensa_cmd_xtdef_do, struct xtensa *xtensa)
int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
int xtensa_soft_reset_halt(struct target *target)
int xtensa_assert_reset(struct target *target)
static int xtensa_queue_dbg_reg_read(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint8_t *data)
static int xtensa_core_status_clear(struct target *target, uint32_t bits)
xtensa_reg_val_t xtensa_reg_get(struct target *target, enum xtensa_reg_id reg_id)
int xtensa_dm_core_status_clear(struct xtensa_debug_module *dm, xtensa_dsr_t bits)
uint32_t xtensa_reg_val_t