OpenOCD
xtensa.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Generic Xtensa target *
5  * Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
6  * Copyright (C) 2019 Espressif Systems Ltd. *
7  ***************************************************************************/
8 
9 #ifndef OPENOCD_TARGET_XTENSA_H
10 #define OPENOCD_TARGET_XTENSA_H
11 
12 #include "assert.h"
13 #include <target/target.h>
14 #include <target/breakpoints.h>
15 #include "xtensa_regs.h"
16 #include "xtensa_debug_module.h"
17 
23 /* Big-endian vs. little-endian detection */
24 #define XT_ISBE(X) ((X)->target->endianness == TARGET_BIG_ENDIAN)
25 
26 /* 24-bit break; BE version field-swapped then byte-swapped for use in memory R/W fns */
27 #define XT_INS_BREAK_LE(S, T) (0x004000 | (((S) & 0xF) << 8) | (((T) & 0xF) << 4))
28 #define XT_INS_BREAK_BE(S, T) (0x000400 | (((S) & 0xF) << 12) | ((T) & 0xF))
29 #define XT_INS_BREAK(X, S, T) (XT_ISBE(X) ? XT_INS_BREAK_BE(S, T) : XT_INS_BREAK_LE(S, T))
30 
31 /* 16-bit break; BE version field-swapped then byte-swapped for use in memory R/W fns */
32 #define XT_INS_BREAKN_LE(IMM4) (0xF02D | (((IMM4) & 0xF) << 8))
33 #define XT_INS_BREAKN_BE(IMM4) (0x0FD2 | (((IMM4) & 0xF) << 12))
34 #define XT_INS_BREAKN(X, IMM4) (XT_ISBE(X) ? XT_INS_BREAKN_BE(IMM4) : XT_INS_BREAKN_LE(IMM4))
35 
36 #define XT_ISNS_SZ_MAX 3
37 
38 #define XT_PS_RING(_v_) ((uint32_t)((_v_) & 0x3) << 6)
39 #define XT_PS_RING_MSK (0x3 << 6)
40 #define XT_PS_RING_GET(_v_) (((_v_) >> 6) & 0x3)
41 #define XT_PS_CALLINC_MSK (0x3 << 16)
42 #define XT_PS_OWB_MSK (0xF << 8)
43 #define XT_PS_WOE_MSK BIT(18)
44 
45 #define XT_LOCAL_MEM_REGIONS_NUM_MAX 8
46 
47 #define XT_AREGS_NUM_MAX 64
48 #define XT_USER_REGS_NUM_MAX 256
49 
50 #define XT_MEM_ACCESS_NONE 0x0
51 #define XT_MEM_ACCESS_READ 0x1
52 #define XT_MEM_ACCESS_WRITE 0x2
53 
54 #define XT_MAX_TIE_REG_WIDTH (512) /* TIE register file max 4096 bits */
55 #define XT_QUERYPKT_RESP_MAX (XT_MAX_TIE_REG_WIDTH * 2 + 1)
56 
63 };
64 
65 /* An and ARn registers potentially used as scratch regs */
72 };
73 
75  char *chrval;
76  int intval;
77 };
78 
80  XT_UNDEF = 0,
82 };
83 
85  uint8_t way_count;
86  uint32_t line_size;
87  uint32_t size;
88  int writeback;
89 };
90 
93  uint32_t size;
94  int access;
95 };
96 
98  uint16_t count;
100 };
101 
103  bool enabled;
106 };
107 
109  bool enabled;
110  uint8_t nfgseg;
111  uint32_t minsegsize;
112  bool lockable;
113  bool execonly;
114 };
115 
117  bool enabled;
118  uint8_t irq_num;
119 };
120 
122  bool enabled;
123  uint8_t level_num;
124  uint8_t excm_level;
125 };
126 
128  bool enabled;
129  uint8_t irq_level;
130  uint8_t ibreaks_num;
131  uint8_t dbreaks_num;
132  uint8_t perfcount_num;
133 };
134 
136  bool enabled;
137  uint32_t mem_sz;
139 };
140 
142  enum xtensa_type core_type;
143  uint8_t aregs_num;
144  bool windowed;
145  bool coproc;
147  struct xtensa_irq_config irq;
149  struct xtensa_mmu_config mmu;
150  struct xtensa_mpu_config mpu;
151  struct xtensa_debug_config debug;
161 };
162 
163 typedef uint32_t xtensa_insn_t;
164 
166  XT_STEPPING_ISR_OFF, /* interrupts are disabled during stepping */
167  XT_STEPPING_ISR_ON, /* interrupts are enabled during stepping */
168 };
169 
170 /* Only supported in cores with in-CPU MMU. None of Espressif chips as of now. */
176  XT_MODE_ANY /* special value to run algorithm in current core mode */
177 };
178 
181  /* original insn */
183  /* original insn size */
184  uint8_t insn_sz; /* 2 or 3 bytes */
185 };
186 
187 #define XTENSA_COMMON_MAGIC 0x54E4E555U
188 
192 struct xtensa {
193  unsigned int common_magic;
198  unsigned int total_regs_num;
199  unsigned int core_regs_num;
201  unsigned int genpkt_regs_num;
204  /* Per-config Xtensa registers as specified via "xtreg" in xtensa-core*.cfg */
206  unsigned int num_optregs;
207  struct reg *empty_regs;
209  /* An array of pointers to buffers to backup registers' values while algo is run on target.
210  * Size is 'regs_num'. */
212  unsigned int eps_dbglevel_idx;
213  unsigned int dbregs_num;
214  struct target *target;
217  struct breakpoint **hw_brps;
218  struct watchpoint **hw_wps;
221  bool permissive_mode; /* bypass memory checks */
223  uint32_t smp_break;
224  uint32_t spill_loc;
225  unsigned int spill_bytes;
226  uint8_t *spill_buf;
228  /* Sometimes debug module's 'powered' bit is cleared after reset, but get set after some
229  * time.This is the number of polling periods after which core is considered to be powered
230  * off (marked as unexamined) if the bit retains to be cleared (e.g. if core is disabled by
231  * SW running on target).*/
236  bool regs_fetched; /* true after first register fetch completed successfully */
237 };
238 
239 static inline struct xtensa *target_to_xtensa(struct target *target)
240 {
241  assert(target);
242  struct xtensa *xtensa = target->arch_info;
244  return xtensa;
245 }
246 
248  struct xtensa *xtensa,
249  const struct xtensa_debug_module_config *dm_cfg);
250 int xtensa_target_init(struct command_context *cmd_ctx, struct target *target);
251 void xtensa_target_deinit(struct target *target);
252 
253 static inline bool xtensa_addr_in_mem(const struct xtensa_local_mem_config *mem, uint32_t addr)
254 {
255  for (unsigned int i = 0; i < mem->count; i++) {
256  if (addr >= mem->regions[i].base &&
257  addr < mem->regions[i].base + mem->regions[i].size)
258  return true;
259  }
260  return false;
261 }
262 
263 static inline bool xtensa_data_addr_valid(struct target *target, uint32_t addr)
264 {
266 
268  return true;
270  return true;
272  return true;
273  return false;
274 }
275 
276 static inline int xtensa_queue_dbg_reg_read(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint8_t *data)
277 {
278  struct xtensa_debug_module *dm = &xtensa->dbg_mod;
279 
280  if (!xtensa->core_config->trace.enabled &&
281  (reg <= XDMREG_MEMADDREND || (reg >= XDMREG_PMG && reg <= XDMREG_PMSTAT7))) {
282  LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg);
283  return ERROR_FAIL;
284  }
285  return dm->dbg_ops->queue_reg_read(dm, reg, data);
286 }
287 
288 static inline int xtensa_queue_dbg_reg_write(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint32_t data)
289 {
290  struct xtensa_debug_module *dm = &xtensa->dbg_mod;
291 
292  if (!xtensa->core_config->trace.enabled &&
293  (reg <= XDMREG_MEMADDREND || (reg >= XDMREG_PMG && reg <= XDMREG_PMSTAT7))) {
294  LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg);
295  return ERROR_FAIL;
296  }
297  return dm->dbg_ops->queue_reg_write(dm, reg, data);
298 }
299 
300 static inline int xtensa_core_status_clear(struct target *target, uint32_t bits)
301 {
304 }
305 
307 
308 int xtensa_examine(struct target *target);
309 int xtensa_wakeup(struct target *target);
310 int xtensa_smpbreak_set(struct target *target, uint32_t set);
311 int xtensa_smpbreak_get(struct target *target, uint32_t *val);
312 int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set);
313 int xtensa_smpbreak_read(struct xtensa *xtensa, uint32_t *val);
315 void xtensa_reg_set(struct target *target, enum xtensa_reg_id reg_id, xtensa_reg_val_t value);
317 int xtensa_fetch_all_regs(struct target *target);
319  struct reg **reg_list[],
320  int *reg_list_size,
321  enum target_register_class reg_class);
322 uint32_t xtensa_cause_get(struct target *target);
323 void xtensa_cause_clear(struct target *target);
325 int xtensa_poll(struct target *target);
327 int xtensa_halt(struct target *target);
328 int xtensa_resume(struct target *target,
329  int current,
330  target_addr_t address,
331  int handle_breakpoints,
332  int debug_execution);
334  int current,
335  target_addr_t address,
336  int handle_breakpoints,
337  int debug_execution);
338 int xtensa_do_resume(struct target *target);
339 int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints);
340 int xtensa_do_step(struct target *target, int current, target_addr_t address, int handle_breakpoints);
341 int xtensa_mmu_is_enabled(struct target *target, int *enabled);
342 int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer);
343 int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer);
344 int xtensa_write_memory(struct target *target,
345  target_addr_t address,
346  uint32_t size,
347  uint32_t count,
348  const uint8_t *buffer);
349 int xtensa_write_buffer(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer);
350 int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum);
351 int xtensa_assert_reset(struct target *target);
352 int xtensa_deassert_reset(struct target *target);
358 void xtensa_set_permissive_mode(struct target *target, bool state);
359 const char *xtensa_get_gdb_arch(struct target *target);
360 int xtensa_gdb_query_custom(struct target *target, const char *packet, char **response_p);
361 
362 COMMAND_HELPER(xtensa_cmd_xtdef_do, struct xtensa *xtensa);
363 COMMAND_HELPER(xtensa_cmd_xtopt_do, struct xtensa *xtensa);
364 COMMAND_HELPER(xtensa_cmd_xtmem_do, struct xtensa *xtensa);
365 COMMAND_HELPER(xtensa_cmd_xtmpu_do, struct xtensa *xtensa);
366 COMMAND_HELPER(xtensa_cmd_xtmmu_do, struct xtensa *xtensa);
367 COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa);
368 COMMAND_HELPER(xtensa_cmd_xtregfmt_do, struct xtensa *xtensa);
369 COMMAND_HELPER(xtensa_cmd_permissive_mode_do, struct xtensa *xtensa);
370 COMMAND_HELPER(xtensa_cmd_mask_interrupts_do, struct xtensa *xtensa);
371 COMMAND_HELPER(xtensa_cmd_smpbreak_do, struct target *target);
372 COMMAND_HELPER(xtensa_cmd_perfmon_dump_do, struct xtensa *xtensa);
373 COMMAND_HELPER(xtensa_cmd_perfmon_enable_do, struct xtensa *xtensa);
374 COMMAND_HELPER(xtensa_cmd_tracestart_do, struct xtensa *xtensa);
375 COMMAND_HELPER(xtensa_cmd_tracestop_do, struct xtensa *xtensa);
376 COMMAND_HELPER(xtensa_cmd_tracedump_do, struct xtensa *xtensa, const char *fname);
377 
378 extern const struct command_registration xtensa_command_handlers[];
379 
380 #endif /* OPENOCD_TARGET_XTENSA_H */
uint32_t bits
Definition: armv4_5.c:359
#define ERROR_FAIL
Definition: log.h:161
#define LOG_ERROR(expr ...)
Definition: log.h:123
uint32_t addr
Definition: nuttx.c:65
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
Definition: register.h:111
Definition: target.h:120
void * arch_info
Definition: target.h:169
Definition: trace.h:21
uint8_t way_count
Definition: xtensa.h:85
uint32_t size
Definition: xtensa.h:87
uint32_t line_size
Definition: xtensa.h:86
struct xtensa_cache_config dcache
Definition: xtensa.h:154
struct xtensa_debug_config debug
Definition: xtensa.h:151
struct xtensa_tracing_config trace
Definition: xtensa.h:152
struct xtensa_local_mem_config irom
Definition: xtensa.h:155
struct xtensa_local_mem_config drom
Definition: xtensa.h:157
struct xtensa_mpu_config mpu
Definition: xtensa.h:150
enum xtensa_type core_type
Definition: xtensa.h:142
struct xtensa_cache_config icache
Definition: xtensa.h:153
struct xtensa_local_mem_config iram
Definition: xtensa.h:156
struct xtensa_high_prio_irq_config high_irq
Definition: xtensa.h:148
struct xtensa_mmu_config mmu
Definition: xtensa.h:149
uint8_t aregs_num
Definition: xtensa.h:143
struct xtensa_irq_config irq
Definition: xtensa.h:147
struct xtensa_local_mem_config dram
Definition: xtensa.h:158
struct xtensa_local_mem_config sram
Definition: xtensa.h:159
bool windowed
Definition: xtensa.h:144
struct xtensa_local_mem_config srom
Definition: xtensa.h:160
bool coproc
Definition: xtensa.h:145
bool exceptions
Definition: xtensa.h:146
uint8_t irq_level
Definition: xtensa.h:129
uint8_t ibreaks_num
Definition: xtensa.h:130
uint8_t dbreaks_num
Definition: xtensa.h:131
uint8_t perfcount_num
Definition: xtensa.h:132
const struct xtensa_debug_ops * dbg_ops
int(* queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t data)
register write.
int(* queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *data)
register read.
uint8_t irq_num
Definition: xtensa.h:118
struct xtensa_local_mem_region_config regions[XT_LOCAL_MEM_REGIONS_NUM_MAX]
Definition: xtensa.h:99
uint8_t itlb_entries_count
Definition: xtensa.h:104
uint8_t dtlb_entries_count
Definition: xtensa.h:105
uint8_t nfgseg
Definition: xtensa.h:110
uint32_t minsegsize
Definition: xtensa.h:111
uint8_t insn[XT_ISNS_SZ_MAX]
Definition: xtensa.h:182
struct breakpoint * oocd_bp
Definition: xtensa.h:180
bool reversed_mem_access
Definition: xtensa.h:138
Represents a generic Xtensa core.
Definition: xtensa.h:192
struct watchpoint ** hw_wps
Definition: xtensa.h:218
uint8_t come_online_probes_num
Definition: xtensa.h:232
unsigned int dbregs_num
Definition: xtensa.h:213
struct xtensa_reg_desc ** contiguous_regs_desc
Definition: xtensa.h:202
unsigned int total_regs_num
Definition: xtensa.h:198
struct reg * empty_regs
Definition: xtensa.h:207
struct xtensa_debug_module dbg_mod
Definition: xtensa.h:196
char qpkt_resp[XT_QUERYPKT_RESP_MAX]
Definition: xtensa.h:208
bool permissive_mode
Definition: xtensa.h:221
struct xtensa_chip_common * xtensa_chip
Definition: xtensa.h:194
uint32_t smp_break
Definition: xtensa.h:223
bool suppress_dsr_errors
Definition: xtensa.h:222
struct reg ** contiguous_regs_list
Definition: xtensa.h:203
bool trace_active
Definition: xtensa.h:220
struct xtensa_keyval_info_s scratch_ars[XT_AR_SCRATCH_NUM]
Definition: xtensa.h:235
uint32_t spill_loc
Definition: xtensa.h:224
struct target * target
Definition: xtensa.h:214
int8_t probe_lsddr32p
Definition: xtensa.h:227
unsigned int eps_dbglevel_idx
Definition: xtensa.h:212
void ** algo_context_backup
Definition: xtensa.h:211
bool reset_asserted
Definition: xtensa.h:215
uint8_t * spill_buf
Definition: xtensa.h:226
struct xtensa_sw_breakpoint * sw_brps
Definition: xtensa.h:219
unsigned int genpkt_regs_num
Definition: xtensa.h:201
enum xtensa_stepping_isr_mode stepping_isr_mode
Definition: xtensa.h:216
bool regmap_contiguous
Definition: xtensa.h:200
bool halt_request
Definition: xtensa.h:234
struct reg_cache * core_cache
Definition: xtensa.h:197
bool regs_fetched
Definition: xtensa.h:236
unsigned int num_optregs
Definition: xtensa.h:206
unsigned int core_regs_num
Definition: xtensa.h:199
struct xtensa_reg_desc * optregs
Definition: xtensa.h:205
struct breakpoint ** hw_brps
Definition: xtensa.h:217
bool proc_syscall
Definition: xtensa.h:233
unsigned int common_magic
Definition: xtensa.h:193
struct xtensa_config * core_config
Definition: xtensa.h:195
unsigned int spill_bytes
Definition: xtensa.h:225
target_register_class
Definition: target.h:114
uint64_t target_addr_t
Definition: types.h:335
uint8_t state[4]
Definition: vdebug.c:21
uint8_t count[4]
Definition: vdebug.c:22
int xtensa_gdb_query_custom(struct target *target, const char *packet, char **response_p)
Definition: xtensa.c:2740
void xtensa_reg_set_deep_relgen(struct target *target, enum xtensa_reg_id a_idx, xtensa_reg_val_t value)
Definition: xtensa.c:935
xtensa_qerr_e
Definition: xtensa.h:57
@ XT_QERR_FAIL
Definition: xtensa.h:59
@ XT_QERR_INVAL
Definition: xtensa.h:60
@ XT_QERR_INTERNAL
Definition: xtensa.h:58
@ XT_QERR_MEM
Definition: xtensa.h:61
@ XT_QERR_NUM
Definition: xtensa.h:62
static struct xtensa * target_to_xtensa(struct target *target)
Definition: xtensa.h:239
static int xtensa_queue_dbg_reg_write(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint32_t data)
Definition: xtensa.h:288
int xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint)
Definition: xtensa.c:2254
void xtensa_target_deinit(struct target *target)
Definition: xtensa.c:2961
xtensa_stepping_isr_mode
Definition: xtensa.h:165
@ XT_STEPPING_ISR_OFF
Definition: xtensa.h:166
@ XT_STEPPING_ISR_ON
Definition: xtensa.h:167
#define XT_ISNS_SZ_MAX
Definition: xtensa.h:36
int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint)
Definition: xtensa.c:2334
static bool xtensa_data_addr_valid(struct target *target, uint32_t addr)
Definition: xtensa.h:263
static bool xtensa_addr_in_mem(const struct xtensa_local_mem_config *mem, uint32_t addr)
Definition: xtensa.h:253
uint32_t xtensa_cause_get(struct target *target)
Definition: xtensa.c:946
const char * xtensa_get_gdb_arch(struct target *target)
Definition: xtensa.c:2994
int xtensa_do_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
Definition: xtensa.c:1453
int xtensa_smpbreak_read(struct xtensa *xtensa, uint32_t *val)
Definition: xtensa.c:851
xtensa_type
Definition: xtensa.h:79
@ XT_LX
Definition: xtensa.h:81
@ XT_UNDEF
Definition: xtensa.h:80
int xtensa_poll(struct target *target)
Definition: xtensa.c:2022
int xtensa_prepare_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Definition: xtensa.c:1329
int xtensa_halt(struct target *target)
Definition: xtensa.c:1302
int xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint)
Definition: xtensa.c:2298
int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer)
Definition: xtensa.c:1805
int xtensa_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: xtensa.c:1225
int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
Definition: xtensa.c:1658
int xtensa_target_init(struct command_context *cmd_ctx, struct target *target)
Definition: xtensa.c:2895
int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Definition: xtensa.c:2016
void xtensa_on_poll(struct target *target)
const struct command_registration xtensa_command_handlers[]
Definition: xtensa.c:4020
int xtensa_smpbreak_set(struct target *target, uint32_t set)
Definition: xtensa.c:839
int xtensa_examine(struct target *target)
Definition: xtensa.c:780
int xtensa_init_arch_info(struct target *target, struct xtensa *xtensa, const struct xtensa_debug_module_config *dm_cfg)
Definition: xtensa.c:2851
int xtensa_fetch_all_regs(struct target *target)
Definition: xtensa.c:1007
int xtensa_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Definition: xtensa.c:1404
int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoint)
Definition: xtensa.c:2390
void xtensa_cause_reset(struct target *target)
int xtensa_write_buffer(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer)
Definition: xtensa.c:2010
int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set)
Definition: xtensa.c:824
int xtensa_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: xtensa.c:1811
void xtensa_reg_set(struct target *target, enum xtensa_reg_id reg_id, xtensa_reg_val_t value)
Definition: xtensa.c:925
xtensa_ar_scratch_set_e
Definition: xtensa.h:66
@ XT_AR_SCRATCH_A3
Definition: xtensa.h:67
@ XT_AR_SCRATCH_AR4
Definition: xtensa.h:70
@ XT_AR_SCRATCH_NUM
Definition: xtensa.h:71
@ XT_AR_SCRATCH_A4
Definition: xtensa.h:69
@ XT_AR_SCRATCH_AR3
Definition: xtensa.h:68
void xtensa_cause_clear(struct target *target)
Definition: xtensa.c:951
xtensa_mode
Definition: xtensa.h:171
@ XT_MODE_RING2
Definition: xtensa.h:174
@ XT_MODE_RING1
Definition: xtensa.h:173
@ XT_MODE_ANY
Definition: xtensa.h:176
@ XT_MODE_RING0
Definition: xtensa.h:172
@ XT_MODE_RING3
Definition: xtensa.h:175
int xtensa_smpbreak_get(struct target *target, uint32_t *val)
Definition: xtensa.c:863
int xtensa_core_status_check(struct target *target)
Definition: xtensa.c:881
int xtensa_do_resume(struct target *target)
Definition: xtensa.c:1388
#define XT_LOCAL_MEM_REGIONS_NUM_MAX
Definition: xtensa.h:45
int xtensa_wakeup(struct target *target)
Definition: xtensa.c:810
int xtensa_mmu_is_enabled(struct target *target, int *enabled)
Definition: xtensa.c:1294
#define XT_QUERYPKT_RESP_MAX
Definition: xtensa.h:55
#define XTENSA_COMMON_MAGIC
Definition: xtensa.h:187
void xtensa_set_permissive_mode(struct target *target, bool state)
Definition: xtensa.c:2890
int xtensa_deassert_reset(struct target *target)
Definition: xtensa.c:979
COMMAND_HELPER(xtensa_cmd_xtdef_do, struct xtensa *xtensa)
Definition: xtensa.c:3069
int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: xtensa.c:1722
int xtensa_soft_reset_halt(struct target *target)
Definition: xtensa.c:1001
int xtensa_assert_reset(struct target *target)
Definition: xtensa.c:958
uint32_t xtensa_insn_t
Definition: xtensa.h:163
static int xtensa_queue_dbg_reg_read(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint8_t *data)
Definition: xtensa.h:276
static int xtensa_core_status_clear(struct target *target, uint32_t bits)
Definition: xtensa.h:300
xtensa_reg_val_t xtensa_reg_get(struct target *target, enum xtensa_reg_id reg_id)
Definition: xtensa.c:918
int xtensa_dm_core_status_clear(struct xtensa_debug_module *dm, xtensa_dsr_t bits)
xtensa_dm_reg
@ XDMREG_MEMADDREND
@ XDMREG_PMSTAT7
@ XDMREG_PMG
xtensa_reg_id
Definition: xtensa_regs.h:15
uint32_t xtensa_reg_val_t
Definition: xtensa_regs.h:70