OpenOCD
xtensa_regs.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Generic Xtensa target API for OpenOCD *
5  * Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
6  * Copyright (C) 2016-2019 Espressif Systems Ltd. *
7  * Author: Angus Gratton gus@projectgus.com *
8  ***************************************************************************/
9 
10 #ifndef OPENOCD_TARGET_XTENSA_REGS_H
11 #define OPENOCD_TARGET_XTENSA_REGS_H
12 
13 struct reg_arch_type;
14 
34  XT_REG_IDX_ARLAST = 64, /* Max 64 ARs */
68 };
69 
70 typedef uint32_t xtensa_reg_val_t;
71 
72 #define XT_NUM_A_REGS 16
73 
75  XT_REG_GENERAL = 0, /* General-purpose register; part of the windowed register set */
76  XT_REG_USER = 1, /* User register, needs RUR to read */
77  XT_REG_SPECIAL = 2, /* Special register, needs RSR to read */
78  XT_REG_DEBUG = 3, /* Register used for the debug interface. Don't mess with this. */
79  XT_REG_RELGEN = 4, /* Relative general address. Points to the absolute addresses plus the window
80  * index */
81  XT_REG_FR = 5, /* Floating-point register */
82  XT_REG_TIE = 6, /* TIE (custom) register */
83  XT_REG_OTHER = 7, /* Other (typically legacy) register */
85 
86  /* enum names must be one of the above types + _VAL or _MASK */
89  XT_REG_USER_MASK = 0xFF00,
90  XT_REG_USER_VAL = 0x0300,
94  XT_REG_DEBUG_VAL = 0x0200,
97  XT_REG_FR_MASK = 0xFFF0,
98  XT_REG_FR_VAL = 0x0030,
99  XT_REG_TIE_MASK = 0xF000,
100  XT_REG_TIE_VAL = 0xF000, /* unused */
102  XT_REG_OTHER_VAL = 0xF000, /* unused */
103 
104  XT_REG_INDEX_MASK = 0x00FF
105 };
106 
108  XT_REGF_NOREAD = 0x01, /* Register is write-only */
109  XT_REGF_COPROC0 = 0x02, /* Can't be read if coproc0 isn't enabled */
110  XT_REGF_MASK = 0x03
111 };
112 
114  const char *name;
115  bool exist;
116  unsigned int reg_num; /* ISA register num (meaning depends on register type) */
117  unsigned int dbreg_num; /* Debugger-visible register num (reg type encoded) */
118  enum xtensa_reg_type type;
119  enum xtensa_reg_flags flags;
120 };
121 
122 #define _XT_MK_DBREGN(reg_num, reg_type) \
123  ((reg_type ## _VAL) | (reg_num))
124 
125 #define _XT_MK_DBREGN_MASK(reg_num, reg_mask) \
126  ((reg_mask) | (reg_num))
127 
128 #define XT_MK_REG_DESC(n, r, t, f) \
129  { .name = (n), .exist = false, .reg_num = (r), \
130  .dbreg_num = _XT_MK_DBREGN(r, t), .type = (t), \
131  .flags = (f) }
132 
134 
135 #endif /* OPENOCD_TARGET_XTENSA_REGS_H */
unsigned int reg_num
Definition: xtensa_regs.h:116
enum xtensa_reg_flags flags
Definition: xtensa_regs.h:119
const char * name
Definition: xtensa_regs.h:114
unsigned int dbreg_num
Definition: xtensa_regs.h:117
enum xtensa_reg_type type
Definition: xtensa_regs.h:118
xtensa_reg_id
Definition: xtensa_regs.h:15
@ XT_REG_IDX_AR12
Definition: xtensa_regs.h:30
@ XT_REG_IDX_AR10
Definition: xtensa_regs.h:28
@ XT_REG_IDX_A15
Definition: xtensa_regs.h:66
@ XT_REG_IDX_A0
Definition: xtensa_regs.h:51
@ XT_REG_IDX_IBREAKA1
Definition: xtensa_regs.h:41
@ XT_REG_IDX_A1
Definition: xtensa_regs.h:52
@ XT_REG_IDX_AR5
Definition: xtensa_regs.h:23
@ XT_REG_IDX_AR14
Definition: xtensa_regs.h:32
@ XT_REG_IDX_PS
Definition: xtensa_regs.h:37
@ XT_REG_IDX_ARFIRST
Definition: xtensa_regs.h:18
@ XT_REG_IDX_A13
Definition: xtensa_regs.h:64
@ XT_REG_IDX_ARLAST
Definition: xtensa_regs.h:34
@ XT_REG_IDX_A9
Definition: xtensa_regs.h:60
@ XT_REG_IDX_AR6
Definition: xtensa_regs.h:24
@ XT_REG_IDX_PC
Definition: xtensa_regs.h:16
@ XT_REG_IDX_DDR
Definition: xtensa_regs.h:39
@ XT_REG_IDX_DEBUGCAUSE
Definition: xtensa_regs.h:48
@ XT_REG_IDX_AR1
Definition: xtensa_regs.h:19
@ XT_REG_IDX_AR15
Definition: xtensa_regs.h:33
@ XT_REG_IDX_DBREAKC1
Definition: xtensa_regs.h:45
@ XT_REG_IDX_A3
Definition: xtensa_regs.h:54
@ XT_REG_IDX_A11
Definition: xtensa_regs.h:62
@ XT_REG_IDX_AR0
Definition: xtensa_regs.h:17
@ XT_REG_IDX_ICOUNT
Definition: xtensa_regs.h:49
@ XT_REG_IDX_AR9
Definition: xtensa_regs.h:27
@ XT_REG_IDX_ICOUNTLEVEL
Definition: xtensa_regs.h:50
@ XT_REG_IDX_A7
Definition: xtensa_regs.h:58
@ XT_REG_IDX_A12
Definition: xtensa_regs.h:63
@ XT_REG_IDX_AR8
Definition: xtensa_regs.h:26
@ XT_REG_IDX_A6
Definition: xtensa_regs.h:57
@ XT_REG_IDX_AR2
Definition: xtensa_regs.h:20
@ XT_REG_IDX_AR11
Definition: xtensa_regs.h:29
@ XT_REG_IDX_DBREAKC0
Definition: xtensa_regs.h:44
@ XT_NUM_REGS
Definition: xtensa_regs.h:67
@ XT_REG_IDX_A10
Definition: xtensa_regs.h:61
@ XT_REG_IDX_A4
Definition: xtensa_regs.h:55
@ XT_REG_IDX_EXCCAUSE
Definition: xtensa_regs.h:47
@ XT_REG_IDX_AR4
Definition: xtensa_regs.h:22
@ XT_REG_IDX_DBREAKA0
Definition: xtensa_regs.h:42
@ XT_REG_IDX_A14
Definition: xtensa_regs.h:65
@ XT_REG_IDX_DBREAKA1
Definition: xtensa_regs.h:43
@ XT_REG_IDX_A2
Definition: xtensa_regs.h:53
@ XT_REG_IDX_AR7
Definition: xtensa_regs.h:25
@ XT_REG_IDX_WINDOWSTART
Definition: xtensa_regs.h:36
@ XT_REG_IDX_A5
Definition: xtensa_regs.h:56
@ XT_REG_IDX_IBREAKENABLE
Definition: xtensa_regs.h:38
@ XT_REG_IDX_WINDOWBASE
Definition: xtensa_regs.h:35
@ XT_REG_IDX_CPENABLE
Definition: xtensa_regs.h:46
@ XT_REG_IDX_AR3
Definition: xtensa_regs.h:21
@ XT_REG_IDX_AR13
Definition: xtensa_regs.h:31
@ XT_REG_IDX_A8
Definition: xtensa_regs.h:59
@ XT_REG_IDX_IBREAKA0
Definition: xtensa_regs.h:40
xtensa_reg_type
Definition: xtensa_regs.h:74
@ XT_REG_TYPE_NUM
Definition: xtensa_regs.h:84
@ XT_REG_GENERAL_VAL
Definition: xtensa_regs.h:88
@ XT_REG_RELGEN_MASK
Definition: xtensa_regs.h:95
@ XT_REG_USER
Definition: xtensa_regs.h:76
@ XT_REG_INDEX_MASK
Definition: xtensa_regs.h:104
@ XT_REG_OTHER_VAL
Definition: xtensa_regs.h:102
@ XT_REG_DEBUG
Definition: xtensa_regs.h:78
@ XT_REG_RELGEN
Definition: xtensa_regs.h:79
@ XT_REG_SPECIAL_MASK
Definition: xtensa_regs.h:91
@ XT_REG_SPECIAL_VAL
Definition: xtensa_regs.h:92
@ XT_REG_DEBUG_MASK
Definition: xtensa_regs.h:93
@ XT_REG_USER_VAL
Definition: xtensa_regs.h:90
@ XT_REG_FR_VAL
Definition: xtensa_regs.h:98
@ XT_REG_USER_MASK
Definition: xtensa_regs.h:89
@ XT_REG_RELGEN_VAL
Definition: xtensa_regs.h:96
@ XT_REG_GENERAL
Definition: xtensa_regs.h:75
@ XT_REG_GENERAL_MASK
Definition: xtensa_regs.h:87
@ XT_REG_OTHER
Definition: xtensa_regs.h:83
@ XT_REG_DEBUG_VAL
Definition: xtensa_regs.h:94
@ XT_REG_SPECIAL
Definition: xtensa_regs.h:77
@ XT_REG_TIE
Definition: xtensa_regs.h:82
@ XT_REG_FR
Definition: xtensa_regs.h:81
@ XT_REG_TIE_MASK
Definition: xtensa_regs.h:99
@ XT_REG_FR_MASK
Definition: xtensa_regs.h:97
@ XT_REG_TIE_VAL
Definition: xtensa_regs.h:100
@ XT_REG_OTHER_MASK
Definition: xtensa_regs.h:101
xtensa_reg_flags
Definition: xtensa_regs.h:107
@ XT_REGF_COPROC0
Definition: xtensa_regs.h:109
@ XT_REGF_MASK
Definition: xtensa_regs.h:110
@ XT_REGF_NOREAD
Definition: xtensa_regs.h:108
uint32_t xtensa_reg_val_t
Definition: xtensa_regs.h:70
struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS]
Definition: xtensa.c:181