OpenOCD
xtensa_regs.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Generic Xtensa target API for OpenOCD *
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* Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
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* Copyright (C) 2016-2019 Espressif Systems Ltd. *
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* Author: Angus Gratton gus@projectgus.com *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_XTENSA_REGS_H
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#define OPENOCD_TARGET_XTENSA_REGS_H
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struct
reg_arch_type
;
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enum
xtensa_reg_id
{
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XT_REG_IDX_PC
= 0,
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XT_REG_IDX_AR0
,
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XT_REG_IDX_ARFIRST
=
XT_REG_IDX_AR0
,
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XT_REG_IDX_AR1
,
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XT_REG_IDX_AR2
,
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XT_REG_IDX_AR3
,
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XT_REG_IDX_AR4
,
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XT_REG_IDX_AR5
,
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XT_REG_IDX_AR6
,
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XT_REG_IDX_AR7
,
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XT_REG_IDX_AR8
,
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XT_REG_IDX_AR9
,
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XT_REG_IDX_AR10
,
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XT_REG_IDX_AR11
,
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XT_REG_IDX_AR12
,
31
XT_REG_IDX_AR13
,
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XT_REG_IDX_AR14
,
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XT_REG_IDX_AR15
,
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XT_REG_IDX_ARLAST
= 64,
/* Max 64 ARs */
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XT_REG_IDX_WINDOWBASE
,
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XT_REG_IDX_WINDOWSTART
,
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XT_REG_IDX_PS
,
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XT_REG_IDX_IBREAKENABLE
,
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XT_REG_IDX_DDR
,
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XT_REG_IDX_IBREAKA0
,
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XT_REG_IDX_IBREAKA1
,
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XT_REG_IDX_DBREAKA0
,
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XT_REG_IDX_DBREAKA1
,
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XT_REG_IDX_DBREAKC0
,
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XT_REG_IDX_DBREAKC1
,
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XT_REG_IDX_CPENABLE
,
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XT_REG_IDX_EXCCAUSE
,
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XT_REG_IDX_DEBUGCAUSE
,
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XT_REG_IDX_ICOUNT
,
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XT_REG_IDX_ICOUNTLEVEL
,
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XT_REG_IDX_A0
,
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XT_REG_IDX_A1
,
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XT_REG_IDX_A2
,
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XT_REG_IDX_A3
,
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XT_REG_IDX_A4
,
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XT_REG_IDX_A5
,
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XT_REG_IDX_A6
,
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XT_REG_IDX_A7
,
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XT_REG_IDX_A8
,
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XT_REG_IDX_A9
,
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XT_REG_IDX_A10
,
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XT_REG_IDX_A11
,
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XT_REG_IDX_A12
,
64
XT_REG_IDX_A13
,
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XT_REG_IDX_A14
,
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XT_REG_IDX_A15
,
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XT_NUM_REGS
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};
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typedef
uint32_t
xtensa_reg_val_t
;
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#define XT_NUM_A_REGS 16
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enum
xtensa_reg_type
{
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XT_REG_GENERAL
= 0,
/* General-purpose register; part of the windowed register set */
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XT_REG_USER
= 1,
/* User register, needs RUR to read */
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XT_REG_SPECIAL
= 2,
/* Special register, needs RSR to read */
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XT_REG_DEBUG
= 3,
/* Register used for the debug interface. Don't mess with this. */
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XT_REG_RELGEN
= 4,
/* Relative general address. Points to the absolute addresses plus the window
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* index */
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XT_REG_FR
= 5,
/* Floating-point register */
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XT_REG_TIE
= 6,
/* TIE (custom) register */
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XT_REG_OTHER
= 7,
/* Other (typically legacy) register */
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XT_REG_TYPE_NUM
,
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/* enum names must be one of the above types + _VAL or _MASK */
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XT_REG_GENERAL_MASK
= 0xFFC0,
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XT_REG_GENERAL_VAL
= 0x0100,
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XT_REG_USER_MASK
= 0xFF00,
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XT_REG_USER_VAL
= 0x0300,
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XT_REG_SPECIAL_MASK
= 0xFF00,
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XT_REG_SPECIAL_VAL
= 0x0200,
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XT_REG_DEBUG_MASK
= 0xFF00,
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XT_REG_DEBUG_VAL
= 0x0200,
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XT_REG_RELGEN_MASK
= 0xFFE0,
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XT_REG_RELGEN_VAL
= 0x0000,
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XT_REG_FR_MASK
= 0xFFF0,
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XT_REG_FR_VAL
= 0x0030,
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XT_REG_TIE_MASK
= 0xF000,
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XT_REG_TIE_VAL
= 0xF000,
/* unused */
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XT_REG_OTHER_MASK
= 0xFFFF,
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XT_REG_OTHER_VAL
= 0xF000,
/* unused */
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XT_REG_INDEX_MASK
= 0x00FF
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};
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enum
xtensa_reg_flags
{
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XT_REGF_NOREAD
= 0x01,
/* Register is write-only */
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XT_REGF_COPROC0
= 0x02,
/* Can't be read if coproc0 isn't enabled */
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XT_REGF_MASK
= 0x03
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};
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struct
xtensa_reg_desc
{
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const
char
*
name
;
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bool
exist
;
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unsigned
int
reg_num
;
/* ISA register num (meaning depends on register type) */
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unsigned
int
dbreg_num
;
/* Debugger-visible register num (reg type encoded) */
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enum
xtensa_reg_type
type
;
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enum
xtensa_reg_flags
flags
;
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};
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#define _XT_MK_DBREGN(reg_num, reg_type) \
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((reg_type ## _VAL) | (reg_num))
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#define _XT_MK_DBREGN_MASK(reg_num, reg_mask) \
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((reg_mask) | (reg_num))
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#define XT_MK_REG_DESC(n, r, t, f) \
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{ .name = (n), .exist = false, .reg_num = (r), \
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.dbreg_num = _XT_MK_DBREGN(r, t), .type = (t), \
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.flags = (f) }
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extern
struct
xtensa_reg_desc
xtensa_regs
[
XT_NUM_REGS
];
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#endif
/* OPENOCD_TARGET_XTENSA_REGS_H */
reg_arch_type
Definition:
register.h:151
xtensa_reg_desc
Definition:
xtensa_regs.h:113
xtensa_reg_desc::reg_num
unsigned int reg_num
Definition:
xtensa_regs.h:116
xtensa_reg_desc::exist
bool exist
Definition:
xtensa_regs.h:115
xtensa_reg_desc::flags
enum xtensa_reg_flags flags
Definition:
xtensa_regs.h:119
xtensa_reg_desc::name
const char * name
Definition:
xtensa_regs.h:114
xtensa_reg_desc::dbreg_num
unsigned int dbreg_num
Definition:
xtensa_regs.h:117
xtensa_reg_desc::type
enum xtensa_reg_type type
Definition:
xtensa_regs.h:118
xtensa_reg_id
xtensa_reg_id
Definition:
xtensa_regs.h:15
XT_REG_IDX_AR12
@ XT_REG_IDX_AR12
Definition:
xtensa_regs.h:30
XT_REG_IDX_AR10
@ XT_REG_IDX_AR10
Definition:
xtensa_regs.h:28
XT_REG_IDX_A15
@ XT_REG_IDX_A15
Definition:
xtensa_regs.h:66
XT_REG_IDX_A0
@ XT_REG_IDX_A0
Definition:
xtensa_regs.h:51
XT_REG_IDX_IBREAKA1
@ XT_REG_IDX_IBREAKA1
Definition:
xtensa_regs.h:41
XT_REG_IDX_A1
@ XT_REG_IDX_A1
Definition:
xtensa_regs.h:52
XT_REG_IDX_AR5
@ XT_REG_IDX_AR5
Definition:
xtensa_regs.h:23
XT_REG_IDX_AR14
@ XT_REG_IDX_AR14
Definition:
xtensa_regs.h:32
XT_REG_IDX_PS
@ XT_REG_IDX_PS
Definition:
xtensa_regs.h:37
XT_REG_IDX_ARFIRST
@ XT_REG_IDX_ARFIRST
Definition:
xtensa_regs.h:18
XT_REG_IDX_A13
@ XT_REG_IDX_A13
Definition:
xtensa_regs.h:64
XT_REG_IDX_ARLAST
@ XT_REG_IDX_ARLAST
Definition:
xtensa_regs.h:34
XT_REG_IDX_A9
@ XT_REG_IDX_A9
Definition:
xtensa_regs.h:60
XT_REG_IDX_AR6
@ XT_REG_IDX_AR6
Definition:
xtensa_regs.h:24
XT_REG_IDX_PC
@ XT_REG_IDX_PC
Definition:
xtensa_regs.h:16
XT_REG_IDX_DDR
@ XT_REG_IDX_DDR
Definition:
xtensa_regs.h:39
XT_REG_IDX_DEBUGCAUSE
@ XT_REG_IDX_DEBUGCAUSE
Definition:
xtensa_regs.h:48
XT_REG_IDX_AR1
@ XT_REG_IDX_AR1
Definition:
xtensa_regs.h:19
XT_REG_IDX_AR15
@ XT_REG_IDX_AR15
Definition:
xtensa_regs.h:33
XT_REG_IDX_DBREAKC1
@ XT_REG_IDX_DBREAKC1
Definition:
xtensa_regs.h:45
XT_REG_IDX_A3
@ XT_REG_IDX_A3
Definition:
xtensa_regs.h:54
XT_REG_IDX_A11
@ XT_REG_IDX_A11
Definition:
xtensa_regs.h:62
XT_REG_IDX_AR0
@ XT_REG_IDX_AR0
Definition:
xtensa_regs.h:17
XT_REG_IDX_ICOUNT
@ XT_REG_IDX_ICOUNT
Definition:
xtensa_regs.h:49
XT_REG_IDX_AR9
@ XT_REG_IDX_AR9
Definition:
xtensa_regs.h:27
XT_REG_IDX_ICOUNTLEVEL
@ XT_REG_IDX_ICOUNTLEVEL
Definition:
xtensa_regs.h:50
XT_REG_IDX_A7
@ XT_REG_IDX_A7
Definition:
xtensa_regs.h:58
XT_REG_IDX_A12
@ XT_REG_IDX_A12
Definition:
xtensa_regs.h:63
XT_REG_IDX_AR8
@ XT_REG_IDX_AR8
Definition:
xtensa_regs.h:26
XT_REG_IDX_A6
@ XT_REG_IDX_A6
Definition:
xtensa_regs.h:57
XT_REG_IDX_AR2
@ XT_REG_IDX_AR2
Definition:
xtensa_regs.h:20
XT_REG_IDX_AR11
@ XT_REG_IDX_AR11
Definition:
xtensa_regs.h:29
XT_REG_IDX_DBREAKC0
@ XT_REG_IDX_DBREAKC0
Definition:
xtensa_regs.h:44
XT_NUM_REGS
@ XT_NUM_REGS
Definition:
xtensa_regs.h:67
XT_REG_IDX_A10
@ XT_REG_IDX_A10
Definition:
xtensa_regs.h:61
XT_REG_IDX_A4
@ XT_REG_IDX_A4
Definition:
xtensa_regs.h:55
XT_REG_IDX_EXCCAUSE
@ XT_REG_IDX_EXCCAUSE
Definition:
xtensa_regs.h:47
XT_REG_IDX_AR4
@ XT_REG_IDX_AR4
Definition:
xtensa_regs.h:22
XT_REG_IDX_DBREAKA0
@ XT_REG_IDX_DBREAKA0
Definition:
xtensa_regs.h:42
XT_REG_IDX_A14
@ XT_REG_IDX_A14
Definition:
xtensa_regs.h:65
XT_REG_IDX_DBREAKA1
@ XT_REG_IDX_DBREAKA1
Definition:
xtensa_regs.h:43
XT_REG_IDX_A2
@ XT_REG_IDX_A2
Definition:
xtensa_regs.h:53
XT_REG_IDX_AR7
@ XT_REG_IDX_AR7
Definition:
xtensa_regs.h:25
XT_REG_IDX_WINDOWSTART
@ XT_REG_IDX_WINDOWSTART
Definition:
xtensa_regs.h:36
XT_REG_IDX_A5
@ XT_REG_IDX_A5
Definition:
xtensa_regs.h:56
XT_REG_IDX_IBREAKENABLE
@ XT_REG_IDX_IBREAKENABLE
Definition:
xtensa_regs.h:38
XT_REG_IDX_WINDOWBASE
@ XT_REG_IDX_WINDOWBASE
Definition:
xtensa_regs.h:35
XT_REG_IDX_CPENABLE
@ XT_REG_IDX_CPENABLE
Definition:
xtensa_regs.h:46
XT_REG_IDX_AR3
@ XT_REG_IDX_AR3
Definition:
xtensa_regs.h:21
XT_REG_IDX_AR13
@ XT_REG_IDX_AR13
Definition:
xtensa_regs.h:31
XT_REG_IDX_A8
@ XT_REG_IDX_A8
Definition:
xtensa_regs.h:59
XT_REG_IDX_IBREAKA0
@ XT_REG_IDX_IBREAKA0
Definition:
xtensa_regs.h:40
xtensa_reg_type
xtensa_reg_type
Definition:
xtensa_regs.h:74
XT_REG_TYPE_NUM
@ XT_REG_TYPE_NUM
Definition:
xtensa_regs.h:84
XT_REG_GENERAL_VAL
@ XT_REG_GENERAL_VAL
Definition:
xtensa_regs.h:88
XT_REG_RELGEN_MASK
@ XT_REG_RELGEN_MASK
Definition:
xtensa_regs.h:95
XT_REG_USER
@ XT_REG_USER
Definition:
xtensa_regs.h:76
XT_REG_INDEX_MASK
@ XT_REG_INDEX_MASK
Definition:
xtensa_regs.h:104
XT_REG_OTHER_VAL
@ XT_REG_OTHER_VAL
Definition:
xtensa_regs.h:102
XT_REG_DEBUG
@ XT_REG_DEBUG
Definition:
xtensa_regs.h:78
XT_REG_RELGEN
@ XT_REG_RELGEN
Definition:
xtensa_regs.h:79
XT_REG_SPECIAL_MASK
@ XT_REG_SPECIAL_MASK
Definition:
xtensa_regs.h:91
XT_REG_SPECIAL_VAL
@ XT_REG_SPECIAL_VAL
Definition:
xtensa_regs.h:92
XT_REG_DEBUG_MASK
@ XT_REG_DEBUG_MASK
Definition:
xtensa_regs.h:93
XT_REG_USER_VAL
@ XT_REG_USER_VAL
Definition:
xtensa_regs.h:90
XT_REG_FR_VAL
@ XT_REG_FR_VAL
Definition:
xtensa_regs.h:98
XT_REG_USER_MASK
@ XT_REG_USER_MASK
Definition:
xtensa_regs.h:89
XT_REG_RELGEN_VAL
@ XT_REG_RELGEN_VAL
Definition:
xtensa_regs.h:96
XT_REG_GENERAL
@ XT_REG_GENERAL
Definition:
xtensa_regs.h:75
XT_REG_GENERAL_MASK
@ XT_REG_GENERAL_MASK
Definition:
xtensa_regs.h:87
XT_REG_OTHER
@ XT_REG_OTHER
Definition:
xtensa_regs.h:83
XT_REG_DEBUG_VAL
@ XT_REG_DEBUG_VAL
Definition:
xtensa_regs.h:94
XT_REG_SPECIAL
@ XT_REG_SPECIAL
Definition:
xtensa_regs.h:77
XT_REG_TIE
@ XT_REG_TIE
Definition:
xtensa_regs.h:82
XT_REG_FR
@ XT_REG_FR
Definition:
xtensa_regs.h:81
XT_REG_TIE_MASK
@ XT_REG_TIE_MASK
Definition:
xtensa_regs.h:99
XT_REG_FR_MASK
@ XT_REG_FR_MASK
Definition:
xtensa_regs.h:97
XT_REG_TIE_VAL
@ XT_REG_TIE_VAL
Definition:
xtensa_regs.h:100
XT_REG_OTHER_MASK
@ XT_REG_OTHER_MASK
Definition:
xtensa_regs.h:101
xtensa_reg_flags
xtensa_reg_flags
Definition:
xtensa_regs.h:107
XT_REGF_COPROC0
@ XT_REGF_COPROC0
Definition:
xtensa_regs.h:109
XT_REGF_MASK
@ XT_REGF_MASK
Definition:
xtensa_regs.h:110
XT_REGF_NOREAD
@ XT_REGF_NOREAD
Definition:
xtensa_regs.h:108
xtensa_reg_val_t
uint32_t xtensa_reg_val_t
Definition:
xtensa_regs.h:70
xtensa_regs
struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS]
Definition:
xtensa.c:181
src
target
xtensa
xtensa_regs.h
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