51 target_addr_t address,
int handle_breakpoints,
int debug_execution);
65 #include "../../contrib/loaders/debug/xscale/debug_handler.inc"
121 uint8_t buf[4] = { 0 };
146 uint8_t scratch[4] = { 0 };
148 memset(&field, 0,
sizeof(field));
164 uint8_t field0 = 0x0;
165 uint8_t field0_check_value = 0x2;
166 uint8_t field0_check_mask = 0x7;
167 uint8_t field2 = 0x0;
168 uint8_t field2_check_value = 0x0;
169 uint8_t field2_check_mask = 0x1;
178 memset(&fields, 0,
sizeof(fields));
200 LOG_ERROR(
"JTAG error while reading DCSR");
210 field0_check_mask = 0x1;
224 uint8_t *in = (uint8_t *)arg;
237 uint8_t *field0 = malloc(num_words * 1);
238 uint8_t field0_check_value = 0x2;
239 uint8_t field0_check_mask = 0x6;
240 uint32_t *field1 = malloc(num_words * 4);
241 uint8_t field2_check_value = 0x0;
242 uint8_t field2_check_mask = 0x1;
244 int words_scheduled = 0;
251 memset(&fields, 0,
sizeof(fields));
275 while (words_done < num_words) {
278 for (i = words_done; i < num_words; i++) {
283 fields[1].
in_value = (uint8_t *)(field1 + i);
294 LOG_ERROR(
"JTAG error while receiving data from debug handler");
299 for (i = words_done; i < num_words; i++) {
300 if (!(field0[i] & 1)) {
303 for (j = i; j < num_words - 1; j++) {
304 field0[j] = field0[j + 1];
305 field1[j] = field1[j + 1];
310 if (words_scheduled == 0) {
311 if (attempts++ == 1000) {
313 "Failed to receiving data from debug handler after 1000 attempts");
319 words_done += words_scheduled;
322 for (i = 0; i < num_words; i++)
338 uint8_t field0_in = 0x0;
339 uint8_t field0_check_value = 0x2;
340 uint8_t field0_check_mask = 0x6;
341 uint8_t field2_check_value = 0x0;
342 uint8_t field2_check_mask = 0x1;
359 memset(&fields, 0,
sizeof(fields));
391 LOG_ERROR(
"JTAG error while reading TX");
397 LOG_ERROR(
"time out reading TX register");
400 if (!((!(field0_in & 1)) && consume))
410 if (!(field0_in & 1))
422 uint8_t field0_out = 0x0;
423 uint8_t field0_in = 0x0;
424 uint8_t field0_check_value = 0x2;
425 uint8_t field0_check_mask = 0x6;
426 uint8_t field2 = 0x0;
427 uint8_t field2_check_value = 0x0;
428 uint8_t field2_check_mask = 0x1;
434 memset(&fields, 0,
sizeof(fields));
461 LOG_ERROR(
"JTAG error while writing RX");
468 LOG_ERROR(
"time out writing RX register");
471 if (!(field0_in & 1))
487 LOG_ERROR(
"JTAG error while writing RX");
505 static const uint8_t t0;
506 uint8_t t1[4] = { 0 };
507 static const uint8_t t2 = 1;
509 { .
num_bits = 3, .out_value = &t0 },
510 { .num_bits = 32, .out_value = t1 },
511 { .num_bits = 1, .out_value = &t2 },
515 while (done_count++ <
count) {
535 LOG_ERROR(
"BUG: size neither 4, 2 nor 1");
550 LOG_ERROR(
"JTAG error while sending data to debug handler");
570 uint8_t field0 = 0x0;
571 uint8_t field0_check_value = 0x2;
572 uint8_t field0_check_mask = 0x7;
573 uint8_t field2 = 0x0;
574 uint8_t field2_check_value = 0x0;
575 uint8_t field2_check_mask = 0x1;
580 if (ext_dbg_brk != -1)
590 memset(&fields, 0,
sizeof(fields));
612 LOG_ERROR(
"JTAG error while writing DCSR");
623 static unsigned int parity(
unsigned int v)
631 return (0x6996 >> v) & 1;
637 uint8_t packet[4] = { 0 };
642 LOG_DEBUG(
"loading miniIC at 0x%8.8" PRIx32
"", va);
658 memset(&fields, 0,
sizeof(fields));
675 for (word = 0; word < 8; word++) {
679 memcpy(&value, packet,
sizeof(uint32_t));
691 uint8_t packet[4] = { 0 };
705 memset(&fields, 0,
sizeof(fields));
724 uint32_t low_reset_branch, high_reset_branch;
726 for (i = 1; i < 8; i++) {
741 for (i = 1; i < 8; i++) {
757 high_reset_branch = (xscale->
handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
777 static const char *
state[] = {
778 "disabled",
"enabled"
781 static const char *arch_dbg_reason[] = {
782 "",
"\n(processor reset)",
"\n(trace buffer full)"
786 LOG_ERROR(
"BUG: called for a non-ARMv4/5 target");
791 LOG_USER(
"MMU: %s, D-Cache: %s, I-Cache: %s%s",
815 LOG_USER(
"error while polling TX register, reset CPU");
871 for (i = 1; i <= 7; i++) {
883 LOG_ERROR(
"cpsr contains invalid mode value - communication failure");
886 LOG_DEBUG(
"target entered debug state in %s mode",
901 for (i = 8; i <= 14; i++) {
959 LOG_ERROR(
"Method of Entry is 'Reserved'");
969 uint32_t cache_type_reg;
1020 LOG_ERROR(
"target was in unknown state when halt was requested");
1023 LOG_DEBUG(
"target->state == TARGET_RESET");
1049 "BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1110 target_addr_t address,
int handle_breakpoints,
int debug_execution)
1114 uint32_t current_pc;
1125 if (!debug_execution)
1140 if (current_pc == 0x0) {
1146 if (handle_breakpoints) {
1162 uint32_t current_opcode;
1165 "BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"",
1183 LOG_DEBUG(
"writing cpsr with value 0x%8.8" PRIx32,
1186 for (i = 7; i >= 0; i--) {
1190 LOG_DEBUG(
"writing r%i with value 0x%8.8" PRIx32
"",
1197 LOG_DEBUG(
"writing PC with value 0x%8.8" PRIx32,
1248 LOG_DEBUG(
"writing cpsr with value 0x%8.8" PRIx32,
1251 for (i = 7; i >= 0; i--) {
1254 LOG_DEBUG(
"writing r%i with value 0x%8.8" PRIx32
"",
1260 LOG_DEBUG(
"wrote PC with value 0x%8.8" PRIx32,
1265 if (!debug_execution) {
1281 uint32_t
address,
int handle_breakpoints)
1294 uint32_t current_opcode, current_pc;
1299 "BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"",
1334 LOG_DEBUG(
"writing cpsr with value 0x%8.8" PRIx32,
1337 for (i = 7; i >= 0; i--) {
1343 LOG_DEBUG(
"writing r%i with value 0x%8.8" PRIx32
"", i,
1352 LOG_DEBUG(
"wrote PC with value 0x%8.8" PRIx32,
1381 uint32_t current_pc;
1396 if (current_pc == 0x0) {
1401 LOG_DEBUG(
"current pc %" PRIx32, current_pc);
1410 if (handle_breakpoints)
1438 LOG_WARNING(
"Reset is not asserted because the target is not examined.");
1439 LOG_WARNING(
"Use a reset button or power cycle the target.");
1544 binary_size -= buf_cnt,
buffer += buf_cnt) {
1545 uint32_t cache_line[8];
1548 buf_cnt = binary_size;
1552 for (i = 0; i < buf_cnt; i += 4) {
1557 for (; i < 32; i += 4)
1558 cache_line[i / 4] = 0xe1a08008;
1561 if ((
address % 0x400) != 0x0) {
1645 for (i = 1; i < 7; i++) {
1655 for (j = 0;
valid && j <= 16; j++) {
1686 for (j = 8; j <= 14; j++) {
1717 for (i = 1; i < 7; i++) {
1725 for (j = 8; j <= 14; j++) {
1751 for (j = 8; j <= 14; j++) {
1792 if (((
size == 4) && (address & 0x3u)) || ((
size == 2) && (address & 0x1u)))
1811 buf32 = malloc(4 *
count);
1819 for (i = 0; i <
count; i++) {
1830 *
buffer++ = buf32[i] & 0xff;
1866 LOG_ERROR(
"%s: %s is not implemented. Disable MMU?",
1891 if (((
size == 4) && (address & 0x3u)) || ((
size == 2) && (address & 0x1u)))
1911 for (i = 0; i <
count; i++) {
1965 LOG_ERROR(
"%s: %s is not implemented. Disable MMU?",
1987 int d_u_cache,
int i_cache)
1990 uint32_t cp15_control;
2000 cp15_control &= ~0x1U;
2016 cp15_control &= ~0x4U;
2024 cp15_control &= ~0x1000U;
2038 int d_u_cache,
int i_cache)
2041 uint32_t cp15_control;
2051 cp15_control |= 0x1U;
2054 cp15_control |= 0x4U;
2057 cp15_control |= 0x1000U;
2098 LOG_ERROR(
"BUG: no hardware comparator available");
2144 LOG_ERROR(
"no breakpoint unit available for hardware breakpoint");
2149 LOG_ERROR(
"only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2230 uint32_t enable = 0;
2250 LOG_ERROR(
"BUG: watchpoint->rw neither read, write nor access");
2257 LOG_ERROR(
"BUG: sufficient hardware comparators unavailable");
2271 dbcon_value |= enable;
2277 dbcon_value |= enable << 2;
2282 LOG_ERROR(
"BUG: no hardware comparator available");
2295 LOG_ERROR(
"no more watchpoint registers available");
2300 LOG_WARNING(
"xscale does not support value, mask arguments; ignoring");
2305 LOG_ERROR(
"xscale requires that watchpoint length is a power of two");
2317 LOG_ERROR(
"insufficient watchpoint registers available");
2322 LOG_ERROR(
"xscale does not support watchpoints with length "
2323 "greater than address");
2350 dbcon_value &= ~0x103;
2353 dbcon_value &= ~0x3;
2358 dbcon_value &= ~0xc;
2394 if (strcmp(
reg->
name,
"XSCALE_DCSR") == 0)
2396 else if (strcmp(
reg->
name,
"XSCALE_TX") == 0) {
2399 }
else if (strcmp(
reg->
name,
"XSCALE_RX") == 0) {
2402 }
else if (strcmp(
reg->
name,
"XSCALE_TXRXCTRL") == 0) {
2431 if (strcmp(
reg->
name,
"XSCALE_DCSR") == 0) {
2434 }
else if (strcmp(
reg->
name,
"XSCALE_RX") == 0) {
2437 }
else if (strcmp(
reg->
name,
"XSCALE_TX") == 0) {
2440 }
else if (strcmp(
reg->
name,
"XSCALE_TXRXCTRL") == 0) {
2487 uint32_t trace_buffer[258];
2488 int is_address[256];
2493 LOG_WARNING(
"target must be stopped to read trace data");
2504 for (i = 255; i >= 0; i--) {
2506 if ((trace_buffer[i] & 0xe0) == 0xc0)
2510 if (((trace_buffer[i] & 0xf0) == 0x90) ||
2511 ((trace_buffer[i] & 0xf0) == 0xd0)) {
2513 is_address[--i] = 1;
2515 is_address[--i] = 1;
2517 is_address[--i] = 1;
2519 is_address[--i] = 1;
2525 for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
2534 if (is_address[0]) {
2537 if (!is_address[i++])
2544 if (((trace_buffer[j] & 0xf0) == 0x90) || ((trace_buffer[j] & 0xf0) == 0xd0))
2548 for (trace_data_p = &xscale->
trace.
data; *trace_data_p;
2549 trace_data_p = &(*trace_data_p)->
next)
2553 (*trace_data_p)->next =
NULL;
2554 (*trace_data_p)->chkpt0 = trace_buffer[256];
2555 (*trace_data_p)->chkpt1 = trace_buffer[257];
2558 (*trace_data_p)->depth = 256 - j;
2561 for (i = j; i < 256; i++) {
2562 (*trace_data_p)->entries[i - j].data = trace_buffer[i];
2594 if (section == -1) {
2603 4, buf, &size_read);
2605 LOG_ERROR(
"error while reading instruction");
2614 2, buf, &size_read);
2616 LOG_ERROR(
"error while reading instruction");
2622 LOG_ERROR(
"BUG: unknown core state encountered");
2660 uint32_t breakpoint_pc = 0;
2662 uint32_t current_pc = 0;
2665 LOG_WARNING(
"No trace image loaded; use 'xscale trace_image'");
2668 while (trace_data) {
2676 for (i = 0; i < trace_data->
depth; i++) {
2678 uint32_t chkpt_reg = 0x0;
2679 uint32_t branch_target = 0;
2683 int trace_msg_type = (trace_data->
entries[i].
data & 0xf0) >> 4;
2690 switch (trace_msg_type) {
2699 exception = (trace_data->
entries[i].
data & 0x70) >> 4;
2702 branch_target = (trace_data->
entries[i].
data & 0xf0) >> 2;
2715 chkpt_reg = trace_data->
chkpt1;
2718 chkpt_reg = trace_data->
chkpt0;
2726 chkpt_reg = trace_data->
chkpt1;
2729 chkpt_reg = trace_data->
chkpt0;
2733 if (current_pc == 0)
2734 branch_target = chkpt_reg;
2743 LOG_WARNING(
"trace is suspect: invalid trace message byte");
2753 if (current_pc == 0) {
2754 current_pc = branch_target;
2761 for (j = 0; j <
count; j++) {
2769 if ((trace_msg_type == 15) || (exception > 0 && exception < 4)) {
2775 if (trace_msg_type == 15)
2788 if ((trace_msg_type == 8) || (trace_msg_type == 12)) {
2796 if (trace_msg_type == 12) {
2797 if (current_pc == 0)
2798 current_pc = chkpt_reg;
2799 else if (current_pc != chkpt_reg)
2800 LOG_WARNING(
"trace is suspect: checkpoint register "
2801 "inconsistent with address from image");
2804 if (current_pc == 0)
2811 if ((trace_msg_type == 9) || (trace_msg_type == 13)) {
2812 current_pc = branch_target;
2815 if ((trace_msg_type == 13) && (chkpt_reg != branch_target))
2816 LOG_WARNING(
"trace is suspect: checkpoint register "
2817 "inconsistent with address from trace buffer");
2823 trace_data = trace_data->
next;
2832 if (current_pc == 0)
2836 int gap_count = (breakpoint_pc - current_pc) /
2840 if (gap_count < 0 || gap_count > 16) {
2841 LOG_WARNING(
"trace is suspect: excessive gap at end of trace");
2846 for (i = 0; i < gap_count; i++) {
2870 (*cache_p)->next = malloc(
sizeof(
struct reg_cache));
2871 cache_p = &(*cache_p)->
next;
2874 (*cache_p)->
name =
"XScale registers";
2875 (*cache_p)->next =
NULL;
2876 (*cache_p)->reg_list = calloc(num_regs,
sizeof(
struct reg));
2877 (*cache_p)->num_regs = num_regs;
2879 for (i = 0; i < num_regs; i++) {
2881 (*cache_p)->reg_list[i].value = calloc(4, 1);
2882 (*cache_p)->reg_list[i].dirty =
false;
2883 (*cache_p)->reg_list[i].valid =
false;
2884 (*cache_p)->reg_list[i].size = 32;
2885 (*cache_p)->reg_list[i].arch_info = &arch_info[i];
2887 (*cache_p)->reg_list[i].exist =
true;
2929 uint32_t high_reset_branch, low_reset_branch;
2956 high_reset_branch = (xscale->
handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
2961 for (i = 1; i <= 7; i++) {
2980 LOG_INFO(
"%s: hardware has 2 breakpoints and 2 watchpoints",
3020 LOG_ERROR(
"debug_handler.bin: larger than 2kb");
3024 xscale = calloc(1,
sizeof(*xscale));
3059 "xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3089 LOG_ERROR(
"xscale cache_clean_address <address> must be 64kb aligned");
3122 virtual, &cb, &ret);
3186 bool icache =
false;
3187 if (strcmp(
CMD_NAME,
"icache") == 0)
3207 bool enabled = icache ?
3210 const char *msg = enabled ?
"enabled" :
"disabled";
3216 static const struct {
3234 uint32_t dcsr_value;
3244 if (strcmp(
CMD_ARGV[0],
"all") == 0) {
3247 }
else if (strcmp(
CMD_ARGV[0],
"none") == 0) {
3273 (dcsr_value &
vec_ids[i].
mask) ?
"catch" :
"ignore");
3295 for (idx = 1; idx < 8; idx++)
3298 "low %d: 0x%" PRIx32,
3301 for (idx = 1; idx < 8; idx++)
3304 "high %d: 0x%" PRIx32,
3318 if (idx < 1 || idx >= 8)
3321 if (!err && strcmp(
CMD_ARGV[0],
"low") == 0) {
3324 }
else if (!err && (strcmp(
CMD_ARGV[0],
"high") == 0)) {
3342 uint32_t dcsr_value;
3355 if (strcmp(
"enable",
CMD_ARGV[0]) == 0)
3357 else if (strcmp(
"disable",
CMD_ARGV[0]) == 0)
3364 if (strcmp(
"fill",
CMD_ARGV[1]) == 0) {
3368 if (buffcount < 1) {
3375 }
else if (strcmp(
"wrap",
CMD_ARGV[1]) == 0)
3384 char fill_string[12];
3388 ? fill_string :
"wrap");
3471 while (trace_data) {
3479 for (i = 0; i < trace_data->
depth; i++)
3483 trace_data = trace_data->
next;
3520 uint32_t reg_no = 0;
3588 .
name =
"cache_info",
3589 .handler = xscale_handle_cache_info_command,
3591 .help =
"display information about CPU caches",
3596 .handler = xscale_handle_mmu_command,
3598 .help =
"enable or disable the MMU",
3599 .usage =
"['enable'|'disable']",
3603 .handler = xscale_handle_idcache_command,
3605 .help =
"display ICache state, optionally enabling or "
3607 .usage =
"['enable'|'disable']",
3611 .handler = xscale_handle_idcache_command,
3613 .help =
"display DCache state, optionally enabling or "
3615 .usage =
"['enable'|'disable']",
3618 .name =
"vector_catch",
3619 .handler = xscale_handle_vector_catch_command,
3621 .help =
"set or display mask of vectors "
3622 "that should trigger debug entry",
3623 .usage =
"['all'|'none'|'fiq'|'irq'|'dabt'|'pabt'|'swi'|'undef'|'reset']",
3626 .name =
"vector_table",
3627 .handler = xscale_handle_vector_table_command,
3629 .help =
"set vector table entry in mini-ICache, "
3630 "or display current tables",
3631 .usage =
"[('high'|'low') index code]",
3634 .name =
"trace_buffer",
3635 .handler = xscale_handle_trace_buffer_command,
3637 .help =
"display trace buffer status, enable or disable "
3638 "tracing, and optionally reconfigure trace mode",
3639 .usage =
"['enable'|'disable' ['fill' [number]|'wrap']]",
3642 .name =
"dump_trace",
3643 .handler = xscale_handle_dump_trace_command,
3645 .help =
"dump content of trace buffer to file",
3646 .usage =
"filename",
3649 .name =
"analyze_trace",
3650 .handler = xscale_handle_analyze_trace_buffer_command,
3652 .help =
"analyze content of trace buffer",
3656 .name =
"trace_image",
3657 .handler = xscale_handle_trace_image_command,
3659 .help =
"load image from file to address (default 0)",
3660 .usage =
"filename [offset [filetype]]",
3664 .handler = xscale_handle_cp15,
3666 .help =
"Read or write coprocessor 15 register.",
3667 .usage =
"register [value]",
3673 .
name =
"debug_handler",
3674 .handler = xscale_handle_debug_handler_command,
3676 .help =
"Change address used for debug handler.",
3677 .usage =
"<target> <address>",
3680 .name =
"cache_clean_address",
3681 .handler = xscale_handle_cache_clean_address_command,
3683 .help =
"Change address used for cleaning data cache.",
3698 .help =
"xscale command group",
int arm_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Runs ARM code in the target to check whether a memory block holds all ones.
int arm_arch_state(struct target *target)
int arm_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Runs ARM code in the target to calculate a CRC32 checksum.
struct reg_cache * arm_build_reg_cache(struct target *target, struct arm *arm)
int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
arm_mode
Represent state of an ARM core.
int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
void arm_free_reg_cache(struct arm *arm)
const char * arm_get_gdb_arch(struct target *target)
bool is_arm_mode(unsigned psr_mode)
Return true iff the parameter denotes a valid ARM processor mode.
const struct command_registration arm_command_handlers[]
const char * arm_mode_name(unsigned psr_mode)
Map PSR mode bits to the name of an ARM processor operating mode.
static struct arm * target_to_arm(struct target *target)
Convert target handle to generic ARM target state handle.
int arm_init_arch_info(struct target *target, struct arm *arm)
void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
Configures host-side ARM records to reflect the specified CPSR.
struct reg * arm_reg_current(struct arm *arm, unsigned regnum)
Returns handle to the register currently mapped to a given number.
int arm_evaluate_opcode(uint32_t opcode, uint32_t address, struct arm_instruction *instruction)
int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, struct arm_instruction *instruction)
Macros used to generate various ARM or Thumb opcodes.
int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
enum arm_mode armv4_5_number_to_mode(int number)
Map linear number indexing armv4_5_core_reg_map to PSR mode bits.
#define ARMV4_5_CORE_REG_MODE(cache, mode, num)
int armv4_5_identify_cache(uint32_t cache_type_reg, struct armv4_5_cache_common *cache)
int armv4_5_handle_cache_info_command(struct command_invocation *cmd, struct armv4_5_cache_common *armv4_5_cache)
int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val)
void * buf_cpy(const void *from, void *_to, unsigned size)
Copies size bits out of from and into to.
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
struct breakpoint * breakpoint_find(struct target *target, target_addr_t address)
static void watchpoint_set(struct watchpoint *watchpoint, unsigned int number)
static void breakpoint_hw_set(struct breakpoint *breakpoint, unsigned int hw_number)
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CMD_NAME
Use this macro to access the name of the command being handled, rather than accessing the variable di...
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_PARSE_ENABLE(in, out)
parses an enable/disable command argument
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
#define ERROR_COMMAND_ARGUMENT_INVALID
int fileio_write_u32(struct fileio *fileio, uint32_t data)
int fileio_close(struct fileio *fileio)
int fileio_open(struct fileio **fileio, const char *url, enum fileio_access access_type, enum fileio_type type)
void image_close(struct image *image)
int image_read_section(struct image *image, int section, target_addr_t offset, uint32_t size, uint8_t *buffer, size_t *size_read)
int image_open(struct image *image, const char *url, const char *type_string)
void jtag_add_pathmove(int num_states, const tap_state_t *path)
Application code must assume that interfaces will implement transitions between states with different...
void jtag_add_reset(int req_tlr_or_trst, int req_srst)
A reset of the TAP state machine can be requested.
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
void jtag_add_dr_scan_check(struct jtag_tap *active, int in_num_fields, struct scan_field *in_fields, tap_state_t state)
A version of jtag_add_dr_scan() that uses the check_value/mask fields.
void jtag_add_sleep(uint32_t us)
void jtag_check_value_mask(struct scan_field *field, uint8_t *value, uint8_t *mask)
Execute jtag queue and check value with an optional mask.
void jtag_add_ir_scan(struct jtag_tap *active, struct scan_field *in_fields, tap_state_t state)
Generate an IR SCAN with a list of scan fields with one entry for each enabled TAP.
void jtag_add_runtest(int num_cycles, tap_state_t state)
Goes to TAP_IDLE (if we're not already there), cycle precisely num_cycles in the TAP_IDLE state,...
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
void jtag_add_callback(jtag_callback1_t f, jtag_callback_data_t data0)
A simpler version of jtag_add_callback4().
enum tap_state tap_state_t
Defines JTAG Test Access Port states.
intptr_t jtag_callback_data_t
Defines the type of data passed to the jtag_callback_t interface.
void alive_sleep(uint64_t ms)
#define LOG_USER(expr ...)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
void register_cache_invalidate(struct reg_cache *cache)
Marks the contents of the register cache as invalid (and clean).
int gettimeofday(struct timeval *tv, struct timezone *tz)
size_t size
Size of the control block search area.
union arm_instruction::@65 info
struct arm_b_bl_bx_blx_instr b_bl_bx_blx
Represents a generic ARM core, with standard application registers.
int(* full_context)(struct target *target)
Retrieve all core registers, for display.
enum arm_core_type core_type
Indicates what registers are in the ARM state core register set.
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
struct reg * cpsr
Handle to the CPSR/xPSR; valid in all core modes.
struct reg * pc
Handle to the PC; valid in all core modes.
int(* write_core_reg)(struct target *target, struct reg *reg, int num, enum arm_mode mode, uint8_t *value)
int(* read_core_reg)(struct target *target, struct reg *reg, int num, enum arm_mode mode)
Retrieve a single core register.
struct reg_cache * core_cache
struct reg * spsr
Handle to the SPSR; valid only in core modes with an SPSR.
unsigned int common_magic
int(* write_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
int(* read_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
int(* get_ttb)(struct target *target, uint32_t *result)
int(* enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache)
int(* disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache)
struct armv4_5_cache_common armv4_5_cache
enum breakpoint_type type
When run_command is called, a new instance will be created on the stack, filled with the proper value...
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
unsigned int num_sections
struct imagesection * sections
target_addr_t base_address
uint8_t * cur_instr
current instruction
int ir_length
size of instruction register
int(* get)(struct reg *reg)
This structure defines a single scan field in the scan.
int num_bits
The number of bits this field specifies.
uint8_t * in_value
A pointer to a 32-bit memory location for data scanned out.
uint8_t * check_value
The value used to check the data scanned out.
const uint8_t * out_value
A pointer to value to be scanned into the device.
uint8_t * check_mask
The mask to go with check_value.
This holds methods shared between all instances of a given target type.
const char * name
Name of this type of target.
enum target_debug_reason debug_reason
enum target_endianness endianness
struct reg_cache * reg_cache
struct breakpoint * breakpoints
struct watchpoint * watchpoints
uint8_t static_low_vectors_set
uint32_t static_high_vectors[8]
uint32_t static_low_vectors[8]
uint32_t cache_clean_address
uint32_t cp15_control_reg
uint8_t static_high_vectors_set
struct reg_cache * reg_cache
struct armv4_5_mmu_common armv4_5_mmu
unsigned int common_magic
struct xscale_trace trace
unsigned int num_checkpoints
struct xscale_trace_data * next
struct xscale_trace_entry * entries
uint32_t last_instruction
enum xscale_trace_entry_type type
struct xscale_trace_data * data
enum arm_state core_state
int target_call_event_callbacks(struct target *target, enum target_event event)
struct target * get_target(const char *id)
void target_free_all_working_areas(struct target *target)
const char * target_state_name(struct target *t)
Return the name of this targets current state.
int target_halt(struct target *target)
void target_buffer_set_u16(struct target *target, uint8_t *buffer, uint16_t value)
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
int target_write_u16(struct target *target, target_addr_t address, uint16_t value)
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
uint16_t target_buffer_get_u16(struct target *target, const uint8_t *buffer)
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
struct target * get_current_target(struct command_context *cmd_ctx)
uint32_t target_buffer_get_u32(struct target *target, const uint8_t *buffer)
#define ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_UNALIGNED_ACCESS
#define ERROR_TARGET_INVALID
@ TARGET_EVENT_DEBUG_RESUMED
@ TARGET_EVENT_DEBUG_HALTED
#define ERROR_TARGET_NOT_EXAMINED
static const char * target_name(struct target *target)
Returns the instance-specific name of the specified target.
#define ERROR_TARGET_TIMEOUT
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
static bool target_was_examined(struct target *target)
#define ERROR_TARGET_DATA_ABORT
#define ERROR_TARGET_FAILURE
int timeval_compare(const struct timeval *x, const struct timeval *y)
int timeval_add_time(struct timeval *result, long sec, long usec)
#define ERROR_TRACE_INSTRUCTION_UNAVAILABLE
#define ERROR_TRACE_IMAGE_UNAVAILABLE
static uint16_t le_to_h_u16(const uint8_t *buf)
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
static uint32_t be_to_h_u32(const uint8_t *buf)
static uint16_t be_to_h_u16(const uint8_t *buf)
static uint32_t le_to_h_u32(const uint8_t *buf)
static int xscale_enable_single_step(struct target *target, uint32_t next_pc)
static int xscale_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
static int xscale_init_arch_info(struct target *target, struct xscale_common *xscale, struct jtag_tap *tap)
static int xscale_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
static int xscale_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
static int xscale_assert_reset(struct target *target)
static int xscale_set_breakpoint(struct target *, struct breakpoint *)
static int xscale_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8])
static void xscale_display_instruction(struct target *target, uint32_t pc, struct arm_instruction *instruction, struct command_invocation *cmd)
static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_brk)
static int xscale_full_context(struct target *target)
static int xscale_target_create(struct target *target, Jim_Interp *interp)
static void xscale_deinit_target(struct target *target)
static int xscale_analyze_trace(struct target *target, struct command_invocation *cmd)
static int xscale_set_watchpoint(struct target *, struct watchpoint *)
static int xscale_verify_pointer(struct command_invocation *cmd, struct xscale_common *xscale)
static int xscale_resume(struct target *, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
static int xscale_read_tx(struct target *target, int consume)
static int xscale_arch_state(struct target *target)
static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
static int xscale_deassert_reset(struct target *target)
static int xscale_read_trace(struct target *)
COMMAND_HANDLER(xscale_handle_debug_handler_command)
static int xscale_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
static int xscale_read_dcsr(struct target *target)
static const uint8_t xscale_debug_handler[]
static int xscale_set_reg(struct reg *reg, uint8_t *buf)
static int xscale_get_ttb(struct target *target, uint32_t *result)
static int xscale_read_core_reg(struct target *target, struct reg *r, int num, enum arm_mode mode)
static unsigned int parity(unsigned int v)
static int xscale_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
static const struct command_registration xscale_any_command_handlers[]
static int xscale_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
static int xscale_get_reg(struct reg *reg)
static const struct reg_arch_type xscale_reg_type
static const struct xscale_reg xscale_reg_arch_info[]
static void xscale_enable_breakpoints(struct target *target)
static const struct command_registration xscale_command_handlers[]
static int xscale_write_rx(struct target *target)
static void xscale_free_trace_data(struct xscale_common *xscale)
static int xscale_write_dcsr_sw(struct target *target, uint32_t value)
static int xscale_mmu(struct target *target, int *enabled)
static void xscale_getbuf(jtag_callback_data_t arg)
static void xscale_free_reg_cache(struct target *target)
static int xscale_receive(struct target *target, uint32_t *buffer, int num_words)
static int xscale_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
static int xscale_poll(struct target *target)
static void xscale_enable_watchpoints(struct target *target)
static void xscale_build_reg_cache(struct target *target)
static int xscale_write_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
static const char xscale_not[]
static int xscale_send_u32(struct target *target, uint32_t value)
static int xscale_restore_banked(struct target *)
static int xscale_init_target(struct command_context *cmd_ctx, struct target *target)
static const struct command_registration xscale_exec_command_handlers[]
static int xscale_step_inner(struct target *target, int current, uint32_t address, int handle_breakpoints)
static int xscale_disable_single_step(struct target *target)
static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
static int xscale_read_instruction(struct target *target, uint32_t pc, struct arm_instruction *instruction)
static int xscale_update_vectors(struct target *target)
static int xscale_debug_entry(struct target *)
static int xscale_write_core_reg(struct target *target, struct reg *r, int num, enum arm_mode mode, uint8_t *value)
static int xscale_read_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static int xscale_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
static int xscale_send(struct target *target, const uint8_t *buffer, int count, int size)
static const struct @118 vec_ids[]
static int xscale_unset_breakpoint(struct target *, struct breakpoint *)
static void xscale_branch_address(struct xscale_trace_data *trace_data, int i, uint32_t *target)
static const char *const xscale_reg_list[]
static int xscale_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static int xscale_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
static int xscale_halt(struct target *target)
struct target_type xscale_target
@ XSCALE_DBG_REASON_RESET
@ XSCALE_DBG_REASON_TB_FULL
@ XSCALE_DBG_REASON_GENERIC
#define XSCALE_IXP4XX_PXA2XX
#define ERROR_XSCALE_NO_TRACE_DATA
static struct xscale_common * target_to_xscale(struct target *target)
#define XSCALE_COMMON_MAGIC