11 #ifndef OPENOCD_TARGET_XSCALE_H
12 #define OPENOCD_TARGET_XSCALE_H
18 #define XSCALE_COMMON_MAGIC 0x58534341U
23 #define XSCALE_DBGRX 0x02
24 #define XSCALE_DBGTX 0x10
25 #define XSCALE_LDIC 0x07
26 #define XSCALE_SELDCSR 0x09
29 #define XSCALE_IXP4XX_PXA2XX 0x0
30 #define XSCALE_PXA3XX 0x4
164 #define ERROR_XSCALE_NO_TRACE_DATA (-700)
167 #define DCSR_TR (1 << 16)
168 #define DCSR_TU (1 << 17)
169 #define DCSR_TS (1 << 18)
170 #define DCSR_TA (1 << 19)
171 #define DCSR_TD (1 << 20)
172 #define DCSR_TI (1 << 22)
173 #define DCSR_TF (1 << 23)
174 #define DCSR_TRAP_MASK \
175 (DCSR_TF | DCSR_TI | DCSR_TD | DCSR_TA | DCSR_TS | DCSR_TU | DCSR_TR)
Holds the interface to ARM cores.
arm_state
The PSR "T" and "J" bits define the mode of "classic ARM" cores.
Represents a generic ARM core, with standard application registers.
uint8_t static_low_vectors_set
uint32_t static_high_vectors[8]
uint32_t static_low_vectors[8]
uint32_t cache_clean_address
uint32_t cp15_control_reg
uint8_t static_high_vectors_set
struct reg_cache * reg_cache
struct armv4_5_mmu_common armv4_5_mmu
unsigned int common_magic
unsigned int num_checkpoints
struct xscale_trace_data * next
struct xscale_trace_entry * entries
uint32_t last_instruction
enum xscale_trace_entry_type type
struct xscale_trace_data * data
enum arm_state core_state
#define container_of(ptr, type, member)
Cast a member of a structure out to the containing structure.
@ XSCALE_DBG_REASON_RESET
@ XSCALE_DBG_REASON_TB_FULL
@ XSCALE_DBG_REASON_GENERIC
static struct xscale_common * target_to_xscale(struct target *target)