OpenOCD
xscale.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2005 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  * *
7  * Copyright (C) 2007,2008 Øyvind Harboe *
8  * oyvind.harboe@zylin.com *
9  ***************************************************************************/
10 
11 #ifndef OPENOCD_TARGET_XSCALE_H
12 #define OPENOCD_TARGET_XSCALE_H
13 
14 #include "arm.h"
15 #include "armv4_5_mmu.h"
16 #include "trace.h"
17 
18 #define XSCALE_COMMON_MAGIC 0x58534341U
19 
20 /* These four JTAG instructions are architecturally defined.
21  * Lengths are core-specific; originally 5 bits, later 7.
22  */
23 #define XSCALE_DBGRX 0x02
24 #define XSCALE_DBGTX 0x10
25 #define XSCALE_LDIC 0x07
26 #define XSCALE_SELDCSR 0x09
27 
28 /* Possible CPU types */
29 #define XSCALE_IXP4XX_PXA2XX 0x0
30 #define XSCALE_PXA3XX 0x4
31 
36 };
37 
41 };
42 
44  uint8_t data;
46 };
47 
50  int depth;
51  uint32_t chkpt0;
52  uint32_t chkpt1;
53  uint32_t last_instruction;
54  unsigned int num_checkpoints;
56 };
57 
58 enum trace_mode {
62 };
63 
64 struct xscale_trace {
65  struct image *image; /* source for target opcodes */
66  struct xscale_trace_data *data; /* linked list of collected trace data */
67  int buffer_fill; /* maximum number of trace runs to read */
68  int fill_counter; /* running count during trace collection */
69  enum trace_mode mode;
70  enum arm_state core_state; /* current core state (ARM, Thumb) */
71 };
72 
73 struct xscale_common {
74  unsigned int common_magic;
75 
76  /* armv4/5 common stuff */
77  struct arm arm;
78 
79  /* XScale registers (CP15, DBG) */
81 
82  /* current state of the debug handler */
83  uint32_t handler_address;
84 
85  /* target-endian buffers with exception vectors */
86  uint32_t low_vectors[8];
87  uint32_t high_vectors[8];
88 
89  /* static low vectors */
90  uint8_t static_low_vectors_set; /* bit field with static vectors set by the user */
91  uint8_t static_high_vectors_set; /* bit field with static vectors set by the user */
92  uint32_t static_low_vectors[8];
93  uint32_t static_high_vectors[8];
94 
95  /* DCache cleaning */
97 
98  /* whether hold_rst and ext_dbg_break should be set */
99  int hold_rst;
101 
102  /* breakpoint / watchpoint handling */
109  uint32_t arm_bkpt;
110  uint16_t thumb_bkpt;
111 
112  uint8_t vector_catch;
113 
114  struct xscale_trace trace;
115 
117 
118  /* MMU/Caches */
121 
123 
124  /* CPU variant */
126 };
127 
128 static inline struct xscale_common *
130 {
131  return container_of(target->arch_info, struct xscale_common, arm);
132 }
133 
134 struct xscale_reg {
136  struct target *target;
137 };
138 
139 enum {
140  XSCALE_MAINID, /* 0 */
150  XSCALE_IBCR0, /* 10 */
160  XSCALE_RX, /* 20 */
162 };
163 
164 #define ERROR_XSCALE_NO_TRACE_DATA (-700)
165 
166 /* DCSR bit and field definitions */
167 #define DCSR_TR (1 << 16)
168 #define DCSR_TU (1 << 17)
169 #define DCSR_TS (1 << 18)
170 #define DCSR_TA (1 << 19)
171 #define DCSR_TD (1 << 20)
172 #define DCSR_TI (1 << 22)
173 #define DCSR_TF (1 << 23)
174 #define DCSR_TRAP_MASK \
175  (DCSR_TF | DCSR_TI | DCSR_TD | DCSR_TA | DCSR_TS | DCSR_TU | DCSR_TR)
176 
177 #endif /* OPENOCD_TARGET_XSCALE_H */
Holds the interface to ARM cores.
arm_state
The PSR "T" and "J" bits define the mode of "classic ARM" cores.
Definition: arm.h:142
Represents a generic ARM core, with standard application registers.
Definition: arm.h:167
Definition: image.h:48
Definition: target.h:120
void * arch_info
Definition: target.h:169
Definition: trace.h:21
uint8_t static_low_vectors_set
Definition: xscale.h:90
uint16_t thumb_bkpt
Definition: xscale.h:110
uint32_t static_high_vectors[8]
Definition: xscale.h:93
uint32_t low_vectors[8]
Definition: xscale.h:86
int arch_debug_reason
Definition: xscale.h:116
int xscale_variant
Definition: xscale.h:125
uint32_t static_low_vectors[8]
Definition: xscale.h:92
uint32_t cache_clean_address
Definition: xscale.h:96
uint32_t cp15_control_reg
Definition: xscale.h:120
int ibcr_available
Definition: xscale.h:106
int dbr0_used
Definition: xscale.h:104
int fast_memory_access
Definition: xscale.h:122
uint8_t static_high_vectors_set
Definition: xscale.h:91
int external_debug_break
Definition: xscale.h:100
int dbr1_used
Definition: xscale.h:105
uint32_t handler_address
Definition: xscale.h:83
int ibcr1_used
Definition: xscale.h:108
int dbr_available
Definition: xscale.h:103
uint32_t high_vectors[8]
Definition: xscale.h:87
int ibcr0_used
Definition: xscale.h:107
uint32_t arm_bkpt
Definition: xscale.h:109
uint8_t vector_catch
Definition: xscale.h:112
int hold_rst
Definition: xscale.h:99
struct reg_cache * reg_cache
Definition: xscale.h:80
struct armv4_5_mmu_common armv4_5_mmu
Definition: xscale.h:119
unsigned int common_magic
Definition: xscale.h:74
int dbg_handler_number
Definition: xscale.h:135
struct target * target
Definition: xscale.h:136
unsigned int num_checkpoints
Definition: xscale.h:54
struct xscale_trace_data * next
Definition: xscale.h:55
uint32_t chkpt0
Definition: xscale.h:51
uint32_t chkpt1
Definition: xscale.h:52
struct xscale_trace_entry * entries
Definition: xscale.h:49
uint32_t last_instruction
Definition: xscale.h:53
Definition: xscale.h:43
uint8_t data
Definition: xscale.h:44
enum xscale_trace_entry_type type
Definition: xscale.h:45
enum trace_mode mode
Definition: xscale.h:69
struct xscale_trace_data * data
Definition: xscale.h:66
int buffer_fill
Definition: xscale.h:67
enum arm_state core_state
Definition: xscale.h:70
struct image * image
Definition: xscale.h:65
int fill_counter
Definition: xscale.h:68
#define container_of(ptr, type, member)
Cast a member of a structure out to the containing structure.
Definition: types.h:68
@ XSCALE_TX
Definition: xscale.h:159
@ XSCALE_FSR
Definition: xscale.h:146
@ XSCALE_CHKPT1
Definition: xscale.h:157
@ XSCALE_IBCR1
Definition: xscale.h:151
@ XSCALE_TXRXCTRL
Definition: xscale.h:161
@ XSCALE_FAR
Definition: xscale.h:147
@ XSCALE_DBCON
Definition: xscale.h:154
@ XSCALE_DAC
Definition: xscale.h:145
@ XSCALE_CTRL
Definition: xscale.h:142
@ XSCALE_TBREG
Definition: xscale.h:155
@ XSCALE_RX
Definition: xscale.h:160
@ XSCALE_DBR1
Definition: xscale.h:153
@ XSCALE_CHKPT0
Definition: xscale.h:156
@ XSCALE_AUXCTRL
Definition: xscale.h:143
@ XSCALE_CPACCESS
Definition: xscale.h:149
@ XSCALE_MAINID
Definition: xscale.h:140
@ XSCALE_CACHETYPE
Definition: xscale.h:141
@ XSCALE_DBR0
Definition: xscale.h:152
@ XSCALE_TTB
Definition: xscale.h:144
@ XSCALE_IBCR0
Definition: xscale.h:150
@ XSCALE_PID
Definition: xscale.h:148
@ XSCALE_DCSR
Definition: xscale.h:158
xscale_debug_reason
Definition: xscale.h:32
@ XSCALE_DBG_REASON_RESET
Definition: xscale.h:34
@ XSCALE_DBG_REASON_TB_FULL
Definition: xscale.h:35
@ XSCALE_DBG_REASON_GENERIC
Definition: xscale.h:33
xscale_trace_entry_type
Definition: xscale.h:38
@ XSCALE_TRACE_MESSAGE
Definition: xscale.h:39
@ XSCALE_TRACE_ADDRESS
Definition: xscale.h:40
static struct xscale_common * target_to_xscale(struct target *target)
Definition: xscale.h:129
trace_mode
Definition: xscale.h:58
@ XSCALE_TRACE_DISABLED
Definition: xscale.h:59
@ XSCALE_TRACE_FILL
Definition: xscale.h:60
@ XSCALE_TRACE_WRAP
Definition: xscale.h:61