40 #define _DEBUG_INSTRUCTION_EXECUTION_
55 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
58 #define CP15PHYS_CACHETYPE ARM920T_CP15_PHYS_ADDR(0, 0x0, 1)
59 #define CP15PHYS_ICACHE_IDX ARM920T_CP15_PHYS_ADDR(1, 0xd, 1)
60 #define CP15PHYS_DCACHE_IDX ARM920T_CP15_PHYS_ADDR(1, 0xe, 1)
64 #define CP15PHYS_CTRL ARM920T_CP15_PHYS_ADDR(0, 0x1, 0)
65 #define CP15PHYS_PID ARM920T_CP15_PHYS_ADDR(0, 0xd, 0)
66 #define CP15PHYS_TESTSTATE ARM920T_CP15_PHYS_ADDR(0, 0xf, 0)
67 #define CP15PHYS_ICACHE ARM920T_CP15_PHYS_ADDR(1, 0x1, 1)
68 #define CP15PHYS_DCACHE ARM920T_CP15_PHYS_ADDR(1, 0x2, 1)
71 int reg_addr, uint32_t *value)
76 uint8_t access_type_buf = 1;
77 uint8_t reg_addr_buf = reg_addr & 0x3f;
108 fields[1].
in_value = (uint8_t *)value;
114 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
116 LOG_DEBUG(
"addr: 0x%x value: %8.8x", reg_addr, *value);
123 int reg_addr, uint32_t value)
128 uint8_t access_type_buf = 1;
129 uint8_t reg_addr_buf = reg_addr & 0x3f;
130 uint8_t nr_w_buf = 1;
131 uint8_t value_buf[4];
163 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
164 LOG_DEBUG(
"addr: 0x%x value: %8.8x", reg_addr, value);
184 uint8_t access_type_buf = 0;
185 uint8_t reg_addr_buf = 0x0;
186 uint8_t nr_w_buf = 0;
187 uint8_t cp15_opcode_buf[4];
226 LOG_ERROR(
"failed executing JTAG queue");
234 uint32_t cp15_opcode, uint32_t address, uint32_t *value)
237 uint32_t *regs_p[16];
239 uint32_t cp15c15 = 0x0;
265 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
266 LOG_DEBUG(
"cp15_opcode: %8.8x, address: %8.8x, value: %8.8x",
267 cp15_opcode, address, *
value);
271 LOG_ERROR(
"not a valid arm core mode - communication failure?");
283 uint32_t cp15_opcode, uint32_t
value, uint32_t address)
285 uint32_t cp15c15 = 0x0;
309 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
310 LOG_DEBUG(
"cp15_opcode: %8.8x, value: %8.8x, address: %8.8x",
311 cp15_opcode,
value, address);
315 LOG_ERROR(
"not a valid arm core mode - communication failure?");
333 0xeebf0f51, 0x0, &ttb);
343 int d_u_cache,
int i_cache)
345 uint32_t cp15_control;
357 cp15_control &= ~0x1U;
360 cp15_control &= ~0x4U;
363 cp15_control &= ~0x1000U;
371 int d_u_cache,
int i_cache)
373 uint32_t cp15_control;
385 cp15_control |= 0x1U;
388 cp15_control |= 0x4U;
391 cp15_control |= 0x1000U;
415 uint32_t cache_type_reg;
450 LOG_DEBUG(
"D FSR: 0x%8.8" PRIx32
", D FAR: 0x%8.8" PRIx32
451 ", I FSR: 0x%8.8" PRIx32
", I FAR: 0x%8.8" PRIx32,
476 uint32_t cp15c15 = 0;
513 static const char *
state[] = {
514 "disabled",
"enabled"
525 LOG_USER(
"MMU: %s, D-Cache: %s, I-Cache: %s",
536 LOG_ERROR(
"%s: target not halted", __func__);
596 const uint32_t cache_mask = ~0x1f;
627 "drain write buffer");
650 LOG_DEBUG(
"D-Cache in 'write back' mode, "
654 address & cache_mask, 1,
655 sizeof(data), &data[0]);
662 sizeof(data), &data[0]);
675 "invalidate cache line");
679 address & cache_mask);
709 "invalidating affected I-Cache line");
712 0x0, address & cache_mask);
760 LOG_ERROR(
"Failed to halt CPU after 1 sec");
790 uint32_t op1, uint32_t op2,
791 uint32_t crn, uint32_t crm,
794 uint32_t op1, uint32_t op2,
795 uint32_t crn, uint32_t crm,
862 uint32_t cp15_ctrl, cp15_ctrl_saved;
864 uint32_t *regs_p[16];
865 uint32_t c15_c_d_ind, c15_c_i_ind;
868 int segment, index_t;
880 LOG_DEBUG(
"error opening cache content file");
884 for (i = 0; i < 16; i++)
885 regs_p[i] = &
regs[i];
892 cp15_ctrl_saved = cp15_ctrl;
902 fprintf(
output,
"DCache:\n");
908 fprintf(
output,
"\nsegment: %i\n----------", segment);
911 regs[0] = 0x0 | (segment << 5);
932 for (index_t = 0; index_t < 64; index_t++) {
936 regs[0] = 0x0 | (segment << 5) | (index_t << 26);
970 regs[9] &= 0xfffffffe;
971 fprintf(
output,
"\nsegment: %i, index: %i, CAM: 0x%8.8"
972 PRIx32
", content (%s):\n",
973 segment, index_t,
regs[9],
974 (
regs[9] & 0x10) ?
"valid" :
"invalid");
976 for (i = 1; i < 9; i++) {
977 fprintf(
output,
"%i: 0x%8.8" PRIx32
"\n",
984 regs[0] = 0x0 | (segment << 5) | (c15_c_d_ind << 26);
1003 fprintf(
output,
"ICache:\n");
1009 fprintf(
output,
"segment: %i\n----------", segment);
1012 regs[0] = 0x0 | (segment << 5);
1033 for (index_t = 0; index_t < 64; index_t++) {
1037 regs[0] = 0x0 | (segment << 5) | (index_t << 26);
1071 regs[9] &= 0xfffffffe;
1072 fprintf(
output,
"\nsegment: %i, index: %i, "
1073 "CAM: 0x%8.8" PRIx32
", content (%s):\n",
1074 segment, index_t,
regs[9],
1075 (
regs[9] & 0x10) ?
"valid" :
"invalid");
1077 for (i = 1; i < 9; i++) {
1078 fprintf(
output,
"%i: 0x%8.8" PRIx32
"\n",
1084 regs[0] = 0x0 | (segment << 5) | (c15_c_d_ind << 26);
1111 LOG_ERROR(
"not a valid arm core mode - communication failure?");
1143 uint32_t cp15_ctrl, cp15_ctrl_saved;
1145 uint32_t *regs_p[16];
1148 uint32_t d_lockdown, i_lockdown;
1162 LOG_DEBUG(
"error opening mmu content file");
1166 for (i = 0; i < 16; i++)
1167 regs_p[i] = &
regs[i];
1174 cp15_ctrl_saved = cp15_ctrl;
1205 d_lockdown =
regs[1];
1207 for (victim = 0; victim < 64; victim += 8) {
1211 regs[1] = (d_lockdown & 0xfc000000) | (victim << 20);
1240 for (i = 0; i < 8; i++)
1241 d_tlb[victim + i].cam =
regs[i + 2];
1244 for (victim = 0; victim < 64; victim++) {
1248 regs[1] = (d_lockdown & 0xfc000000) | (victim << 20);
1284 regs[1] = d_lockdown;
1311 i_lockdown =
regs[1];
1313 for (victim = 0; victim < 64; victim += 8) {
1317 regs[1] = (i_lockdown & 0xfc000000) | (victim << 20);
1346 for (i = 0; i < 8; i++)
1347 i_tlb[i + victim].cam =
regs[i + 2];
1350 for (victim = 0; victim < 64; victim++) {
1354 regs[1] = (d_lockdown & 0xfc000000) | (victim << 20);
1390 regs[1] = i_lockdown;
1401 fprintf(
output,
"D TLB content:\n");
1402 for (i = 0; i < 64; i++) {
1403 fprintf(
output,
"%i: 0x%8.8" PRIx32
" 0x%8.8" PRIx32
1404 " 0x%8.8" PRIx32
" %s\n",
1405 i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2,
1406 (d_tlb[i].cam & 0x20) ?
"(valid)" :
"(invalid)");
1409 fprintf(
output,
"\n\nI TLB content:\n");
1410 for (i = 0; i < 64; i++) {
1411 fprintf(
output,
"%i: 0x%8.8" PRIx32
" 0x%8.8" PRIx32
1412 " 0x%8.8" PRIx32
" %s\n",
1413 i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2,
1414 (i_tlb[i].cam & 0x20) ?
"(valid)" :
"(invalid)");
1423 LOG_ERROR(
"not a valid arm core mode - communication failure?");
1475 "couldn't access reg %i", address);
1491 "couldn't access reg %i", address);
1519 uint32_t op1, uint32_t op2,
1520 uint32_t crn, uint32_t crm,
1535 uint32_t op1, uint32_t op2,
1536 uint32_t crn, uint32_t crm,
1553 .handler = arm920t_handle_cp15_command,
1555 .help =
"display/modify cp15 register",
1556 .usage =
"regnum [value]",
1559 .name =
"cache_info",
1560 .handler = arm920t_handle_cache_info_command,
1563 .help =
"display information about target caches",
1566 .name =
"read_cache",
1567 .handler = arm920t_handle_read_cache_command,
1569 .help =
"dump I/D cache content to file",
1570 .usage =
"filename",
1574 .handler = arm920t_handle_read_mmu_command,
1576 .help =
"dump I/D mmu content to file",
1577 .usage =
"filename",
1588 .help =
"arm920t command group",
int arm7_9_write_memory_opt(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
int arm7_9_examine(struct target *target)
Perform per-target setup that requires JTAG access.
void arm7_9_deinit(struct target *target)
int arm7_9_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
Add a breakpoint to an ARM7/9 target.
int arm7_9_assert_reset(struct target *target)
Asserts the reset (SRST) on an ARM7/9 target.
int arm7_9_poll(struct target *target)
Polls an ARM7/9 target for its current status.
int arm7_9_execute_sys_speed(struct target *target)
Restarts the target by sending a RESTART instruction and moving the JTAG state to IDLE.
int arm7_9_halt(struct target *target)
Halt an ARM7/9 target.
int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
Removes a breakpoint from an ARM7/9 target.
int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
Remove a watchpoint from an ARM7/9 target.
int arm7_9_deassert_reset(struct target *target)
Deassert the reset (SRST) signal on an ARM7/9 target.
int arm7_9_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
int arm7_9_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
Get some data from the ARM7/9 target.
int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
Add a watchpoint to an ARM7/9 target.
int arm7_9_check_reset(struct target *target)
int arm7_9_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
static struct arm7_9_common * target_to_arm7_9(struct target *target)
static const struct command_registration arm920t_exec_command_handlers[]
static int arm920t_write_cp15_physical(struct target *target, int reg_addr, uint32_t value)
int arm920t_post_debug_entry(struct target *target)
#define CP15PHYS_ICACHE_IDX
const struct command_registration arm920t_command_handlers[]
int arm920t_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Writes a buffer, in the specified word size, with current MMU settings.
static const char arm920_not[]
int arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
int arm920t_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Reads a buffer, in the specified word size, with current MMU settings.
int arm920t_soft_reset_halt(struct target *target)
static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
static int arm920t_read_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value)
static void arm920t_deinit_target(struct target *target)
static int arm920t_verify_pointer(struct command_invocation *cmd, struct arm920t_common *arm920t)
int arm920t_get_ttb(struct target *target, uint32_t *result)
static int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
COMMAND_HANDLER(arm920t_handle_read_cache_command)
void arm920t_pre_restore_context(struct target *target)
static int arm920t_write_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
static int arm920_mmu(struct target *target, int *enabled)
#define CP15PHYS_CACHETYPE
static int arm920t_target_create(struct target *target, Jim_Interp *interp)
#define CP15PHYS_TESTSTATE
int arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
int arm920t_arch_state(struct target *target)
Logs summary of ARM920 state for a halted target.
static int arm920t_read_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static int arm920t_write_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t value, uint32_t address)
struct target_type arm920t_target
Holds methods for ARM920 targets.
static int arm920t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
static int arm920_virt2phys(struct target *target, target_addr_t virt, target_addr_t *phys)
static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, uint32_t arm_opcode)
static int arm920t_read_cp15_physical(struct target *target, int reg_addr, uint32_t *value)
#define CP15PHYS_DCACHE_IDX
#define ARM920T_COMMON_MAGIC
static struct arm920t_common * target_to_arm920(struct target *target)
int arm9tdmi_init_arch_info(struct target *target, struct arm7_9_common *arm7_9, struct jtag_tap *tap)
void arm9tdmi_read_core_regs(struct target *target, uint32_t mask, uint32_t *core_regs[16])
int arm9tdmi_init_target(struct command_context *cmd_ctx, struct target *target)
const struct command_registration arm9tdmi_command_handlers[]
void arm9tdmi_write_core_regs(struct target *target, uint32_t mask, uint32_t core_regs[16])
int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr, uint32_t out, uint32_t *in, int sysspeed)
int arm_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Runs ARM code in the target to check whether a memory block holds all ones.
int arm_arch_state(struct target *target)
int arm_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Runs ARM code in the target to calculate a CRC32 checksum.
int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
void arm_free_reg_cache(struct arm *arm)
const char * arm_get_gdb_arch(struct target *target)
bool is_arm_mode(unsigned psr_mode)
Return true iff the parameter denotes a valid ARM processor mode.
static struct arm * target_to_arm(struct target *target)
Convert target handle to generic ARM target state handle.
void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
Configures host-side ARM records to reflect the specified CPSR.
struct reg * arm_reg_current(struct arm *arm, unsigned regnum)
Returns handle to the register currently mapped to a given number.
static int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain, tap_state_t end_state)
static int arm_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, void *no_verify_capture, tap_state_t end_state)
static void arm_le_to_h_u32(jtag_callback_data_t arg)
Macros used to generate various ARM or Thumb opcodes.
#define ARMV4_5_LDMIA(rn, list, s, w)
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
#define ARMV4_5_LDR(rd, rn)
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
#define ARMV4_5_STR(rd, rn)
int armv4_5_identify_cache(uint32_t cache_type_reg, struct armv4_5_cache_common *cache)
int armv4_5_handle_cache_info_command(struct command_invocation *cmd, struct armv4_5_cache_common *armv4_5_cache)
@ ARMV4_5_D_U_CACHE_ENABLED
@ ARMV4_5_I_CACHE_ENABLED
int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val)
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CMD_NAME
Use this macro to access the name of the command being handled, rather than accessing the variable di...
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
int embeddedice_read_reg(struct reg *reg)
Queue a read for an EmbeddedICE register into the register cache, not checking the value read.
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
void jtag_add_callback(jtag_callback1_t f, jtag_callback_data_t data0)
A simpler version of jtag_add_callback4().
intptr_t jtag_callback_data_t
Defines the type of data passed to the jtag_callback_t interface.
static const struct @101 regs[]
void alive_sleep(uint64_t ms)
#define LOG_USER(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_DEBUG(expr ...)
size_t size
Size of the control block search area.
Structure for items that are common between both ARM7 and ARM9 targets.
int(* write_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Variant specific memory write function that does not dispatch to bulk_write_memory.
struct arm_jtag jtag_info
JTAG information for target.
struct reg_cache * eice_cache
Embedded ICE register cache.
int(* post_debug_entry)(struct target *target)
Callback function called after entering debug mode.
void(* pre_restore_context)(struct target *target)
Callback function called before restoring the processor context.
uint32_t cp15_control_reg
unsigned int common_magic
struct arm7_9_common arm7_9_common
struct armv4_5_mmu_common armv4_5_mmu
Represents a generic ARM core, with standard application registers.
int(* mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
Read coprocessor register.
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
struct reg * cpsr
Handle to the CPSR/xPSR; valid in all core modes.
struct reg * pc
Handle to the PC; valid in all core modes.
struct reg_cache * core_cache
int(* mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
Write coprocessor register.
struct armv4_5_cachesize d_u_size
int(* write_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
int(* read_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
int(* get_ttb)(struct target *target, uint32_t *result)
int(* enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache)
int(* disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache)
struct armv4_5_cache_common armv4_5_cache
When run_command is called, a new instance will be created on the stack, filled with the proper value...
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
This structure defines a single scan field in the scan.
int num_bits
The number of bits this field specifies.
uint8_t * in_value
A pointer to a 32-bit memory location for data scanned out.
const uint8_t * out_value
A pointer to value to be scanned into the device.
This holds methods shared between all instances of a given target type.
const char * name
Name of this type of target.
int target_call_event_callbacks(struct target *target, enum target_event event)
int target_halt(struct target *target)
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
struct target * get_current_target(struct command_context *cmd_ctx)
#define ERROR_TARGET_INVALID
#define ERROR_TARGET_TIMEOUT