OpenOCD
embeddedice.h File Reference
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Data Structures

struct  embeddedice_reg
 

Enumerations

enum  {
  EICE_DBG_CTRL = 0 , EICE_DBG_STAT = 1 , EICE_COMMS_CTRL = 2 , EICE_COMMS_DATA = 3 ,
  EICE_W0_ADDR_VALUE = 4 , EICE_W0_ADDR_MASK = 5 , EICE_W0_DATA_VALUE = 6 , EICE_W0_DATA_MASK = 7 ,
  EICE_W0_CONTROL_VALUE = 8 , EICE_W0_CONTROL_MASK = 9 , EICE_W1_ADDR_VALUE = 10 , EICE_W1_ADDR_MASK = 11 ,
  EICE_W1_DATA_VALUE = 12 , EICE_W1_DATA_MASK = 13 , EICE_W1_CONTROL_VALUE = 14 , EICE_W1_CONTROL_MASK = 15 ,
  EICE_VEC_CATCH = 16
}
 
enum  {
  EICE_DBG_CONTROL_ICEDIS = 5 , EICE_DBG_CONTROL_MONEN = 4 , EICE_DBG_CONTROL_INTDIS = 2 , EICE_DBG_CONTROL_DBGRQ = 1 ,
  EICE_DBG_CONTROL_DBGACK = 0
}
 
enum  {
  EICE_DBG_STATUS_IJBIT = 5 , EICE_DBG_STATUS_ITBIT = 4 , EICE_DBG_STATUS_SYSCOMP = 3 , EICE_DBG_STATUS_IFEN = 2 ,
  EICE_DBG_STATUS_DBGRQ = 1 , EICE_DBG_STATUS_DBGACK = 0
}
 
enum  {
  EICE_W_CTRL_ENABLE = 0x100 , EICE_W_CTRL_RANGE = 0x80 , EICE_W_CTRL_CHAIN = 0x40 , EICE_W_CTRL_EXTERN = 0x20 ,
  EICE_W_CTRL_NTRANS = 0x10 , EICE_W_CTRL_NOPC = 0x8 , EICE_W_CTRL_MAS = 0x6 , EICE_W_CTRL_ITBIT = 0x2 ,
  EICE_W_CTRL_NRW = 0x1
}
 
enum  { EICE_COMM_CTRL_WBIT = 1 , EICE_COMM_CTRL_RBIT = 0 }
 

Functions

struct reg_cacheembeddedice_build_reg_cache (struct target *target, struct arm7_9_common *arm7_9)
 Probe EmbeddedICE module and set up local records of its registers. More...
 
void embeddedice_free_reg_cache (struct reg_cache *reg_cache)
 Free all memory allocated for EmbeddedICE register cache. More...
 
int embeddedice_handshake (struct arm_jtag *jtag_info, int hsbit, uint32_t timeout)
 Poll DCC control register until read or write handshake completes. More...
 
int embeddedice_read_reg (struct reg *reg)
 Queue a read for an EmbeddedICE register into the register cache, not checking the value read. More...
 
int embeddedice_read_reg_w_check (struct reg *reg, uint8_t *check_value, uint8_t *check_mask)
 Queue a read for an EmbeddedICE register into the register cache, optionally checking the value read. More...
 
int embeddedice_receive (struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 Receive a block of size 32-bit words from the DCC. More...
 
int embeddedice_send (struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 Send a block of size 32-bit words to the DCC. More...
 
void embeddedice_set_reg (struct reg *reg, uint32_t value)
 Queue a write for an EmbeddedICE register, updating the register cache. More...
 
int embeddedice_setup (struct target *target)
 Initialize EmbeddedICE module, if needed. More...
 
void embeddedice_store_reg (struct reg *reg)
 Queue a write for an EmbeddedICE register, using cached value. More...
 
void embeddedice_write_dcc (struct jtag_tap *tap, int reg_addr, const uint8_t *buffer, int little, int count)
 This is an inner loop of the open loop DCC write of data to target. More...
 
void embeddedice_write_reg (struct reg *reg, uint32_t value)
 Queue a write for an EmbeddedICE register, bypassing the register cache. More...
 
static void embeddedice_write_reg_inner (struct jtag_tap *tap, int reg_addr, uint32_t value)
 

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
EICE_DBG_CTRL 
EICE_DBG_STAT 
EICE_COMMS_CTRL 
EICE_COMMS_DATA 
EICE_W0_ADDR_VALUE 
EICE_W0_ADDR_MASK 
EICE_W0_DATA_VALUE 
EICE_W0_DATA_MASK 
EICE_W0_CONTROL_VALUE 
EICE_W0_CONTROL_MASK 
EICE_W1_ADDR_VALUE 
EICE_W1_ADDR_MASK 
EICE_W1_DATA_VALUE 
EICE_W1_DATA_MASK 
EICE_W1_CONTROL_VALUE 
EICE_W1_CONTROL_MASK 
EICE_VEC_CATCH 

Definition at line 19 of file embeddedice.h.

◆ anonymous enum

anonymous enum
Enumerator
EICE_DBG_CONTROL_ICEDIS 
EICE_DBG_CONTROL_MONEN 
EICE_DBG_CONTROL_INTDIS 
EICE_DBG_CONTROL_DBGRQ 
EICE_DBG_CONTROL_DBGACK 

Definition at line 39 of file embeddedice.h.

◆ anonymous enum

anonymous enum
Enumerator
EICE_DBG_STATUS_IJBIT 
EICE_DBG_STATUS_ITBIT 
EICE_DBG_STATUS_SYSCOMP 
EICE_DBG_STATUS_IFEN 
EICE_DBG_STATUS_DBGRQ 
EICE_DBG_STATUS_DBGACK 

Definition at line 47 of file embeddedice.h.

◆ anonymous enum

anonymous enum
Enumerator
EICE_W_CTRL_ENABLE 
EICE_W_CTRL_RANGE 
EICE_W_CTRL_CHAIN 
EICE_W_CTRL_EXTERN 
EICE_W_CTRL_NTRANS 
EICE_W_CTRL_NOPC 
EICE_W_CTRL_MAS 
EICE_W_CTRL_ITBIT 
EICE_W_CTRL_NRW 

Definition at line 56 of file embeddedice.h.

◆ anonymous enum

anonymous enum
Enumerator
EICE_COMM_CTRL_WBIT 
EICE_COMM_CTRL_RBIT 

Definition at line 68 of file embeddedice.h.

Function Documentation

◆ embeddedice_build_reg_cache()

struct reg_cache* embeddedice_build_reg_cache ( struct target target,
struct arm7_9_common arm7_9 
)

◆ embeddedice_free_reg_cache()

void embeddedice_free_reg_cache ( struct reg_cache reg_cache)

Free all memory allocated for EmbeddedICE register cache.

Definition at line 298 of file embeddedice.c.

References reg::arch_info, reg_cache::num_regs, reg_cache::reg_list, and reg::value.

Referenced by arm7_9_deinit().

◆ embeddedice_handshake()

◆ embeddedice_read_reg()

◆ embeddedice_read_reg_w_check()

int embeddedice_read_reg_w_check ( struct reg reg,
uint8_t *  check_value,
uint8_t *  check_mask 
)

◆ embeddedice_receive()

int embeddedice_receive ( struct arm_jtag jtag_info,
uint32_t *  data,
uint32_t  size 
)

Receive a block of size 32-bit words from the DCC.

We assume the target is always going to be fast enough (relative to the JTAG clock) that the debugger won't need to poll the handshake bit. The JTAG clock is usually at least six times slower than the functional clock, so the 50+ JTAG clocks needed to receive the word allow hundreds of instruction cycles (per word) in the target.

Definition at line 412 of file embeddedice.c.

References arm_jtag_scann(), arm_jtag_set_instr(), arm_le_to_h_u32(), EICE_COMMS_CTRL, EICE_COMMS_DATA, eice_regs, ERROR_OK, scan_field::in_value, arm_jtag::intest_instr, jtag_add_callback(), jtag_add_dr_scan(), jtag_execute_queue(), NULL, scan_field::num_bits, scan_field::out_value, size, arm_jtag::tap, and TAP_IDLE.

Referenced by arm7_9_handle_target_request(), arm7_9_target_request_data(), ocl_erase(), ocl_probe(), and ocl_write().

◆ embeddedice_send()

int embeddedice_send ( struct arm_jtag jtag_info,
uint32_t *  data,
uint32_t  size 
)

Send a block of size 32-bit words to the DCC.

We assume the target is always going to be fast enough (relative to the JTAG clock) that the debugger won't need to poll the handshake bit. The JTAG clock is usually at least six times slower than the functional clock, so the 50+ JTAG clocks needed to receive the word allow hundreds of instruction cycles (per word) in the target.

Definition at line 532 of file embeddedice.c.

References arm_jtag_scann(), arm_jtag_set_instr(), buf_set_u32(), EICE_COMMS_DATA, eice_regs, ERROR_OK, scan_field::in_value, arm_jtag::intest_instr, jtag_add_dr_scan(), NULL, scan_field::num_bits, scan_field::out_value, size, arm_jtag::tap, and TAP_IDLE.

Referenced by ocl_erase(), ocl_probe(), and ocl_write().

◆ embeddedice_set_reg()

void embeddedice_set_reg ( struct reg reg,
uint32_t  value 
)

◆ embeddedice_setup()

int embeddedice_setup ( struct target target)

◆ embeddedice_store_reg()

◆ embeddedice_write_dcc()

void embeddedice_write_dcc ( struct jtag_tap tap,
int  reg_addr,
const uint8_t *  buffer,
int  little,
int  count 
)

This is an inner loop of the open loop DCC write of data to target.

Definition at line 640 of file embeddedice.c.

References buffer, count, embeddedice_write_reg_inner(), and fast_target_buffer_get_u32().

Referenced by arm7_9_dcc_completion().

◆ embeddedice_write_reg()

◆ embeddedice_write_reg_inner()

static void embeddedice_write_reg_inner ( struct jtag_tap tap,
int  reg_addr,
uint32_t  value 
)
inlinestatic