56 LOG_WARNING(
"Reset is not asserted because the target is not examined.");
57 LOG_WARNING(
"Use a reset button or power cycle the target.");
73 uint8_t sysspeed_buf = 0x0;
156 uint32_t
mask, uint32_t *core_regs[16])
167 for (i = 0; i <= 15; i++)
183 uint32_t *buf_u32 =
buffer;
184 uint16_t *buf_u16 =
buffer;
191 for (i = 0; i <= 15; i++) {
192 if (
mask & (1 << i)) {
240 LOG_DEBUG(
"xpsr: %8.8" PRIx32
", spsr: %i", xpsr, spsr);
276 uint8_t xpsr_im,
int rot,
int spsr)
282 LOG_DEBUG(
"xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
294 uint32_t
mask, uint32_t core_regs[16])
305 for (i = 0; i <= 15; i++)
365 uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
388 uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
458 uint32_t x, flip, shift, save[7];
488 uint32_t dcc_size =
sizeof(
dcc_code);
490 if (address % 4 != 0)
498 uint8_t dcc_code_buf[dcc_size];
502 LOG_INFO(
"no working area available, falling back to memory writes");
518 for (i = 0; i <= 5; i++)
535 for (i = 0; i <
count; i++) {
537 uint32_t z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000);
539 x = y << (32 - shift);
540 if (++shift >= 32 || i + 1 >=
count) {
541 z = (x >> 1) | (flip ^= 0x80000000);
553 uint32_t endaddress =
555 if (endaddress != address +
count*4) {
558 " got 0x%0" PRIx32
"",
559 address +
count*4, endaddress);
565 for (i = 0; i <= 5; i++) {
672 LOG_ERROR(
"unexpected Feroceon EICE version signature");
int arm7_9_write_memory_opt(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
int arm7_9_examine(struct target *target)
Perform per-target setup that requires JTAG access.
int arm7_9_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
Add a breakpoint to an ARM7/9 target.
int arm7_9_soft_reset_halt(struct target *target)
Issue a software reset and halt to an ARM7/9 target.
int arm7_9_assert_reset(struct target *target)
Asserts the reset (SRST) on an ARM7/9 target.
static const uint32_t dcc_code[]
int arm7_9_poll(struct target *target)
Polls an ARM7/9 target for its current status.
int arm7_9_execute_sys_speed(struct target *target)
Restarts the target by sending a RESTART instruction and moving the JTAG state to IDLE.
int arm7_9_halt(struct target *target)
Halt an ARM7/9 target.
int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
Removes a breakpoint from an ARM7/9 target.
int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
Remove a watchpoint from an ARM7/9 target.
int arm7_9_deassert_reset(struct target *target)
Deassert the reset (SRST) signal on an ARM7/9 target.
int arm7_9_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
int arm7_9_write_memory_no_opt(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
int arm7_9_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
Get some data from the ARM7/9 target.
int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
Add a watchpoint to an ARM7/9 target.
int arm7_9_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
int arm926ejs_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Writes a buffer, in the specified word size, with current MMU settings.
const struct command_registration arm926ejs_command_handlers[]
int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm926ejs, struct jtag_tap *tap)
int arm926ejs_arch_state(struct target *target)
Logs summary of ARM926 state for a halted target.
int arm926ejs_soft_reset_halt(struct target *target)
const struct command_registration arm966e_command_handlers[]
int arm966e_init_arch_info(struct target *target, struct arm966e_common *arm966e, struct jtag_tap *tap)
void arm9tdmi_deinit_target(struct target *target)
int arm9tdmi_init_target(struct command_context *cmd_ctx, struct target *target)
int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, void *in, int size, int be)
int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr, uint32_t out, uint32_t *in, int sysspeed)
int arm_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Runs ARM code in the target to check whether a memory block holds all ones.
int arm_arch_state(struct target *target)
int arm_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Runs ARM code in the target to calculate a CRC32 checksum.
int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
const char * arm_get_gdb_arch(struct target *target)
arm_state
The PSR "T" and "J" bits define the mode of "classic ARM" cores.
static int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain, tap_state_t end_state)
static int arm_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, void *no_verify_capture, tap_state_t end_state)
Macros used to generate various ARM or Thumb opcodes.
#define ARMV4_5_LDMIA(rn, list, s, w)
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
#define ARMV4_5_MRS(rn, r)
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
#define ARMV4_5_T_MOV(rd, rm)
#define ARMV4_5_T_LDMIA(rn, list)
#define ARMV4_5_STMIA(rn, list, s, w)
#define ARMV4_5_MSR_IM(im, rotate, field, r)
#define ARMV4_5_T_STR(rd, rn)
uint32_t flip_u32(uint32_t value, unsigned int num)
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
void embeddedice_set_reg(struct reg *reg, uint32_t value)
Queue a write for an EmbeddedICE register, updating the register cache.
void embeddedice_write_reg(struct reg *reg, uint32_t value)
Queue a write for an EmbeddedICE register, bypassing the register cache.
void embeddedice_store_reg(struct reg *reg)
Queue a write for an EmbeddedICE register, using cached value.
int embeddedice_read_reg(struct reg *reg)
Queue a read for an EmbeddedICE register into the register cache, not checking the value read.
static void feroceon_read_core_regs(struct target *target, uint32_t mask, uint32_t *core_regs[16])
static int feroceon_read_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
static int feroceon_assert_reset(struct target *target)
static int feroceon_target_create(struct target *target, Jim_Interp *interp)
static int feroceon_init_target(struct command_context *cmd_ctx, struct target *target)
static void feroceon_enable_single_step(struct target *target, uint32_t next_pc)
static void feroceon_read_core_regs_target_buffer(struct target *target, uint32_t mask, void *buffer, int size)
static void feroceon_disable_single_step(struct target *target)
struct target_type dragonite_target
static void feroceon_deinit_target(struct target *target)
static void feroceon_branch_resume(struct target *target)
static void feroceon_common_setup(struct target *target)
struct target_type feroceon_target
static void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
static int feroceon_examine_debug_reason(struct target *target)
static int feroceon_write_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
static void feroceon_change_to_arm(struct target *target, uint32_t *r0, uint32_t *pc)
static void feroceon_write_core_regs(struct target *target, uint32_t mask, uint32_t core_regs[16])
static void feroceon_write_xpsr_im8(struct target *target, uint8_t xpsr_im, int rot, int spsr)
static void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
static int feroceon_bulk_write_memory(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer)
static void feroceon_set_dbgrq(struct target *target)
static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
static int dragonite_target_create(struct target *target, Jim_Interp *interp)
static int feroceon_examine(struct target *target)
static void feroceon_branch_resume_thumb(struct target *target)
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
size_t size
Size of the control block search area.
Structure for items that are common between both ARM7 and ARM9 targets.
void(* enable_single_step)(struct target *target, uint32_t next_pc)
void(* read_xpsr)(struct target *target, uint32_t *xpsr, int spsr)
Function for reading CPSR or SPSR.
void(* write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr)
Function for writing an immediate value to CPSR or SPSR.
void(* write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16])
bool use_dbgrq
Specifies if DBGRQ should be used to halt the target.
struct working_area * dcc_working_area
int(* bulk_write_memory)(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer)
Write target memory in multiples of 4 bytes, optimized for writing large quantities of data.
void(* branch_resume)(struct target *target)
int(* write_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Variant specific memory write function that does not dispatch to bulk_write_memory.
struct arm_jtag jtag_info
JTAG information for target.
void(* set_special_dbgrq)(struct target *target)
Function for setting DBGRQ if the normal way won't work.
void(* read_core_regs_target_buffer)(struct target *target, uint32_t mask, void *buffer, int size)
bool need_bypass_before_restart
Specifies if there should be a bypass before a JTAG restart.
struct reg_cache * eice_cache
Embedded ICE register cache.
void(* read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16])
Function for reading the core registers.
int wp1_used_default
Specifies if and how watchpoint unit 1 is used by default.
void(* disable_single_step)(struct target *target)
int(* examine_debug_reason)(struct target *target)
Function for determining why debug state was entered.
int wp_available_max
Maximum number of available watchpoint units.
void(* branch_resume_thumb)(struct target *target)
void(* change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc)
Function for changing from Thumb to ARM mode.
void(* write_xpsr)(struct target *target, uint32_t xpsr, int spsr)
Function for writing to CPSR or SPSR.
int(* write_cp15)(struct target *target, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
int(* read_cp15)(struct target *target, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
Represents a generic ARM core, with standard application registers.
struct reg * pc
Handle to the PC; valid in all core modes.
struct reg_cache * core_cache
enum arm_state core_state
Record the current core state: ARM, Thumb, or otherwise.
This structure defines a single scan field in the scan.
int num_bits
The number of bits this field specifies.
uint8_t * in_value
A pointer to a 32-bit memory location for data scanned out.
const uint8_t * out_value
A pointer to value to be scanned into the device.
This holds methods shared between all instances of a given target type.
const char * name
Name of this type of target.
enum target_debug_reason debug_reason
enum target_endianness endianness
int target_halt(struct target *target)
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
void target_buffer_set_u32_array(struct target *target, uint8_t *buffer, uint32_t count, const uint32_t *srcbuf)
uint32_t target_buffer_get_u32(struct target *target, const uint8_t *buffer)
int target_wait_state(struct target *target, enum target_state state, int ms)
#define ERROR_TARGET_UNALIGNED_ACCESS
#define ERROR_TARGET_NOT_EXAMINED
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
static bool target_was_examined(struct target *target)
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.