OpenOCD
cortex_a.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2005 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  * *
7  * Copyright (C) 2006 by Magnus Lundin *
8  * lundin@mlu.mine.nu *
9  * *
10  * Copyright (C) 2008 by Spencer Oliver *
11  * spen@spen-soft.co.uk *
12  * *
13  * Copyright (C) 2009 by Dirk Behme *
14  * dirk.behme@gmail.com - copy from cortex_m3 *
15  ***************************************************************************/
16 
17 #ifndef OPENOCD_TARGET_CORTEX_A_H
18 #define OPENOCD_TARGET_CORTEX_A_H
19 
20 #include "armv7a.h"
21 
22 #define CORTEX_A_COMMON_MAGIC 0x411fc082U
23 
24 #define CORTEX_A5_PARTNUM 0xc05
25 #define CORTEX_A7_PARTNUM 0xc07
26 #define CORTEX_A8_PARTNUM 0xc08
27 #define CORTEX_A9_PARTNUM 0xc09
28 #define CORTEX_A15_PARTNUM 0xc0f
29 #define CORTEX_A_MIDR_PARTNUM_MASK 0x0000fff0
30 #define CORTEX_A_MIDR_PARTNUM_SHIFT 4
31 
32 #define CPUDBG_CPUID 0xD00
33 #define CPUDBG_CTYPR 0xD04
34 #define CPUDBG_TTYPR 0xD0C
35 #define CPUDBG_LOCKACCESS 0xFB0
36 #define CPUDBG_LOCKSTATUS 0xFB4
37 #define CPUDBG_OSLAR_LK_MASK (1 << 1)
38 
39 #define BRP_NORMAL 0
40 #define BRP_CONTEXT 1
41 
42 #define CORTEX_A_PADDRDBG_CPU_SHIFT 13
43 
47 };
48 
52 };
53 
54 struct cortex_a_brp {
55  bool used;
56  int type;
57  uint32_t value;
58  uint32_t control;
59  uint8_t brpn;
60 };
61 
62 struct cortex_a_wrp {
63  bool used;
64  uint32_t value;
65  uint32_t control;
66  uint8_t wrpn;
67 };
68 
70  unsigned int common_magic;
71 
73 
74  /* Context information */
75  uint32_t cpudbg_dscr;
76 
77  /* Saved cp15 registers */
78  uint32_t cp15_control_reg;
79  /* latest cp15 register value written and cpsr processor mode */
81  /* auxiliary control reg */
83  /* DACR */
84  uint32_t cp15_dacr_reg;
85  enum arm_mode curr_mode;
86 
87  /* Breakpoint register pairs */
89  int brp_num;
92  int wrp_num;
95 
96  uint32_t cpuid;
97  uint32_t didr;
98 
101 };
102 
103 static inline struct cortex_a_common *
105 {
107 }
108 
109 #endif /* OPENOCD_TARGET_CORTEX_A_H */
arm_mode
Represent state of an ARM core.
Definition: arm.h:74
static struct cortex_a_common * target_to_cortex_a(struct target *target)
Definition: cortex_a.h:104
cortex_a_isrmasking_mode
Definition: cortex_a.h:44
@ CORTEX_A_ISRMASK_OFF
Definition: cortex_a.h:45
@ CORTEX_A_ISRMASK_ON
Definition: cortex_a.h:46
cortex_a_dacrfixup_mode
Definition: cortex_a.h:49
@ CORTEX_A_DACRFIXUP_ON
Definition: cortex_a.h:51
@ CORTEX_A_DACRFIXUP_OFF
Definition: cortex_a.h:50
struct arm arm
Definition: armv7a.h:92
uint32_t value
Definition: cortex_a.h:57
uint32_t control
Definition: cortex_a.h:58
bool used
Definition: cortex_a.h:55
uint8_t brpn
Definition: cortex_a.h:59
struct cortex_a_wrp * wrp_list
Definition: cortex_a.h:94
uint32_t didr
Definition: cortex_a.h:97
int brp_num_context
Definition: cortex_a.h:88
struct cortex_a_brp * brp_list
Definition: cortex_a.h:91
uint32_t cp15_control_reg_curr
Definition: cortex_a.h:80
enum cortex_a_dacrfixup_mode dacrfixup_mode
Definition: cortex_a.h:100
int wrp_num_available
Definition: cortex_a.h:93
uint32_t cpudbg_dscr
Definition: cortex_a.h:75
uint32_t cp15_dacr_reg
Definition: cortex_a.h:84
unsigned int common_magic
Definition: cortex_a.h:70
enum cortex_a_isrmasking_mode isrmasking_mode
Definition: cortex_a.h:99
uint32_t cpuid
Definition: cortex_a.h:96
enum arm_mode curr_mode
Definition: cortex_a.h:85
uint32_t cp15_control_reg
Definition: cortex_a.h:78
int brp_num_available
Definition: cortex_a.h:90
uint32_t cp15_aux_control_reg
Definition: cortex_a.h:82
uint8_t wrpn
Definition: cortex_a.h:66
bool used
Definition: cortex_a.h:63
uint32_t value
Definition: cortex_a.h:64
uint32_t control
Definition: cortex_a.h:65
Definition: target.h:120
void * arch_info
Definition: target.h:169
#define container_of(ptr, type, member)
Cast a member of a structure out to the containing structure.
Definition: types.h:68