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aarch64.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2015 by David Ung *
5  * *
6  ***************************************************************************/
7 
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11 
12 #include "breakpoints.h"
13 #include "aarch64.h"
14 #include "a64_disassembler.h"
15 #include "register.h"
16 #include "target_request.h"
17 #include "target_type.h"
18 #include "armv8_opcodes.h"
19 #include "armv8_cache.h"
20 #include "arm_coresight.h"
21 #include "arm_semihosting.h"
22 #include "jtag/interface.h"
23 #include "smp.h"
24 #include <helper/nvp.h>
25 #include <helper/time_support.h>
26 
27 enum restart_mode {
28  RESTART_LAZY,
29  RESTART_SYNC,
30 };
31 
32 enum halt_mode {
33  HALT_LAZY,
34  HALT_SYNC,
35 };
36 
37 struct aarch64_private_config {
38  struct adiv5_private_config adiv5_config;
39  struct arm_cti *cti;
40 };
41 
42 static int aarch64_poll(struct target *target);
43 static int aarch64_debug_entry(struct target *target);
44 static int aarch64_restore_context(struct target *target, bool bpwp);
45 static int aarch64_set_breakpoint(struct target *target,
46  struct breakpoint *breakpoint, uint8_t matchmode);
47 static int aarch64_set_context_breakpoint(struct target *target,
48  struct breakpoint *breakpoint, uint8_t matchmode);
49 static int aarch64_set_hybrid_breakpoint(struct target *target,
50  struct breakpoint *breakpoint);
51 static int aarch64_unset_breakpoint(struct target *target,
52  struct breakpoint *breakpoint);
53 static int aarch64_mmu(struct target *target, bool *enabled);
54 static int aarch64_virt2phys(struct target *target,
55  target_addr_t virt, target_addr_t *phys);
56 static int aarch64_read_cpu_memory(struct target *target,
57  uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer);
58 
59 static int aarch64_restore_system_control_reg(struct target *target)
60 {
61  enum arm_mode target_mode = ARM_MODE_ANY;
62  int retval = ERROR_OK;
63  uint32_t instr;
64 
65  struct aarch64_common *aarch64 = target_to_aarch64(target);
66  struct armv8_common *armv8 = target_to_armv8(target);
67 
68  if (aarch64->system_control_reg != aarch64->system_control_reg_curr) {
69  aarch64->system_control_reg_curr = aarch64->system_control_reg;
70  /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_v8->cp15_control_reg); */
71 
72  switch (armv8->arm.core_mode) {
73  case ARMV8_64_EL0T:
74  target_mode = ARMV8_64_EL1H;
75  /* fall through */
76  case ARMV8_64_EL1T:
77  case ARMV8_64_EL1H:
78  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL1, 0);
79  break;
80  case ARMV8_64_EL2T:
81  case ARMV8_64_EL2H:
82  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL2, 0);
83  break;
84  case ARMV8_64_EL3H:
85  case ARMV8_64_EL3T:
86  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL3, 0);
87  break;
88 
89  case ARM_MODE_SVC:
90  case ARM_MODE_ABT:
91  case ARM_MODE_FIQ:
92  case ARM_MODE_IRQ:
93  case ARM_MODE_HYP:
94  case ARM_MODE_UND:
95  case ARM_MODE_SYS:
96  case ARM_MODE_MON:
97  instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
98  break;
99 
100  default:
101  LOG_ERROR("cannot read system control register in this mode: (%s : 0x%x)",
102  armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
103  return ERROR_FAIL;
104  }
105 
106  if (target_mode != ARM_MODE_ANY)
107  armv8_dpm_modeswitch(&armv8->dpm, target_mode);
108 
109  retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr, aarch64->system_control_reg);
110  if (retval != ERROR_OK)
111  return retval;
112 
113  if (target_mode != ARM_MODE_ANY)
114  armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
115  }
116 
117  return retval;
118 }
119 
120 /* modify system_control_reg in order to enable or disable mmu for :
121  * - virt2phys address conversion
122  * - read or write memory in phys or virt address */
123 static int aarch64_mmu_modify(struct target *target, int enable)
124 {
125  struct aarch64_common *aarch64 = target_to_aarch64(target);
126  struct armv8_common *armv8 = &aarch64->armv8_common;
127  int retval = ERROR_OK;
128  enum arm_mode target_mode = ARM_MODE_ANY;
129  uint32_t instr = 0;
130 
131  if (enable) {
132  /* if mmu enabled at target stop and mmu not enable */
133  if (!(aarch64->system_control_reg & 0x1U)) {
134  LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
135  return ERROR_FAIL;
136  }
137  if (!(aarch64->system_control_reg_curr & 0x1U))
138  aarch64->system_control_reg_curr |= 0x1U;
139  } else {
140  if (aarch64->system_control_reg_curr & 0x4U) {
141  /* data cache is active */
142  aarch64->system_control_reg_curr &= ~0x4U;
143  /* flush data cache armv8 function to be called */
144  if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache)
145  armv8->armv8_mmu.armv8_cache.flush_all_data_cache(target);
146  }
147  if ((aarch64->system_control_reg_curr & 0x1U)) {
148  aarch64->system_control_reg_curr &= ~0x1U;
149  }
150  }
151 
152  switch (armv8->arm.core_mode) {
153  case ARMV8_64_EL0T:
154  target_mode = ARMV8_64_EL1H;
155  /* fall through */
156  case ARMV8_64_EL1T:
157  case ARMV8_64_EL1H:
158  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL1, 0);
159  break;
160  case ARMV8_64_EL2T:
161  case ARMV8_64_EL2H:
162  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL2, 0);
163  break;
164  case ARMV8_64_EL3H:
165  case ARMV8_64_EL3T:
166  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL3, 0);
167  break;
168 
169  case ARM_MODE_SVC:
170  case ARM_MODE_ABT:
171  case ARM_MODE_FIQ:
172  case ARM_MODE_IRQ:
173  case ARM_MODE_HYP:
174  case ARM_MODE_UND:
175  case ARM_MODE_SYS:
176  case ARM_MODE_MON:
177  instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
178  break;
179 
180  default:
181  LOG_DEBUG("unknown cpu state 0x%x", armv8->arm.core_mode);
182  break;
183  }
184  if (target_mode != ARM_MODE_ANY)
185  armv8_dpm_modeswitch(&armv8->dpm, target_mode);
186 
187  retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr,
188  aarch64->system_control_reg_curr);
189 
190  if (target_mode != ARM_MODE_ANY)
191  armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
192 
193  return retval;
194 }
195 
196 static int aarch64_read_prsr(struct target *target, uint32_t *prsr)
197 {
198  struct armv8_common *armv8 = target_to_armv8(target);
199  int retval;
200 
201  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
202  armv8->debug_base + CPUV8_DBG_PRSR, prsr);
203  if (retval != ERROR_OK)
204  return retval;
205 
206  armv8->sticky_reset |= *prsr & PRSR_SR;
207  return ERROR_OK;
208 }
209 
210 /*
211  * Basic debug access, very low level assumes state is saved
212  */
213 static int aarch64_init_debug_access(struct target *target)
214 {
215  struct armv8_common *armv8 = target_to_armv8(target);
216  int retval;
217  uint32_t dummy;
218 
219  LOG_DEBUG("%s", target_name(target));
220 
221  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
222  armv8->debug_base + CPUV8_DBG_OSLAR, 0);
223  if (retval != ERROR_OK) {
224  LOG_DEBUG("Examine %s failed", "oslock");
225  return retval;
226  }
227 
228  /* Clear Sticky Power Down status Bit in PRSR to enable access to
229  the registers in the Core Power Domain */
230  retval = aarch64_read_prsr(target, &dummy);
231  if (retval != ERROR_OK)
232  return retval;
233 
234  /*
235  * Static CTI configuration:
236  * Channel 0 -> trigger outputs HALT request to PE
237  * Channel 1 -> trigger outputs Resume request to PE
238  * Gate all channel trigger events from entering the CTM
239  */
240 
241  /* Enable CTI */
242  retval = arm_cti_enable(armv8->cti, true);
243  /* By default, gate all channel events to and from the CTM */
244  if (retval == ERROR_OK)
245  retval = arm_cti_write_reg(armv8->cti, CTI_GATE, 0);
246  /* output halt requests to PE on channel 0 event */
247  if (retval == ERROR_OK)
248  retval = arm_cti_write_reg(armv8->cti, CTI_OUTEN0, CTI_CHNL(0));
249  /* output restart requests to PE on channel 1 event */
250  if (retval == ERROR_OK)
251  retval = arm_cti_write_reg(armv8->cti, CTI_OUTEN1, CTI_CHNL(1));
252  if (retval != ERROR_OK)
253  return retval;
254 
255  /* Resync breakpoint registers */
256 
257  return ERROR_OK;
258 }
259 
260 /* Write to memory mapped registers directly with no cache or mmu handling */
261 static int aarch64_dap_write_memap_register_u32(struct target *target,
262  target_addr_t address,
263  uint32_t value)
264 {
265  int retval;
266  struct armv8_common *armv8 = target_to_armv8(target);
267 
268  retval = mem_ap_write_atomic_u32(armv8->debug_ap, address, value);
269 
270  return retval;
271 }
272 
273 static int aarch64_dpm_setup(struct aarch64_common *a8, uint64_t debug)
274 {
275  struct arm_dpm *dpm = &a8->armv8_common.dpm;
276  int retval;
277 
278  dpm->arm = &a8->armv8_common.arm;
279  dpm->didr = debug;
280 
281  retval = armv8_dpm_setup(dpm);
282  if (retval == ERROR_OK)
283  retval = armv8_dpm_initialize(dpm);
284 
285  return retval;
286 }
287 
288 static int aarch64_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
289 {
290  struct armv8_common *armv8 = target_to_armv8(target);
291  return armv8_set_dbgreg_bits(armv8, CPUV8_DBG_DSCR, bit_mask, value);
292 }
293 
294 static int aarch64_check_state_one(struct target *target,
295  uint32_t mask, uint32_t val, int *p_result, uint32_t *p_prsr)
296 {
297  uint32_t prsr;
298  int retval;
299 
300  retval = aarch64_read_prsr(target, &prsr);
301  if (retval != ERROR_OK)
302  return retval;
303 
304  if (p_prsr)
305  *p_prsr = prsr;
306 
307  if (p_result)
308  *p_result = (prsr & mask) == (val & mask);
309 
310  return ERROR_OK;
311 }
312 
313 static int aarch64_wait_halt_one(struct target *target)
314 {
315  int retval = ERROR_OK;
316  uint32_t prsr;
317 
318  int64_t then = timeval_ms();
319  for (;;) {
320  int halted;
321 
322  retval = aarch64_check_state_one(target, PRSR_HALT, PRSR_HALT, &halted, &prsr);
323  if (retval != ERROR_OK || halted)
324  break;
325 
326  if (timeval_ms() > then + 1000) {
327  retval = ERROR_TARGET_TIMEOUT;
328  LOG_DEBUG("target %s timeout, prsr=0x%08"PRIx32, target_name(target), prsr);
329  break;
330  }
331  }
332  return retval;
333 }
334 
335 static int aarch64_prepare_halt_smp(struct target *target, bool exc_target, struct target **p_first)
336 {
337  int retval = ERROR_OK;
338  struct target_list *head;
339  struct target *first = NULL;
340 
341  LOG_DEBUG("target %s exc %i", target_name(target), exc_target);
342 
343  foreach_smp_target(head, target->smp_targets) {
344  struct target *curr = head->target;
345  struct armv8_common *armv8 = target_to_armv8(curr);
346 
347  if (exc_target && curr == target)
348  continue;
349  if (!target_was_examined(curr))
350  continue;
351  if (curr->state != TARGET_RUNNING)
352  continue;
353 
354  /* HACK: mark this target as prepared for halting */
355  curr->debug_reason = DBG_REASON_DBGRQ;
356 
357  /* open the gate for channel 0 to let HALT requests pass to the CTM */
358  retval = arm_cti_ungate_channel(armv8->cti, 0);
359  if (retval == ERROR_OK)
360  retval = aarch64_set_dscr_bits(curr, DSCR_HDE, DSCR_HDE);
361  if (retval != ERROR_OK)
362  break;
363 
364  LOG_DEBUG("target %s prepared", target_name(curr));
365 
366  if (!first)
367  first = curr;
368  }
369 
370  if (p_first) {
371  if (exc_target && first)
372  *p_first = first;
373  else
374  *p_first = target;
375  }
376 
377  return retval;
378 }
379 
380 static int aarch64_halt_one(struct target *target, enum halt_mode mode)
381 {
382  int retval = ERROR_OK;
383  struct armv8_common *armv8 = target_to_armv8(target);
384 
385  LOG_DEBUG("%s", target_name(target));
386 
387  /* allow Halting Debug Mode */
388  retval = aarch64_set_dscr_bits(target, DSCR_HDE, DSCR_HDE);
389  if (retval != ERROR_OK)
390  return retval;
391 
392  /* trigger an event on channel 0, this outputs a halt request to the PE */
393  retval = arm_cti_pulse_channel(armv8->cti, 0);
394  if (retval != ERROR_OK)
395  return retval;
396 
397  if (mode == HALT_SYNC) {
398  retval = aarch64_wait_halt_one(target);
399  if (retval != ERROR_OK) {
400  if (retval == ERROR_TARGET_TIMEOUT)
401  LOG_ERROR("Timeout waiting for target %s halt", target_name(target));
402  return retval;
403  }
404  }
405 
406  return ERROR_OK;
407 }
408 
409 static int aarch64_halt_smp(struct target *target, bool exc_target)
410 {
411  struct target *next = target;
412  int retval;
413 
414  /* prepare halt on all PEs of the group */
415  retval = aarch64_prepare_halt_smp(target, exc_target, &next);
416 
417  if (exc_target && next == target)
418  return retval;
419 
420  /* halt the target PE */
421  if (retval == ERROR_OK)
422  retval = aarch64_halt_one(next, HALT_LAZY);
423 
424  if (retval != ERROR_OK)
425  return retval;
426 
427  /* wait for all PEs to halt */
428  int64_t then = timeval_ms();
429  for (;;) {
430  bool all_halted = true;
431  struct target_list *head;
432  struct target *curr;
433 
434  foreach_smp_target(head, target->smp_targets) {
435  int halted;
436 
437  curr = head->target;
438 
439  if (!target_was_examined(curr))
440  continue;
441 
442  retval = aarch64_check_state_one(curr, PRSR_HALT, PRSR_HALT, &halted, NULL);
443  if (retval != ERROR_OK || !halted) {
444  all_halted = false;
445  break;
446  }
447  }
448 
449  if (all_halted)
450  break;
451 
452  if (timeval_ms() > then + 1000) {
453  retval = ERROR_TARGET_TIMEOUT;
454  break;
455  }
456 
457  /*
458  * HACK: on Hi6220 there are 8 cores organized in 2 clusters
459  * and it looks like the CTI's are not connected by a common
460  * trigger matrix. It seems that we need to halt one core in each
461  * cluster explicitly. So if we find that a core has not halted
462  * yet, we trigger an explicit halt for the second cluster.
463  */
464  retval = aarch64_halt_one(curr, HALT_LAZY);
465  if (retval != ERROR_OK)
466  break;
467  }
468 
469  return retval;
470 }
471 
472 static int update_halt_gdb(struct target *target, enum target_debug_reason debug_reason)
473 {
474  struct target *gdb_target = NULL;
475  struct target_list *head;
476  struct target *curr;
477 
478  if (debug_reason == DBG_REASON_NOTHALTED) {
479  LOG_DEBUG("Halting remaining targets in SMP group");
480  aarch64_halt_smp(target, true);
481  }
482 
483  /* poll all targets in the group, but skip the target that serves GDB */
484  foreach_smp_target(head, target->smp_targets) {
485  curr = head->target;
486  /* skip calling context */
487  if (curr == target)
488  continue;
489  if (!target_was_examined(curr))
490  continue;
491  /* skip targets that were already halted */
492  if (curr->state == TARGET_HALTED)
493  continue;
494  /* remember the gdb_service->target */
495  if (curr->gdb_service)
496  gdb_target = curr->gdb_service->target;
497  /* skip it */
498  if (curr == gdb_target)
499  continue;
500 
501  /* avoid recursion in aarch64_poll() */
502  curr->smp = 0;
503  aarch64_poll(curr);
504  curr->smp = 1;
505  }
506 
507  /* after all targets were updated, poll the gdb serving target */
508  if (gdb_target && gdb_target != target)
509  aarch64_poll(gdb_target);
510 
511  return ERROR_OK;
512 }
513 
514 /*
515  * Aarch64 Run control
516  */
517 
518 static int aarch64_poll(struct target *target)
519 {
520  struct armv8_common *armv8 = target_to_armv8(target);
521  enum target_state prev_target_state;
522  int retval = ERROR_OK;
523  uint32_t prsr;
524 
525  retval = aarch64_read_prsr(target, &prsr);
526  if (retval != ERROR_OK)
527  return retval;
528 
529  if (armv8->sticky_reset) {
530  armv8->sticky_reset = false;
531  if (target->state != TARGET_RESET) {
532  target->state = TARGET_RESET;
533  LOG_TARGET_INFO(target, "external reset detected");
534  if (armv8->arm.core_cache) {
535  register_cache_invalidate(armv8->arm.core_cache);
536  register_cache_invalidate(armv8->arm.core_cache->next);
537  }
538  }
539  }
540 
541  if (prsr & PRSR_HALT) {
542  prev_target_state = target->state;
543  if (prev_target_state != TARGET_HALTED) {
544  enum target_debug_reason debug_reason = target->debug_reason;
545 
546  /* We have a halting debug event */
547  target->state = TARGET_HALTED;
548  LOG_DEBUG("Target %s halted", target_name(target));
549  retval = aarch64_debug_entry(target);
550  if (retval != ERROR_OK)
551  return retval;
552 
553  if (target->smp)
554  update_halt_gdb(target, debug_reason);
555 
556  if (arm_semihosting(target, &retval) != 0)
557  return retval;
558 
559  switch (prev_target_state) {
560  case TARGET_RUNNING:
561  case TARGET_UNKNOWN:
562  case TARGET_RESET:
563  target_call_event_callbacks(target, TARGET_EVENT_HALTED);
564  break;
565  case TARGET_DEBUG_RUNNING:
566  target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
567  break;
568  default:
569  break;
570  }
571  }
572  } else if (prsr & PRSR_RESET) {
573  target->state = TARGET_RESET;
574  } else {
575  target->state = TARGET_RUNNING;
576  }
577 
578  return retval;
579 }
580 
581 static int aarch64_halt(struct target *target)
582 {
583  struct armv8_common *armv8 = target_to_armv8(target);
584  armv8->last_run_control_op = ARMV8_RUNCONTROL_HALT;
585 
586  if (target->smp)
587  return aarch64_halt_smp(target, false);
588 
589  return aarch64_halt_one(target, HALT_SYNC);
590 }
591 
592 static int aarch64_restore_one(struct target *target, bool current,
593  uint64_t *address, bool handle_breakpoints, bool debug_execution)
594 {
595  struct armv8_common *armv8 = target_to_armv8(target);
596  struct arm *arm = &armv8->arm;
597  int retval;
598  uint64_t resume_pc;
599 
600  LOG_DEBUG("%s", target_name(target));
601 
602  if (!debug_execution)
603  target_free_all_working_areas(target);
604 
605  /* current = true: continue on current pc, otherwise continue at <address> */
606  resume_pc = buf_get_u64(arm->pc->value, 0, 64);
607  if (!current)
608  resume_pc = *address;
609  else
610  *address = resume_pc;
611 
612  /* Make sure that the Armv7 gdb thumb fixups does not
613  * kill the return address
614  */
615  switch (arm->core_state) {
616  case ARM_STATE_ARM:
617  resume_pc &= 0xFFFFFFFC;
618  break;
619  case ARM_STATE_AARCH64:
620  resume_pc &= 0xFFFFFFFFFFFFFFFCULL;
621  break;
622  case ARM_STATE_THUMB:
623  case ARM_STATE_THUMB_EE:
624  /* When the return address is loaded into PC
625  * bit 0 must be 1 to stay in Thumb state
626  */
627  resume_pc |= 0x1;
628  break;
629  case ARM_STATE_JAZELLE:
630  LOG_ERROR("How do I resume into Jazelle state??");
631  return ERROR_FAIL;
632  }
633  LOG_DEBUG("resume pc = 0x%016" PRIx64, resume_pc);
634  buf_set_u64(arm->pc->value, 0, 64, resume_pc);
635  arm->pc->dirty = true;
636  arm->pc->valid = true;
637 
638  /* called it now before restoring context because it uses cpu
639  * register r0 for restoring system control register */
640  retval = aarch64_restore_system_control_reg(target);
641  if (retval == ERROR_OK)
642  retval = aarch64_restore_context(target, handle_breakpoints);
643 
644  return retval;
645 }
646 
652 static int aarch64_prepare_restart_one(struct target *target)
653 {
654  struct armv8_common *armv8 = target_to_armv8(target);
655  int retval;
656  uint32_t dscr;
657  uint32_t tmp;
658 
659  LOG_DEBUG("%s", target_name(target));
660 
661  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
662  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
663  if (retval != ERROR_OK)
664  return retval;
665 
666  if ((dscr & DSCR_ITE) == 0)
667  LOG_ERROR("DSCR.ITE must be set before leaving debug!");
668  if ((dscr & DSCR_ERR) != 0)
669  LOG_ERROR("DSCR.ERR must be cleared before leaving debug!");
670 
671  /* acknowledge a pending CTI halt event */
672  retval = arm_cti_ack_events(armv8->cti, CTI_TRIG(HALT));
673  /*
674  * open the CTI gate for channel 1 so that the restart events
675  * get passed along to all PEs. Also close gate for channel 0
676  * to isolate the PE from halt events.
677  */
678  if (retval == ERROR_OK)
679  retval = arm_cti_ungate_channel(armv8->cti, 1);
680  if (retval == ERROR_OK)
681  retval = arm_cti_gate_channel(armv8->cti, 0);
682 
683  /* make sure that DSCR.HDE is set */
684  if (retval == ERROR_OK) {
685  dscr |= DSCR_HDE;
686  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
687  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
688  }
689 
690  if (retval == ERROR_OK) {
691  /* clear sticky bits in PRSR, SDR is now 0 */
692  retval = aarch64_read_prsr(target, &tmp);
693  }
694 
695  return retval;
696 }
697 
698 static int aarch64_do_restart_one(struct target *target, enum restart_mode mode)
699 {
700  struct armv8_common *armv8 = target_to_armv8(target);
701  int retval;
702 
703  LOG_DEBUG("%s", target_name(target));
704 
705  /* trigger an event on channel 1, generates a restart request to the PE */
706  retval = arm_cti_pulse_channel(armv8->cti, 1);
707  if (retval != ERROR_OK)
708  return retval;
709 
710  if (mode == RESTART_SYNC) {
711  int64_t then = timeval_ms();
712  for (;;) {
713  int resumed;
714  /*
715  * if PRSR.SDR is set now, the target did restart, even
716  * if it's now already halted again (e.g. due to breakpoint)
717  */
718  retval = aarch64_check_state_one(target,
719  PRSR_SDR, PRSR_SDR, &resumed, NULL);
720  if (retval != ERROR_OK || resumed)
721  break;
722 
723  if (timeval_ms() > then + 1000) {
724  LOG_ERROR("%s: Timeout waiting for resume"PRIx32, target_name(target));
725  retval = ERROR_TARGET_TIMEOUT;
726  break;
727  }
728  }
729  }
730 
731  if (retval != ERROR_OK)
732  return retval;
733 
734  target->debug_reason = DBG_REASON_NOTHALTED;
735  target->state = TARGET_RUNNING;
736 
737  return ERROR_OK;
738 }
739 
740 static int aarch64_restart_one(struct target *target, enum restart_mode mode)
741 {
742  int retval;
743 
744  LOG_DEBUG("%s", target_name(target));
745 
746  retval = aarch64_prepare_restart_one(target);
747  if (retval == ERROR_OK)
748  retval = aarch64_do_restart_one(target, mode);
749 
750  return retval;
751 }
752 
753 /*
754  * prepare all but the current target for restart
755  */
756 static int aarch64_prep_restart_smp(struct target *target,
757  bool handle_breakpoints, struct target **p_first)
758 {
759  int retval = ERROR_OK;
760  struct target_list *head;
761  struct target *first = NULL;
762  uint64_t address;
763 
764  foreach_smp_target(head, target->smp_targets) {
765  struct target *curr = head->target;
766 
767  /* skip calling target */
768  if (curr == target)
769  continue;
770  if (!target_was_examined(curr))
771  continue;
772  if (curr->state != TARGET_HALTED)
773  continue;
774 
775  /* resume at current address, not in step mode */
776  retval = aarch64_restore_one(curr, true, &address, handle_breakpoints,
777  false);
778  if (retval == ERROR_OK)
779  retval = aarch64_prepare_restart_one(curr);
780  if (retval != ERROR_OK) {
781  LOG_ERROR("failed to restore target %s", target_name(curr));
782  break;
783  }
784  /* remember the first valid target in the group */
785  if (!first)
786  first = curr;
787  }
788 
789  if (p_first)
790  *p_first = first;
791 
792  return retval;
793 }
794 
795 
796 static int aarch64_step_restart_smp(struct target *target)
797 {
798  int retval = ERROR_OK;
799  struct target_list *head;
800  struct target *first = NULL;
801 
802  LOG_DEBUG("%s", target_name(target));
803 
804  retval = aarch64_prep_restart_smp(target, false, &first);
805  if (retval != ERROR_OK)
806  return retval;
807 
808  if (first)
809  retval = aarch64_do_restart_one(first, RESTART_LAZY);
810  if (retval != ERROR_OK) {
811  LOG_DEBUG("error restarting target %s", target_name(first));
812  return retval;
813  }
814 
815  int64_t then = timeval_ms();
816  for (;;) {
817  struct target *curr = target;
818  bool all_resumed = true;
819 
820  foreach_smp_target(head, target->smp_targets) {
821  uint32_t prsr;
822  int resumed;
823 
824  curr = head->target;
825 
826  if (curr == target)
827  continue;
828 
829  if (!target_was_examined(curr))
830  continue;
831 
832  retval = aarch64_check_state_one(curr,
833  PRSR_SDR, PRSR_SDR, &resumed, &prsr);
834  if (retval != ERROR_OK || (!resumed && (prsr & PRSR_HALT))) {
835  all_resumed = false;
836  break;
837  }
838 
839  if (curr->state != TARGET_RUNNING) {
840  curr->state = TARGET_RUNNING;
841  curr->debug_reason = DBG_REASON_NOTHALTED;
842  target_call_event_callbacks(curr, TARGET_EVENT_RESUMED);
843  }
844  }
845 
846  if (all_resumed)
847  break;
848 
849  if (timeval_ms() > then + 1000) {
850  LOG_ERROR("%s: timeout waiting for target resume", __func__);
851  retval = ERROR_TARGET_TIMEOUT;
852  break;
853  }
854  /*
855  * HACK: on Hi6220 there are 8 cores organized in 2 clusters
856  * and it looks like the CTI's are not connected by a common
857  * trigger matrix. It seems that we need to halt one core in each
858  * cluster explicitly. So if we find that a core has not halted
859  * yet, we trigger an explicit resume for the second cluster.
860  */
861  retval = aarch64_do_restart_one(curr, RESTART_LAZY);
862  if (retval != ERROR_OK)
863  break;
864 }
865 
866  return retval;
867 }
868 
869 static int aarch64_resume(struct target *target, bool current,
870  target_addr_t address, bool handle_breakpoints, bool debug_execution)
871 {
872  int retval = 0;
873  uint64_t addr = address;
874 
875  struct armv8_common *armv8 = target_to_armv8(target);
876  armv8->last_run_control_op = ARMV8_RUNCONTROL_RESUME;
877 
878  if (target->state != TARGET_HALTED) {
879  LOG_TARGET_ERROR(target, "not halted");
880  return ERROR_TARGET_NOT_HALTED;
881  }
882 
883  /*
884  * If this target is part of a SMP group, prepare the others
885  * targets for resuming. This involves restoring the complete
886  * target register context and setting up CTI gates to accept
887  * resume events from the trigger matrix.
888  */
889  if (target->smp) {
890  retval = aarch64_prep_restart_smp(target, handle_breakpoints, NULL);
891  if (retval != ERROR_OK)
892  return retval;
893  }
894 
895  /* all targets prepared, restore and restart the current target */
896  retval = aarch64_restore_one(target, current, &addr, handle_breakpoints,
897  debug_execution);
898  if (retval == ERROR_OK)
899  retval = aarch64_restart_one(target, RESTART_SYNC);
900  if (retval != ERROR_OK)
901  return retval;
902 
903  if (target->smp) {
904  int64_t then = timeval_ms();
905  for (;;) {
906  struct target *curr = target;
907  struct target_list *head;
908  bool all_resumed = true;
909 
910  foreach_smp_target(head, target->smp_targets) {
911  uint32_t prsr;
912  int resumed;
913 
914  curr = head->target;
915  if (curr == target)
916  continue;
917  if (!target_was_examined(curr))
918  continue;
919 
920  retval = aarch64_check_state_one(curr,
921  PRSR_SDR, PRSR_SDR, &resumed, &prsr);
922  if (retval != ERROR_OK || (!resumed && (prsr & PRSR_HALT))) {
923  all_resumed = false;
924  break;
925  }
926 
927  if (curr->state != TARGET_RUNNING) {
928  curr->state = TARGET_RUNNING;
929  curr->debug_reason = DBG_REASON_NOTHALTED;
930  target_call_event_callbacks(curr, TARGET_EVENT_RESUMED);
931  }
932  }
933 
934  if (all_resumed)
935  break;
936 
937  if (timeval_ms() > then + 1000) {
938  LOG_ERROR("%s: timeout waiting for target %s to resume", __func__, target_name(curr));
939  retval = ERROR_TARGET_TIMEOUT;
940  break;
941  }
942 
943  /*
944  * HACK: on Hi6220 there are 8 cores organized in 2 clusters
945  * and it looks like the CTI's are not connected by a common
946  * trigger matrix. It seems that we need to halt one core in each
947  * cluster explicitly. So if we find that a core has not halted
948  * yet, we trigger an explicit resume for the second cluster.
949  */
950  retval = aarch64_do_restart_one(curr, RESTART_LAZY);
951  if (retval != ERROR_OK)
952  break;
953  }
954  }
955 
956  if (retval != ERROR_OK)
957  return retval;
958 
959  target->debug_reason = DBG_REASON_NOTHALTED;
960 
961  if (!debug_execution) {
962  target->state = TARGET_RUNNING;
963  target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
964  LOG_DEBUG("target resumed at 0x%" PRIx64, addr);
965  } else {
966  target->state = TARGET_DEBUG_RUNNING;
967  target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
968  LOG_DEBUG("target debug resumed at 0x%" PRIx64, addr);
969  }
970 
971  return ERROR_OK;
972 }
973 
974 static int aarch64_debug_entry(struct target *target)
975 {
976  int retval = ERROR_OK;
977  struct armv8_common *armv8 = target_to_armv8(target);
978  struct arm_dpm *dpm = &armv8->dpm;
979  enum arm_state core_state;
980  uint32_t dscr;
981 
982  /* make sure to clear all sticky errors */
983  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
984  armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
985  if (retval == ERROR_OK)
986  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
987  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
988  if (retval == ERROR_OK)
989  retval = arm_cti_ack_events(armv8->cti, CTI_TRIG(HALT));
990 
991  if (retval != ERROR_OK)
992  return retval;
993 
994  LOG_DEBUG("%s dscr = 0x%08" PRIx32, target_name(target), dscr);
995 
996  dpm->dscr = dscr;
997  core_state = armv8_dpm_get_core_state(dpm);
998  armv8_select_opcodes(armv8, core_state == ARM_STATE_AARCH64);
999  armv8_select_reg_access(armv8, core_state == ARM_STATE_AARCH64);
1000 
1001  /* close the CTI gate for all events */
1002  if (retval == ERROR_OK)
1003  retval = arm_cti_write_reg(armv8->cti, CTI_GATE, 0);
1004  /* discard async exceptions */
1005  if (retval == ERROR_OK)
1006  retval = dpm->instr_cpsr_sync(dpm);
1007  if (retval != ERROR_OK)
1008  return retval;
1009 
1010  /* Examine debug reason */
1011  armv8_dpm_report_dscr(dpm, dscr);
1012 
1013  /* save the memory address that triggered the watchpoint */
1014  if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1015  uint32_t tmp;
1016 
1017  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1018  armv8->debug_base + CPUV8_DBG_EDWAR0, &tmp);
1019  if (retval != ERROR_OK)
1020  return retval;
1021  target_addr_t edwar = tmp;
1022 
1023  /* EDWAR[63:32] has unknown content in aarch32 state */
1024  if (core_state == ARM_STATE_AARCH64) {
1025  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1026  armv8->debug_base + CPUV8_DBG_EDWAR1, &tmp);
1027  if (retval != ERROR_OK)
1028  return retval;
1029  edwar |= ((target_addr_t)tmp) << 32;
1030  }
1031 
1032  armv8->dpm.wp_addr = edwar;
1033  }
1034 
1035  retval = armv8_dpm_read_current_registers(&armv8->dpm);
1036 
1037  if (retval == ERROR_OK && armv8->post_debug_entry)
1038  retval = armv8->post_debug_entry(target);
1039 
1040  return retval;
1041 }
1042 
1043 static int aarch64_post_debug_entry(struct target *target)
1044 {
1045  struct aarch64_common *aarch64 = target_to_aarch64(target);
1046  struct armv8_common *armv8 = &aarch64->armv8_common;
1047  int retval;
1048  enum arm_mode target_mode = ARM_MODE_ANY;
1049  uint32_t instr;
1050 
1051  switch (armv8->arm.core_mode) {
1052  case ARMV8_64_EL0T:
1053  target_mode = ARMV8_64_EL1H;
1054  /* fall through */
1055  case ARMV8_64_EL1T:
1056  case ARMV8_64_EL1H:
1057  instr = ARMV8_MRS(SYSTEM_SCTLR_EL1, 0);
1058  break;
1059  case ARMV8_64_EL2T:
1060  case ARMV8_64_EL2H:
1061  instr = ARMV8_MRS(SYSTEM_SCTLR_EL2, 0);
1062  break;
1063  case ARMV8_64_EL3H:
1064  case ARMV8_64_EL3T:
1065  instr = ARMV8_MRS(SYSTEM_SCTLR_EL3, 0);
1066  break;
1067 
1068  case ARM_MODE_SVC:
1069  case ARM_MODE_ABT:
1070  case ARM_MODE_FIQ:
1071  case ARM_MODE_IRQ:
1072  case ARM_MODE_HYP:
1073  case ARM_MODE_UND:
1074  case ARM_MODE_SYS:
1075  case ARM_MODE_MON:
1076  instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
1077  break;
1078 
1079  default:
1080  LOG_ERROR("cannot read system control register in this mode: (%s : 0x%x)",
1081  armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
1082  return ERROR_FAIL;
1083  }
1084 
1085  if (target_mode != ARM_MODE_ANY)
1086  armv8_dpm_modeswitch(&armv8->dpm, target_mode);
1087 
1088  retval = armv8->dpm.instr_read_data_r0_64(&armv8->dpm, instr, &aarch64->system_control_reg);
1089  if (retval != ERROR_OK)
1090  return retval;
1091 
1092  if (target_mode != ARM_MODE_ANY)
1093  armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
1094 
1095  LOG_DEBUG("System_register: %8.8" PRIx64, aarch64->system_control_reg);
1096  aarch64->system_control_reg_curr = aarch64->system_control_reg;
1097 
1098  if (!armv8->armv8_mmu.armv8_cache.info_valid) {
1099  armv8_identify_cache(armv8);
1100  armv8_read_mpidr(armv8);
1101  }
1102  if (armv8->is_armv8r) {
1103  armv8->armv8_mmu.mmu_enabled = false;
1104  } else {
1105  armv8->armv8_mmu.mmu_enabled = aarch64->system_control_reg & 0x1U;
1106  }
1107  armv8->armv8_mmu.armv8_cache.d_u_cache_enabled =
1108  aarch64->system_control_reg & 0x4U;
1109  armv8->armv8_mmu.armv8_cache.i_cache_enabled =
1110  aarch64->system_control_reg & 0x1000U;
1111  return ERROR_OK;
1112 }
1113 
1114 /*
1115  * single-step a target
1116  */
1117 static int aarch64_step(struct target *target, bool current, target_addr_t address,
1118  bool handle_breakpoints)
1119 {
1120  struct armv8_common *armv8 = target_to_armv8(target);
1121  struct aarch64_common *aarch64 = target_to_aarch64(target);
1122  int saved_retval = ERROR_OK;
1123  int poll_retval;
1124  int retval;
1125  uint32_t edecr;
1126 
1127  armv8->last_run_control_op = ARMV8_RUNCONTROL_STEP;
1128 
1129  if (target->state != TARGET_HALTED) {
1130  LOG_TARGET_ERROR(target, "not halted");
1131  return ERROR_TARGET_NOT_HALTED;
1132  }
1133 
1134  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1135  armv8->debug_base + CPUV8_DBG_EDECR, &edecr);
1136  /* make sure EDECR.SS is not set when restoring the register */
1137 
1138  if (retval == ERROR_OK) {
1139  edecr &= ~0x4;
1140  /* set EDECR.SS to enter hardware step mode */
1141  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1142  armv8->debug_base + CPUV8_DBG_EDECR, (edecr|0x4));
1143  }
1144  /* disable interrupts while stepping */
1145  if (retval == ERROR_OK && aarch64->isrmasking_mode == AARCH64_ISRMASK_ON)
1146  retval = aarch64_set_dscr_bits(target, 0x3 << 22, 0x3 << 22);
1147  /* bail out if stepping setup has failed */
1148  if (retval != ERROR_OK)
1149  return retval;
1150 
1151  if (target->smp && current) {
1152  /*
1153  * isolate current target so that it doesn't get resumed
1154  * together with the others
1155  */
1156  retval = arm_cti_gate_channel(armv8->cti, 1);
1157  /* resume all other targets in the group */
1158  if (retval == ERROR_OK)
1159  retval = aarch64_step_restart_smp(target);
1160  if (retval != ERROR_OK) {
1161  LOG_ERROR("Failed to restart non-stepping targets in SMP group");
1162  return retval;
1163  }
1164  LOG_DEBUG("Restarted all non-stepping targets in SMP group");
1165  }
1166 
1167  /* all other targets running, restore and restart the current target */
1168  retval = aarch64_restore_one(target, current, &address, false, false);
1169  if (retval == ERROR_OK)
1170  retval = aarch64_restart_one(target, RESTART_LAZY);
1171 
1172  if (retval != ERROR_OK)
1173  return retval;
1174 
1175  LOG_DEBUG("target step-resumed at 0x%" PRIx64, address);
1176  if (!handle_breakpoints)
1177  target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1178 
1179  int64_t then = timeval_ms();
1180  for (;;) {
1181  int stepped;
1182  uint32_t prsr;
1183 
1184  retval = aarch64_check_state_one(target,
1185  PRSR_SDR|PRSR_HALT, PRSR_SDR|PRSR_HALT, &stepped, &prsr);
1186  if (retval != ERROR_OK || stepped)
1187  break;
1188 
1189  if (timeval_ms() > then + 100) {
1190  LOG_ERROR("timeout waiting for target %s halt after step",
1191  target_name(target));
1192  retval = ERROR_TARGET_TIMEOUT;
1193  break;
1194  }
1195  }
1196 
1197  /*
1198  * At least on one SoC (Renesas R8A7795) stepping over a WFI instruction
1199  * causes a timeout. The core takes the step but doesn't complete it and so
1200  * debug state is never entered. However, you can manually halt the core
1201  * as an external debug even is also a WFI wakeup event.
1202  */
1203  if (retval == ERROR_TARGET_TIMEOUT)
1204  saved_retval = aarch64_halt_one(target, HALT_SYNC);
1205 
1206  poll_retval = aarch64_poll(target);
1207 
1208  /* restore EDECR */
1209  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1210  armv8->debug_base + CPUV8_DBG_EDECR, edecr);
1211  if (retval != ERROR_OK)
1212  return retval;
1213 
1214  /* restore interrupts */
1215  if (aarch64->isrmasking_mode == AARCH64_ISRMASK_ON) {
1216  retval = aarch64_set_dscr_bits(target, 0x3 << 22, 0);
1217  if (retval != ERROR_OK)
1218  return ERROR_OK;
1219  }
1220 
1221  if (saved_retval != ERROR_OK)
1222  return saved_retval;
1223 
1224  if (poll_retval != ERROR_OK)
1225  return poll_retval;
1226 
1227  return ERROR_OK;
1228 }
1229 
1230 static int aarch64_restore_context(struct target *target, bool bpwp)
1231 {
1232  struct armv8_common *armv8 = target_to_armv8(target);
1233  struct arm *arm = &armv8->arm;
1234 
1235  int retval;
1236 
1237  LOG_DEBUG("%s", target_name(target));
1238 
1239  if (armv8->pre_restore_context)
1240  armv8->pre_restore_context(target);
1241 
1242  retval = armv8_dpm_write_dirty_registers(&armv8->dpm, bpwp);
1243  if (retval == ERROR_OK) {
1244  /* registers are now invalid */
1245  register_cache_invalidate(arm->core_cache);
1246  register_cache_invalidate(arm->core_cache->next);
1247  }
1248 
1249  return retval;
1250 }
1251 
1252 /*
1253  * Cortex-A8 Breakpoint and watchpoint functions
1254  */
1255 
1256 /* Setup hardware Breakpoint Register Pair */
1257 static int aarch64_set_breakpoint(struct target *target,
1258  struct breakpoint *breakpoint, uint8_t matchmode)
1259 {
1260  int retval;
1261  int brp_i = 0;
1262  uint32_t control;
1263  uint8_t byte_addr_select = 0x0F;
1264  struct aarch64_common *aarch64 = target_to_aarch64(target);
1265  struct armv8_common *armv8 = &aarch64->armv8_common;
1266  struct aarch64_brp *brp_list = aarch64->brp_list;
1267 
1268  if (breakpoint->is_set) {
1269  LOG_WARNING("breakpoint already set");
1270  return ERROR_OK;
1271  }
1272 
1273  if (breakpoint->type == BKPT_HARD) {
1274  int64_t bpt_value;
1275  while (brp_list[brp_i].used && (brp_i < aarch64->brp_num))
1276  brp_i++;
1277  if (brp_i >= aarch64->brp_num) {
1278  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1279  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1280  }
1281  breakpoint_hw_set(breakpoint, brp_i);
1282  if (breakpoint->length == 2)
1283  byte_addr_select = (3 << (breakpoint->address & 0x02));
1284  control = ((matchmode & 0x7) << 20)
1285  | (1 << 13)
1286  | (byte_addr_select << 5)
1287  | (3 << 1) | 1;
1288  brp_list[brp_i].used = 1;
1289  brp_list[brp_i].value = breakpoint->address & 0xFFFFFFFFFFFFFFFCULL;
1290  brp_list[brp_i].control = control;
1291  bpt_value = brp_list[brp_i].value;
1292 
1293  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1294  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
1295  (uint32_t)(bpt_value & 0xFFFFFFFF));
1296  if (retval != ERROR_OK)
1297  return retval;
1298  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1299  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
1300  (uint32_t)(bpt_value >> 32));
1301  if (retval != ERROR_OK)
1302  return retval;
1303 
1304  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1305  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
1306  brp_list[brp_i].control);
1307  if (retval != ERROR_OK)
1308  return retval;
1309  LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
1310  brp_list[brp_i].control,
1311  brp_list[brp_i].value);
1312 
1313  } else if (breakpoint->type == BKPT_SOFT) {
1314  uint32_t opcode;
1315  uint8_t code[4];
1316 
1317  if (armv8_dpm_get_core_state(&armv8->dpm) == ARM_STATE_AARCH64) {
1318  opcode = ARMV8_HLT(11);
1319 
1320  if (breakpoint->length != 4)
1321  LOG_ERROR("bug: breakpoint length should be 4 in AArch64 mode");
1322  } else {
1331  opcode = (breakpoint->length == 4) ? ARMV8_HLT_A1(11) :
1332  (uint32_t) (ARMV8_HLT_T1(11) | ARMV8_HLT_T1(11) << 16);
1333 
1334  if (breakpoint->length == 3)
1335  breakpoint->length = 4;
1336  }
1337 
1338  buf_set_u32(code, 0, 32, opcode);
1339 
1340  retval = target_read_memory(target,
1341  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1342  breakpoint->length, 1,
1343  breakpoint->orig_instr);
1344  if (retval != ERROR_OK)
1345  return retval;
1346 
1347  armv8_cache_d_inner_flush_virt(armv8,
1348  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1349  breakpoint->length);
1350 
1351  retval = target_write_memory(target,
1352  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1353  breakpoint->length, 1, code);
1354  if (retval != ERROR_OK)
1355  return retval;
1356 
1357  armv8_cache_d_inner_flush_virt(armv8,
1358  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1359  breakpoint->length);
1360 
1361  armv8_cache_i_inner_inval_virt(armv8,
1362  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1363  breakpoint->length);
1364 
1365  breakpoint->is_set = true;
1366  }
1367 
1368  /* Ensure that halting debug mode is enable */
1369  retval = aarch64_set_dscr_bits(target, DSCR_HDE, DSCR_HDE);
1370  if (retval != ERROR_OK) {
1371  LOG_DEBUG("Failed to set DSCR.HDE");
1372  return retval;
1373  }
1374 
1375  return ERROR_OK;
1376 }
1377 
1378 static int aarch64_set_context_breakpoint(struct target *target,
1379  struct breakpoint *breakpoint, uint8_t matchmode)
1380 {
1381  int retval = ERROR_FAIL;
1382  int brp_i = 0;
1383  uint32_t control;
1384  uint8_t byte_addr_select = 0x0F;
1385  struct aarch64_common *aarch64 = target_to_aarch64(target);
1386  struct armv8_common *armv8 = &aarch64->armv8_common;
1387  struct aarch64_brp *brp_list = aarch64->brp_list;
1388 
1389  if (breakpoint->is_set) {
1390  LOG_WARNING("breakpoint already set");
1391  return retval;
1392  }
1393  /*check available context BRPs*/
1394  while ((brp_list[brp_i].used ||
1395  (brp_list[brp_i].type != BRP_CONTEXT)) && (brp_i < aarch64->brp_num))
1396  brp_i++;
1397 
1398  if (brp_i >= aarch64->brp_num) {
1399  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1400  return ERROR_FAIL;
1401  }
1402 
1403  breakpoint_hw_set(breakpoint, brp_i);
1404  control = ((matchmode & 0x7) << 20)
1405  | (1 << 13)
1406  | (byte_addr_select << 5)
1407  | (3 << 1) | 1;
1408  brp_list[brp_i].used = 1;
1409  brp_list[brp_i].value = (breakpoint->asid);
1410  brp_list[brp_i].control = control;
1411  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1412  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
1413  brp_list[brp_i].value);
1414  if (retval != ERROR_OK)
1415  return retval;
1416  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1417  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
1418  brp_list[brp_i].control);
1419  if (retval != ERROR_OK)
1420  return retval;
1421  LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
1422  brp_list[brp_i].control,
1423  brp_list[brp_i].value);
1424  return ERROR_OK;
1425 
1426 }
1427 
1428 static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
1429 {
1430  int retval = ERROR_FAIL;
1431  int brp_1 = 0; /* holds the contextID pair */
1432  int brp_2 = 0; /* holds the IVA pair */
1433  uint32_t control_ctx, control_iva;
1434  uint8_t ctx_byte_addr_select = 0x0F;
1435  uint8_t iva_byte_addr_select = 0x0F;
1436  uint8_t ctx_machmode = 0x03;
1437  uint8_t iva_machmode = 0x01;
1438  struct aarch64_common *aarch64 = target_to_aarch64(target);
1439  struct armv8_common *armv8 = &aarch64->armv8_common;
1440  struct aarch64_brp *brp_list = aarch64->brp_list;
1441 
1442  if (breakpoint->is_set) {
1443  LOG_WARNING("breakpoint already set");
1444  return retval;
1445  }
1446  /*check available context BRPs*/
1447  while ((brp_list[brp_1].used ||
1448  (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < aarch64->brp_num))
1449  brp_1++;
1450 
1451  LOG_DEBUG("brp(CTX) found num: %d", brp_1);
1452  if (brp_1 >= aarch64->brp_num) {
1453  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1454  return ERROR_FAIL;
1455  }
1456 
1457  while ((brp_list[brp_2].used ||
1458  (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < aarch64->brp_num))
1459  brp_2++;
1460 
1461  LOG_DEBUG("brp(IVA) found num: %d", brp_2);
1462  if (brp_2 >= aarch64->brp_num) {
1463  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1464  return ERROR_FAIL;
1465  }
1466 
1467  breakpoint_hw_set(breakpoint, brp_1);
1468  breakpoint->linked_brp = brp_2;
1469  control_ctx = ((ctx_machmode & 0x7) << 20)
1470  | (brp_2 << 16)
1471  | (0 << 14)
1472  | (ctx_byte_addr_select << 5)
1473  | (3 << 1) | 1;
1474  brp_list[brp_1].used = 1;
1475  brp_list[brp_1].value = (breakpoint->asid);
1476  brp_list[brp_1].control = control_ctx;
1477  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1478  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_1].brpn,
1479  brp_list[brp_1].value);
1480  if (retval != ERROR_OK)
1481  return retval;
1482  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1483  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_1].brpn,
1484  brp_list[brp_1].control);
1485  if (retval != ERROR_OK)
1486  return retval;
1487 
1488  control_iva = ((iva_machmode & 0x7) << 20)
1489  | (brp_1 << 16)
1490  | (1 << 13)
1491  | (iva_byte_addr_select << 5)
1492  | (3 << 1) | 1;
1493  brp_list[brp_2].used = 1;
1494  brp_list[brp_2].value = breakpoint->address & 0xFFFFFFFFFFFFFFFCULL;
1495  brp_list[brp_2].control = control_iva;
1496  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1497  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_2].brpn,
1498  brp_list[brp_2].value & 0xFFFFFFFF);
1499  if (retval != ERROR_OK)
1500  return retval;
1501  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1502  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_2].brpn,
1503  brp_list[brp_2].value >> 32);
1504  if (retval != ERROR_OK)
1505  return retval;
1506  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1507  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_2].brpn,
1508  brp_list[brp_2].control);
1509  if (retval != ERROR_OK)
1510  return retval;
1511 
1512  return ERROR_OK;
1513 }
1514 
1515 static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1516 {
1517  int retval;
1518  struct aarch64_common *aarch64 = target_to_aarch64(target);
1519  struct armv8_common *armv8 = &aarch64->armv8_common;
1520  struct aarch64_brp *brp_list = aarch64->brp_list;
1521 
1522  if (!breakpoint->is_set) {
1523  LOG_WARNING("breakpoint not set");
1524  return ERROR_OK;
1525  }
1526 
1527  if (breakpoint->type == BKPT_HARD) {
1528  if ((breakpoint->address != 0) && (breakpoint->asid != 0)) {
1529  int brp_i = breakpoint->number;
1530  int brp_j = breakpoint->linked_brp;
1531  if (brp_i >= aarch64->brp_num) {
1532  LOG_DEBUG("Invalid BRP number in breakpoint");
1533  return ERROR_OK;
1534  }
1535  LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
1536  brp_list[brp_i].control, brp_list[brp_i].value);
1537  brp_list[brp_i].used = 0;
1538  brp_list[brp_i].value = 0;
1539  brp_list[brp_i].control = 0;
1540  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1541  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
1542  brp_list[brp_i].control);
1543  if (retval != ERROR_OK)
1544  return retval;
1545  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1546  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
1547  (uint32_t)brp_list[brp_i].value);
1548  if (retval != ERROR_OK)
1549  return retval;
1550  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1551  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
1552  (uint32_t)brp_list[brp_i].value);
1553  if (retval != ERROR_OK)
1554  return retval;
1555  if ((brp_j < 0) || (brp_j >= aarch64->brp_num)) {
1556  LOG_DEBUG("Invalid BRP number in breakpoint");
1557  return ERROR_OK;
1558  }
1559  LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, brp_j,
1560  brp_list[brp_j].control, brp_list[brp_j].value);
1561  brp_list[brp_j].used = 0;
1562  brp_list[brp_j].value = 0;
1563  brp_list[brp_j].control = 0;
1564  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1565  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_j].brpn,
1566  brp_list[brp_j].control);
1567  if (retval != ERROR_OK)
1568  return retval;
1569  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1570  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_j].brpn,
1571  (uint32_t)brp_list[brp_j].value);
1572  if (retval != ERROR_OK)
1573  return retval;
1574  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1575  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_j].brpn,
1576  (uint32_t)brp_list[brp_j].value);
1577  if (retval != ERROR_OK)
1578  return retval;
1579 
1580  breakpoint->linked_brp = 0;
1581  breakpoint->is_set = false;
1582  return ERROR_OK;
1583 
1584  } else {
1585  int brp_i = breakpoint->number;
1586  if (brp_i >= aarch64->brp_num) {
1587  LOG_DEBUG("Invalid BRP number in breakpoint");
1588  return ERROR_OK;
1589  }
1590  LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, brp_i,
1591  brp_list[brp_i].control, brp_list[brp_i].value);
1592  brp_list[brp_i].used = 0;
1593  brp_list[brp_i].value = 0;
1594  brp_list[brp_i].control = 0;
1595  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1596  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
1597  brp_list[brp_i].control);
1598  if (retval != ERROR_OK)
1599  return retval;
1600  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1601  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
1602  brp_list[brp_i].value);
1603  if (retval != ERROR_OK)
1604  return retval;
1605 
1606  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1607  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
1608  (uint32_t)brp_list[brp_i].value);
1609  if (retval != ERROR_OK)
1610  return retval;
1611  breakpoint->is_set = false;
1612  return ERROR_OK;
1613  }
1614  } else {
1615  /* restore original instruction (kept in target endianness) */
1616 
1617  armv8_cache_d_inner_flush_virt(armv8,
1618  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1619  breakpoint->length);
1620 
1621  if (breakpoint->length == 4) {
1622  retval = target_write_memory(target,
1623  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1624  4, 1, breakpoint->orig_instr);
1625  if (retval != ERROR_OK)
1626  return retval;
1627  } else {
1628  retval = target_write_memory(target,
1629  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1630  2, 1, breakpoint->orig_instr);
1631  if (retval != ERROR_OK)
1632  return retval;
1633  }
1634 
1635  armv8_cache_d_inner_flush_virt(armv8,
1636  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1637  breakpoint->length);
1638 
1639  armv8_cache_i_inner_inval_virt(armv8,
1640  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1641  breakpoint->length);
1642  }
1643  breakpoint->is_set = false;
1644 
1645  return ERROR_OK;
1646 }
1647 
1648 static int aarch64_add_breakpoint(struct target *target,
1649  struct breakpoint *breakpoint)
1650 {
1651  struct aarch64_common *aarch64 = target_to_aarch64(target);
1652 
1653  if ((breakpoint->type == BKPT_HARD) && (aarch64->brp_num_available < 1)) {
1654  LOG_INFO("no hardware breakpoint available");
1655  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1656  }
1657 
1658  if (breakpoint->type == BKPT_HARD)
1659  aarch64->brp_num_available--;
1660 
1661  return aarch64_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
1662 }
1663 
1664 static int aarch64_add_context_breakpoint(struct target *target,
1665  struct breakpoint *breakpoint)
1666 {
1667  struct aarch64_common *aarch64 = target_to_aarch64(target);
1668 
1669  if ((breakpoint->type == BKPT_HARD) && (aarch64->brp_num_available < 1)) {
1670  LOG_INFO("no hardware breakpoint available");
1671  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1672  }
1673 
1674  if (breakpoint->type == BKPT_HARD)
1675  aarch64->brp_num_available--;
1676 
1677  return aarch64_set_context_breakpoint(target, breakpoint, 0x02); /* asid match */
1678 }
1679 
1680 static int aarch64_add_hybrid_breakpoint(struct target *target,
1681  struct breakpoint *breakpoint)
1682 {
1683  struct aarch64_common *aarch64 = target_to_aarch64(target);
1684 
1685  if ((breakpoint->type == BKPT_HARD) && (aarch64->brp_num_available < 1)) {
1686  LOG_INFO("no hardware breakpoint available");
1687  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1688  }
1689 
1690  if (breakpoint->type == BKPT_HARD)
1691  aarch64->brp_num_available--;
1692 
1693  return aarch64_set_hybrid_breakpoint(target, breakpoint); /* ??? */
1694 }
1695 
1696 static int aarch64_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1697 {
1698  struct aarch64_common *aarch64 = target_to_aarch64(target);
1699 
1700 #if 0
1701 /* It is perfectly possible to remove breakpoints while the target is running */
1702  if (target->state != TARGET_HALTED) {
1703  LOG_WARNING("target not halted");
1704  return ERROR_TARGET_NOT_HALTED;
1705  }
1706 #endif
1707 
1708  if (breakpoint->is_set) {
1709  aarch64_unset_breakpoint(target, breakpoint);
1710  if (breakpoint->type == BKPT_HARD)
1711  aarch64->brp_num_available++;
1712  }
1713 
1714  return ERROR_OK;
1715 }
1716 
1717 /* Setup hardware Watchpoint Register Pair */
1718 static int aarch64_set_watchpoint(struct target *target,
1719  struct watchpoint *watchpoint)
1720 {
1721  int retval;
1722  int wp_i = 0;
1723  uint32_t control, offset, length;
1724  struct aarch64_common *aarch64 = target_to_aarch64(target);
1725  struct armv8_common *armv8 = &aarch64->armv8_common;
1726  struct aarch64_brp *wp_list = aarch64->wp_list;
1727 
1728  if (watchpoint->is_set) {
1729  LOG_WARNING("watchpoint already set");
1730  return ERROR_OK;
1731  }
1732 
1733  while (wp_list[wp_i].used && (wp_i < aarch64->wp_num))
1734  wp_i++;
1735  if (wp_i >= aarch64->wp_num) {
1736  LOG_ERROR("ERROR Can not find free Watchpoint Register Pair");
1737  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1738  }
1739 
1740  control = (1 << 0) /* enable */
1741  | (3 << 1) /* both user and privileged access */
1742  | (1 << 13); /* higher mode control */
1743 
1744  switch (watchpoint->rw) {
1745  case WPT_READ:
1746  control |= 1 << 3;
1747  break;
1748  case WPT_WRITE:
1749  control |= 2 << 3;
1750  break;
1751  case WPT_ACCESS:
1752  control |= 3 << 3;
1753  break;
1754  }
1755 
1756  /* Match up to 8 bytes. */
1757  offset = watchpoint->address & 7;
1758  length = watchpoint->length;
1759  if (offset + length > sizeof(uint64_t)) {
1760  length = sizeof(uint64_t) - offset;
1761  LOG_WARNING("Adjust watchpoint match inside 8-byte boundary");
1762  }
1763  for (; length > 0; offset++, length--)
1764  control |= (1 << offset) << 5;
1765 
1766  wp_list[wp_i].value = watchpoint->address & 0xFFFFFFFFFFFFFFF8ULL;
1767  wp_list[wp_i].control = control;
1768 
1769  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1770  + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].brpn,
1771  (uint32_t)(wp_list[wp_i].value & 0xFFFFFFFF));
1772  if (retval != ERROR_OK)
1773  return retval;
1774  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1775  + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].brpn,
1776  (uint32_t)(wp_list[wp_i].value >> 32));
1777  if (retval != ERROR_OK)
1778  return retval;
1779 
1780  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1781  + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].brpn,
1782  control);
1783  if (retval != ERROR_OK)
1784  return retval;
1785  LOG_DEBUG("wp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, wp_i,
1786  wp_list[wp_i].control, wp_list[wp_i].value);
1787 
1788  /* Ensure that halting debug mode is enable */
1789  retval = aarch64_set_dscr_bits(target, DSCR_HDE, DSCR_HDE);
1790  if (retval != ERROR_OK) {
1791  LOG_DEBUG("Failed to set DSCR.HDE");
1792  return retval;
1793  }
1794 
1795  wp_list[wp_i].used = 1;
1796  watchpoint_set(watchpoint, wp_i);
1797 
1798  return ERROR_OK;
1799 }
1800 
1801 /* Clear hardware Watchpoint Register Pair */
1802 static int aarch64_unset_watchpoint(struct target *target,
1803  struct watchpoint *watchpoint)
1804 {
1805  int retval;
1806  struct aarch64_common *aarch64 = target_to_aarch64(target);
1807  struct armv8_common *armv8 = &aarch64->armv8_common;
1808  struct aarch64_brp *wp_list = aarch64->wp_list;
1809 
1810  if (!watchpoint->is_set) {
1811  LOG_WARNING("watchpoint not set");
1812  return ERROR_OK;
1813  }
1814 
1815  int wp_i = watchpoint->number;
1816  if (wp_i >= aarch64->wp_num) {
1817  LOG_DEBUG("Invalid WP number in watchpoint");
1818  return ERROR_OK;
1819  }
1820  LOG_DEBUG("rwp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, wp_i,
1821  wp_list[wp_i].control, wp_list[wp_i].value);
1822  wp_list[wp_i].used = 0;
1823  wp_list[wp_i].value = 0;
1824  wp_list[wp_i].control = 0;
1825  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1826  + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].brpn,
1827  wp_list[wp_i].control);
1828  if (retval != ERROR_OK)
1829  return retval;
1830  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1831  + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].brpn,
1832  wp_list[wp_i].value);
1833  if (retval != ERROR_OK)
1834  return retval;
1835 
1836  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1837  + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].brpn,
1838  (uint32_t)wp_list[wp_i].value);
1839  if (retval != ERROR_OK)
1840  return retval;
1841  watchpoint->is_set = false;
1842 
1843  return ERROR_OK;
1844 }
1845 
1846 static int aarch64_add_watchpoint(struct target *target,
1847  struct watchpoint *watchpoint)
1848 {
1849  int retval;
1850  struct aarch64_common *aarch64 = target_to_aarch64(target);
1851 
1852  if (aarch64->wp_num_available < 1) {
1853  LOG_INFO("no hardware watchpoint available");
1854  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1855  }
1856 
1857  retval = aarch64_set_watchpoint(target, watchpoint);
1858  if (retval == ERROR_OK)
1859  aarch64->wp_num_available--;
1860 
1861  return retval;
1862 }
1863 
1864 static int aarch64_remove_watchpoint(struct target *target,
1865  struct watchpoint *watchpoint)
1866 {
1867  struct aarch64_common *aarch64 = target_to_aarch64(target);
1868 
1869  if (watchpoint->is_set) {
1870  aarch64_unset_watchpoint(target, watchpoint);
1871  aarch64->wp_num_available++;
1872  }
1873 
1874  return ERROR_OK;
1875 }
1876 
1881 static int aarch64_hit_watchpoint(struct target *target,
1882  struct watchpoint **hit_watchpoint)
1883 {
1884  if (target->debug_reason != DBG_REASON_WATCHPOINT)
1885  return ERROR_FAIL;
1886 
1887  struct armv8_common *armv8 = target_to_armv8(target);
1888 
1889  target_addr_t exception_address;
1890  struct watchpoint *wp;
1891 
1892  exception_address = armv8->dpm.wp_addr;
1893 
1894  if (exception_address == 0xFFFFFFFF)
1895  return ERROR_FAIL;
1896 
1897  for (wp = target->watchpoints; wp; wp = wp->next)
1898  if (exception_address >= wp->address && exception_address < (wp->address + wp->length)) {
1899  *hit_watchpoint = wp;
1900  return ERROR_OK;
1901  }
1902 
1903  return ERROR_FAIL;
1904 }
1905 
1906 /*
1907  * Cortex-A8 Reset functions
1908  */
1909 
1910 static int aarch64_enable_reset_catch(struct target *target, bool enable)
1911 {
1912  struct armv8_common *armv8 = target_to_armv8(target);
1913  uint32_t edecr;
1914  int retval;
1915 
1916  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1917  armv8->debug_base + CPUV8_DBG_EDECR, &edecr);
1918  LOG_DEBUG("EDECR = 0x%08" PRIx32 ", enable=%d", edecr, enable);
1919  if (retval != ERROR_OK)
1920  return retval;
1921 
1922  if (enable)
1923  edecr |= ECR_RCE;
1924  else
1925  edecr &= ~ECR_RCE;
1926 
1927  return mem_ap_write_atomic_u32(armv8->debug_ap,
1928  armv8->debug_base + CPUV8_DBG_EDECR, edecr);
1929 }
1930 
1931 static int aarch64_clear_reset_catch(struct target *target)
1932 {
1933  struct armv8_common *armv8 = target_to_armv8(target);
1934  uint32_t edesr;
1935  int retval;
1936  bool was_triggered;
1937 
1938  /* check if Reset Catch debug event triggered as expected */
1939  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1940  armv8->debug_base + CPUV8_DBG_EDESR, &edesr);
1941  if (retval != ERROR_OK)
1942  return retval;
1943 
1944  was_triggered = !!(edesr & ESR_RC);
1945  LOG_DEBUG("Reset Catch debug event %s",
1946  was_triggered ? "triggered" : "NOT triggered!");
1947 
1948  if (was_triggered) {
1949  /* clear pending Reset Catch debug event */
1950  edesr &= ~ESR_RC;
1951  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1952  armv8->debug_base + CPUV8_DBG_EDESR, edesr);
1953  if (retval != ERROR_OK)
1954  return retval;
1955  }
1956 
1957  return ERROR_OK;
1958 }
1959 
1960 static int aarch64_assert_reset(struct target *target)
1961 {
1962  struct armv8_common *armv8 = target_to_armv8(target);
1963  enum reset_types reset_config = jtag_get_reset_config();
1964  int retval;
1965 
1966  LOG_DEBUG(" ");
1967 
1968  /* Issue some kind of warm reset. */
1969  if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
1970  target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1971  else if (reset_config & RESET_HAS_SRST) {
1972  bool srst_asserted = false;
1973 
1974  if (target->reset_halt && !(reset_config & RESET_SRST_PULLS_TRST)) {
1975  if (target_was_examined(target)) {
1976 
1977  if (reset_config & RESET_SRST_NO_GATING) {
1978  /*
1979  * SRST needs to be asserted *before* Reset Catch
1980  * debug event can be set up.
1981  */
1982  adapter_assert_reset();
1983  srst_asserted = true;
1984  }
1985 
1986  /* make sure to clear all sticky errors */
1987  mem_ap_write_atomic_u32(armv8->debug_ap,
1988  armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
1989 
1990  /* set up Reset Catch debug event to halt the CPU after reset */
1991  retval = aarch64_enable_reset_catch(target, true);
1992  if (retval != ERROR_OK)
1993  LOG_WARNING("%s: Error enabling Reset Catch debug event; the CPU will not halt immediately after reset!",
1994  target_name(target));
1995  } else {
1996  LOG_WARNING("%s: Target not examined, will not halt immediately after reset!",
1997  target_name(target));
1998  }
1999  }
2000 
2001  /* REVISIT handle "pulls" cases, if there's
2002  * hardware that needs them to work.
2003  */
2004  if (!srst_asserted)
2005  adapter_assert_reset();
2006  } else {
2007  LOG_ERROR("%s: how to reset?", target_name(target));
2008  return ERROR_FAIL;
2009  }
2010 
2011  /* registers are now invalid */
2012  if (armv8->arm.core_cache) {
2013  register_cache_invalidate(armv8->arm.core_cache);
2014  register_cache_invalidate(armv8->arm.core_cache->next);
2015  }
2016 
2017  target->state = TARGET_RESET;
2018 
2019  return ERROR_OK;
2020 }
2021 
2022 static int aarch64_deassert_reset(struct target *target)
2023 {
2024  int retval;
2025 
2026  LOG_DEBUG(" ");
2027 
2028  /* be certain SRST is off */
2029  adapter_deassert_reset();
2030 
2031  if (!target_was_examined(target))
2032  return ERROR_OK;
2033 
2034  retval = aarch64_init_debug_access(target);
2035  if (retval != ERROR_OK)
2036  return retval;
2037 
2038  retval = aarch64_poll(target);
2039  if (retval != ERROR_OK)
2040  return retval;
2041 
2042  if (target->reset_halt) {
2043  /* clear pending Reset Catch debug event */
2044  retval = aarch64_clear_reset_catch(target);
2045  if (retval != ERROR_OK)
2046  LOG_WARNING("%s: Clearing Reset Catch debug event failed",
2047  target_name(target));
2048 
2049  /* disable Reset Catch debug event */
2050  retval = aarch64_enable_reset_catch(target, false);
2051  if (retval != ERROR_OK)
2052  LOG_WARNING("%s: Disabling Reset Catch debug event failed",
2053  target_name(target));
2054 
2055  if (target->state != TARGET_HALTED) {
2056  LOG_WARNING("%s: ran after reset and before halt ...",
2057  target_name(target));
2058  if (target_was_examined(target)) {
2059  retval = aarch64_halt_one(target, HALT_LAZY);
2060  if (retval != ERROR_OK)
2061  return retval;
2062  } else {
2063  target->state = TARGET_UNKNOWN;
2064  }
2065  }
2066  }
2067 
2068  return ERROR_OK;
2069 }
2070 
2071 static int aarch64_write_cpu_memory_slow(struct target *target,
2072  uint32_t size, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
2073 {
2074  struct armv8_common *armv8 = target_to_armv8(target);
2075  struct arm_dpm *dpm = &armv8->dpm;
2076  struct arm *arm = &armv8->arm;
2077  int retval;
2078 
2079  if (size > 4 && arm->core_state != ARM_STATE_AARCH64) {
2080  LOG_ERROR("memory write sizes greater than 4 bytes is only supported for AArch64 state");
2081  return ERROR_FAIL;
2082  }
2083 
2084  armv8_reg_current(arm, 1)->dirty = true;
2085 
2086  /* change DCC to normal mode if necessary */
2087  if (*dscr & DSCR_MA) {
2088  *dscr &= ~DSCR_MA;
2089  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2090  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2091  if (retval != ERROR_OK)
2092  return retval;
2093  }
2094 
2095  while (count) {
2096  uint32_t opcode;
2097  uint64_t data;
2098 
2099  /* write the data to store into DTRRX (and DTRTX for 64-bit) */
2100  if (size == 1)
2101  data = *buffer;
2102  else if (size == 2)
2103  data = target_buffer_get_u16(target, buffer);
2104  else if (size == 4)
2105  data = target_buffer_get_u32(target, buffer);
2106  else
2107  data = target_buffer_get_u64(target, buffer);
2108 
2109  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2110  armv8->debug_base + CPUV8_DBG_DTRRX, (uint32_t)data);
2111  if (retval == ERROR_OK && size > 4)
2112  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2113  armv8->debug_base + CPUV8_DBG_DTRTX, (uint32_t)(data >> 32));
2114  if (retval != ERROR_OK)
2115  return retval;
2116 
2117  if (arm->core_state == ARM_STATE_AARCH64)
2118  if (size <= 4)
2119  retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 1));
2120  else
2121  retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 1));
2122  else
2123  retval = dpm->instr_execute(dpm, ARMV4_5_MRC(14, 0, 1, 0, 5, 0));
2124  if (retval != ERROR_OK)
2125  return retval;
2126 
2127  if (size == 1)
2128  opcode = armv8_opcode(armv8, ARMV8_OPC_STRB_IP);
2129  else if (size == 2)
2130  opcode = armv8_opcode(armv8, ARMV8_OPC_STRH_IP);
2131  else if (size == 4)
2132  opcode = armv8_opcode(armv8, ARMV8_OPC_STRW_IP);
2133  else
2134  opcode = armv8_opcode(armv8, ARMV8_OPC_STRD_IP);
2135 
2136  retval = dpm->instr_execute(dpm, opcode);
2137  if (retval != ERROR_OK)
2138  return retval;
2139 
2140  /* Advance */
2141  buffer += size;
2142  --count;
2143  }
2144 
2145  return ERROR_OK;
2146 }
2147 
2148 static int aarch64_write_cpu_memory_fast(struct target *target,
2149  uint32_t count, const uint8_t *buffer, uint32_t *dscr)
2150 {
2151  struct armv8_common *armv8 = target_to_armv8(target);
2152  struct arm *arm = &armv8->arm;
2153  int retval;
2154 
2155  armv8_reg_current(arm, 1)->dirty = true;
2156 
2157  /* Step 1.d - Change DCC to memory mode */
2158  *dscr |= DSCR_MA;
2159  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2160  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2161  if (retval != ERROR_OK)
2162  return retval;
2163 
2164 
2165  /* Step 2.a - Do the write */
2166  retval = mem_ap_write_buf_noincr(armv8->debug_ap,
2167  buffer, 4, count, armv8->debug_base + CPUV8_DBG_DTRRX);
2168  if (retval != ERROR_OK)
2169  return retval;
2170 
2171  /* Step 3.a - Switch DTR mode back to Normal mode */
2172  *dscr &= ~DSCR_MA;
2173  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2174  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2175  if (retval != ERROR_OK)
2176  return retval;
2177 
2178  return ERROR_OK;
2179 }
2180 
2181 static int aarch64_write_cpu_memory(struct target *target,
2182  uint64_t address, uint32_t size,
2183  uint32_t count, const uint8_t *buffer)
2184 {
2185  /* write memory through APB-AP */
2186  int retval = ERROR_COMMAND_SYNTAX_ERROR;
2187  struct armv8_common *armv8 = target_to_armv8(target);
2188  struct arm_dpm *dpm = &armv8->dpm;
2189  struct arm *arm = &armv8->arm;
2190  uint32_t dscr;
2191 
2192  if (target->state != TARGET_HALTED) {
2193  LOG_TARGET_ERROR(target, "not halted");
2194  return ERROR_TARGET_NOT_HALTED;
2195  }
2196 
2197  /* Mark register X0 as dirty, as it will be used
2198  * for transferring the data.
2199  * It will be restored automatically when exiting
2200  * debug mode
2201  */
2202  armv8_reg_current(arm, 0)->dirty = true;
2203 
2204  /* This algorithm comes from DDI0487A.g, chapter J9.1 */
2205 
2206  /* Read DSCR */
2207  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2208  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2209  if (retval != ERROR_OK)
2210  return retval;
2211 
2212  /* Set Normal access mode */
2213  dscr = (dscr & ~DSCR_MA);
2214  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2215  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
2216  if (retval != ERROR_OK)
2217  return retval;
2218 
2219  if (arm->core_state == ARM_STATE_AARCH64) {
2220  /* Write X0 with value 'address' using write procedure */
2221  /* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
2222  /* Step 1.c - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
2223  retval = dpm->instr_write_data_dcc_64(dpm,
2224  ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), address);
2225  } else {
2226  /* Write R0 with value 'address' using write procedure */
2227  /* Step 1.a+b - Write the address for read access into DBGDTRRX */
2228  /* Step 1.c - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
2229  retval = dpm->instr_write_data_dcc(dpm,
2230  ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address);
2231  }
2232 
2233  if (retval != ERROR_OK)
2234  return retval;
2235 
2236  if (size == 4 && (address % 4) == 0)
2237  retval = aarch64_write_cpu_memory_fast(target, count, buffer, &dscr);
2238  else
2239  retval = aarch64_write_cpu_memory_slow(target, size, count, buffer, &dscr);
2240 
2241  if (retval != ERROR_OK) {
2242  /* Unset DTR mode */
2243  mem_ap_read_atomic_u32(armv8->debug_ap,
2244  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2245  dscr &= ~DSCR_MA;
2246  mem_ap_write_atomic_u32(armv8->debug_ap,
2247  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
2248  }
2249 
2250  /* Check for sticky abort flags in the DSCR */
2251  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2252  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2253  if (retval != ERROR_OK)
2254  return retval;
2255 
2256  dpm->dscr = dscr;
2257  if (dscr & (DSCR_ERR | DSCR_SYS_ERROR_PEND)) {
2258  /* Abort occurred - clear it and exit */
2259  LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr);
2260  armv8_dpm_handle_exception(dpm, true);
2261  return ERROR_FAIL;
2262  }
2263 
2264  /* Done */
2265  return ERROR_OK;
2266 }
2267 
2268 static int aarch64_read_cpu_memory_slow(struct target *target,
2269  uint32_t size, uint32_t count, uint8_t *buffer, uint32_t *dscr)
2270 {
2271  struct armv8_common *armv8 = target_to_armv8(target);
2272  struct arm_dpm *dpm = &armv8->dpm;
2273  struct arm *arm = &armv8->arm;
2274  int retval;
2275 
2276  if (size > 4 && arm->core_state != ARM_STATE_AARCH64) {
2277  LOG_ERROR("memory read sizes greater than 4 bytes is only supported for AArch64 state");
2278  return ERROR_FAIL;
2279  }
2280 
2281  armv8_reg_current(arm, 1)->dirty = true;
2282 
2283  /* change DCC to normal mode (if necessary) */
2284  if (*dscr & DSCR_MA) {
2285  *dscr &= DSCR_MA;
2286  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2287  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2288  if (retval != ERROR_OK)
2289  return retval;
2290  }
2291 
2292  while (count) {
2293  uint32_t opcode;
2294  uint32_t lower;
2295  uint32_t higher;
2296  uint64_t data;
2297 
2298  if (size == 1)
2299  opcode = armv8_opcode(armv8, ARMV8_OPC_LDRB_IP);
2300  else if (size == 2)
2301  opcode = armv8_opcode(armv8, ARMV8_OPC_LDRH_IP);
2302  else if (size == 4)
2303  opcode = armv8_opcode(armv8, ARMV8_OPC_LDRW_IP);
2304  else
2305  opcode = armv8_opcode(armv8, ARMV8_OPC_LDRD_IP);
2306 
2307  retval = dpm->instr_execute(dpm, opcode);
2308  if (retval != ERROR_OK)
2309  return retval;
2310 
2311  if (arm->core_state == ARM_STATE_AARCH64)
2312  if (size <= 4)
2313  retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 1));
2314  else
2315  retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 1));
2316  else
2317  retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 1, 0, 5, 0));
2318  if (retval != ERROR_OK)
2319  return retval;
2320 
2321  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2322  armv8->debug_base + CPUV8_DBG_DTRTX, &lower);
2323  if (retval == ERROR_OK) {
2324  if (size > 4)
2325  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2326  armv8->debug_base + CPUV8_DBG_DTRRX, &higher);
2327  else
2328  higher = 0;
2329  }
2330  if (retval != ERROR_OK)
2331  return retval;
2332 
2333  data = (uint64_t)lower | (uint64_t)higher << 32;
2334 
2335  if (size == 1)
2336  *buffer = (uint8_t)data;
2337  else if (size == 2)
2338  target_buffer_set_u16(target, buffer, (uint16_t)data);
2339  else if (size == 4)
2340  target_buffer_set_u32(target, buffer, (uint32_t)data);
2341  else
2342  target_buffer_set_u64(target, buffer, data);
2343 
2344  /* Advance */
2345  buffer += size;
2346  --count;
2347  }
2348 
2349  return ERROR_OK;
2350 }
2351 
2352 static int aarch64_read_cpu_memory_fast(struct target *target,
2353  uint32_t count, uint8_t *buffer, uint32_t *dscr)
2354 {
2355  struct armv8_common *armv8 = target_to_armv8(target);
2356  struct arm_dpm *dpm = &armv8->dpm;
2357  struct arm *arm = &armv8->arm;
2358  int retval;
2359  uint32_t value;
2360 
2361  /* Mark X1 as dirty */
2362  armv8_reg_current(arm, 1)->dirty = true;
2363 
2364  if (arm->core_state == ARM_STATE_AARCH64) {
2365  /* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
2366  retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0));
2367  } else {
2368  /* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
2369  retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
2370  }
2371 
2372  if (retval != ERROR_OK)
2373  return retval;
2374 
2375  /* Step 1.e - Change DCC to memory mode */
2376  *dscr |= DSCR_MA;
2377  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2378  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2379  if (retval != ERROR_OK)
2380  return retval;
2381 
2382  /* Step 1.f - read DBGDTRTX and discard the value */
2383  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2384  armv8->debug_base + CPUV8_DBG_DTRTX, &value);
2385  if (retval != ERROR_OK)
2386  return retval;
2387 
2388  count--;
2389  /* Read the data - Each read of the DTRTX register causes the instruction to be reissued
2390  * Abort flags are sticky, so can be read at end of transactions
2391  *
2392  * This data is read in aligned to 32 bit boundary.
2393  */
2394 
2395  if (count) {
2396  /* Step 2.a - Loop n-1 times, each read of DBGDTRTX reads the data from [X0] and
2397  * increments X0 by 4. */
2398  retval = mem_ap_read_buf_noincr(armv8->debug_ap, buffer, 4, count,
2399  armv8->debug_base + CPUV8_DBG_DTRTX);
2400  if (retval != ERROR_OK)
2401  return retval;
2402  }
2403 
2404  /* Step 3.a - set DTR access mode back to Normal mode */
2405  *dscr &= ~DSCR_MA;
2406  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2407  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2408  if (retval != ERROR_OK)
2409  return retval;
2410 
2411  /* Step 3.b - read DBGDTRTX for the final value */
2412  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2413  armv8->debug_base + CPUV8_DBG_DTRTX, &value);
2414  if (retval != ERROR_OK)
2415  return retval;
2416 
2417  target_buffer_set_u32(target, buffer + count * 4, value);
2418  return retval;
2419 }
2420 
2421 static int aarch64_read_cpu_memory(struct target *target,
2422  target_addr_t address, uint32_t size,
2423  uint32_t count, uint8_t *buffer)
2424 {
2425  /* read memory through APB-AP */
2426  int retval = ERROR_COMMAND_SYNTAX_ERROR;
2427  struct armv8_common *armv8 = target_to_armv8(target);
2428  struct arm_dpm *dpm = &armv8->dpm;
2429  struct arm *arm = &armv8->arm;
2430  uint32_t dscr;
2431 
2432  LOG_DEBUG("Reading CPU memory address 0x%016" PRIx64 " size %" PRIu32 " count %" PRIu32,
2433  address, size, count);
2434 
2435  if (target->state != TARGET_HALTED) {
2436  LOG_TARGET_ERROR(target, "not halted");
2437  return ERROR_TARGET_NOT_HALTED;
2438  }
2439 
2440  /* Mark register X0 as dirty, as it will be used
2441  * for transferring the data.
2442  * It will be restored automatically when exiting
2443  * debug mode
2444  */
2445  armv8_reg_current(arm, 0)->dirty = true;
2446 
2447  /* Read DSCR */
2448  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2449  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2450  if (retval != ERROR_OK)
2451  return retval;
2452 
2453  /* This algorithm comes from DDI0487A.g, chapter J9.1 */
2454 
2455  /* Set Normal access mode */
2456  dscr &= ~DSCR_MA;
2457  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2458  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
2459  if (retval != ERROR_OK)
2460  return retval;
2461 
2462  if (arm->core_state == ARM_STATE_AARCH64) {
2463  /* Write X0 with value 'address' using write procedure */
2464  /* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
2465  /* Step 1.c - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
2466  retval = dpm->instr_write_data_dcc_64(dpm,
2467  ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), address);
2468  } else {
2469  /* Write R0 with value 'address' using write procedure */
2470  /* Step 1.a+b - Write the address for read access into DBGDTRRXint */
2471  /* Step 1.c - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
2472  retval = dpm->instr_write_data_dcc(dpm,
2473  ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address);
2474  }
2475 
2476  if (retval != ERROR_OK)
2477  return retval;
2478 
2479  if (size == 4 && (address % 4) == 0)
2480  retval = aarch64_read_cpu_memory_fast(target, count, buffer, &dscr);
2481  else
2482  retval = aarch64_read_cpu_memory_slow(target, size, count, buffer, &dscr);
2483 
2484  if (dscr & DSCR_MA) {
2485  dscr &= ~DSCR_MA;
2486  mem_ap_write_atomic_u32(armv8->debug_ap,
2487  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
2488  }
2489 
2490  if (retval != ERROR_OK)
2491  return retval;
2492 
2493  /* Check for sticky abort flags in the DSCR */
2494  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2495  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2496  if (retval != ERROR_OK)
2497  return retval;
2498 
2499  dpm->dscr = dscr;
2500 
2501  if (dscr & (DSCR_ERR | DSCR_SYS_ERROR_PEND)) {
2502  /* Abort occurred - clear it and exit */
2503  LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr);
2504  armv8_dpm_handle_exception(dpm, true);
2505  return ERROR_FAIL;
2506  }
2507 
2508  /* Done */
2509  return ERROR_OK;
2510 }
2511 
2512 static int aarch64_read_phys_memory(struct target *target,
2513  target_addr_t address, uint32_t size,
2514  uint32_t count, uint8_t *buffer)
2515 {
2516  int retval = ERROR_COMMAND_SYNTAX_ERROR;
2517 
2518  if (count && buffer) {
2519  /* read memory through APB-AP */
2520  retval = aarch64_mmu_modify(target, 0);
2521  if (retval != ERROR_OK)
2522  return retval;
2523  retval = aarch64_read_cpu_memory(target, address, size, count, buffer);
2524  }
2525  return retval;
2526 }
2527 
2528 static int aarch64_read_memory(struct target *target, target_addr_t address,
2529  uint32_t size, uint32_t count, uint8_t *buffer)
2530 {
2531  bool mmu_enabled = false;
2532  int retval;
2533 
2534  /* determine if MMU was enabled on target stop */
2535  retval = aarch64_mmu(target, &mmu_enabled);
2536  if (retval != ERROR_OK)
2537  return retval;
2538 
2539  if (mmu_enabled) {
2540  /* enable MMU as we could have disabled it for phys access */
2541  retval = aarch64_mmu_modify(target, 1);
2542  if (retval != ERROR_OK)
2543  return retval;
2544  }
2545  return aarch64_read_cpu_memory(target, address, size, count, buffer);
2546 }
2547 
2548 static int aarch64_write_phys_memory(struct target *target,
2549  target_addr_t address, uint32_t size,
2550  uint32_t count, const uint8_t *buffer)
2551 {
2552  int retval = ERROR_COMMAND_SYNTAX_ERROR;
2553 
2554  if (count && buffer) {
2555  /* write memory through APB-AP */
2556  retval = aarch64_mmu_modify(target, 0);
2557  if (retval != ERROR_OK)
2558  return retval;
2559  return aarch64_write_cpu_memory(target, address, size, count, buffer);
2560  }
2561 
2562  return retval;
2563 }
2564 
2565 static int aarch64_write_memory(struct target *target, target_addr_t address,
2566  uint32_t size, uint32_t count, const uint8_t *buffer)
2567 {
2568  bool mmu_enabled = false;
2569  int retval;
2570 
2571  /* determine if MMU was enabled on target stop */
2572  retval = aarch64_mmu(target, &mmu_enabled);
2573  if (retval != ERROR_OK)
2574  return retval;
2575 
2576  if (mmu_enabled) {
2577  /* enable MMU as we could have disabled it for phys access */
2578  retval = aarch64_mmu_modify(target, 1);
2579  if (retval != ERROR_OK)
2580  return retval;
2581  }
2582  return aarch64_write_cpu_memory(target, address, size, count, buffer);
2583 }
2584 
2585 static int aarch64_handle_target_request(void *priv)
2586 {
2587  struct target *target = priv;
2588  struct armv8_common *armv8 = target_to_armv8(target);
2589  int retval;
2590 
2591  if (!target_was_examined(target))
2592  return ERROR_OK;
2593  if (!target->dbg_msg_enabled)
2594  return ERROR_OK;
2595 
2596  if (target->state == TARGET_RUNNING) {
2597  uint32_t request;
2598  uint32_t dscr;
2599  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2600  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2601 
2602  /* check if we have data */
2603  while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
2604  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2605  armv8->debug_base + CPUV8_DBG_DTRTX, &request);
2606  if (retval == ERROR_OK) {
2607  target_request(target, request);
2608  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2609  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2610  }
2611  }
2612  }
2613 
2614  return ERROR_OK;
2615 }
2616 
2617 static int aarch64_examine_first(struct target *target)
2618 {
2619  struct aarch64_common *aarch64 = target_to_aarch64(target);
2620  struct armv8_common *armv8 = &aarch64->armv8_common;
2621  struct adiv5_dap *swjdp = armv8->arm.dap;
2622  struct aarch64_private_config *pc = target->private_config;
2623  int i;
2624  int retval = ERROR_OK;
2625  uint64_t debug, ttypr;
2626  uint32_t cpuid;
2627  uint32_t tmp0, tmp1, tmp2, tmp3;
2628  debug = ttypr = cpuid = 0;
2629 
2630  if (!pc)
2631  return ERROR_FAIL;
2632 
2633  if (!armv8->debug_ap) {
2634  if (pc->adiv5_config.ap_num == DP_APSEL_INVALID) {
2635  /* Search for the APB-AB */
2636  retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv8->debug_ap);
2637  if (retval != ERROR_OK) {
2638  LOG_ERROR("Could not find APB-AP for debug access");
2639  return retval;
2640  }
2641  } else {
2642  armv8->debug_ap = dap_get_ap(swjdp, pc->adiv5_config.ap_num);
2643  if (!armv8->debug_ap) {
2644  LOG_ERROR("Cannot get AP");
2645  return ERROR_FAIL;
2646  }
2647  }
2648  }
2649 
2650  retval = mem_ap_init(armv8->debug_ap);
2651  if (retval != ERROR_OK) {
2652  LOG_ERROR("Could not initialize the APB-AP");
2653  return retval;
2654  }
2655 
2656  armv8->debug_ap->memaccess_tck = 10;
2657 
2658  if (!target->dbgbase_set) {
2659  /* Lookup Processor DAP */
2660  retval = dap_lookup_cs_component(armv8->debug_ap, ARM_CS_C9_DEVTYPE_CORE_DEBUG,
2661  &armv8->debug_base, target->coreid);
2662  if (retval != ERROR_OK)
2663  return retval;
2664  LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT,
2665  target->coreid, armv8->debug_base);
2666  } else
2667  armv8->debug_base = target->dbgbase;
2668 
2669  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2670  armv8->debug_base + CPUV8_DBG_OSLAR, 0);
2671  if (retval != ERROR_OK) {
2672  LOG_DEBUG("Examine %s failed", "oslock");
2673  return retval;
2674  }
2675 
2676  retval = mem_ap_read_u32(armv8->debug_ap,
2677  armv8->debug_base + CPUV8_DBG_MAINID0, &cpuid);
2678  if (retval != ERROR_OK) {
2679  LOG_DEBUG("Examine %s failed", "CPUID");
2680  return retval;
2681  }
2682 
2683  retval = mem_ap_read_u32(armv8->debug_ap,
2684  armv8->debug_base + CPUV8_DBG_MEMFEATURE0, &tmp0);
2685  retval += mem_ap_read_u32(armv8->debug_ap,
2686  armv8->debug_base + CPUV8_DBG_MEMFEATURE0 + 4, &tmp1);
2687  if (retval != ERROR_OK) {
2688  LOG_DEBUG("Examine %s failed", "Memory Model Type");
2689  return retval;
2690  }
2691  retval = mem_ap_read_u32(armv8->debug_ap,
2692  armv8->debug_base + CPUV8_DBG_DBGFEATURE0, &tmp2);
2693  retval += mem_ap_read_u32(armv8->debug_ap,
2694  armv8->debug_base + CPUV8_DBG_DBGFEATURE0 + 4, &tmp3);
2695  if (retval != ERROR_OK) {
2696  LOG_DEBUG("Examine %s failed", "ID_AA64DFR0_EL1");
2697  return retval;
2698  }
2699 
2700  retval = dap_run(armv8->debug_ap->dap);
2701  if (retval != ERROR_OK) {
2702  LOG_ERROR("%s: examination failed\n", target_name(target));
2703  return retval;
2704  }
2705 
2706  ttypr |= tmp1;
2707  ttypr = (ttypr << 32) | tmp0;
2708  debug |= tmp3;
2709  debug = (debug << 32) | tmp2;
2710 
2711  LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
2712  LOG_DEBUG("ttypr = 0x%08" PRIx64, ttypr);
2713  LOG_DEBUG("debug = 0x%08" PRIx64, debug);
2714 
2715  if (!pc->cti) {
2716  LOG_TARGET_ERROR(target, "CTI not specified");
2717  return ERROR_FAIL;
2718  }
2719 
2720  armv8->cti = pc->cti;
2721 
2722  retval = aarch64_dpm_setup(aarch64, debug);
2723  if (retval != ERROR_OK)
2724  return retval;
2725 
2726  /* Setup Breakpoint Register Pairs */
2727  aarch64->brp_num = (uint32_t)((debug >> 12) & 0x0F) + 1;
2728  aarch64->brp_num_context = (uint32_t)((debug >> 28) & 0x0F) + 1;
2729  aarch64->brp_num_available = aarch64->brp_num;
2730  aarch64->brp_list = calloc(aarch64->brp_num, sizeof(struct aarch64_brp));
2731  for (i = 0; i < aarch64->brp_num; i++) {
2732  aarch64->brp_list[i].used = 0;
2733  if (i < (aarch64->brp_num-aarch64->brp_num_context))
2734  aarch64->brp_list[i].type = BRP_NORMAL;
2735  else
2736  aarch64->brp_list[i].type = BRP_CONTEXT;
2737  aarch64->brp_list[i].value = 0;
2738  aarch64->brp_list[i].control = 0;
2739  aarch64->brp_list[i].brpn = i;
2740  }
2741 
2742  /* Setup Watchpoint Register Pairs */
2743  aarch64->wp_num = (uint32_t)((debug >> 20) & 0x0F) + 1;
2744  aarch64->wp_num_available = aarch64->wp_num;
2745  aarch64->wp_list = calloc(aarch64->wp_num, sizeof(struct aarch64_brp));
2746  for (i = 0; i < aarch64->wp_num; i++) {
2747  aarch64->wp_list[i].used = 0;
2748  aarch64->wp_list[i].type = BRP_NORMAL;
2749  aarch64->wp_list[i].value = 0;
2750  aarch64->wp_list[i].control = 0;
2751  aarch64->wp_list[i].brpn = i;
2752  }
2753 
2754  LOG_DEBUG("Configured %i hw breakpoints, %i watchpoints",
2755  aarch64->brp_num, aarch64->wp_num);
2756 
2757  target->state = TARGET_UNKNOWN;
2758  target->debug_reason = DBG_REASON_NOTHALTED;
2759  aarch64->isrmasking_mode = AARCH64_ISRMASK_ON;
2760  target_set_examined(target);
2761  return ERROR_OK;
2762 }
2763 
2764 static int aarch64_examine(struct target *target)
2765 {
2766  int retval = ERROR_OK;
2767 
2768  /* don't re-probe hardware after each reset */
2769  if (!target_was_examined(target))
2770  retval = aarch64_examine_first(target);
2771 
2772  /* Configure core debug access */
2773  if (retval == ERROR_OK)
2774  retval = aarch64_init_debug_access(target);
2775 
2776  if (retval == ERROR_OK)
2777  retval = aarch64_poll(target);
2778 
2779  return retval;
2780 }
2781 
2782 /*
2783  * Cortex-A8 target creation and initialization
2784  */
2785 
2786 static int aarch64_init_target(struct command_context *cmd_ctx,
2787  struct target *target)
2788 {
2789  /* examine_first() does a bunch of this */
2790  arm_semihosting_init(target);
2791  return ERROR_OK;
2792 }
2793 
2794 static int aarch64_init_arch_info(struct target *target,
2795  struct aarch64_common *aarch64, struct adiv5_dap *dap)
2796 {
2797  struct armv8_common *armv8 = &aarch64->armv8_common;
2798 
2799  /* Setup struct aarch64_common */
2800  aarch64->common_magic = AARCH64_COMMON_MAGIC;
2801  armv8->arm.dap = dap;
2802 
2803  /* register arch-specific functions */
2804  armv8->examine_debug_reason = NULL;
2805  armv8->post_debug_entry = aarch64_post_debug_entry;
2806  armv8->pre_restore_context = NULL;
2807  armv8->armv8_mmu.read_physical_memory = aarch64_read_phys_memory;
2808 
2809  armv8_init_arch_info(target, armv8);
2810  target_register_timer_callback(aarch64_handle_target_request, 1,
2811  TARGET_TIMER_TYPE_PERIODIC, target);
2812 
2813  return ERROR_OK;
2814 }
2815 
2816 static int armv8r_target_create(struct target *target)
2817 {
2818  struct aarch64_private_config *pc = target->private_config;
2819  struct aarch64_common *aarch64;
2820 
2821  if (adiv5_verify_config(&pc->adiv5_config) != ERROR_OK)
2822  return ERROR_FAIL;
2823 
2824  aarch64 = calloc(1, sizeof(struct aarch64_common));
2825  if (!aarch64) {
2826  LOG_ERROR("Out of memory");
2827  return ERROR_FAIL;
2828  }
2829 
2830  aarch64->armv8_common.is_armv8r = true;
2831 
2832  return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap);
2833 }
2834 
2835 static int aarch64_target_create(struct target *target)
2836 {
2837  struct aarch64_private_config *pc = target->private_config;
2838  struct aarch64_common *aarch64;
2839 
2840  if (adiv5_verify_config(&pc->adiv5_config) != ERROR_OK)
2841  return ERROR_FAIL;
2842 
2843  aarch64 = calloc(1, sizeof(struct aarch64_common));
2844  if (!aarch64) {
2845  LOG_ERROR("Out of memory");
2846  return ERROR_FAIL;
2847  }
2848 
2849  aarch64->armv8_common.is_armv8r = false;
2850 
2851  return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap);
2852 }
2853 
2854 static void aarch64_deinit_target(struct target *target)
2855 {
2856  struct aarch64_common *aarch64 = target_to_aarch64(target);
2857  struct armv8_common *armv8 = &aarch64->armv8_common;
2858  struct arm_dpm *dpm = &armv8->dpm;
2859  uint64_t address;
2860 
2861  if (target->state == TARGET_HALTED) {
2862  // Restore the previous state of the target (gp registers, MMU, caches, etc)
2863  int retval = aarch64_restore_one(target, true, &address, false, false);
2864  if (retval != ERROR_OK)
2865  LOG_TARGET_ERROR(target, "Failed to restore target state");
2866  }
2867 
2868  if (armv8->debug_ap)
2869  dap_put_ap(armv8->debug_ap);
2870 
2871  armv8_free_reg_cache(target);
2872  free(aarch64->brp_list);
2873  free(dpm->dbp);
2874  free(dpm->dwp);
2875  free(target->private_config);
2876  free(aarch64);
2877 }
2878 
2879 static int aarch64_mmu(struct target *target, bool *enabled)
2880 {
2881  struct aarch64_common *aarch64 = target_to_aarch64(target);
2882  struct armv8_common *armv8 = &aarch64->armv8_common;
2883  if (target->state != TARGET_HALTED) {
2884  LOG_TARGET_ERROR(target, "not halted");
2885  return ERROR_TARGET_NOT_HALTED;
2886  }
2887  if (armv8->is_armv8r)
2888  *enabled = false;
2889  else
2890  *enabled = target_to_aarch64(target)->armv8_common.armv8_mmu.mmu_enabled;
2891  return ERROR_OK;
2892 }
2893 
2894 static int aarch64_virt2phys(struct target *target, target_addr_t virt,
2895  target_addr_t *phys)
2896 {
2897  return armv8_mmu_translate_va_pa(target, virt, phys, 1);
2898 }
2899 
2900 /*
2901  * private target configuration items
2902  */
2903 enum aarch64_cfg_param {
2904  CFG_CTI,
2905 };
2906 
2907 static const struct jim_nvp nvp_config_opts[] = {
2908  { .name = "-cti", .value = CFG_CTI },
2909  { .name = NULL, .value = -1 }
2910 };
2911 
2912 static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *goi)
2913 {
2914  struct aarch64_private_config *pc;
2915  struct jim_nvp *n;
2916  int e;
2917 
2918  pc = (struct aarch64_private_config *)target->private_config;
2919  if (!pc) {
2920  pc = calloc(1, sizeof(struct aarch64_private_config));
2921  pc->adiv5_config.ap_num = DP_APSEL_INVALID;
2922  target->private_config = pc;
2923  }
2924 
2925  /*
2926  * Call adiv5_jim_configure() to parse the common DAP options
2927  * It will return JIM_CONTINUE if it didn't find any known
2928  * options, JIM_OK if it correctly parsed the topmost option
2929  * and JIM_ERR if an error occurred during parameter evaluation.
2930  * For JIM_CONTINUE, we check our own params.
2931  */
2932  e = adiv5_jim_configure_ext(target, goi, &pc->adiv5_config, ADI_CONFIGURE_DAP_COMPULSORY);
2933  if (e != JIM_CONTINUE)
2934  return e;
2935 
2936  /* parse config or cget options ... */
2937  if (goi->argc > 0) {
2938  Jim_SetEmptyResult(goi->interp);
2939 
2940  /* check first if topmost item is for us */
2941  e = jim_nvp_name2value_obj(goi->interp, nvp_config_opts,
2942  goi->argv[0], &n);
2943  if (e != JIM_OK)
2944  return JIM_CONTINUE;
2945 
2946  e = jim_getopt_obj(goi, NULL);
2947  if (e != JIM_OK)
2948  return e;
2949 
2950  switch (n->value) {
2951  case CFG_CTI: {
2952  if (goi->is_configure) {
2953  Jim_Obj *o_cti;
2954  struct arm_cti *cti;
2955  e = jim_getopt_obj(goi, &o_cti);
2956  if (e != JIM_OK)
2957  return e;
2958  cti = cti_instance_by_jim_obj(goi->interp, o_cti);
2959  if (!cti) {
2960  Jim_SetResultString(goi->interp, "CTI name invalid!", -1);
2961  return JIM_ERR;
2962  }
2963  pc->cti = cti;
2964  } else {
2965  if (goi->argc != 0) {
2966  Jim_WrongNumArgs(goi->interp,
2967  goi->argc, goi->argv,
2968  "NO PARAMS");
2969  return JIM_ERR;
2970  }
2971 
2972  if (!pc || !pc->cti) {
2973  Jim_SetResultString(goi->interp, "CTI not configured", -1);
2974  return JIM_ERR;
2975  }
2976  Jim_SetResultString(goi->interp, arm_cti_name(pc->cti), -1);
2977  }
2978  break;
2979  }
2980 
2981  default:
2982  return JIM_CONTINUE;
2983  }
2984  }
2985 
2986  return JIM_OK;
2987 }
2988 
2989 COMMAND_HANDLER(aarch64_handle_cache_info_command)
2990 {
2991  struct target *target = get_current_target(CMD_CTX);
2992  struct armv8_common *armv8 = target_to_armv8(target);
2993 
2994  return armv8_handle_cache_info_command(CMD,
2995  &armv8->armv8_mmu.armv8_cache);
2996 }
2997 
2998 COMMAND_HANDLER(aarch64_handle_dbginit_command)
2999 {
3000  struct target *target = get_current_target(CMD_CTX);
3001  if (!target_was_examined(target)) {
3002  LOG_ERROR("target not examined yet");
3003  return ERROR_FAIL;
3004  }
3005 
3006  return aarch64_init_debug_access(target);
3007 }
3008 
3009 COMMAND_HANDLER(aarch64_handle_disassemble_command)
3010 {
3011  struct target *target = get_current_target(CMD_CTX);
3012 
3013  if (!target) {
3014  LOG_ERROR("No target selected");
3015  return ERROR_FAIL;
3016  }
3017 
3018  struct aarch64_common *aarch64 = target_to_aarch64(target);
3019 
3020  if (aarch64->common_magic != AARCH64_COMMON_MAGIC) {
3021  command_print(CMD, "current target isn't an AArch64");
3022  return ERROR_FAIL;
3023  }
3024 
3025  int count = 1;
3026  target_addr_t address;
3027 
3028  switch (CMD_ARGC) {
3029  case 2:
3030  COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
3031  /* FALL THROUGH */
3032  case 1:
3033  COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
3034  break;
3035  default:
3036  return ERROR_COMMAND_SYNTAX_ERROR;
3037  }
3038 
3039  return a64_disassemble(CMD, target, address, count);
3040 }
3041 
3042 COMMAND_HANDLER(aarch64_mask_interrupts_command)
3043 {
3044  struct target *target = get_current_target(CMD_CTX);
3045  struct aarch64_common *aarch64 = target_to_aarch64(target);
3046 
3047  static const struct nvp nvp_maskisr_modes[] = {
3048  { .name = "off", .value = AARCH64_ISRMASK_OFF },
3049  { .name = "on", .value = AARCH64_ISRMASK_ON },
3050  { .name = NULL, .value = -1 },
3051  };
3052  const struct nvp *n;
3053 
3054  if (CMD_ARGC > 0) {
3055  n = nvp_name2value(nvp_maskisr_modes, CMD_ARGV[0]);
3056  if (!n->name) {
3057  LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV[0]);
3058  return ERROR_COMMAND_SYNTAX_ERROR;
3059  }
3060 
3061  aarch64->isrmasking_mode = n->value;
3062  }
3063 
3064  n = nvp_value2name(nvp_maskisr_modes, aarch64->isrmasking_mode);
3065  command_print(CMD, "aarch64 interrupt mask %s", n->name);
3066 
3067  return ERROR_OK;
3068 }
3069 
3070 COMMAND_HANDLER(aarch64_mcrmrc_command)
3071 {
3072  bool is_mcr = false;
3073  unsigned int arg_cnt = 5;
3074 
3075  if (!strcmp(CMD_NAME, "mcr")) {
3076  is_mcr = true;
3077  arg_cnt = 6;
3078  }
3079 
3080  if (arg_cnt != CMD_ARGC)
3081  return ERROR_COMMAND_SYNTAX_ERROR;
3082 
3083  struct target *target = get_current_target(CMD_CTX);
3084  if (!target) {
3085  command_print(CMD, "no current target");
3086  return ERROR_FAIL;
3087  }
3088  if (!target_was_examined(target)) {
3089  command_print(CMD, "%s: not yet examined", target_name(target));
3090  return ERROR_TARGET_NOT_EXAMINED;
3091  }
3092 
3093  struct arm *arm = target_to_arm(target);
3094  if (!is_arm(arm)) {
3095  command_print(CMD, "%s: not an ARM", target_name(target));
3096  return ERROR_FAIL;
3097  }
3098 
3099  if (target->state != TARGET_HALTED) {
3100  command_print(CMD, "Error: [%s] not halted", target_name(target));
3101  return ERROR_TARGET_NOT_HALTED;
3102  }
3103 
3104  if (arm->core_state == ARM_STATE_AARCH64) {
3105  command_print(CMD, "%s: not 32-bit arm target", target_name(target));
3106  return ERROR_FAIL;
3107  }
3108 
3109  int cpnum;
3110  uint32_t op1;
3111  uint32_t op2;
3112  uint32_t crn;
3113  uint32_t crm;
3114  uint32_t value;
3115 
3116  /* NOTE: parameter sequence matches ARM instruction set usage:
3117  * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
3118  * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
3119  * The "rX" is necessarily omitted; it uses Tcl mechanisms.
3120  */
3121  COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cpnum);
3122  if (cpnum & ~0xf) {
3123  command_print(CMD, "coprocessor %d out of range", cpnum);
3124  return ERROR_COMMAND_ARGUMENT_INVALID;
3125  }
3126 
3127  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], op1);
3128  if (op1 & ~0x7) {
3129  command_print(CMD, "op1 %d out of range", op1);
3130  return ERROR_COMMAND_ARGUMENT_INVALID;
3131  }
3132 
3133  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], crn);
3134  if (crn & ~0xf) {
3135  command_print(CMD, "CRn %d out of range", crn);
3136  return ERROR_COMMAND_ARGUMENT_INVALID;
3137  }
3138 
3139  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], crm);
3140  if (crm & ~0xf) {
3141  command_print(CMD, "CRm %d out of range", crm);
3142  return ERROR_COMMAND_ARGUMENT_INVALID;
3143  }
3144 
3145  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], op2);
3146  if (op2 & ~0x7) {
3147  command_print(CMD, "op2 %d out of range", op2);
3148  return ERROR_COMMAND_ARGUMENT_INVALID;
3149  }
3150 
3151  if (is_mcr) {
3152  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[5], value);
3153 
3154  /* NOTE: parameters reordered! */
3155  /* ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2) */
3156  int retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value);
3157  if (retval != ERROR_OK)
3158  return retval;
3159  } else {
3160  value = 0;
3161  /* NOTE: parameters reordered! */
3162  /* ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2) */
3163  int retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value);
3164  if (retval != ERROR_OK)
3165  return retval;
3166 
3167  command_print(CMD, "0x%" PRIx32, value);
3168  }
3169 
3170  return ERROR_OK;
3171 }
3172 
3173 static const struct command_registration aarch64_exec_command_handlers[] = {
3174  {
3175  .name = "cache_info",
3176  .handler = aarch64_handle_cache_info_command,
3177  .mode = COMMAND_EXEC,
3178  .help = "display information about target caches",
3179  .usage = "",
3180  },
3181  {
3182  .name = "dbginit",
3183  .handler = aarch64_handle_dbginit_command,
3184  .mode = COMMAND_EXEC,
3185  .help = "Initialize core debug",
3186  .usage = "",
3187  },
3188  {
3189  .name = "disassemble",
3190  .handler = aarch64_handle_disassemble_command,
3191  .mode = COMMAND_EXEC,
3192  .help = "Disassemble instructions",
3193  .usage = "address [count]",
3194  },
3195  {
3196  .name = "maskisr",
3197  .handler = aarch64_mask_interrupts_command,
3198  .mode = COMMAND_ANY,
3199  .help = "mask aarch64 interrupts during single-step",
3200  .usage = "['on'|'off']",
3201  },
3202  {
3203  .name = "mcr",
3204  .mode = COMMAND_EXEC,
3205  .handler = aarch64_mcrmrc_command,
3206  .help = "write coprocessor register",
3207  .usage = "cpnum op1 CRn CRm op2 value",
3208  },
3209  {
3210  .name = "mrc",
3211  .mode = COMMAND_EXEC,
3212  .handler = aarch64_mcrmrc_command,
3213  .help = "read coprocessor register",
3214  .usage = "cpnum op1 CRn CRm op2",
3215  },
3216  {
3217  .chain = smp_command_handlers,
3218  },
3219 
3220 
3221  COMMAND_REGISTRATION_DONE
3222 };
3223 
3224 static const struct command_registration aarch64_command_handlers[] = {
3225  {
3226  .name = "arm",
3227  .mode = COMMAND_ANY,
3228  .help = "ARM Command Group",
3229  .usage = "",
3230  .chain = semihosting_common_handlers
3231  },
3232  {
3233  .chain = armv8_command_handlers,
3234  },
3235  {
3236  .name = "aarch64",
3237  .mode = COMMAND_ANY,
3238  .help = "Aarch64 command group",
3239  .usage = "",
3240  .chain = aarch64_exec_command_handlers,
3241  },
3242  COMMAND_REGISTRATION_DONE
3243 };
3244 
3245 struct target_type aarch64_target = {
3246  .name = "aarch64",
3247 
3248  .poll = aarch64_poll,
3249  .arch_state = armv8_arch_state,
3250 
3251  .halt = aarch64_halt,
3252  .resume = aarch64_resume,
3253  .step = aarch64_step,
3254 
3255  .assert_reset = aarch64_assert_reset,
3256  .deassert_reset = aarch64_deassert_reset,
3257 
3258  /* REVISIT allow exporting VFP3 registers ... */
3259  .get_gdb_arch = armv8_get_gdb_arch,
3260  .get_gdb_reg_list = armv8_get_gdb_reg_list,
3261 
3262  .read_memory = aarch64_read_memory,
3263  .write_memory = aarch64_write_memory,
3264 
3265  .add_breakpoint = aarch64_add_breakpoint,
3266  .add_context_breakpoint = aarch64_add_context_breakpoint,
3267  .add_hybrid_breakpoint = aarch64_add_hybrid_breakpoint,
3268  .remove_breakpoint = aarch64_remove_breakpoint,
3269  .add_watchpoint = aarch64_add_watchpoint,
3270  .remove_watchpoint = aarch64_remove_watchpoint,
3271  .hit_watchpoint = aarch64_hit_watchpoint,
3272 
3273  .commands = aarch64_command_handlers,
3274  .target_create = aarch64_target_create,
3275  .target_jim_configure = aarch64_jim_configure,
3276  .init_target = aarch64_init_target,
3277  .deinit_target = aarch64_deinit_target,
3278  .examine = aarch64_examine,
3279 
3280  .read_phys_memory = aarch64_read_phys_memory,
3281  .write_phys_memory = aarch64_write_phys_memory,
3282  .mmu = aarch64_mmu,
3283  .virt2phys = aarch64_virt2phys,
3284 };
3285 
3286 struct target_type armv8r_target = {
3287  .name = "armv8r",
3288 
3289  .poll = aarch64_poll,
3290  .arch_state = armv8_arch_state,
3291 
3292  .halt = aarch64_halt,
3293  .resume = aarch64_resume,
3294  .step = aarch64_step,
3295 
3296  .assert_reset = aarch64_assert_reset,
3297  .deassert_reset = aarch64_deassert_reset,
3298 
3299  /* REVISIT allow exporting VFP3 registers ... */
3300  .get_gdb_arch = armv8_get_gdb_arch,
3301  .get_gdb_reg_list = armv8_get_gdb_reg_list,
3302 
3303  .read_memory = aarch64_read_phys_memory,
3304  .write_memory = aarch64_write_phys_memory,
3305 
3306  .add_breakpoint = aarch64_add_breakpoint,
3307  .add_context_breakpoint = aarch64_add_context_breakpoint,
3308  .add_hybrid_breakpoint = aarch64_add_hybrid_breakpoint,
3309  .remove_breakpoint = aarch64_remove_breakpoint,
3310  .add_watchpoint = aarch64_add_watchpoint,
3311  .remove_watchpoint = aarch64_remove_watchpoint,
3312  .hit_watchpoint = aarch64_hit_watchpoint,
3313 
3314  .commands = aarch64_command_handlers,
3315  .target_create = armv8r_target_create,
3316  .target_jim_configure = aarch64_jim_configure,
3317  .init_target = aarch64_init_target,
3318  .deinit_target = aarch64_deinit_target,
3319  .examine = aarch64_examine,
3320 };
a64_disassemble
int a64_disassemble(struct command_invocation *cmd, struct target *target, target_addr_t address, size_t count)
Definition: a64_disassembler.c:127
a64_disassembler.h
aarch64_write_cpu_memory_slow
static int aarch64_write_cpu_memory_slow(struct target *target, uint32_t size, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
Definition: aarch64.c:2071
aarch64_set_breakpoint
static int aarch64_set_breakpoint(struct target *target, struct breakpoint *breakpoint, uint8_t matchmode)
Definition: aarch64.c:1257
aarch64_unset_watchpoint
static int aarch64_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: aarch64.c:1802
aarch64_add_watchpoint
static int aarch64_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: aarch64.c:1846
COMMAND_HANDLER
COMMAND_HANDLER(aarch64_handle_cache_info_command)
Definition: aarch64.c:2989
aarch64_set_dscr_bits
static int aarch64_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
Definition: aarch64.c:288
aarch64_assert_reset
static int aarch64_assert_reset(struct target *target)
Definition: aarch64.c:1960
halt_mode
halt_mode
Definition: aarch64.c:32
HALT_SYNC
@ HALT_SYNC
Definition: aarch64.c:34
HALT_LAZY
@ HALT_LAZY
Definition: aarch64.c:33
aarch64_deinit_target
static void aarch64_deinit_target(struct target *target)
Definition: aarch64.c:2854
aarch64_add_context_breakpoint
static int aarch64_add_context_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1664
aarch64_write_phys_memory
static int aarch64_write_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: aarch64.c:2548
nvp_config_opts
static const struct jim_nvp nvp_config_opts[]
Definition: aarch64.c:2907
aarch64_examine
static int aarch64_examine(struct target *target)
Definition: aarch64.c:2764
aarch64_exec_command_handlers
static const struct command_registration aarch64_exec_command_handlers[]
Definition: aarch64.c:3173
aarch64_add_breakpoint
static int aarch64_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1648
aarch64_read_prsr
static int aarch64_read_prsr(struct target *target, uint32_t *prsr)
Definition: aarch64.c:196
aarch64_set_context_breakpoint
static int aarch64_set_context_breakpoint(struct target *target, struct breakpoint *breakpoint, uint8_t matchmode)
Definition: aarch64.c:1378
aarch64_mmu_modify
static int aarch64_mmu_modify(struct target *target, int enable)
Definition: aarch64.c:123
aarch64_read_cpu_memory_fast
static int aarch64_read_cpu_memory_fast(struct target *target, uint32_t count, uint8_t *buffer, uint32_t *dscr)
Definition: aarch64.c:2352
aarch64_examine_first
static int aarch64_examine_first(struct target *target)
Definition: aarch64.c:2617
aarch64_poll
static int aarch64_poll(struct target *target)
Definition: aarch64.c:518
aarch64_init_target
static int aarch64_init_target(struct command_context *cmd_ctx, struct target *target)
Definition: aarch64.c:2786
aarch64_read_cpu_memory
static int aarch64_read_cpu_memory(struct target *target, uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: aarch64.c:2421
armv8r_target_create
static int armv8r_target_create(struct target *target)
Definition: aarch64.c:2816
aarch64_prepare_restart_one
static int aarch64_prepare_restart_one(struct target *target)
prepare single target for restart
Definition: aarch64.c:652
aarch64_step
static int aarch64_step(struct target *target, bool current, target_addr_t address, bool handle_breakpoints)
Definition: aarch64.c:1117
aarch64_restore_context
static int aarch64_restore_context(struct target *target, bool bpwp)
Definition: aarch64.c:1230
aarch64_enable_reset_catch
static int aarch64_enable_reset_catch(struct target *target, bool enable)
Definition: aarch64.c:1910
aarch64_jim_configure
static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *goi)
Definition: aarch64.c:2912
aarch64_mmu
static int aarch64_mmu(struct target *target, bool *enabled)
Definition: aarch64.c:2879
aarch64_halt
static int aarch64_halt(struct target *target)
Definition: aarch64.c:581
aarch64_restore_one
static int aarch64_restore_one(struct target *target, bool current, uint64_t *address, bool handle_breakpoints, bool debug_execution)
Definition: aarch64.c:592
update_halt_gdb
static int update_halt_gdb(struct target *target, enum target_debug_reason debug_reason)
Definition: aarch64.c:472
aarch64_read_phys_memory
static int aarch64_read_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: aarch64.c:2512
aarch64_check_state_one
static int aarch64_check_state_one(struct target *target, uint32_t mask, uint32_t val, int *p_result, uint32_t *p_prsr)
Definition: aarch64.c:294
aarch64_restore_system_control_reg
static int aarch64_restore_system_control_reg(struct target *target)
Definition: aarch64.c:59
aarch64_write_cpu_memory_fast
static int aarch64_write_cpu_memory_fast(struct target *target, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
Definition: aarch64.c:2148
aarch64_set_watchpoint
static int aarch64_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: aarch64.c:1718
aarch64_remove_watchpoint
static int aarch64_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: aarch64.c:1864
aarch64_restart_one
static int aarch64_restart_one(struct target *target, enum restart_mode mode)
Definition: aarch64.c:740
aarch64_step_restart_smp
static int aarch64_step_restart_smp(struct target *target)
Definition: aarch64.c:796
aarch64_dap_write_memap_register_u32
static int aarch64_dap_write_memap_register_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: aarch64.c:261
aarch64_debug_entry
static int aarch64_debug_entry(struct target *target)
Definition: aarch64.c:974
aarch64_prep_restart_smp
static int aarch64_prep_restart_smp(struct target *target, bool handle_breakpoints, struct target **p_first)
Definition: aarch64.c:756
aarch64_prepare_halt_smp
static int aarch64_prepare_halt_smp(struct target *target, bool exc_target, struct target **p_first)
Definition: aarch64.c:335
aarch64_target
struct target_type aarch64_target
Definition: aarch64.c:3245
aarch64_command_handlers
static const struct command_registration aarch64_command_handlers[]
Definition: aarch64.c:3224
aarch64_write_cpu_memory
static int aarch64_write_cpu_memory(struct target *target, uint64_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: aarch64.c:2181
aarch64_unset_breakpoint
static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1515
aarch64_virt2phys
static int aarch64_virt2phys(struct target *target, target_addr_t virt, target_addr_t *phys)
Definition: aarch64.c:2894
aarch64_handle_target_request
static int aarch64_handle_target_request(void *priv)
Definition: aarch64.c:2585
aarch64_clear_reset_catch
static int aarch64_clear_reset_catch(struct target *target)
Definition: aarch64.c:1931
aarch64_halt_one
static int aarch64_halt_one(struct target *target, enum halt_mode mode)
Definition: aarch64.c:380
aarch64_hit_watchpoint
static int aarch64_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
find out which watchpoint hits get exception address and compare the address to watchpoints
Definition: aarch64.c:1881
aarch64_cfg_param
aarch64_cfg_param
Definition: aarch64.c:2903
CFG_CTI
@ CFG_CTI
Definition: aarch64.c:2904
aarch64_deassert_reset
static int aarch64_deassert_reset(struct target *target)
Definition: aarch64.c:2022
aarch64_write_memory
static int aarch64_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: aarch64.c:2565
armv8r_target
struct target_type armv8r_target
Definition: aarch64.c:3286
aarch64_do_restart_one
static int aarch64_do_restart_one(struct target *target, enum restart_mode mode)
Definition: aarch64.c:698
aarch64_target_create
static int aarch64_target_create(struct target *target)
Definition: aarch64.c:2835
aarch64_dpm_setup
static int aarch64_dpm_setup(struct aarch64_common *a8, uint64_t debug)
Definition: aarch64.c:273
aarch64_add_hybrid_breakpoint
static int aarch64_add_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1680
aarch64_wait_halt_one
static int aarch64_wait_halt_one(struct target *target)
Definition: aarch64.c:313
aarch64_read_cpu_memory_slow
static int aarch64_read_cpu_memory_slow(struct target *target, uint32_t size, uint32_t count, uint8_t *buffer, uint32_t *dscr)
Definition: aarch64.c:2268
aarch64_init_arch_info
static int aarch64_init_arch_info(struct target *target, struct aarch64_common *aarch64, struct adiv5_dap *dap)
Definition: aarch64.c:2794
aarch64_remove_breakpoint
static int aarch64_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1696
aarch64_resume
static int aarch64_resume(struct target *target, bool current, target_addr_t address, bool handle_breakpoints, bool debug_execution)
Definition: aarch64.c:869
aarch64_set_hybrid_breakpoint
static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1428
aarch64_read_memory
static int aarch64_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: aarch64.c:2528
restart_mode
restart_mode
Definition: aarch64.c:27
RESTART_SYNC
@ RESTART_SYNC
Definition: aarch64.c:29
RESTART_LAZY
@ RESTART_LAZY
Definition: aarch64.c:28
aarch64_halt_smp
static int aarch64_halt_smp(struct target *target, bool exc_target)
Definition: aarch64.c:409
aarch64_post_debug_entry
static int aarch64_post_debug_entry(struct target *target)
Definition: aarch64.c:1043
aarch64_init_debug_access
static int aarch64_init_debug_access(struct target *target)
Definition: aarch64.c:213
target_to_aarch64
static struct aarch64_common * target_to_aarch64(struct target *target)
Definition: aarch64.h:64
BRP_CONTEXT
#define BRP_CONTEXT
Definition: aarch64.h:23
AARCH64_ISRMASK_ON
@ AARCH64_ISRMASK_ON
Definition: aarch64.h:29
AARCH64_ISRMASK_OFF
@ AARCH64_ISRMASK_OFF
Definition: aarch64.h:28
BRP_NORMAL
#define BRP_NORMAL
Definition: aarch64.h:22
AARCH64_COMMON_MAGIC
#define AARCH64_COMMON_MAGIC
Definition: aarch64.h:12
armv8_get_gdb_arch
const char * armv8_get_gdb_arch(const struct target *target)
Definition: armv8.c:1981
armv8_reg_current
struct reg * armv8_reg_current(struct arm *arm, unsigned int regnum)
Definition: armv8.c:1913
armv8_get_gdb_reg_list
int armv8_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: armv8.c:1987
is_arm
static bool is_arm(struct arm *arm)
Definition: arm.h:267
arm_mode
arm_mode
Represent state of an ARM core.
Definition: arm.h:82
ARM_MODE_IRQ
@ ARM_MODE_IRQ
Definition: arm.h:85
ARM_MODE_SYS
@ ARM_MODE_SYS
Definition: arm.h:92
ARM_MODE_HYP
@ ARM_MODE_HYP
Definition: arm.h:89
ARMV8_64_EL0T
@ ARMV8_64_EL0T
Definition: arm.h:98
ARMV8_64_EL3H
@ ARMV8_64_EL3H
Definition: arm.h:104
ARM_MODE_MON
@ ARM_MODE_MON
Definition: arm.h:87
ARMV8_64_EL3T
@ ARMV8_64_EL3T
Definition: arm.h:103
ARM_MODE_FIQ
@ ARM_MODE_FIQ
Definition: arm.h:84
ARM_MODE_UND
@ ARM_MODE_UND
Definition: arm.h:90
ARM_MODE_ANY
@ ARM_MODE_ANY
Definition: arm.h:106
ARMV8_64_EL1H
@ ARMV8_64_EL1H
Definition: arm.h:100
ARM_MODE_SVC
@ ARM_MODE_SVC
Definition: arm.h:86
ARMV8_64_EL2H
@ ARMV8_64_EL2H
Definition: arm.h:102
ARMV8_64_EL2T
@ ARMV8_64_EL2T
Definition: arm.h:101
ARMV8_64_EL1T
@ ARMV8_64_EL1T
Definition: arm.h:99
ARM_MODE_ABT
@ ARM_MODE_ABT
Definition: arm.h:88
target_to_arm
static struct arm * target_to_arm(const struct target *target)
Convert target handle to generic ARM target state handle.
Definition: arm.h:261
arm_state
arm_state
The PSR "T" and "J" bits define the mode of "classic ARM" cores.
Definition: arm.h:150
ARM_STATE_JAZELLE
@ ARM_STATE_JAZELLE
Definition: arm.h:153
ARM_STATE_THUMB
@ ARM_STATE_THUMB
Definition: arm.h:152
ARM_STATE_ARM
@ ARM_STATE_ARM
Definition: arm.h:151
ARM_STATE_AARCH64
@ ARM_STATE_AARCH64
Definition: arm.h:155
ARM_STATE_THUMB_EE
@ ARM_STATE_THUMB_EE
Definition: arm.h:154
dap_lookup_cs_component
int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type, target_addr_t *addr, int32_t core_id)
Definition: arm_adi_v5.c:2295
mem_ap_read_buf_noincr
int mem_ap_read_buf_noincr(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:742
adiv5_verify_config
int adiv5_verify_config(struct adiv5_private_config *pc)
Definition: arm_adi_v5.c:2494
mem_ap_read_u32
int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Asynchronous (queued) read of a word from memory or a system register.
Definition: arm_adi_v5.c:245
dap_find_get_ap
int dap_find_get_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
Definition: arm_adi_v5.c:1115
mem_ap_write_buf_noincr
int mem_ap_write_buf_noincr(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:748
adiv5_jim_configure_ext
int adiv5_jim_configure_ext(struct target *target, struct jim_getopt_info *goi, struct adiv5_private_config *pc, enum adiv5_configure_dap_optional optional)
Definition: arm_adi_v5.c:2449
mem_ap_read_atomic_u32
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Synchronous read of a word from memory or a system register.
Definition: arm_adi_v5.c:274
dap_get_ap
struct adiv5_ap * dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1197
dap_put_ap
int dap_put_ap(struct adiv5_ap *ap)
Definition: arm_adi_v5.c:1217
mem_ap_init
int mem_ap_init(struct adiv5_ap *ap)
Initialize a DAP.
Definition: arm_adi_v5.c:896
mem_ap_write_atomic_u32
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Synchronous write of a word to memory or a system register.
Definition: arm_adi_v5.c:326
AP_TYPE_APB_AP
@ AP_TYPE_APB_AP
Definition: arm_adi_v5.h:491
ADI_CONFIGURE_DAP_COMPULSORY
@ ADI_CONFIGURE_DAP_COMPULSORY
Definition: arm_adi_v5.h:793
DP_APSEL_INVALID
#define DP_APSEL_INVALID
Definition: arm_adi_v5.h:110
dap_run
static int dap_run(struct adiv5_dap *dap)
Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they ar...
Definition: arm_adi_v5.h:648
arm_coresight.h
ARM_CS_C9_DEVTYPE_CORE_DEBUG
#define ARM_CS_C9_DEVTYPE_CORE_DEBUG
Definition: arm_coresight.h:88
arm_cti_ack_events
int arm_cti_ack_events(struct arm_cti *self, uint32_t event)
Definition: arm_cti.c:81
arm_cti_write_reg
int arm_cti_write_reg(struct arm_cti *self, unsigned int reg, uint32_t value)
Definition: arm_cti.c:123
arm_cti_gate_channel
int arm_cti_gate_channel(struct arm_cti *self, uint32_t channel)
Definition: arm_cti.c:107
arm_cti_pulse_channel
int arm_cti_pulse_channel(struct arm_cti *self, uint32_t channel)
Definition: arm_cti.c:136
arm_cti_enable
int arm_cti_enable(struct arm_cti *self, bool enable)
Definition: arm_cti.c:74
arm_cti_name
const char * arm_cti_name(struct arm_cti *self)
Definition: arm_cti.c:30
cti_instance_by_jim_obj
struct arm_cti * cti_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o)
Definition: arm_cti.c:35
arm_cti_ungate_channel
int arm_cti_ungate_channel(struct arm_cti *self, uint32_t channel)
Definition: arm_cti.c:115
CTI_CHNL
#define CTI_CHNL(x)
Definition: arm_cti.h:45
CTI_GATE
#define CTI_GATE
Definition: arm_cti.h:41
CTI_TRIG
#define CTI_TRIG(n)
Definition: arm_cti.h:48
CTI_OUTEN0
#define CTI_OUTEN0
Definition: arm_cti.h:27
CTI_OUTEN1
#define CTI_OUTEN1
Definition: arm_cti.h:28
DSCR_DTR_TX_FULL
#define DSCR_DTR_TX_FULL
Definition: arm_dpm.h:194
ARMV4_5_MRC
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:186
ARMV4_5_MCR
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:209
arm_semihosting
int arm_semihosting(struct target *target, int *retval)
Checks for and processes an ARM semihosting request.
Definition: arm_semihosting.c:172
arm_semihosting_init
int arm_semihosting_init(struct target *target)
Initialize ARM semihosting support.
Definition: arm_semihosting.c:150
arm_semihosting.h
mode
enum arm_mode mode
Definition: armv4_5.c:281
armv8_init_arch_info
int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
Definition: armv8.c:1321
armv8_set_dbgreg_bits
int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value)
Definition: armv8.c:2049
armv8_read_mpidr
int armv8_read_mpidr(struct armv8_common *armv8)
Definition: armv8.c:882
armv8_free_reg_cache
void armv8_free_reg_cache(struct target *target)
Definition: armv8.c:1945
armv8_arch_state
int armv8_arch_state(struct target *target)
Definition: armv8.c:1361
armv8_mmu_translate_va_pa
int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va, target_addr_t *val, int meminfo)
Definition: armv8.c:1138
armv8_command_handlers
const struct command_registration armv8_command_handlers[]
Definition: armv8.c:1959
armv8_select_reg_access
void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64)
Definition: armv8.c:865
armv8_mode_name
const char * armv8_mode_name(unsigned int psr_mode)
Map PSR mode bits to the name of an ARM processor operating mode.
Definition: armv8.c:109
armv8_handle_cache_info_command
int armv8_handle_cache_info_command(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache)
Definition: armv8.c:1303
armv8_identify_cache
int armv8_identify_cache(struct armv8_common *armv8)
Definition: armv8_cache.c:354
CPUV8_DBG_DRCR
#define CPUV8_DBG_DRCR
Definition: armv8.h:258
target_to_armv8
static struct armv8_common * target_to_armv8(struct target *target)
Definition: armv8.h:234
CPUV8_DBG_BVR_BASE
#define CPUV8_DBG_BVR_BASE
Definition: armv8.h:268
CPUV8_DBG_OSLAR
#define CPUV8_DBG_OSLAR
Definition: armv8.h:274
CPUV8_DBG_EDWAR0
#define CPUV8_DBG_EDWAR0
Definition: armv8.h:255
ARMV8_RUNCONTROL_HALT
@ ARMV8_RUNCONTROL_HALT
Definition: armv8.h:111
ARMV8_RUNCONTROL_RESUME
@ ARMV8_RUNCONTROL_RESUME
Definition: armv8.h:110
ARMV8_RUNCONTROL_STEP
@ ARMV8_RUNCONTROL_STEP
Definition: armv8.h:112
CPUV8_DBG_MAINID0
#define CPUV8_DBG_MAINID0
Definition: armv8.h:245
CPUV8_DBG_MEMFEATURE0
#define CPUV8_DBG_MEMFEATURE0
Definition: armv8.h:248
CPUV8_DBG_DSCR
#define CPUV8_DBG_DSCR
Definition: armv8.h:257
CPUV8_DBG_DTRTX
#define CPUV8_DBG_DTRTX
Definition: armv8.h:266
CPUV8_DBG_EDWAR1
#define CPUV8_DBG_EDWAR1
Definition: armv8.h:256
CPUV8_DBG_EDESR
#define CPUV8_DBG_EDESR
Definition: armv8.h:253
CPUV8_DBG_PRSR
#define CPUV8_DBG_PRSR
Definition: armv8.h:261
CPUV8_DBG_DBGFEATURE0
#define CPUV8_DBG_DBGFEATURE0
Definition: armv8.h:247
CPUV8_DBG_WVR_BASE
#define CPUV8_DBG_WVR_BASE
Definition: armv8.h:270
CPUV8_DBG_WCR_BASE
#define CPUV8_DBG_WCR_BASE
Definition: armv8.h:271
CPUV8_DBG_EDECR
#define CPUV8_DBG_EDECR
Definition: armv8.h:254
CPUV8_DBG_DTRRX
#define CPUV8_DBG_DTRRX
Definition: armv8.h:263
CPUV8_DBG_BCR_BASE
#define CPUV8_DBG_BCR_BASE
Definition: armv8.h:269
armv8_cache_d_inner_flush_virt
int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va, size_t size)
Definition: armv8_cache.c:105
armv8_cache_i_inner_inval_virt
int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va, size_t size)
Definition: armv8_cache.c:174
armv8_cache.h
armv8_dpm_report_dscr
void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
Definition: armv8_dpm.c:1357
armv8_dpm_write_dirty_registers
int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
Writes all modified core registers for all processor modes.
Definition: armv8_dpm.c:878
armv8_dpm_get_core_state
enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm)
Get core state from EDSCR, without necessity to retrieve CPSR.
Definition: armv8_dpm.c:41
armv8_dpm_read_current_registers
int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
Read basic registers of the current context: R0 to R15, and CPSR in AArch32 state or R0 to R31,...
Definition: armv8_dpm.c:740
armv8_dpm_initialize
int armv8_dpm_initialize(struct arm_dpm *dpm)
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affec...
Definition: armv8_dpm.c:1489
armv8_dpm_modeswitch
int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
Definition: armv8_dpm.c:538
armv8_dpm_handle_exception
void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore)
Definition: armv8_dpm.c:1301
armv8_dpm_setup
int armv8_dpm_setup(struct arm_dpm *dpm)
Hooks up this DPM to its associated target; call only once.
Definition: armv8_dpm.c:1407
PRSR_RESET
#define PRSR_RESET
Definition: armv8_dpm.h:99
PRSR_SDR
#define PRSR_SDR
Definition: armv8_dpm.h:108
ESR_RC
#define ESR_RC
Definition: armv8_dpm.h:94
DSCR_MA
#define DSCR_MA
Definition: armv8_dpm.h:44
PRSR_HALT
#define PRSR_HALT
Definition: armv8_dpm.h:101
DRCR_CSE
#define DRCR_CSE
Definition: armv8_dpm.h:74
DSCR_HDE
#define DSCR_HDE
Definition: armv8_dpm.h:41
ECR_RCE
#define ECR_RCE
Definition: armv8_dpm.h:91
PRSR_SR
#define PRSR_SR
Definition: armv8_dpm.h:100
DSCR_SYS_ERROR_PEND
#define DSCR_SYS_ERROR_PEND
Definition: armv8_dpm.h:38
DSCR_ERR
#define DSCR_ERR
Definition: armv8_dpm.h:37
DSCR_ITE
#define DSCR_ITE
Definition: armv8_dpm.h:47
armv8_select_opcodes
void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)
Definition: armv8_opcodes.c:75
armv8_opcodes.h
ARMV8_HLT_T1
#define ARMV8_HLT_T1(im)
Definition: armv8_opcodes.h:150
SYSTEM_SCTLR_EL1
#define SYSTEM_SCTLR_EL1
Definition: armv8_opcodes.h:37
ARMV8_MSR_GP
#define ARMV8_MSR_GP(system, rt)
Definition: armv8_opcodes.h:136
SYSTEM_SCTLR_EL3
#define SYSTEM_SCTLR_EL3
Definition: armv8_opcodes.h:39
ARMV8_MRS
#define ARMV8_MRS(system, rt)
Definition: armv8_opcodes.h:134
ARMV8_HLT
#define ARMV8_HLT(im)
Definition: armv8_opcodes.h:148
armv8_opcode
armv8_opcode
Definition: armv8_opcodes.h:185
ARMV8_OPC_LDRD_IP
@ ARMV8_OPC_LDRD_IP
Definition: armv8_opcodes.h:211
ARMV8_OPC_LDRW_IP
@ ARMV8_OPC_LDRW_IP
Definition: armv8_opcodes.h:210
ARMV8_OPC_LDRB_IP
@ ARMV8_OPC_LDRB_IP
Definition: armv8_opcodes.h:208
ARMV8_OPC_LDRH_IP
@ ARMV8_OPC_LDRH_IP
Definition: armv8_opcodes.h:209
ARMV8_OPC_STRD_IP
@ ARMV8_OPC_STRD_IP
Definition: armv8_opcodes.h:207
ARMV8_OPC_STRH_IP
@ ARMV8_OPC_STRH_IP
Definition: armv8_opcodes.h:205
ARMV8_OPC_STRW_IP
@ ARMV8_OPC_STRW_IP
Definition: armv8_opcodes.h:206
ARMV8_OPC_STRB_IP
@ ARMV8_OPC_STRB_IP
Definition: armv8_opcodes.h:204
SYSTEM_SCTLR_EL2
#define SYSTEM_SCTLR_EL2
Definition: armv8_opcodes.h:38
SYSTEM_DBG_DTRTX_EL0
#define SYSTEM_DBG_DTRTX_EL0
Definition: armv8_opcodes.h:63
SYSTEM_DBG_DBGDTR_EL0
#define SYSTEM_DBG_DBGDTR_EL0
Definition: armv8_opcodes.h:64
SYSTEM_DBG_DTRRX_EL0
#define SYSTEM_DBG_DTRRX_EL0
Definition: armv8_opcodes.h:62
ARMV8_HLT_A1
#define ARMV8_HLT_A1(im)
Definition: armv8_opcodes.h:149
buf_set_u32
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
buf_get_u64
static uint64_t buf_get_u64(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 64-bit word.
Definition: binarybuffer.h:134
buf_set_u64
static void buf_set_u64(uint8_t *_buffer, unsigned int first, unsigned int num, uint64_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:65
BKPT_HARD
@ BKPT_HARD
Definition: breakpoints.h:18
BKPT_SOFT
@ BKPT_SOFT
Definition: breakpoints.h:19
watchpoint_set
static void watchpoint_set(struct watchpoint *watchpoint, unsigned int number)
Definition: breakpoints.h:83
breakpoint_hw_set
static void breakpoint_hw_set(struct breakpoint *breakpoint, unsigned int hw_number)
Definition: breakpoints.h:66
WPT_ACCESS
@ WPT_ACCESS
Definition: breakpoints.h:23
WPT_READ
@ WPT_READ
Definition: breakpoints.h:23
WPT_WRITE
@ WPT_WRITE
Definition: breakpoints.h:23
command_print
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:375
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
CMD_NAME
#define CMD_NAME
Use this macro to access the name of the command being handled, rather than accessing the variable di...
Definition: command.h:166
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
COMMAND_PARSE_ADDRESS
#define COMMAND_PARSE_ADDRESS(in, out)
Definition: command.h:450
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:400
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
COMMAND_PARSE_NUMBER
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:440
CMD_CTX
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:146
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:251
ERROR_COMMAND_ARGUMENT_INVALID
#define ERROR_COMMAND_ARGUMENT_INVALID
Definition: command.h:402
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
halted
static int halted(struct target *target, const char *label)
Definition: davinci.c:58
buffer
uint64_t buffer
Pointer to data buffer to send over SPI.
Definition: dw-spi-helper.h:0
size
uint32_t size
Size of dw_spi_transaction::buffer.
Definition: dw-spi-helper.h:4
address
uint32_t address
Starting address. Sector aligned.
Definition: dw-spi-helper.h:0
mask
int mask
Definition: esirisc.c:1740
type
uint8_t type
Definition: esp_usb_jtag.c:0
priv
static struct esp_usb_jtag * priv
Definition: esp_usb_jtag.c:219
length
uint8_t length
Definition: esp_usb_jtag.c:1
jim_nvp_name2value_obj
int jim_nvp_name2value_obj(Jim_Interp *interp, const struct jim_nvp *p, Jim_Obj *o, struct jim_nvp **result)
Definition: jim-nvp.c:66
jim_getopt_obj
int jim_getopt_obj(struct jim_getopt_info *goi, Jim_Obj **puthere)
Remove argv[0] from the list.
Definition: jim-nvp.c:169
adapter_deassert_reset
int adapter_deassert_reset(void)
Definition: jtag/core.c:1912
jtag_get_reset_config
enum reset_types jtag_get_reset_config(void)
Definition: jtag/core.c:1747
adapter_assert_reset
int adapter_assert_reset(void)
Definition: jtag/core.c:1892
reset_types
reset_types
Definition: jtag.h:215
RESET_SRST_NO_GATING
@ RESET_SRST_NO_GATING
Definition: jtag.h:224
RESET_HAS_SRST
@ RESET_HAS_SRST
Definition: jtag.h:218
RESET_SRST_PULLS_TRST
@ RESET_SRST_PULLS_TRST
Definition: jtag.h:220
LOG_TARGET_INFO
#define LOG_TARGET_INFO(target, fmt_str,...)
Definition: log.h:153
LOG_WARNING
#define LOG_WARNING(expr ...)
Definition: log.h:130
ERROR_FAIL
#define ERROR_FAIL
Definition: log.h:174
LOG_TARGET_ERROR
#define LOG_TARGET_ERROR(target, fmt_str,...)
Definition: log.h:162
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:133
LOG_INFO
#define LOG_INFO(expr ...)
Definition: log.h:127
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:110
ERROR_OK
#define ERROR_OK
Definition: log.h:168
nvp_name2value
const struct nvp * nvp_name2value(const struct nvp *p, const char *name)
Definition: nvp.c:29
nvp_value2name
const struct nvp * nvp_value2name(const struct nvp *p, int value)
Definition: nvp.c:39
register_cache_invalidate
void register_cache_invalidate(struct reg_cache *cache)
Marks the contents of the register cache as invalid (and clean).
Definition: register.c:94
addr
target_addr_t addr
Start address to search for the control block.
Definition: rtt/rtt.c:28
target
struct target * target
Definition: rtt/rtt.c:26
semihosting_common_handlers
const struct command_registration semihosting_common_handlers[]
Definition: semihosting_common.c:2119
smp_command_handlers
const struct command_registration smp_command_handlers[]
Definition: smp.c:153
foreach_smp_target
#define foreach_smp_target(pos, head)
Definition: smp.h:15
aarch64_brp
Definition: aarch64.h:32
aarch64_brp::brpn
uint8_t brpn
Definition: aarch64.h:37
aarch64_brp::value
target_addr_t value
Definition: aarch64.h:35
aarch64_brp::type
int type
Definition: aarch64.h:34
aarch64_brp::control
uint32_t control
Definition: aarch64.h:36
aarch64_brp::used
int used
Definition: aarch64.h:33
aarch64_common
Definition: aarch64.h:40
aarch64_common::common_magic
unsigned int common_magic
Definition: aarch64.h:41
aarch64_common::wp_num_available
int wp_num_available
Definition: aarch64.h:57
aarch64_common::wp_list
struct aarch64_brp * wp_list
Definition: aarch64.h:58
aarch64_common::brp_num_available
int brp_num_available
Definition: aarch64.h:52
aarch64_common::brp_num
int brp_num
Definition: aarch64.h:51
aarch64_common::system_control_reg_curr
uint64_t system_control_reg_curr
Definition: aarch64.h:47
aarch64_common::wp_num
int wp_num
Definition: aarch64.h:56
aarch64_common::armv8_common
struct armv8_common armv8_common
Definition: aarch64.h:43
aarch64_common::brp_list
struct aarch64_brp * brp_list
Definition: aarch64.h:53
aarch64_common::isrmasking_mode
enum aarch64_isrmasking_mode isrmasking_mode
Definition: aarch64.h:60
aarch64_common::system_control_reg
uint64_t system_control_reg
Definition: aarch64.h:46
aarch64_common::brp_num_context
int brp_num_context
Definition: aarch64.h:50
aarch64_private_config
Definition: aarch64.c:37
aarch64_private_config::cti
struct arm_cti * cti
Definition: aarch64.c:39
aarch64_private_config::adiv5_config
struct adiv5_private_config adiv5_config
Definition: aarch64.c:38
adiv5_ap::dap
struct adiv5_dap * dap
DAP this AP belongs to.
Definition: arm_adi_v5.h:254
adiv5_ap::memaccess_tck
uint32_t memaccess_tck
Configures how many extra tck clocks are added after starting a MEM-AP access before we try to read i...
Definition: arm_adi_v5.h:306
adiv5_dap
This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
Definition: arm_adi_v5.h:348
adiv5_private_config
Definition: arm_adi_v5.h:785
adiv5_private_config::ap_num
uint64_t ap_num
Definition: arm_adi_v5.h:786
adiv5_private_config::dap
struct adiv5_dap * dap
Definition: arm_adi_v5.h:787
arm_cti
Definition: arm_cti.c:21
arm_dpm
This wraps an implementation of DPM primitives.
Definition: arm_dpm.h:47
arm_dpm::wp_addr
target_addr_t wp_addr
Target dependent watchpoint address.
Definition: arm_dpm.h:147
arm_dpm::didr
uint64_t didr
Cache of DIDR.
Definition: arm_dpm.h:51
arm_dpm::instr_write_data_r0_64
int(* instr_write_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Runs one instruction, writing data to R0 before execution.
Definition: arm_dpm.h:82
arm_dpm::instr_execute
int(* instr_execute)(struct arm_dpm *dpm, uint32_t opcode)
Runs one instruction.
Definition: arm_dpm.h:60
arm_dpm::instr_write_data_dcc_64
int(* instr_write_data_dcc_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Definition: arm_dpm.h:68
arm_dpm::arm
struct arm * arm
Definition: arm_dpm.h:48
arm_dpm::dbp
struct dpm_bp * dbp
Definition: arm_dpm.h:139
arm_dpm::instr_write_data_dcc
int(* instr_write_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
Definition: arm_dpm.h:65
arm_dpm::instr_read_data_r0_64
int(* instr_read_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Definition: arm_dpm.h:108
arm_dpm::dwp
struct dpm_wp * dwp
Definition: arm_dpm.h:140
arm_dpm::instr_cpsr_sync
int(* instr_cpsr_sync)(struct arm_dpm *dpm)
Optional core-specific operation invoked after CPSR writes.
Definition: arm_dpm.h:86
arm_dpm::dscr
uint32_t dscr
Recent value of DSCR.
Definition: arm_dpm.h:150
arm
Represents a generic ARM core, with standard application registers.
Definition: arm.h:175
arm::mrc
int(* mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
Read coprocessor register.
Definition: arm.h:230
arm::core_mode
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
Definition: arm.h:196
arm::dap
struct adiv5_dap * dap
For targets conforming to ARM Debug Interface v5, this handle references the Debug Access Port (DAP) ...
Definition: arm.h:257
arm::pc
struct reg * pc
Handle to the PC; valid in all core modes.
Definition: arm.h:181
arm::core_cache
struct reg_cache * core_cache
Definition: arm.h:178
arm::dpm
struct arm_dpm * dpm
Handle for the debug module, if one is present.
Definition: arm.h:213
arm::mcr
int(* mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
Write coprocessor register.
Definition: arm.h:241
arm::core_state
enum arm_state core_state
Record the current core state: ARM, Thumb, or otherwise.
Definition: arm.h:199
armv8_cache_common::d_u_cache_enabled
bool d_u_cache_enabled
Definition: armv8.h:160
armv8_cache_common::info_valid
bool info_valid
Definition: armv8.h:154
armv8_cache_common::i_cache_enabled
bool i_cache_enabled
Definition: armv8.h:159
armv8_cache_common::flush_all_data_cache
int(* flush_all_data_cache)(struct target *target)
Definition: armv8.h:164
armv8_common
Definition: armv8.h:185
armv8_common::arm
struct arm arm
Definition: armv8.h:188
armv8_common::dpm
struct arm_dpm dpm
Definition: armv8.h:192
armv8_common::is_armv8r
bool is_armv8r
Definition: armv8.h:203
armv8_common::debug_base
target_addr_t debug_base
Definition: armv8.h:193
armv8_common::sticky_reset
bool sticky_reset
Definition: armv8.h:212
armv8_common::last_run_control_op
enum run_control_op last_run_control_op
Definition: armv8.h:215
armv8_common::armv8_mmu
struct armv8_mmu_common armv8_mmu
Definition: armv8.h:205
armv8_common::debug_ap
struct adiv5_ap * debug_ap
Definition: armv8.h:194
armv8_common::cti
struct arm_cti * cti
Definition: armv8.h:207
armv8_common::pre_restore_context
void(* pre_restore_context)(struct target *target)
Definition: armv8.h:230
armv8_common::examine_debug_reason
int(* examine_debug_reason)(struct target *target)
Definition: armv8.h:227
armv8_common::post_debug_entry
int(* post_debug_entry)(struct target *target)
Definition: armv8.h:228
armv8_mmu_common::read_physical_memory
int(* read_physical_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: armv8.h:179
armv8_mmu_common::armv8_cache
struct armv8_cache_common armv8_cache
Definition: armv8.h:181
armv8_mmu_common::mmu_enabled
bool mmu_enabled
Definition: armv8.h:182
breakpoint::linked_brp
int linked_brp
Definition: breakpoints.h:36
breakpoint::length
unsigned int length
Definition: breakpoints.h:29
breakpoint::orig_instr
uint8_t * orig_instr
Definition: breakpoints.h:33
breakpoint::type
enum breakpoint_type type
Definition: breakpoints.h:30
breakpoint::is_set
bool is_set
Definition: breakpoints.h:31
breakpoint::number
unsigned int number
Definition: breakpoints.h:32
breakpoint::asid
uint32_t asid
Definition: breakpoints.h:28
breakpoint::address
target_addr_t address
Definition: breakpoints.h:27
command_context
Definition: command.h:52
command_registration
Definition: command.h:233
command_registration::name
const char * name
Definition: command.h:234
command_registration::chain
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
Definition: command.h:247
gdb_service::target
struct target * target
Definition: target.h:98
jim_getopt_info
A TCL -ish GetOpt like code.
Definition: jim-nvp.h:136
jim_getopt_info::interp
Jim_Interp * interp
Definition: jim-nvp.h:137
jim_getopt_info::is_configure
bool is_configure
Definition: jim-nvp.h:140
jim_getopt_info::argc
int argc
Definition: jim-nvp.h:138
jim_getopt_info::argv
Jim_Obj *const * argv
Definition: jim-nvp.h:139
jim_nvp
Name Value Pairs, aka: NVP.
Definition: jim-nvp.h:60
jim_nvp::name
const char * name
Definition: jim-nvp.h:61
jim_nvp::value
int value
Definition: jim-nvp.h:62
nvp
Name Value Pairs, aka: NVP.
Definition: nvp.h:61
nvp::value
int value
Definition: nvp.h:63
nvp::name
const char * name
Definition: nvp.h:62
reg_cache::next
struct reg_cache * next
Definition: register.h:146
reg::valid
bool valid
Definition: register.h:126
reg::value
uint8_t * value
Definition: register.h:122
reg::dirty
bool dirty
Definition: register.h:124
target_list
Definition: target.h:215
target_list::target
struct target * target
Definition: target.h:217
target_type
This holds methods shared between all instances of a given target type.
Definition: target_type.h:26
target_type::name
const char * name
Name of this type of target.
Definition: target_type.h:31
target
Definition: target.h:119
target::coreid
int32_t coreid
Definition: target.h:123
target::gdb_service
struct gdb_service * gdb_service
Definition: target.h:202
target::dbgbase_set
bool dbgbase_set
Definition: target.h:177
target::dbg_msg_enabled
bool dbg_msg_enabled
Definition: target.h:166
target::debug_reason
enum target_debug_reason debug_reason
Definition: target.h:157
target::state
enum target_state state
Definition: target.h:160
target::dbgbase
uint32_t dbgbase
Definition: target.h:178
target::private_config
void * private_config
Definition: target.h:168
target::smp_targets
struct list_head * smp_targets
Definition: target.h:191
target::smp
unsigned int smp
Definition: target.h:190
target::watchpoints
struct watchpoint * watchpoints
Definition: target.h:163
target::reset_halt
bool reset_halt
Definition: target.h:147
target::next
struct target * next
Definition: target.h:169
watchpoint::rw
enum watchpoint_rw rw
Definition: breakpoints.h:46
watchpoint::is_set
bool is_set
Definition: breakpoints.h:47
watchpoint::next
struct watchpoint * next
Definition: breakpoints.h:49
watchpoint::length
unsigned int length
Definition: breakpoints.h:43
watchpoint::number
unsigned int number
Definition: breakpoints.h:48
watchpoint::address
target_addr_t address
Definition: breakpoints.h:42
target_buffer_get_u64
uint64_t target_buffer_get_u64(struct target *target, const uint8_t *buffer)
Definition: target.c:316
target_call_event_callbacks
int target_call_event_callbacks(struct target *target, enum target_event event)
Definition: target.c:1774
target_free_all_working_areas
void target_free_all_working_areas(struct target *target)
Definition: target.c:2160
target_buffer_set_u16
void target_buffer_set_u16(struct target *target, uint8_t *buffer, uint16_t value)
Definition: target.c:379
target_buffer_set_u32
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
Definition: target.c:361
target_write_memory
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1275
srst_asserted
static int srst_asserted
Definition: target.c:2857
target_register_timer_callback
int target_register_timer_callback(int(*callback)(void *priv), unsigned int time_ms, enum target_timer_type type, void *priv)
The period is very approximate, the callback can happen much more often or much more rarely than spec...
Definition: target.c:1668
target_buffer_set_u64
void target_buffer_set_u64(struct target *target, uint8_t *buffer, uint64_t value)
Definition: target.c:352
target_buffer_get_u16
uint16_t target_buffer_get_u16(struct target *target, const uint8_t *buffer)
Definition: target.c:343
target_read_memory
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
Definition: target.c:1247
target_has_event_action
bool target_has_event_action(const struct target *target, enum target_event event)
Returns true only if the target has a handler for the specified event.
Definition: target.c:4832
get_current_target
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:467
target_handle_event
void target_handle_event(struct target *target, enum target_event e)
Definition: target.c:4668
target_buffer_get_u32
uint32_t target_buffer_get_u32(struct target *target, const uint8_t *buffer)
Definition: target.c:325
target_debug_reason
target_debug_reason
Definition: target.h:71
DBG_REASON_NOTHALTED
@ DBG_REASON_NOTHALTED
Definition: target.h:77
DBG_REASON_DBGRQ
@ DBG_REASON_DBGRQ
Definition: target.h:72
DBG_REASON_WATCHPOINT
@ DBG_REASON_WATCHPOINT
Definition: target.h:74
ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:786
target_was_examined
static bool target_was_examined(const struct target *target)
Definition: target.h:432
TARGET_TIMER_TYPE_PERIODIC
@ TARGET_TIMER_TYPE_PERIODIC
Definition: target.h:323
TARGET_EVENT_DEBUG_RESUMED
@ TARGET_EVENT_DEBUG_RESUMED
Definition: target.h:275
TARGET_EVENT_HALTED
@ TARGET_EVENT_HALTED
Definition: target.h:255
TARGET_EVENT_RESUMED
@ TARGET_EVENT_RESUMED
Definition: target.h:256
TARGET_EVENT_DEBUG_HALTED
@ TARGET_EVENT_DEBUG_HALTED
Definition: target.h:274
TARGET_EVENT_RESET_ASSERT
@ TARGET_EVENT_RESET_ASSERT
Definition: target.h:267
target_name
static const char * target_name(const struct target *target)
Returns the instance-specific name of the specified target.
Definition: target.h:236
target_state
target_state
Definition: target.h:55
TARGET_RESET
@ TARGET_RESET
Definition: target.h:59
TARGET_DEBUG_RUNNING
@ TARGET_DEBUG_RUNNING
Definition: target.h:60
TARGET_UNKNOWN
@ TARGET_UNKNOWN
Definition: target.h:56
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:58
TARGET_RUNNING
@ TARGET_RUNNING
Definition: target.h:57
ERROR_TARGET_NOT_EXAMINED
#define ERROR_TARGET_NOT_EXAMINED
Definition: target.h:793
ERROR_TARGET_TIMEOUT
#define ERROR_TARGET_TIMEOUT
Definition: target.h:785
ERROR_TARGET_RESOURCE_NOT_AVAILABLE
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:790
target_set_examined
static void target_set_examined(struct target *target)
Sets the examined flag for the given target.
Definition: target.h:439
target_request
int target_request(struct target *target, uint32_t request)
Definition: target_request.c:108
target_request.h
target_type.h
time_support.h
timeval_ms
int64_t timeval_ms(void)
Definition: time_support_common.c:23
TARGET_ADDR_FMT
#define TARGET_ADDR_FMT
Definition: types.h:342
target_addr_t
uint64_t target_addr_t
Definition: types.h:335
TARGET_PRIxADDR
#define TARGET_PRIxADDR
Definition: types.h:340
NULL
#define NULL
Definition: usb.h:16
offset
uint8_t offset[4]
Definition: vdebug.c:9
dummy
uint8_t dummy[96]
Definition: vdebug.c:23
count
uint8_t count[4]
Definition: vdebug.c:22