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aarch64.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2015 by David Ung *
5  * *
6  ***************************************************************************/
7 
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11 
12 #include "breakpoints.h"
13 #include "aarch64.h"
14 #include "a64_disassembler.h"
15 #include "register.h"
16 #include "target_request.h"
17 #include "target_type.h"
18 #include "armv8_opcodes.h"
19 #include "armv8_cache.h"
20 #include "arm_coresight.h"
21 #include "arm_semihosting.h"
22 #include "jtag/interface.h"
23 #include "smp.h"
24 #include <helper/nvp.h>
25 #include <helper/time_support.h>
26 
27 enum restart_mode {
28  RESTART_LAZY,
29  RESTART_SYNC,
30 };
31 
32 enum halt_mode {
33  HALT_LAZY,
34  HALT_SYNC,
35 };
36 
37 struct aarch64_private_config {
38  struct adiv5_private_config adiv5_config;
39  struct arm_cti *cti;
40 };
41 
42 static int aarch64_poll(struct target *target);
43 static int aarch64_debug_entry(struct target *target);
44 static int aarch64_restore_context(struct target *target, bool bpwp);
45 static int aarch64_set_breakpoint(struct target *target,
46  struct breakpoint *breakpoint, uint8_t matchmode);
47 static int aarch64_set_context_breakpoint(struct target *target,
48  struct breakpoint *breakpoint, uint8_t matchmode);
49 static int aarch64_set_hybrid_breakpoint(struct target *target,
50  struct breakpoint *breakpoint);
51 static int aarch64_unset_breakpoint(struct target *target,
52  struct breakpoint *breakpoint);
53 static int aarch64_mmu(struct target *target, int *enabled);
54 static int aarch64_virt2phys(struct target *target,
55  target_addr_t virt, target_addr_t *phys);
56 static int aarch64_read_cpu_memory(struct target *target,
57  uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer);
58 
59 static int aarch64_restore_system_control_reg(struct target *target)
60 {
61  enum arm_mode target_mode = ARM_MODE_ANY;
62  int retval = ERROR_OK;
63  uint32_t instr;
64 
65  struct aarch64_common *aarch64 = target_to_aarch64(target);
66  struct armv8_common *armv8 = target_to_armv8(target);
67 
68  if (aarch64->system_control_reg != aarch64->system_control_reg_curr) {
69  aarch64->system_control_reg_curr = aarch64->system_control_reg;
70  /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_v8->cp15_control_reg); */
71 
72  switch (armv8->arm.core_mode) {
73  case ARMV8_64_EL0T:
74  target_mode = ARMV8_64_EL1H;
75  /* fall through */
76  case ARMV8_64_EL1T:
77  case ARMV8_64_EL1H:
78  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL1, 0);
79  break;
80  case ARMV8_64_EL2T:
81  case ARMV8_64_EL2H:
82  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL2, 0);
83  break;
84  case ARMV8_64_EL3H:
85  case ARMV8_64_EL3T:
86  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL3, 0);
87  break;
88 
89  case ARM_MODE_SVC:
90  case ARM_MODE_ABT:
91  case ARM_MODE_FIQ:
92  case ARM_MODE_IRQ:
93  case ARM_MODE_HYP:
94  case ARM_MODE_UND:
95  case ARM_MODE_SYS:
96  case ARM_MODE_MON:
97  instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
98  break;
99 
100  default:
101  LOG_ERROR("cannot read system control register in this mode: (%s : 0x%x)",
102  armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
103  return ERROR_FAIL;
104  }
105 
106  if (target_mode != ARM_MODE_ANY)
107  armv8_dpm_modeswitch(&armv8->dpm, target_mode);
108 
109  retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr, aarch64->system_control_reg);
110  if (retval != ERROR_OK)
111  return retval;
112 
113  if (target_mode != ARM_MODE_ANY)
114  armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
115  }
116 
117  return retval;
118 }
119 
120 /* modify system_control_reg in order to enable or disable mmu for :
121  * - virt2phys address conversion
122  * - read or write memory in phys or virt address */
123 static int aarch64_mmu_modify(struct target *target, int enable)
124 {
125  struct aarch64_common *aarch64 = target_to_aarch64(target);
126  struct armv8_common *armv8 = &aarch64->armv8_common;
127  int retval = ERROR_OK;
128  enum arm_mode target_mode = ARM_MODE_ANY;
129  uint32_t instr = 0;
130 
131  if (enable) {
132  /* if mmu enabled at target stop and mmu not enable */
133  if (!(aarch64->system_control_reg & 0x1U)) {
134  LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
135  return ERROR_FAIL;
136  }
137  if (!(aarch64->system_control_reg_curr & 0x1U))
138  aarch64->system_control_reg_curr |= 0x1U;
139  } else {
140  if (aarch64->system_control_reg_curr & 0x4U) {
141  /* data cache is active */
142  aarch64->system_control_reg_curr &= ~0x4U;
143  /* flush data cache armv8 function to be called */
144  if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache)
145  armv8->armv8_mmu.armv8_cache.flush_all_data_cache(target);
146  }
147  if ((aarch64->system_control_reg_curr & 0x1U)) {
148  aarch64->system_control_reg_curr &= ~0x1U;
149  }
150  }
151 
152  switch (armv8->arm.core_mode) {
153  case ARMV8_64_EL0T:
154  target_mode = ARMV8_64_EL1H;
155  /* fall through */
156  case ARMV8_64_EL1T:
157  case ARMV8_64_EL1H:
158  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL1, 0);
159  break;
160  case ARMV8_64_EL2T:
161  case ARMV8_64_EL2H:
162  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL2, 0);
163  break;
164  case ARMV8_64_EL3H:
165  case ARMV8_64_EL3T:
166  instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL3, 0);
167  break;
168 
169  case ARM_MODE_SVC:
170  case ARM_MODE_ABT:
171  case ARM_MODE_FIQ:
172  case ARM_MODE_IRQ:
173  case ARM_MODE_HYP:
174  case ARM_MODE_UND:
175  case ARM_MODE_SYS:
176  case ARM_MODE_MON:
177  instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
178  break;
179 
180  default:
181  LOG_DEBUG("unknown cpu state 0x%x", armv8->arm.core_mode);
182  break;
183  }
184  if (target_mode != ARM_MODE_ANY)
185  armv8_dpm_modeswitch(&armv8->dpm, target_mode);
186 
187  retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr,
188  aarch64->system_control_reg_curr);
189 
190  if (target_mode != ARM_MODE_ANY)
191  armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
192 
193  return retval;
194 }
195 
196 static int aarch64_read_prsr(struct target *target, uint32_t *prsr)
197 {
198  struct armv8_common *armv8 = target_to_armv8(target);
199  int retval;
200 
201  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
202  armv8->debug_base + CPUV8_DBG_PRSR, prsr);
203  if (retval != ERROR_OK)
204  return retval;
205 
206  armv8->sticky_reset |= *prsr & PRSR_SR;
207  return ERROR_OK;
208 }
209 
210 /*
211  * Basic debug access, very low level assumes state is saved
212  */
213 static int aarch64_init_debug_access(struct target *target)
214 {
215  struct armv8_common *armv8 = target_to_armv8(target);
216  int retval;
217  uint32_t dummy;
218 
219  LOG_DEBUG("%s", target_name(target));
220 
221  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
222  armv8->debug_base + CPUV8_DBG_OSLAR, 0);
223  if (retval != ERROR_OK) {
224  LOG_DEBUG("Examine %s failed", "oslock");
225  return retval;
226  }
227 
228  /* Clear Sticky Power Down status Bit in PRSR to enable access to
229  the registers in the Core Power Domain */
230  retval = aarch64_read_prsr(target, &dummy);
231  if (retval != ERROR_OK)
232  return retval;
233 
234  /*
235  * Static CTI configuration:
236  * Channel 0 -> trigger outputs HALT request to PE
237  * Channel 1 -> trigger outputs Resume request to PE
238  * Gate all channel trigger events from entering the CTM
239  */
240 
241  /* Enable CTI */
242  retval = arm_cti_enable(armv8->cti, true);
243  /* By default, gate all channel events to and from the CTM */
244  if (retval == ERROR_OK)
245  retval = arm_cti_write_reg(armv8->cti, CTI_GATE, 0);
246  /* output halt requests to PE on channel 0 event */
247  if (retval == ERROR_OK)
248  retval = arm_cti_write_reg(armv8->cti, CTI_OUTEN0, CTI_CHNL(0));
249  /* output restart requests to PE on channel 1 event */
250  if (retval == ERROR_OK)
251  retval = arm_cti_write_reg(armv8->cti, CTI_OUTEN1, CTI_CHNL(1));
252  if (retval != ERROR_OK)
253  return retval;
254 
255  /* Resync breakpoint registers */
256 
257  return ERROR_OK;
258 }
259 
260 /* Write to memory mapped registers directly with no cache or mmu handling */
261 static int aarch64_dap_write_memap_register_u32(struct target *target,
262  target_addr_t address,
263  uint32_t value)
264 {
265  int retval;
266  struct armv8_common *armv8 = target_to_armv8(target);
267 
268  retval = mem_ap_write_atomic_u32(armv8->debug_ap, address, value);
269 
270  return retval;
271 }
272 
273 static int aarch64_dpm_setup(struct aarch64_common *a8, uint64_t debug)
274 {
275  struct arm_dpm *dpm = &a8->armv8_common.dpm;
276  int retval;
277 
278  dpm->arm = &a8->armv8_common.arm;
279  dpm->didr = debug;
280 
281  retval = armv8_dpm_setup(dpm);
282  if (retval == ERROR_OK)
283  retval = armv8_dpm_initialize(dpm);
284 
285  return retval;
286 }
287 
288 static int aarch64_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
289 {
290  struct armv8_common *armv8 = target_to_armv8(target);
291  return armv8_set_dbgreg_bits(armv8, CPUV8_DBG_DSCR, bit_mask, value);
292 }
293 
294 static int aarch64_check_state_one(struct target *target,
295  uint32_t mask, uint32_t val, int *p_result, uint32_t *p_prsr)
296 {
297  uint32_t prsr;
298  int retval;
299 
300  retval = aarch64_read_prsr(target, &prsr);
301  if (retval != ERROR_OK)
302  return retval;
303 
304  if (p_prsr)
305  *p_prsr = prsr;
306 
307  if (p_result)
308  *p_result = (prsr & mask) == (val & mask);
309 
310  return ERROR_OK;
311 }
312 
313 static int aarch64_wait_halt_one(struct target *target)
314 {
315  int retval = ERROR_OK;
316  uint32_t prsr;
317 
318  int64_t then = timeval_ms();
319  for (;;) {
320  int halted;
321 
322  retval = aarch64_check_state_one(target, PRSR_HALT, PRSR_HALT, &halted, &prsr);
323  if (retval != ERROR_OK || halted)
324  break;
325 
326  if (timeval_ms() > then + 1000) {
327  retval = ERROR_TARGET_TIMEOUT;
328  LOG_DEBUG("target %s timeout, prsr=0x%08"PRIx32, target_name(target), prsr);
329  break;
330  }
331  }
332  return retval;
333 }
334 
335 static int aarch64_prepare_halt_smp(struct target *target, bool exc_target, struct target **p_first)
336 {
337  int retval = ERROR_OK;
338  struct target_list *head;
339  struct target *first = NULL;
340 
341  LOG_DEBUG("target %s exc %i", target_name(target), exc_target);
342 
343  foreach_smp_target(head, target->smp_targets) {
344  struct target *curr = head->target;
345  struct armv8_common *armv8 = target_to_armv8(curr);
346 
347  if (exc_target && curr == target)
348  continue;
349  if (!target_was_examined(curr))
350  continue;
351  if (curr->state != TARGET_RUNNING)
352  continue;
353 
354  /* HACK: mark this target as prepared for halting */
355  curr->debug_reason = DBG_REASON_DBGRQ;
356 
357  /* open the gate for channel 0 to let HALT requests pass to the CTM */
358  retval = arm_cti_ungate_channel(armv8->cti, 0);
359  if (retval == ERROR_OK)
360  retval = aarch64_set_dscr_bits(curr, DSCR_HDE, DSCR_HDE);
361  if (retval != ERROR_OK)
362  break;
363 
364  LOG_DEBUG("target %s prepared", target_name(curr));
365 
366  if (!first)
367  first = curr;
368  }
369 
370  if (p_first) {
371  if (exc_target && first)
372  *p_first = first;
373  else
374  *p_first = target;
375  }
376 
377  return retval;
378 }
379 
380 static int aarch64_halt_one(struct target *target, enum halt_mode mode)
381 {
382  int retval = ERROR_OK;
383  struct armv8_common *armv8 = target_to_armv8(target);
384 
385  LOG_DEBUG("%s", target_name(target));
386 
387  /* allow Halting Debug Mode */
388  retval = aarch64_set_dscr_bits(target, DSCR_HDE, DSCR_HDE);
389  if (retval != ERROR_OK)
390  return retval;
391 
392  /* trigger an event on channel 0, this outputs a halt request to the PE */
393  retval = arm_cti_pulse_channel(armv8->cti, 0);
394  if (retval != ERROR_OK)
395  return retval;
396 
397  if (mode == HALT_SYNC) {
398  retval = aarch64_wait_halt_one(target);
399  if (retval != ERROR_OK) {
400  if (retval == ERROR_TARGET_TIMEOUT)
401  LOG_ERROR("Timeout waiting for target %s halt", target_name(target));
402  return retval;
403  }
404  }
405 
406  return ERROR_OK;
407 }
408 
409 static int aarch64_halt_smp(struct target *target, bool exc_target)
410 {
411  struct target *next = target;
412  int retval;
413 
414  /* prepare halt on all PEs of the group */
415  retval = aarch64_prepare_halt_smp(target, exc_target, &next);
416 
417  if (exc_target && next == target)
418  return retval;
419 
420  /* halt the target PE */
421  if (retval == ERROR_OK)
422  retval = aarch64_halt_one(next, HALT_LAZY);
423 
424  if (retval != ERROR_OK)
425  return retval;
426 
427  /* wait for all PEs to halt */
428  int64_t then = timeval_ms();
429  for (;;) {
430  bool all_halted = true;
431  struct target_list *head;
432  struct target *curr;
433 
434  foreach_smp_target(head, target->smp_targets) {
435  int halted;
436 
437  curr = head->target;
438 
439  if (!target_was_examined(curr))
440  continue;
441 
442  retval = aarch64_check_state_one(curr, PRSR_HALT, PRSR_HALT, &halted, NULL);
443  if (retval != ERROR_OK || !halted) {
444  all_halted = false;
445  break;
446  }
447  }
448 
449  if (all_halted)
450  break;
451 
452  if (timeval_ms() > then + 1000) {
453  retval = ERROR_TARGET_TIMEOUT;
454  break;
455  }
456 
457  /*
458  * HACK: on Hi6220 there are 8 cores organized in 2 clusters
459  * and it looks like the CTI's are not connected by a common
460  * trigger matrix. It seems that we need to halt one core in each
461  * cluster explicitly. So if we find that a core has not halted
462  * yet, we trigger an explicit halt for the second cluster.
463  */
464  retval = aarch64_halt_one(curr, HALT_LAZY);
465  if (retval != ERROR_OK)
466  break;
467  }
468 
469  return retval;
470 }
471 
472 static int update_halt_gdb(struct target *target, enum target_debug_reason debug_reason)
473 {
474  struct target *gdb_target = NULL;
475  struct target_list *head;
476  struct target *curr;
477 
478  if (debug_reason == DBG_REASON_NOTHALTED) {
479  LOG_DEBUG("Halting remaining targets in SMP group");
480  aarch64_halt_smp(target, true);
481  }
482 
483  /* poll all targets in the group, but skip the target that serves GDB */
484  foreach_smp_target(head, target->smp_targets) {
485  curr = head->target;
486  /* skip calling context */
487  if (curr == target)
488  continue;
489  if (!target_was_examined(curr))
490  continue;
491  /* skip targets that were already halted */
492  if (curr->state == TARGET_HALTED)
493  continue;
494  /* remember the gdb_service->target */
495  if (curr->gdb_service)
496  gdb_target = curr->gdb_service->target;
497  /* skip it */
498  if (curr == gdb_target)
499  continue;
500 
501  /* avoid recursion in aarch64_poll() */
502  curr->smp = 0;
503  aarch64_poll(curr);
504  curr->smp = 1;
505  }
506 
507  /* after all targets were updated, poll the gdb serving target */
508  if (gdb_target && gdb_target != target)
509  aarch64_poll(gdb_target);
510 
511  return ERROR_OK;
512 }
513 
514 /*
515  * Aarch64 Run control
516  */
517 
518 static int aarch64_poll(struct target *target)
519 {
520  struct armv8_common *armv8 = target_to_armv8(target);
521  enum target_state prev_target_state;
522  int retval = ERROR_OK;
523  uint32_t prsr;
524 
525  retval = aarch64_read_prsr(target, &prsr);
526  if (retval != ERROR_OK)
527  return retval;
528 
529  if (armv8->sticky_reset) {
530  armv8->sticky_reset = false;
531  if (target->state != TARGET_RESET) {
532  target->state = TARGET_RESET;
533  LOG_TARGET_INFO(target, "external reset detected");
534  if (armv8->arm.core_cache) {
535  register_cache_invalidate(armv8->arm.core_cache);
536  register_cache_invalidate(armv8->arm.core_cache->next);
537  }
538  }
539  }
540 
541  if (prsr & PRSR_HALT) {
542  prev_target_state = target->state;
543  if (prev_target_state != TARGET_HALTED) {
544  enum target_debug_reason debug_reason = target->debug_reason;
545 
546  /* We have a halting debug event */
547  target->state = TARGET_HALTED;
548  LOG_DEBUG("Target %s halted", target_name(target));
549  retval = aarch64_debug_entry(target);
550  if (retval != ERROR_OK)
551  return retval;
552 
553  if (target->smp)
554  update_halt_gdb(target, debug_reason);
555 
556  if (arm_semihosting(target, &retval) != 0)
557  return retval;
558 
559  switch (prev_target_state) {
560  case TARGET_RUNNING:
561  case TARGET_UNKNOWN:
562  case TARGET_RESET:
563  target_call_event_callbacks(target, TARGET_EVENT_HALTED);
564  break;
565  case TARGET_DEBUG_RUNNING:
566  target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
567  break;
568  default:
569  break;
570  }
571  }
572  } else if (prsr & PRSR_RESET) {
573  target->state = TARGET_RESET;
574  } else {
575  target->state = TARGET_RUNNING;
576  }
577 
578  return retval;
579 }
580 
581 static int aarch64_halt(struct target *target)
582 {
583  struct armv8_common *armv8 = target_to_armv8(target);
584  armv8->last_run_control_op = ARMV8_RUNCONTROL_HALT;
585 
586  if (target->smp)
587  return aarch64_halt_smp(target, false);
588 
589  return aarch64_halt_one(target, HALT_SYNC);
590 }
591 
592 static int aarch64_restore_one(struct target *target, int current,
593  uint64_t *address, int handle_breakpoints, int debug_execution)
594 {
595  struct armv8_common *armv8 = target_to_armv8(target);
596  struct arm *arm = &armv8->arm;
597  int retval;
598  uint64_t resume_pc;
599 
600  LOG_DEBUG("%s", target_name(target));
601 
602  if (!debug_execution)
603  target_free_all_working_areas(target);
604 
605  /* current = 1: continue on current pc, otherwise continue at <address> */
606  resume_pc = buf_get_u64(arm->pc->value, 0, 64);
607  if (!current)
608  resume_pc = *address;
609  else
610  *address = resume_pc;
611 
612  /* Make sure that the Armv7 gdb thumb fixups does not
613  * kill the return address
614  */
615  switch (arm->core_state) {
616  case ARM_STATE_ARM:
617  resume_pc &= 0xFFFFFFFC;
618  break;
619  case ARM_STATE_AARCH64:
620  resume_pc &= 0xFFFFFFFFFFFFFFFCULL;
621  break;
622  case ARM_STATE_THUMB:
623  case ARM_STATE_THUMB_EE:
624  /* When the return address is loaded into PC
625  * bit 0 must be 1 to stay in Thumb state
626  */
627  resume_pc |= 0x1;
628  break;
629  case ARM_STATE_JAZELLE:
630  LOG_ERROR("How do I resume into Jazelle state??");
631  return ERROR_FAIL;
632  }
633  LOG_DEBUG("resume pc = 0x%016" PRIx64, resume_pc);
634  buf_set_u64(arm->pc->value, 0, 64, resume_pc);
635  arm->pc->dirty = true;
636  arm->pc->valid = true;
637 
638  /* called it now before restoring context because it uses cpu
639  * register r0 for restoring system control register */
640  retval = aarch64_restore_system_control_reg(target);
641  if (retval == ERROR_OK)
642  retval = aarch64_restore_context(target, handle_breakpoints);
643 
644  return retval;
645 }
646 
652 static int aarch64_prepare_restart_one(struct target *target)
653 {
654  struct armv8_common *armv8 = target_to_armv8(target);
655  int retval;
656  uint32_t dscr;
657  uint32_t tmp;
658 
659  LOG_DEBUG("%s", target_name(target));
660 
661  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
662  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
663  if (retval != ERROR_OK)
664  return retval;
665 
666  if ((dscr & DSCR_ITE) == 0)
667  LOG_ERROR("DSCR.ITE must be set before leaving debug!");
668  if ((dscr & DSCR_ERR) != 0)
669  LOG_ERROR("DSCR.ERR must be cleared before leaving debug!");
670 
671  /* acknowledge a pending CTI halt event */
672  retval = arm_cti_ack_events(armv8->cti, CTI_TRIG(HALT));
673  /*
674  * open the CTI gate for channel 1 so that the restart events
675  * get passed along to all PEs. Also close gate for channel 0
676  * to isolate the PE from halt events.
677  */
678  if (retval == ERROR_OK)
679  retval = arm_cti_ungate_channel(armv8->cti, 1);
680  if (retval == ERROR_OK)
681  retval = arm_cti_gate_channel(armv8->cti, 0);
682 
683  /* make sure that DSCR.HDE is set */
684  if (retval == ERROR_OK) {
685  dscr |= DSCR_HDE;
686  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
687  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
688  }
689 
690  if (retval == ERROR_OK) {
691  /* clear sticky bits in PRSR, SDR is now 0 */
692  retval = aarch64_read_prsr(target, &tmp);
693  }
694 
695  return retval;
696 }
697 
698 static int aarch64_do_restart_one(struct target *target, enum restart_mode mode)
699 {
700  struct armv8_common *armv8 = target_to_armv8(target);
701  int retval;
702 
703  LOG_DEBUG("%s", target_name(target));
704 
705  /* trigger an event on channel 1, generates a restart request to the PE */
706  retval = arm_cti_pulse_channel(armv8->cti, 1);
707  if (retval != ERROR_OK)
708  return retval;
709 
710  if (mode == RESTART_SYNC) {
711  int64_t then = timeval_ms();
712  for (;;) {
713  int resumed;
714  /*
715  * if PRSR.SDR is set now, the target did restart, even
716  * if it's now already halted again (e.g. due to breakpoint)
717  */
718  retval = aarch64_check_state_one(target,
719  PRSR_SDR, PRSR_SDR, &resumed, NULL);
720  if (retval != ERROR_OK || resumed)
721  break;
722 
723  if (timeval_ms() > then + 1000) {
724  LOG_ERROR("%s: Timeout waiting for resume"PRIx32, target_name(target));
725  retval = ERROR_TARGET_TIMEOUT;
726  break;
727  }
728  }
729  }
730 
731  if (retval != ERROR_OK)
732  return retval;
733 
734  target->debug_reason = DBG_REASON_NOTHALTED;
735  target->state = TARGET_RUNNING;
736 
737  return ERROR_OK;
738 }
739 
740 static int aarch64_restart_one(struct target *target, enum restart_mode mode)
741 {
742  int retval;
743 
744  LOG_DEBUG("%s", target_name(target));
745 
746  retval = aarch64_prepare_restart_one(target);
747  if (retval == ERROR_OK)
748  retval = aarch64_do_restart_one(target, mode);
749 
750  return retval;
751 }
752 
753 /*
754  * prepare all but the current target for restart
755  */
756 static int aarch64_prep_restart_smp(struct target *target, int handle_breakpoints, struct target **p_first)
757 {
758  int retval = ERROR_OK;
759  struct target_list *head;
760  struct target *first = NULL;
761  uint64_t address;
762 
763  foreach_smp_target(head, target->smp_targets) {
764  struct target *curr = head->target;
765 
766  /* skip calling target */
767  if (curr == target)
768  continue;
769  if (!target_was_examined(curr))
770  continue;
771  if (curr->state != TARGET_HALTED)
772  continue;
773 
774  /* resume at current address, not in step mode */
775  retval = aarch64_restore_one(curr, 1, &address, handle_breakpoints, 0);
776  if (retval == ERROR_OK)
777  retval = aarch64_prepare_restart_one(curr);
778  if (retval != ERROR_OK) {
779  LOG_ERROR("failed to restore target %s", target_name(curr));
780  break;
781  }
782  /* remember the first valid target in the group */
783  if (!first)
784  first = curr;
785  }
786 
787  if (p_first)
788  *p_first = first;
789 
790  return retval;
791 }
792 
793 
794 static int aarch64_step_restart_smp(struct target *target)
795 {
796  int retval = ERROR_OK;
797  struct target_list *head;
798  struct target *first = NULL;
799 
800  LOG_DEBUG("%s", target_name(target));
801 
802  retval = aarch64_prep_restart_smp(target, 0, &first);
803  if (retval != ERROR_OK)
804  return retval;
805 
806  if (first)
807  retval = aarch64_do_restart_one(first, RESTART_LAZY);
808  if (retval != ERROR_OK) {
809  LOG_DEBUG("error restarting target %s", target_name(first));
810  return retval;
811  }
812 
813  int64_t then = timeval_ms();
814  for (;;) {
815  struct target *curr = target;
816  bool all_resumed = true;
817 
818  foreach_smp_target(head, target->smp_targets) {
819  uint32_t prsr;
820  int resumed;
821 
822  curr = head->target;
823 
824  if (curr == target)
825  continue;
826 
827  if (!target_was_examined(curr))
828  continue;
829 
830  retval = aarch64_check_state_one(curr,
831  PRSR_SDR, PRSR_SDR, &resumed, &prsr);
832  if (retval != ERROR_OK || (!resumed && (prsr & PRSR_HALT))) {
833  all_resumed = false;
834  break;
835  }
836 
837  if (curr->state != TARGET_RUNNING) {
838  curr->state = TARGET_RUNNING;
839  curr->debug_reason = DBG_REASON_NOTHALTED;
840  target_call_event_callbacks(curr, TARGET_EVENT_RESUMED);
841  }
842  }
843 
844  if (all_resumed)
845  break;
846 
847  if (timeval_ms() > then + 1000) {
848  LOG_ERROR("%s: timeout waiting for target resume", __func__);
849  retval = ERROR_TARGET_TIMEOUT;
850  break;
851  }
852  /*
853  * HACK: on Hi6220 there are 8 cores organized in 2 clusters
854  * and it looks like the CTI's are not connected by a common
855  * trigger matrix. It seems that we need to halt one core in each
856  * cluster explicitly. So if we find that a core has not halted
857  * yet, we trigger an explicit resume for the second cluster.
858  */
859  retval = aarch64_do_restart_one(curr, RESTART_LAZY);
860  if (retval != ERROR_OK)
861  break;
862 }
863 
864  return retval;
865 }
866 
867 static int aarch64_resume(struct target *target, int current,
868  target_addr_t address, int handle_breakpoints, int debug_execution)
869 {
870  int retval = 0;
871  uint64_t addr = address;
872 
873  struct armv8_common *armv8 = target_to_armv8(target);
874  armv8->last_run_control_op = ARMV8_RUNCONTROL_RESUME;
875 
876  if (target->state != TARGET_HALTED) {
877  LOG_TARGET_ERROR(target, "not halted");
878  return ERROR_TARGET_NOT_HALTED;
879  }
880 
881  /*
882  * If this target is part of a SMP group, prepare the others
883  * targets for resuming. This involves restoring the complete
884  * target register context and setting up CTI gates to accept
885  * resume events from the trigger matrix.
886  */
887  if (target->smp) {
888  retval = aarch64_prep_restart_smp(target, handle_breakpoints, NULL);
889  if (retval != ERROR_OK)
890  return retval;
891  }
892 
893  /* all targets prepared, restore and restart the current target */
894  retval = aarch64_restore_one(target, current, &addr, handle_breakpoints,
895  debug_execution);
896  if (retval == ERROR_OK)
897  retval = aarch64_restart_one(target, RESTART_SYNC);
898  if (retval != ERROR_OK)
899  return retval;
900 
901  if (target->smp) {
902  int64_t then = timeval_ms();
903  for (;;) {
904  struct target *curr = target;
905  struct target_list *head;
906  bool all_resumed = true;
907 
908  foreach_smp_target(head, target->smp_targets) {
909  uint32_t prsr;
910  int resumed;
911 
912  curr = head->target;
913  if (curr == target)
914  continue;
915  if (!target_was_examined(curr))
916  continue;
917 
918  retval = aarch64_check_state_one(curr,
919  PRSR_SDR, PRSR_SDR, &resumed, &prsr);
920  if (retval != ERROR_OK || (!resumed && (prsr & PRSR_HALT))) {
921  all_resumed = false;
922  break;
923  }
924 
925  if (curr->state != TARGET_RUNNING) {
926  curr->state = TARGET_RUNNING;
927  curr->debug_reason = DBG_REASON_NOTHALTED;
928  target_call_event_callbacks(curr, TARGET_EVENT_RESUMED);
929  }
930  }
931 
932  if (all_resumed)
933  break;
934 
935  if (timeval_ms() > then + 1000) {
936  LOG_ERROR("%s: timeout waiting for target %s to resume", __func__, target_name(curr));
937  retval = ERROR_TARGET_TIMEOUT;
938  break;
939  }
940 
941  /*
942  * HACK: on Hi6220 there are 8 cores organized in 2 clusters
943  * and it looks like the CTI's are not connected by a common
944  * trigger matrix. It seems that we need to halt one core in each
945  * cluster explicitly. So if we find that a core has not halted
946  * yet, we trigger an explicit resume for the second cluster.
947  */
948  retval = aarch64_do_restart_one(curr, RESTART_LAZY);
949  if (retval != ERROR_OK)
950  break;
951  }
952  }
953 
954  if (retval != ERROR_OK)
955  return retval;
956 
957  target->debug_reason = DBG_REASON_NOTHALTED;
958 
959  if (!debug_execution) {
960  target->state = TARGET_RUNNING;
961  target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
962  LOG_DEBUG("target resumed at 0x%" PRIx64, addr);
963  } else {
964  target->state = TARGET_DEBUG_RUNNING;
965  target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
966  LOG_DEBUG("target debug resumed at 0x%" PRIx64, addr);
967  }
968 
969  return ERROR_OK;
970 }
971 
972 static int aarch64_debug_entry(struct target *target)
973 {
974  int retval = ERROR_OK;
975  struct armv8_common *armv8 = target_to_armv8(target);
976  struct arm_dpm *dpm = &armv8->dpm;
977  enum arm_state core_state;
978  uint32_t dscr;
979 
980  /* make sure to clear all sticky errors */
981  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
982  armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
983  if (retval == ERROR_OK)
984  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
985  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
986  if (retval == ERROR_OK)
987  retval = arm_cti_ack_events(armv8->cti, CTI_TRIG(HALT));
988 
989  if (retval != ERROR_OK)
990  return retval;
991 
992  LOG_DEBUG("%s dscr = 0x%08" PRIx32, target_name(target), dscr);
993 
994  dpm->dscr = dscr;
995  core_state = armv8_dpm_get_core_state(dpm);
996  armv8_select_opcodes(armv8, core_state == ARM_STATE_AARCH64);
997  armv8_select_reg_access(armv8, core_state == ARM_STATE_AARCH64);
998 
999  /* close the CTI gate for all events */
1000  if (retval == ERROR_OK)
1001  retval = arm_cti_write_reg(armv8->cti, CTI_GATE, 0);
1002  /* discard async exceptions */
1003  if (retval == ERROR_OK)
1004  retval = dpm->instr_cpsr_sync(dpm);
1005  if (retval != ERROR_OK)
1006  return retval;
1007 
1008  /* Examine debug reason */
1009  armv8_dpm_report_dscr(dpm, dscr);
1010 
1011  /* save the memory address that triggered the watchpoint */
1012  if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1013  uint32_t tmp;
1014 
1015  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1016  armv8->debug_base + CPUV8_DBG_EDWAR0, &tmp);
1017  if (retval != ERROR_OK)
1018  return retval;
1019  target_addr_t edwar = tmp;
1020 
1021  /* EDWAR[63:32] has unknown content in aarch32 state */
1022  if (core_state == ARM_STATE_AARCH64) {
1023  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1024  armv8->debug_base + CPUV8_DBG_EDWAR1, &tmp);
1025  if (retval != ERROR_OK)
1026  return retval;
1027  edwar |= ((target_addr_t)tmp) << 32;
1028  }
1029 
1030  armv8->dpm.wp_addr = edwar;
1031  }
1032 
1033  retval = armv8_dpm_read_current_registers(&armv8->dpm);
1034 
1035  if (retval == ERROR_OK && armv8->post_debug_entry)
1036  retval = armv8->post_debug_entry(target);
1037 
1038  return retval;
1039 }
1040 
1041 static int aarch64_post_debug_entry(struct target *target)
1042 {
1043  struct aarch64_common *aarch64 = target_to_aarch64(target);
1044  struct armv8_common *armv8 = &aarch64->armv8_common;
1045  int retval;
1046  enum arm_mode target_mode = ARM_MODE_ANY;
1047  uint32_t instr;
1048 
1049  switch (armv8->arm.core_mode) {
1050  case ARMV8_64_EL0T:
1051  target_mode = ARMV8_64_EL1H;
1052  /* fall through */
1053  case ARMV8_64_EL1T:
1054  case ARMV8_64_EL1H:
1055  instr = ARMV8_MRS(SYSTEM_SCTLR_EL1, 0);
1056  break;
1057  case ARMV8_64_EL2T:
1058  case ARMV8_64_EL2H:
1059  instr = ARMV8_MRS(SYSTEM_SCTLR_EL2, 0);
1060  break;
1061  case ARMV8_64_EL3H:
1062  case ARMV8_64_EL3T:
1063  instr = ARMV8_MRS(SYSTEM_SCTLR_EL3, 0);
1064  break;
1065 
1066  case ARM_MODE_SVC:
1067  case ARM_MODE_ABT:
1068  case ARM_MODE_FIQ:
1069  case ARM_MODE_IRQ:
1070  case ARM_MODE_HYP:
1071  case ARM_MODE_UND:
1072  case ARM_MODE_SYS:
1073  case ARM_MODE_MON:
1074  instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
1075  break;
1076 
1077  default:
1078  LOG_ERROR("cannot read system control register in this mode: (%s : 0x%x)",
1079  armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
1080  return ERROR_FAIL;
1081  }
1082 
1083  if (target_mode != ARM_MODE_ANY)
1084  armv8_dpm_modeswitch(&armv8->dpm, target_mode);
1085 
1086  retval = armv8->dpm.instr_read_data_r0_64(&armv8->dpm, instr, &aarch64->system_control_reg);
1087  if (retval != ERROR_OK)
1088  return retval;
1089 
1090  if (target_mode != ARM_MODE_ANY)
1091  armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
1092 
1093  LOG_DEBUG("System_register: %8.8" PRIx64, aarch64->system_control_reg);
1094  aarch64->system_control_reg_curr = aarch64->system_control_reg;
1095 
1096  if (armv8->armv8_mmu.armv8_cache.info == -1) {
1097  armv8_identify_cache(armv8);
1098  armv8_read_mpidr(armv8);
1099  }
1100  if (armv8->is_armv8r) {
1101  armv8->armv8_mmu.mmu_enabled = 0;
1102  } else {
1103  armv8->armv8_mmu.mmu_enabled =
1104  (aarch64->system_control_reg & 0x1U) ? 1 : 0;
1105  }
1106  armv8->armv8_mmu.armv8_cache.d_u_cache_enabled =
1107  (aarch64->system_control_reg & 0x4U) ? 1 : 0;
1108  armv8->armv8_mmu.armv8_cache.i_cache_enabled =
1109  (aarch64->system_control_reg & 0x1000U) ? 1 : 0;
1110  return ERROR_OK;
1111 }
1112 
1113 /*
1114  * single-step a target
1115  */
1116 static int aarch64_step(struct target *target, int current, target_addr_t address,
1117  int handle_breakpoints)
1118 {
1119  struct armv8_common *armv8 = target_to_armv8(target);
1120  struct aarch64_common *aarch64 = target_to_aarch64(target);
1121  int saved_retval = ERROR_OK;
1122  int poll_retval;
1123  int retval;
1124  uint32_t edecr;
1125 
1126  armv8->last_run_control_op = ARMV8_RUNCONTROL_STEP;
1127 
1128  if (target->state != TARGET_HALTED) {
1129  LOG_TARGET_ERROR(target, "not halted");
1130  return ERROR_TARGET_NOT_HALTED;
1131  }
1132 
1133  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1134  armv8->debug_base + CPUV8_DBG_EDECR, &edecr);
1135  /* make sure EDECR.SS is not set when restoring the register */
1136 
1137  if (retval == ERROR_OK) {
1138  edecr &= ~0x4;
1139  /* set EDECR.SS to enter hardware step mode */
1140  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1141  armv8->debug_base + CPUV8_DBG_EDECR, (edecr|0x4));
1142  }
1143  /* disable interrupts while stepping */
1144  if (retval == ERROR_OK && aarch64->isrmasking_mode == AARCH64_ISRMASK_ON)
1145  retval = aarch64_set_dscr_bits(target, 0x3 << 22, 0x3 << 22);
1146  /* bail out if stepping setup has failed */
1147  if (retval != ERROR_OK)
1148  return retval;
1149 
1150  if (target->smp && (current == 1)) {
1151  /*
1152  * isolate current target so that it doesn't get resumed
1153  * together with the others
1154  */
1155  retval = arm_cti_gate_channel(armv8->cti, 1);
1156  /* resume all other targets in the group */
1157  if (retval == ERROR_OK)
1158  retval = aarch64_step_restart_smp(target);
1159  if (retval != ERROR_OK) {
1160  LOG_ERROR("Failed to restart non-stepping targets in SMP group");
1161  return retval;
1162  }
1163  LOG_DEBUG("Restarted all non-stepping targets in SMP group");
1164  }
1165 
1166  /* all other targets running, restore and restart the current target */
1167  retval = aarch64_restore_one(target, current, &address, 0, 0);
1168  if (retval == ERROR_OK)
1169  retval = aarch64_restart_one(target, RESTART_LAZY);
1170 
1171  if (retval != ERROR_OK)
1172  return retval;
1173 
1174  LOG_DEBUG("target step-resumed at 0x%" PRIx64, address);
1175  if (!handle_breakpoints)
1176  target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1177 
1178  int64_t then = timeval_ms();
1179  for (;;) {
1180  int stepped;
1181  uint32_t prsr;
1182 
1183  retval = aarch64_check_state_one(target,
1184  PRSR_SDR|PRSR_HALT, PRSR_SDR|PRSR_HALT, &stepped, &prsr);
1185  if (retval != ERROR_OK || stepped)
1186  break;
1187 
1188  if (timeval_ms() > then + 100) {
1189  LOG_ERROR("timeout waiting for target %s halt after step",
1190  target_name(target));
1191  retval = ERROR_TARGET_TIMEOUT;
1192  break;
1193  }
1194  }
1195 
1196  /*
1197  * At least on one SoC (Renesas R8A7795) stepping over a WFI instruction
1198  * causes a timeout. The core takes the step but doesn't complete it and so
1199  * debug state is never entered. However, you can manually halt the core
1200  * as an external debug even is also a WFI wakeup event.
1201  */
1202  if (retval == ERROR_TARGET_TIMEOUT)
1203  saved_retval = aarch64_halt_one(target, HALT_SYNC);
1204 
1205  poll_retval = aarch64_poll(target);
1206 
1207  /* restore EDECR */
1208  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1209  armv8->debug_base + CPUV8_DBG_EDECR, edecr);
1210  if (retval != ERROR_OK)
1211  return retval;
1212 
1213  /* restore interrupts */
1214  if (aarch64->isrmasking_mode == AARCH64_ISRMASK_ON) {
1215  retval = aarch64_set_dscr_bits(target, 0x3 << 22, 0);
1216  if (retval != ERROR_OK)
1217  return ERROR_OK;
1218  }
1219 
1220  if (saved_retval != ERROR_OK)
1221  return saved_retval;
1222 
1223  if (poll_retval != ERROR_OK)
1224  return poll_retval;
1225 
1226  return ERROR_OK;
1227 }
1228 
1229 static int aarch64_restore_context(struct target *target, bool bpwp)
1230 {
1231  struct armv8_common *armv8 = target_to_armv8(target);
1232  struct arm *arm = &armv8->arm;
1233 
1234  int retval;
1235 
1236  LOG_DEBUG("%s", target_name(target));
1237 
1238  if (armv8->pre_restore_context)
1239  armv8->pre_restore_context(target);
1240 
1241  retval = armv8_dpm_write_dirty_registers(&armv8->dpm, bpwp);
1242  if (retval == ERROR_OK) {
1243  /* registers are now invalid */
1244  register_cache_invalidate(arm->core_cache);
1245  register_cache_invalidate(arm->core_cache->next);
1246  }
1247 
1248  return retval;
1249 }
1250 
1251 /*
1252  * Cortex-A8 Breakpoint and watchpoint functions
1253  */
1254 
1255 /* Setup hardware Breakpoint Register Pair */
1256 static int aarch64_set_breakpoint(struct target *target,
1257  struct breakpoint *breakpoint, uint8_t matchmode)
1258 {
1259  int retval;
1260  int brp_i = 0;
1261  uint32_t control;
1262  uint8_t byte_addr_select = 0x0F;
1263  struct aarch64_common *aarch64 = target_to_aarch64(target);
1264  struct armv8_common *armv8 = &aarch64->armv8_common;
1265  struct aarch64_brp *brp_list = aarch64->brp_list;
1266 
1267  if (breakpoint->is_set) {
1268  LOG_WARNING("breakpoint already set");
1269  return ERROR_OK;
1270  }
1271 
1272  if (breakpoint->type == BKPT_HARD) {
1273  int64_t bpt_value;
1274  while (brp_list[brp_i].used && (brp_i < aarch64->brp_num))
1275  brp_i++;
1276  if (brp_i >= aarch64->brp_num) {
1277  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1278  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1279  }
1280  breakpoint_hw_set(breakpoint, brp_i);
1281  if (breakpoint->length == 2)
1282  byte_addr_select = (3 << (breakpoint->address & 0x02));
1283  control = ((matchmode & 0x7) << 20)
1284  | (1 << 13)
1285  | (byte_addr_select << 5)
1286  | (3 << 1) | 1;
1287  brp_list[brp_i].used = 1;
1288  brp_list[brp_i].value = breakpoint->address & 0xFFFFFFFFFFFFFFFCULL;
1289  brp_list[brp_i].control = control;
1290  bpt_value = brp_list[brp_i].value;
1291 
1292  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1293  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
1294  (uint32_t)(bpt_value & 0xFFFFFFFF));
1295  if (retval != ERROR_OK)
1296  return retval;
1297  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1298  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
1299  (uint32_t)(bpt_value >> 32));
1300  if (retval != ERROR_OK)
1301  return retval;
1302 
1303  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1304  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
1305  brp_list[brp_i].control);
1306  if (retval != ERROR_OK)
1307  return retval;
1308  LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
1309  brp_list[brp_i].control,
1310  brp_list[brp_i].value);
1311 
1312  } else if (breakpoint->type == BKPT_SOFT) {
1313  uint32_t opcode;
1314  uint8_t code[4];
1315 
1316  if (armv8_dpm_get_core_state(&armv8->dpm) == ARM_STATE_AARCH64) {
1317  opcode = ARMV8_HLT(11);
1318 
1319  if (breakpoint->length != 4)
1320  LOG_ERROR("bug: breakpoint length should be 4 in AArch64 mode");
1321  } else {
1330  opcode = (breakpoint->length == 4) ? ARMV8_HLT_A1(11) :
1331  (uint32_t) (ARMV8_HLT_T1(11) | ARMV8_HLT_T1(11) << 16);
1332 
1333  if (breakpoint->length == 3)
1334  breakpoint->length = 4;
1335  }
1336 
1337  buf_set_u32(code, 0, 32, opcode);
1338 
1339  retval = target_read_memory(target,
1340  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1341  breakpoint->length, 1,
1342  breakpoint->orig_instr);
1343  if (retval != ERROR_OK)
1344  return retval;
1345 
1346  armv8_cache_d_inner_flush_virt(armv8,
1347  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1348  breakpoint->length);
1349 
1350  retval = target_write_memory(target,
1351  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1352  breakpoint->length, 1, code);
1353  if (retval != ERROR_OK)
1354  return retval;
1355 
1356  armv8_cache_d_inner_flush_virt(armv8,
1357  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1358  breakpoint->length);
1359 
1360  armv8_cache_i_inner_inval_virt(armv8,
1361  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1362  breakpoint->length);
1363 
1364  breakpoint->is_set = true;
1365  }
1366 
1367  /* Ensure that halting debug mode is enable */
1368  retval = aarch64_set_dscr_bits(target, DSCR_HDE, DSCR_HDE);
1369  if (retval != ERROR_OK) {
1370  LOG_DEBUG("Failed to set DSCR.HDE");
1371  return retval;
1372  }
1373 
1374  return ERROR_OK;
1375 }
1376 
1377 static int aarch64_set_context_breakpoint(struct target *target,
1378  struct breakpoint *breakpoint, uint8_t matchmode)
1379 {
1380  int retval = ERROR_FAIL;
1381  int brp_i = 0;
1382  uint32_t control;
1383  uint8_t byte_addr_select = 0x0F;
1384  struct aarch64_common *aarch64 = target_to_aarch64(target);
1385  struct armv8_common *armv8 = &aarch64->armv8_common;
1386  struct aarch64_brp *brp_list = aarch64->brp_list;
1387 
1388  if (breakpoint->is_set) {
1389  LOG_WARNING("breakpoint already set");
1390  return retval;
1391  }
1392  /*check available context BRPs*/
1393  while ((brp_list[brp_i].used ||
1394  (brp_list[brp_i].type != BRP_CONTEXT)) && (brp_i < aarch64->brp_num))
1395  brp_i++;
1396 
1397  if (brp_i >= aarch64->brp_num) {
1398  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1399  return ERROR_FAIL;
1400  }
1401 
1402  breakpoint_hw_set(breakpoint, brp_i);
1403  control = ((matchmode & 0x7) << 20)
1404  | (1 << 13)
1405  | (byte_addr_select << 5)
1406  | (3 << 1) | 1;
1407  brp_list[brp_i].used = 1;
1408  brp_list[brp_i].value = (breakpoint->asid);
1409  brp_list[brp_i].control = control;
1410  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1411  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
1412  brp_list[brp_i].value);
1413  if (retval != ERROR_OK)
1414  return retval;
1415  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1416  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
1417  brp_list[brp_i].control);
1418  if (retval != ERROR_OK)
1419  return retval;
1420  LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
1421  brp_list[brp_i].control,
1422  brp_list[brp_i].value);
1423  return ERROR_OK;
1424 
1425 }
1426 
1427 static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
1428 {
1429  int retval = ERROR_FAIL;
1430  int brp_1 = 0; /* holds the contextID pair */
1431  int brp_2 = 0; /* holds the IVA pair */
1432  uint32_t control_ctx, control_iva;
1433  uint8_t ctx_byte_addr_select = 0x0F;
1434  uint8_t iva_byte_addr_select = 0x0F;
1435  uint8_t ctx_machmode = 0x03;
1436  uint8_t iva_machmode = 0x01;
1437  struct aarch64_common *aarch64 = target_to_aarch64(target);
1438  struct armv8_common *armv8 = &aarch64->armv8_common;
1439  struct aarch64_brp *brp_list = aarch64->brp_list;
1440 
1441  if (breakpoint->is_set) {
1442  LOG_WARNING("breakpoint already set");
1443  return retval;
1444  }
1445  /*check available context BRPs*/
1446  while ((brp_list[brp_1].used ||
1447  (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < aarch64->brp_num))
1448  brp_1++;
1449 
1450  LOG_DEBUG("brp(CTX) found num: %d", brp_1);
1451  if (brp_1 >= aarch64->brp_num) {
1452  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1453  return ERROR_FAIL;
1454  }
1455 
1456  while ((brp_list[brp_2].used ||
1457  (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < aarch64->brp_num))
1458  brp_2++;
1459 
1460  LOG_DEBUG("brp(IVA) found num: %d", brp_2);
1461  if (brp_2 >= aarch64->brp_num) {
1462  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1463  return ERROR_FAIL;
1464  }
1465 
1466  breakpoint_hw_set(breakpoint, brp_1);
1467  breakpoint->linked_brp = brp_2;
1468  control_ctx = ((ctx_machmode & 0x7) << 20)
1469  | (brp_2 << 16)
1470  | (0 << 14)
1471  | (ctx_byte_addr_select << 5)
1472  | (3 << 1) | 1;
1473  brp_list[brp_1].used = 1;
1474  brp_list[brp_1].value = (breakpoint->asid);
1475  brp_list[brp_1].control = control_ctx;
1476  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1477  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_1].brpn,
1478  brp_list[brp_1].value);
1479  if (retval != ERROR_OK)
1480  return retval;
1481  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1482  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_1].brpn,
1483  brp_list[brp_1].control);
1484  if (retval != ERROR_OK)
1485  return retval;
1486 
1487  control_iva = ((iva_machmode & 0x7) << 20)
1488  | (brp_1 << 16)
1489  | (1 << 13)
1490  | (iva_byte_addr_select << 5)
1491  | (3 << 1) | 1;
1492  brp_list[brp_2].used = 1;
1493  brp_list[brp_2].value = breakpoint->address & 0xFFFFFFFFFFFFFFFCULL;
1494  brp_list[brp_2].control = control_iva;
1495  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1496  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_2].brpn,
1497  brp_list[brp_2].value & 0xFFFFFFFF);
1498  if (retval != ERROR_OK)
1499  return retval;
1500  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1501  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_2].brpn,
1502  brp_list[brp_2].value >> 32);
1503  if (retval != ERROR_OK)
1504  return retval;
1505  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1506  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_2].brpn,
1507  brp_list[brp_2].control);
1508  if (retval != ERROR_OK)
1509  return retval;
1510 
1511  return ERROR_OK;
1512 }
1513 
1514 static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1515 {
1516  int retval;
1517  struct aarch64_common *aarch64 = target_to_aarch64(target);
1518  struct armv8_common *armv8 = &aarch64->armv8_common;
1519  struct aarch64_brp *brp_list = aarch64->brp_list;
1520 
1521  if (!breakpoint->is_set) {
1522  LOG_WARNING("breakpoint not set");
1523  return ERROR_OK;
1524  }
1525 
1526  if (breakpoint->type == BKPT_HARD) {
1527  if ((breakpoint->address != 0) && (breakpoint->asid != 0)) {
1528  int brp_i = breakpoint->number;
1529  int brp_j = breakpoint->linked_brp;
1530  if (brp_i >= aarch64->brp_num) {
1531  LOG_DEBUG("Invalid BRP number in breakpoint");
1532  return ERROR_OK;
1533  }
1534  LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
1535  brp_list[brp_i].control, brp_list[brp_i].value);
1536  brp_list[brp_i].used = 0;
1537  brp_list[brp_i].value = 0;
1538  brp_list[brp_i].control = 0;
1539  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1540  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
1541  brp_list[brp_i].control);
1542  if (retval != ERROR_OK)
1543  return retval;
1544  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1545  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
1546  (uint32_t)brp_list[brp_i].value);
1547  if (retval != ERROR_OK)
1548  return retval;
1549  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1550  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
1551  (uint32_t)brp_list[brp_i].value);
1552  if (retval != ERROR_OK)
1553  return retval;
1554  if ((brp_j < 0) || (brp_j >= aarch64->brp_num)) {
1555  LOG_DEBUG("Invalid BRP number in breakpoint");
1556  return ERROR_OK;
1557  }
1558  LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, brp_j,
1559  brp_list[brp_j].control, brp_list[brp_j].value);
1560  brp_list[brp_j].used = 0;
1561  brp_list[brp_j].value = 0;
1562  brp_list[brp_j].control = 0;
1563  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1564  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_j].brpn,
1565  brp_list[brp_j].control);
1566  if (retval != ERROR_OK)
1567  return retval;
1568  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1569  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_j].brpn,
1570  (uint32_t)brp_list[brp_j].value);
1571  if (retval != ERROR_OK)
1572  return retval;
1573  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1574  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_j].brpn,
1575  (uint32_t)brp_list[brp_j].value);
1576  if (retval != ERROR_OK)
1577  return retval;
1578 
1579  breakpoint->linked_brp = 0;
1580  breakpoint->is_set = false;
1581  return ERROR_OK;
1582 
1583  } else {
1584  int brp_i = breakpoint->number;
1585  if (brp_i >= aarch64->brp_num) {
1586  LOG_DEBUG("Invalid BRP number in breakpoint");
1587  return ERROR_OK;
1588  }
1589  LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, brp_i,
1590  brp_list[brp_i].control, brp_list[brp_i].value);
1591  brp_list[brp_i].used = 0;
1592  brp_list[brp_i].value = 0;
1593  brp_list[brp_i].control = 0;
1594  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1595  + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
1596  brp_list[brp_i].control);
1597  if (retval != ERROR_OK)
1598  return retval;
1599  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1600  + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
1601  brp_list[brp_i].value);
1602  if (retval != ERROR_OK)
1603  return retval;
1604 
1605  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1606  + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
1607  (uint32_t)brp_list[brp_i].value);
1608  if (retval != ERROR_OK)
1609  return retval;
1610  breakpoint->is_set = false;
1611  return ERROR_OK;
1612  }
1613  } else {
1614  /* restore original instruction (kept in target endianness) */
1615 
1616  armv8_cache_d_inner_flush_virt(armv8,
1617  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1618  breakpoint->length);
1619 
1620  if (breakpoint->length == 4) {
1621  retval = target_write_memory(target,
1622  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1623  4, 1, breakpoint->orig_instr);
1624  if (retval != ERROR_OK)
1625  return retval;
1626  } else {
1627  retval = target_write_memory(target,
1628  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1629  2, 1, breakpoint->orig_instr);
1630  if (retval != ERROR_OK)
1631  return retval;
1632  }
1633 
1634  armv8_cache_d_inner_flush_virt(armv8,
1635  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1636  breakpoint->length);
1637 
1638  armv8_cache_i_inner_inval_virt(armv8,
1639  breakpoint->address & 0xFFFFFFFFFFFFFFFEULL,
1640  breakpoint->length);
1641  }
1642  breakpoint->is_set = false;
1643 
1644  return ERROR_OK;
1645 }
1646 
1647 static int aarch64_add_breakpoint(struct target *target,
1648  struct breakpoint *breakpoint)
1649 {
1650  struct aarch64_common *aarch64 = target_to_aarch64(target);
1651 
1652  if ((breakpoint->type == BKPT_HARD) && (aarch64->brp_num_available < 1)) {
1653  LOG_INFO("no hardware breakpoint available");
1654  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1655  }
1656 
1657  if (breakpoint->type == BKPT_HARD)
1658  aarch64->brp_num_available--;
1659 
1660  return aarch64_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
1661 }
1662 
1663 static int aarch64_add_context_breakpoint(struct target *target,
1664  struct breakpoint *breakpoint)
1665 {
1666  struct aarch64_common *aarch64 = target_to_aarch64(target);
1667 
1668  if ((breakpoint->type == BKPT_HARD) && (aarch64->brp_num_available < 1)) {
1669  LOG_INFO("no hardware breakpoint available");
1670  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1671  }
1672 
1673  if (breakpoint->type == BKPT_HARD)
1674  aarch64->brp_num_available--;
1675 
1676  return aarch64_set_context_breakpoint(target, breakpoint, 0x02); /* asid match */
1677 }
1678 
1679 static int aarch64_add_hybrid_breakpoint(struct target *target,
1680  struct breakpoint *breakpoint)
1681 {
1682  struct aarch64_common *aarch64 = target_to_aarch64(target);
1683 
1684  if ((breakpoint->type == BKPT_HARD) && (aarch64->brp_num_available < 1)) {
1685  LOG_INFO("no hardware breakpoint available");
1686  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1687  }
1688 
1689  if (breakpoint->type == BKPT_HARD)
1690  aarch64->brp_num_available--;
1691 
1692  return aarch64_set_hybrid_breakpoint(target, breakpoint); /* ??? */
1693 }
1694 
1695 static int aarch64_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1696 {
1697  struct aarch64_common *aarch64 = target_to_aarch64(target);
1698 
1699 #if 0
1700 /* It is perfectly possible to remove breakpoints while the target is running */
1701  if (target->state != TARGET_HALTED) {
1702  LOG_WARNING("target not halted");
1703  return ERROR_TARGET_NOT_HALTED;
1704  }
1705 #endif
1706 
1707  if (breakpoint->is_set) {
1708  aarch64_unset_breakpoint(target, breakpoint);
1709  if (breakpoint->type == BKPT_HARD)
1710  aarch64->brp_num_available++;
1711  }
1712 
1713  return ERROR_OK;
1714 }
1715 
1716 /* Setup hardware Watchpoint Register Pair */
1717 static int aarch64_set_watchpoint(struct target *target,
1718  struct watchpoint *watchpoint)
1719 {
1720  int retval;
1721  int wp_i = 0;
1722  uint32_t control, offset, length;
1723  struct aarch64_common *aarch64 = target_to_aarch64(target);
1724  struct armv8_common *armv8 = &aarch64->armv8_common;
1725  struct aarch64_brp *wp_list = aarch64->wp_list;
1726 
1727  if (watchpoint->is_set) {
1728  LOG_WARNING("watchpoint already set");
1729  return ERROR_OK;
1730  }
1731 
1732  while (wp_list[wp_i].used && (wp_i < aarch64->wp_num))
1733  wp_i++;
1734  if (wp_i >= aarch64->wp_num) {
1735  LOG_ERROR("ERROR Can not find free Watchpoint Register Pair");
1736  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1737  }
1738 
1739  control = (1 << 0) /* enable */
1740  | (3 << 1) /* both user and privileged access */
1741  | (1 << 13); /* higher mode control */
1742 
1743  switch (watchpoint->rw) {
1744  case WPT_READ:
1745  control |= 1 << 3;
1746  break;
1747  case WPT_WRITE:
1748  control |= 2 << 3;
1749  break;
1750  case WPT_ACCESS:
1751  control |= 3 << 3;
1752  break;
1753  }
1754 
1755  /* Match up to 8 bytes. */
1756  offset = watchpoint->address & 7;
1757  length = watchpoint->length;
1758  if (offset + length > sizeof(uint64_t)) {
1759  length = sizeof(uint64_t) - offset;
1760  LOG_WARNING("Adjust watchpoint match inside 8-byte boundary");
1761  }
1762  for (; length > 0; offset++, length--)
1763  control |= (1 << offset) << 5;
1764 
1765  wp_list[wp_i].value = watchpoint->address & 0xFFFFFFFFFFFFFFF8ULL;
1766  wp_list[wp_i].control = control;
1767 
1768  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1769  + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].brpn,
1770  (uint32_t)(wp_list[wp_i].value & 0xFFFFFFFF));
1771  if (retval != ERROR_OK)
1772  return retval;
1773  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1774  + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].brpn,
1775  (uint32_t)(wp_list[wp_i].value >> 32));
1776  if (retval != ERROR_OK)
1777  return retval;
1778 
1779  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1780  + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].brpn,
1781  control);
1782  if (retval != ERROR_OK)
1783  return retval;
1784  LOG_DEBUG("wp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, wp_i,
1785  wp_list[wp_i].control, wp_list[wp_i].value);
1786 
1787  /* Ensure that halting debug mode is enable */
1788  retval = aarch64_set_dscr_bits(target, DSCR_HDE, DSCR_HDE);
1789  if (retval != ERROR_OK) {
1790  LOG_DEBUG("Failed to set DSCR.HDE");
1791  return retval;
1792  }
1793 
1794  wp_list[wp_i].used = 1;
1795  watchpoint_set(watchpoint, wp_i);
1796 
1797  return ERROR_OK;
1798 }
1799 
1800 /* Clear hardware Watchpoint Register Pair */
1801 static int aarch64_unset_watchpoint(struct target *target,
1802  struct watchpoint *watchpoint)
1803 {
1804  int retval;
1805  struct aarch64_common *aarch64 = target_to_aarch64(target);
1806  struct armv8_common *armv8 = &aarch64->armv8_common;
1807  struct aarch64_brp *wp_list = aarch64->wp_list;
1808 
1809  if (!watchpoint->is_set) {
1810  LOG_WARNING("watchpoint not set");
1811  return ERROR_OK;
1812  }
1813 
1814  int wp_i = watchpoint->number;
1815  if (wp_i >= aarch64->wp_num) {
1816  LOG_DEBUG("Invalid WP number in watchpoint");
1817  return ERROR_OK;
1818  }
1819  LOG_DEBUG("rwp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, wp_i,
1820  wp_list[wp_i].control, wp_list[wp_i].value);
1821  wp_list[wp_i].used = 0;
1822  wp_list[wp_i].value = 0;
1823  wp_list[wp_i].control = 0;
1824  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1825  + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].brpn,
1826  wp_list[wp_i].control);
1827  if (retval != ERROR_OK)
1828  return retval;
1829  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1830  + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].brpn,
1831  wp_list[wp_i].value);
1832  if (retval != ERROR_OK)
1833  return retval;
1834 
1835  retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1836  + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].brpn,
1837  (uint32_t)wp_list[wp_i].value);
1838  if (retval != ERROR_OK)
1839  return retval;
1840  watchpoint->is_set = false;
1841 
1842  return ERROR_OK;
1843 }
1844 
1845 static int aarch64_add_watchpoint(struct target *target,
1846  struct watchpoint *watchpoint)
1847 {
1848  int retval;
1849  struct aarch64_common *aarch64 = target_to_aarch64(target);
1850 
1851  if (aarch64->wp_num_available < 1) {
1852  LOG_INFO("no hardware watchpoint available");
1853  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1854  }
1855 
1856  retval = aarch64_set_watchpoint(target, watchpoint);
1857  if (retval == ERROR_OK)
1858  aarch64->wp_num_available--;
1859 
1860  return retval;
1861 }
1862 
1863 static int aarch64_remove_watchpoint(struct target *target,
1864  struct watchpoint *watchpoint)
1865 {
1866  struct aarch64_common *aarch64 = target_to_aarch64(target);
1867 
1868  if (watchpoint->is_set) {
1869  aarch64_unset_watchpoint(target, watchpoint);
1870  aarch64->wp_num_available++;
1871  }
1872 
1873  return ERROR_OK;
1874 }
1875 
1880 static int aarch64_hit_watchpoint(struct target *target,
1881  struct watchpoint **hit_watchpoint)
1882 {
1883  if (target->debug_reason != DBG_REASON_WATCHPOINT)
1884  return ERROR_FAIL;
1885 
1886  struct armv8_common *armv8 = target_to_armv8(target);
1887 
1888  target_addr_t exception_address;
1889  struct watchpoint *wp;
1890 
1891  exception_address = armv8->dpm.wp_addr;
1892 
1893  if (exception_address == 0xFFFFFFFF)
1894  return ERROR_FAIL;
1895 
1896  for (wp = target->watchpoints; wp; wp = wp->next)
1897  if (exception_address >= wp->address && exception_address < (wp->address + wp->length)) {
1898  *hit_watchpoint = wp;
1899  return ERROR_OK;
1900  }
1901 
1902  return ERROR_FAIL;
1903 }
1904 
1905 /*
1906  * Cortex-A8 Reset functions
1907  */
1908 
1909 static int aarch64_enable_reset_catch(struct target *target, bool enable)
1910 {
1911  struct armv8_common *armv8 = target_to_armv8(target);
1912  uint32_t edecr;
1913  int retval;
1914 
1915  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1916  armv8->debug_base + CPUV8_DBG_EDECR, &edecr);
1917  LOG_DEBUG("EDECR = 0x%08" PRIx32 ", enable=%d", edecr, enable);
1918  if (retval != ERROR_OK)
1919  return retval;
1920 
1921  if (enable)
1922  edecr |= ECR_RCE;
1923  else
1924  edecr &= ~ECR_RCE;
1925 
1926  return mem_ap_write_atomic_u32(armv8->debug_ap,
1927  armv8->debug_base + CPUV8_DBG_EDECR, edecr);
1928 }
1929 
1930 static int aarch64_clear_reset_catch(struct target *target)
1931 {
1932  struct armv8_common *armv8 = target_to_armv8(target);
1933  uint32_t edesr;
1934  int retval;
1935  bool was_triggered;
1936 
1937  /* check if Reset Catch debug event triggered as expected */
1938  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1939  armv8->debug_base + CPUV8_DBG_EDESR, &edesr);
1940  if (retval != ERROR_OK)
1941  return retval;
1942 
1943  was_triggered = !!(edesr & ESR_RC);
1944  LOG_DEBUG("Reset Catch debug event %s",
1945  was_triggered ? "triggered" : "NOT triggered!");
1946 
1947  if (was_triggered) {
1948  /* clear pending Reset Catch debug event */
1949  edesr &= ~ESR_RC;
1950  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1951  armv8->debug_base + CPUV8_DBG_EDESR, edesr);
1952  if (retval != ERROR_OK)
1953  return retval;
1954  }
1955 
1956  return ERROR_OK;
1957 }
1958 
1959 static int aarch64_assert_reset(struct target *target)
1960 {
1961  struct armv8_common *armv8 = target_to_armv8(target);
1962  enum reset_types reset_config = jtag_get_reset_config();
1963  int retval;
1964 
1965  LOG_DEBUG(" ");
1966 
1967  /* Issue some kind of warm reset. */
1968  if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
1969  target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1970  else if (reset_config & RESET_HAS_SRST) {
1971  bool srst_asserted = false;
1972 
1973  if (target->reset_halt && !(reset_config & RESET_SRST_PULLS_TRST)) {
1974  if (target_was_examined(target)) {
1975 
1976  if (reset_config & RESET_SRST_NO_GATING) {
1977  /*
1978  * SRST needs to be asserted *before* Reset Catch
1979  * debug event can be set up.
1980  */
1981  adapter_assert_reset();
1982  srst_asserted = true;
1983  }
1984 
1985  /* make sure to clear all sticky errors */
1986  mem_ap_write_atomic_u32(armv8->debug_ap,
1987  armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
1988 
1989  /* set up Reset Catch debug event to halt the CPU after reset */
1990  retval = aarch64_enable_reset_catch(target, true);
1991  if (retval != ERROR_OK)
1992  LOG_WARNING("%s: Error enabling Reset Catch debug event; the CPU will not halt immediately after reset!",
1993  target_name(target));
1994  } else {
1995  LOG_WARNING("%s: Target not examined, will not halt immediately after reset!",
1996  target_name(target));
1997  }
1998  }
1999 
2000  /* REVISIT handle "pulls" cases, if there's
2001  * hardware that needs them to work.
2002  */
2003  if (!srst_asserted)
2004  adapter_assert_reset();
2005  } else {
2006  LOG_ERROR("%s: how to reset?", target_name(target));
2007  return ERROR_FAIL;
2008  }
2009 
2010  /* registers are now invalid */
2011  if (armv8->arm.core_cache) {
2012  register_cache_invalidate(armv8->arm.core_cache);
2013  register_cache_invalidate(armv8->arm.core_cache->next);
2014  }
2015 
2016  target->state = TARGET_RESET;
2017 
2018  return ERROR_OK;
2019 }
2020 
2021 static int aarch64_deassert_reset(struct target *target)
2022 {
2023  int retval;
2024 
2025  LOG_DEBUG(" ");
2026 
2027  /* be certain SRST is off */
2028  adapter_deassert_reset();
2029 
2030  if (!target_was_examined(target))
2031  return ERROR_OK;
2032 
2033  retval = aarch64_init_debug_access(target);
2034  if (retval != ERROR_OK)
2035  return retval;
2036 
2037  retval = aarch64_poll(target);
2038  if (retval != ERROR_OK)
2039  return retval;
2040 
2041  if (target->reset_halt) {
2042  /* clear pending Reset Catch debug event */
2043  retval = aarch64_clear_reset_catch(target);
2044  if (retval != ERROR_OK)
2045  LOG_WARNING("%s: Clearing Reset Catch debug event failed",
2046  target_name(target));
2047 
2048  /* disable Reset Catch debug event */
2049  retval = aarch64_enable_reset_catch(target, false);
2050  if (retval != ERROR_OK)
2051  LOG_WARNING("%s: Disabling Reset Catch debug event failed",
2052  target_name(target));
2053 
2054  if (target->state != TARGET_HALTED) {
2055  LOG_WARNING("%s: ran after reset and before halt ...",
2056  target_name(target));
2057  if (target_was_examined(target)) {
2058  retval = aarch64_halt_one(target, HALT_LAZY);
2059  if (retval != ERROR_OK)
2060  return retval;
2061  } else {
2062  target->state = TARGET_UNKNOWN;
2063  }
2064  }
2065  }
2066 
2067  return ERROR_OK;
2068 }
2069 
2070 static int aarch64_write_cpu_memory_slow(struct target *target,
2071  uint32_t size, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
2072 {
2073  struct armv8_common *armv8 = target_to_armv8(target);
2074  struct arm_dpm *dpm = &armv8->dpm;
2075  struct arm *arm = &armv8->arm;
2076  int retval;
2077 
2078  if (size > 4 && arm->core_state != ARM_STATE_AARCH64) {
2079  LOG_ERROR("memory write sizes greater than 4 bytes is only supported for AArch64 state");
2080  return ERROR_FAIL;
2081  }
2082 
2083  armv8_reg_current(arm, 1)->dirty = true;
2084 
2085  /* change DCC to normal mode if necessary */
2086  if (*dscr & DSCR_MA) {
2087  *dscr &= ~DSCR_MA;
2088  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2089  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2090  if (retval != ERROR_OK)
2091  return retval;
2092  }
2093 
2094  while (count) {
2095  uint32_t opcode;
2096  uint64_t data;
2097 
2098  /* write the data to store into DTRRX (and DTRTX for 64-bit) */
2099  if (size == 1)
2100  data = *buffer;
2101  else if (size == 2)
2102  data = target_buffer_get_u16(target, buffer);
2103  else if (size == 4)
2104  data = target_buffer_get_u32(target, buffer);
2105  else
2106  data = target_buffer_get_u64(target, buffer);
2107 
2108  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2109  armv8->debug_base + CPUV8_DBG_DTRRX, (uint32_t)data);
2110  if (retval == ERROR_OK && size > 4)
2111  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2112  armv8->debug_base + CPUV8_DBG_DTRTX, (uint32_t)(data >> 32));
2113  if (retval != ERROR_OK)
2114  return retval;
2115 
2116  if (arm->core_state == ARM_STATE_AARCH64)
2117  if (size <= 4)
2118  retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 1));
2119  else
2120  retval = dpm->instr_execute(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 1));
2121  else
2122  retval = dpm->instr_execute(dpm, ARMV4_5_MRC(14, 0, 1, 0, 5, 0));
2123  if (retval != ERROR_OK)
2124  return retval;
2125 
2126  if (size == 1)
2127  opcode = armv8_opcode(armv8, ARMV8_OPC_STRB_IP);
2128  else if (size == 2)
2129  opcode = armv8_opcode(armv8, ARMV8_OPC_STRH_IP);
2130  else if (size == 4)
2131  opcode = armv8_opcode(armv8, ARMV8_OPC_STRW_IP);
2132  else
2133  opcode = armv8_opcode(armv8, ARMV8_OPC_STRD_IP);
2134 
2135  retval = dpm->instr_execute(dpm, opcode);
2136  if (retval != ERROR_OK)
2137  return retval;
2138 
2139  /* Advance */
2140  buffer += size;
2141  --count;
2142  }
2143 
2144  return ERROR_OK;
2145 }
2146 
2147 static int aarch64_write_cpu_memory_fast(struct target *target,
2148  uint32_t count, const uint8_t *buffer, uint32_t *dscr)
2149 {
2150  struct armv8_common *armv8 = target_to_armv8(target);
2151  struct arm *arm = &armv8->arm;
2152  int retval;
2153 
2154  armv8_reg_current(arm, 1)->dirty = true;
2155 
2156  /* Step 1.d - Change DCC to memory mode */
2157  *dscr |= DSCR_MA;
2158  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2159  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2160  if (retval != ERROR_OK)
2161  return retval;
2162 
2163 
2164  /* Step 2.a - Do the write */
2165  retval = mem_ap_write_buf_noincr(armv8->debug_ap,
2166  buffer, 4, count, armv8->debug_base + CPUV8_DBG_DTRRX);
2167  if (retval != ERROR_OK)
2168  return retval;
2169 
2170  /* Step 3.a - Switch DTR mode back to Normal mode */
2171  *dscr &= ~DSCR_MA;
2172  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2173  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2174  if (retval != ERROR_OK)
2175  return retval;
2176 
2177  return ERROR_OK;
2178 }
2179 
2180 static int aarch64_write_cpu_memory(struct target *target,
2181  uint64_t address, uint32_t size,
2182  uint32_t count, const uint8_t *buffer)
2183 {
2184  /* write memory through APB-AP */
2185  int retval = ERROR_COMMAND_SYNTAX_ERROR;
2186  struct armv8_common *armv8 = target_to_armv8(target);
2187  struct arm_dpm *dpm = &armv8->dpm;
2188  struct arm *arm = &armv8->arm;
2189  uint32_t dscr;
2190 
2191  if (target->state != TARGET_HALTED) {
2192  LOG_TARGET_ERROR(target, "not halted");
2193  return ERROR_TARGET_NOT_HALTED;
2194  }
2195 
2196  /* Mark register X0 as dirty, as it will be used
2197  * for transferring the data.
2198  * It will be restored automatically when exiting
2199  * debug mode
2200  */
2201  armv8_reg_current(arm, 0)->dirty = true;
2202 
2203  /* This algorithm comes from DDI0487A.g, chapter J9.1 */
2204 
2205  /* Read DSCR */
2206  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2207  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2208  if (retval != ERROR_OK)
2209  return retval;
2210 
2211  /* Set Normal access mode */
2212  dscr = (dscr & ~DSCR_MA);
2213  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2214  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
2215  if (retval != ERROR_OK)
2216  return retval;
2217 
2218  if (arm->core_state == ARM_STATE_AARCH64) {
2219  /* Write X0 with value 'address' using write procedure */
2220  /* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
2221  /* Step 1.c - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
2222  retval = dpm->instr_write_data_dcc_64(dpm,
2223  ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), address);
2224  } else {
2225  /* Write R0 with value 'address' using write procedure */
2226  /* Step 1.a+b - Write the address for read access into DBGDTRRX */
2227  /* Step 1.c - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
2228  retval = dpm->instr_write_data_dcc(dpm,
2229  ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address);
2230  }
2231 
2232  if (retval != ERROR_OK)
2233  return retval;
2234 
2235  if (size == 4 && (address % 4) == 0)
2236  retval = aarch64_write_cpu_memory_fast(target, count, buffer, &dscr);
2237  else
2238  retval = aarch64_write_cpu_memory_slow(target, size, count, buffer, &dscr);
2239 
2240  if (retval != ERROR_OK) {
2241  /* Unset DTR mode */
2242  mem_ap_read_atomic_u32(armv8->debug_ap,
2243  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2244  dscr &= ~DSCR_MA;
2245  mem_ap_write_atomic_u32(armv8->debug_ap,
2246  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
2247  }
2248 
2249  /* Check for sticky abort flags in the DSCR */
2250  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2251  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2252  if (retval != ERROR_OK)
2253  return retval;
2254 
2255  dpm->dscr = dscr;
2256  if (dscr & (DSCR_ERR | DSCR_SYS_ERROR_PEND)) {
2257  /* Abort occurred - clear it and exit */
2258  LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr);
2259  armv8_dpm_handle_exception(dpm, true);
2260  return ERROR_FAIL;
2261  }
2262 
2263  /* Done */
2264  return ERROR_OK;
2265 }
2266 
2267 static int aarch64_read_cpu_memory_slow(struct target *target,
2268  uint32_t size, uint32_t count, uint8_t *buffer, uint32_t *dscr)
2269 {
2270  struct armv8_common *armv8 = target_to_armv8(target);
2271  struct arm_dpm *dpm = &armv8->dpm;
2272  struct arm *arm = &armv8->arm;
2273  int retval;
2274 
2275  if (size > 4 && arm->core_state != ARM_STATE_AARCH64) {
2276  LOG_ERROR("memory read sizes greater than 4 bytes is only supported for AArch64 state");
2277  return ERROR_FAIL;
2278  }
2279 
2280  armv8_reg_current(arm, 1)->dirty = true;
2281 
2282  /* change DCC to normal mode (if necessary) */
2283  if (*dscr & DSCR_MA) {
2284  *dscr &= DSCR_MA;
2285  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2286  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2287  if (retval != ERROR_OK)
2288  return retval;
2289  }
2290 
2291  while (count) {
2292  uint32_t opcode;
2293  uint32_t lower;
2294  uint32_t higher;
2295  uint64_t data;
2296 
2297  if (size == 1)
2298  opcode = armv8_opcode(armv8, ARMV8_OPC_LDRB_IP);
2299  else if (size == 2)
2300  opcode = armv8_opcode(armv8, ARMV8_OPC_LDRH_IP);
2301  else if (size == 4)
2302  opcode = armv8_opcode(armv8, ARMV8_OPC_LDRW_IP);
2303  else
2304  opcode = armv8_opcode(armv8, ARMV8_OPC_LDRD_IP);
2305 
2306  retval = dpm->instr_execute(dpm, opcode);
2307  if (retval != ERROR_OK)
2308  return retval;
2309 
2310  if (arm->core_state == ARM_STATE_AARCH64)
2311  if (size <= 4)
2312  retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 1));
2313  else
2314  retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 1));
2315  else
2316  retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 1, 0, 5, 0));
2317  if (retval != ERROR_OK)
2318  return retval;
2319 
2320  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2321  armv8->debug_base + CPUV8_DBG_DTRTX, &lower);
2322  if (retval == ERROR_OK) {
2323  if (size > 4)
2324  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2325  armv8->debug_base + CPUV8_DBG_DTRRX, &higher);
2326  else
2327  higher = 0;
2328  }
2329  if (retval != ERROR_OK)
2330  return retval;
2331 
2332  data = (uint64_t)lower | (uint64_t)higher << 32;
2333 
2334  if (size == 1)
2335  *buffer = (uint8_t)data;
2336  else if (size == 2)
2337  target_buffer_set_u16(target, buffer, (uint16_t)data);
2338  else if (size == 4)
2339  target_buffer_set_u32(target, buffer, (uint32_t)data);
2340  else
2341  target_buffer_set_u64(target, buffer, data);
2342 
2343  /* Advance */
2344  buffer += size;
2345  --count;
2346  }
2347 
2348  return ERROR_OK;
2349 }
2350 
2351 static int aarch64_read_cpu_memory_fast(struct target *target,
2352  uint32_t count, uint8_t *buffer, uint32_t *dscr)
2353 {
2354  struct armv8_common *armv8 = target_to_armv8(target);
2355  struct arm_dpm *dpm = &armv8->dpm;
2356  struct arm *arm = &armv8->arm;
2357  int retval;
2358  uint32_t value;
2359 
2360  /* Mark X1 as dirty */
2361  armv8_reg_current(arm, 1)->dirty = true;
2362 
2363  if (arm->core_state == ARM_STATE_AARCH64) {
2364  /* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
2365  retval = dpm->instr_execute(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0));
2366  } else {
2367  /* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
2368  retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
2369  }
2370 
2371  if (retval != ERROR_OK)
2372  return retval;
2373 
2374  /* Step 1.e - Change DCC to memory mode */
2375  *dscr |= DSCR_MA;
2376  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2377  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2378  if (retval != ERROR_OK)
2379  return retval;
2380 
2381  /* Step 1.f - read DBGDTRTX and discard the value */
2382  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2383  armv8->debug_base + CPUV8_DBG_DTRTX, &value);
2384  if (retval != ERROR_OK)
2385  return retval;
2386 
2387  count--;
2388  /* Read the data - Each read of the DTRTX register causes the instruction to be reissued
2389  * Abort flags are sticky, so can be read at end of transactions
2390  *
2391  * This data is read in aligned to 32 bit boundary.
2392  */
2393 
2394  if (count) {
2395  /* Step 2.a - Loop n-1 times, each read of DBGDTRTX reads the data from [X0] and
2396  * increments X0 by 4. */
2397  retval = mem_ap_read_buf_noincr(armv8->debug_ap, buffer, 4, count,
2398  armv8->debug_base + CPUV8_DBG_DTRTX);
2399  if (retval != ERROR_OK)
2400  return retval;
2401  }
2402 
2403  /* Step 3.a - set DTR access mode back to Normal mode */
2404  *dscr &= ~DSCR_MA;
2405  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2406  armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
2407  if (retval != ERROR_OK)
2408  return retval;
2409 
2410  /* Step 3.b - read DBGDTRTX for the final value */
2411  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2412  armv8->debug_base + CPUV8_DBG_DTRTX, &value);
2413  if (retval != ERROR_OK)
2414  return retval;
2415 
2416  target_buffer_set_u32(target, buffer + count * 4, value);
2417  return retval;
2418 }
2419 
2420 static int aarch64_read_cpu_memory(struct target *target,
2421  target_addr_t address, uint32_t size,
2422  uint32_t count, uint8_t *buffer)
2423 {
2424  /* read memory through APB-AP */
2425  int retval = ERROR_COMMAND_SYNTAX_ERROR;
2426  struct armv8_common *armv8 = target_to_armv8(target);
2427  struct arm_dpm *dpm = &armv8->dpm;
2428  struct arm *arm = &armv8->arm;
2429  uint32_t dscr;
2430 
2431  LOG_DEBUG("Reading CPU memory address 0x%016" PRIx64 " size %" PRIu32 " count %" PRIu32,
2432  address, size, count);
2433 
2434  if (target->state != TARGET_HALTED) {
2435  LOG_TARGET_ERROR(target, "not halted");
2436  return ERROR_TARGET_NOT_HALTED;
2437  }
2438 
2439  /* Mark register X0 as dirty, as it will be used
2440  * for transferring the data.
2441  * It will be restored automatically when exiting
2442  * debug mode
2443  */
2444  armv8_reg_current(arm, 0)->dirty = true;
2445 
2446  /* Read DSCR */
2447  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2448  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2449  if (retval != ERROR_OK)
2450  return retval;
2451 
2452  /* This algorithm comes from DDI0487A.g, chapter J9.1 */
2453 
2454  /* Set Normal access mode */
2455  dscr &= ~DSCR_MA;
2456  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2457  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
2458  if (retval != ERROR_OK)
2459  return retval;
2460 
2461  if (arm->core_state == ARM_STATE_AARCH64) {
2462  /* Write X0 with value 'address' using write procedure */
2463  /* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
2464  /* Step 1.c - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
2465  retval = dpm->instr_write_data_dcc_64(dpm,
2466  ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), address);
2467  } else {
2468  /* Write R0 with value 'address' using write procedure */
2469  /* Step 1.a+b - Write the address for read access into DBGDTRRXint */
2470  /* Step 1.c - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
2471  retval = dpm->instr_write_data_dcc(dpm,
2472  ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address);
2473  }
2474 
2475  if (retval != ERROR_OK)
2476  return retval;
2477 
2478  if (size == 4 && (address % 4) == 0)
2479  retval = aarch64_read_cpu_memory_fast(target, count, buffer, &dscr);
2480  else
2481  retval = aarch64_read_cpu_memory_slow(target, size, count, buffer, &dscr);
2482 
2483  if (dscr & DSCR_MA) {
2484  dscr &= ~DSCR_MA;
2485  mem_ap_write_atomic_u32(armv8->debug_ap,
2486  armv8->debug_base + CPUV8_DBG_DSCR, dscr);
2487  }
2488 
2489  if (retval != ERROR_OK)
2490  return retval;
2491 
2492  /* Check for sticky abort flags in the DSCR */
2493  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2494  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2495  if (retval != ERROR_OK)
2496  return retval;
2497 
2498  dpm->dscr = dscr;
2499 
2500  if (dscr & (DSCR_ERR | DSCR_SYS_ERROR_PEND)) {
2501  /* Abort occurred - clear it and exit */
2502  LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr);
2503  armv8_dpm_handle_exception(dpm, true);
2504  return ERROR_FAIL;
2505  }
2506 
2507  /* Done */
2508  return ERROR_OK;
2509 }
2510 
2511 static int aarch64_read_phys_memory(struct target *target,
2512  target_addr_t address, uint32_t size,
2513  uint32_t count, uint8_t *buffer)
2514 {
2515  int retval = ERROR_COMMAND_SYNTAX_ERROR;
2516 
2517  if (count && buffer) {
2518  /* read memory through APB-AP */
2519  retval = aarch64_mmu_modify(target, 0);
2520  if (retval != ERROR_OK)
2521  return retval;
2522  retval = aarch64_read_cpu_memory(target, address, size, count, buffer);
2523  }
2524  return retval;
2525 }
2526 
2527 static int aarch64_read_memory(struct target *target, target_addr_t address,
2528  uint32_t size, uint32_t count, uint8_t *buffer)
2529 {
2530  int mmu_enabled = 0;
2531  int retval;
2532 
2533  /* determine if MMU was enabled on target stop */
2534  retval = aarch64_mmu(target, &mmu_enabled);
2535  if (retval != ERROR_OK)
2536  return retval;
2537 
2538  if (mmu_enabled) {
2539  /* enable MMU as we could have disabled it for phys access */
2540  retval = aarch64_mmu_modify(target, 1);
2541  if (retval != ERROR_OK)
2542  return retval;
2543  }
2544  return aarch64_read_cpu_memory(target, address, size, count, buffer);
2545 }
2546 
2547 static int aarch64_write_phys_memory(struct target *target,
2548  target_addr_t address, uint32_t size,
2549  uint32_t count, const uint8_t *buffer)
2550 {
2551  int retval = ERROR_COMMAND_SYNTAX_ERROR;
2552 
2553  if (count && buffer) {
2554  /* write memory through APB-AP */
2555  retval = aarch64_mmu_modify(target, 0);
2556  if (retval != ERROR_OK)
2557  return retval;
2558  return aarch64_write_cpu_memory(target, address, size, count, buffer);
2559  }
2560 
2561  return retval;
2562 }
2563 
2564 static int aarch64_write_memory(struct target *target, target_addr_t address,
2565  uint32_t size, uint32_t count, const uint8_t *buffer)
2566 {
2567  int mmu_enabled = 0;
2568  int retval;
2569 
2570  /* determine if MMU was enabled on target stop */
2571  retval = aarch64_mmu(target, &mmu_enabled);
2572  if (retval != ERROR_OK)
2573  return retval;
2574 
2575  if (mmu_enabled) {
2576  /* enable MMU as we could have disabled it for phys access */
2577  retval = aarch64_mmu_modify(target, 1);
2578  if (retval != ERROR_OK)
2579  return retval;
2580  }
2581  return aarch64_write_cpu_memory(target, address, size, count, buffer);
2582 }
2583 
2584 static int aarch64_handle_target_request(void *priv)
2585 {
2586  struct target *target = priv;
2587  struct armv8_common *armv8 = target_to_armv8(target);
2588  int retval;
2589 
2590  if (!target_was_examined(target))
2591  return ERROR_OK;
2592  if (!target->dbg_msg_enabled)
2593  return ERROR_OK;
2594 
2595  if (target->state == TARGET_RUNNING) {
2596  uint32_t request;
2597  uint32_t dscr;
2598  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2599  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2600 
2601  /* check if we have data */
2602  while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
2603  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2604  armv8->debug_base + CPUV8_DBG_DTRTX, &request);
2605  if (retval == ERROR_OK) {
2606  target_request(target, request);
2607  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2608  armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
2609  }
2610  }
2611  }
2612 
2613  return ERROR_OK;
2614 }
2615 
2616 static int aarch64_examine_first(struct target *target)
2617 {
2618  struct aarch64_common *aarch64 = target_to_aarch64(target);
2619  struct armv8_common *armv8 = &aarch64->armv8_common;
2620  struct adiv5_dap *swjdp = armv8->arm.dap;
2621  struct aarch64_private_config *pc = target->private_config;
2622  int i;
2623  int retval = ERROR_OK;
2624  uint64_t debug, ttypr;
2625  uint32_t cpuid;
2626  uint32_t tmp0, tmp1, tmp2, tmp3;
2627  debug = ttypr = cpuid = 0;
2628 
2629  if (!pc)
2630  return ERROR_FAIL;
2631 
2632  if (!armv8->debug_ap) {
2633  if (pc->adiv5_config.ap_num == DP_APSEL_INVALID) {
2634  /* Search for the APB-AB */
2635  retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv8->debug_ap);
2636  if (retval != ERROR_OK) {
2637  LOG_ERROR("Could not find APB-AP for debug access");
2638  return retval;
2639  }
2640  } else {
2641  armv8->debug_ap = dap_get_ap(swjdp, pc->adiv5_config.ap_num);
2642  if (!armv8->debug_ap) {
2643  LOG_ERROR("Cannot get AP");
2644  return ERROR_FAIL;
2645  }
2646  }
2647  }
2648 
2649  retval = mem_ap_init(armv8->debug_ap);
2650  if (retval != ERROR_OK) {
2651  LOG_ERROR("Could not initialize the APB-AP");
2652  return retval;
2653  }
2654 
2655  armv8->debug_ap->memaccess_tck = 10;
2656 
2657  if (!target->dbgbase_set) {
2658  /* Lookup Processor DAP */
2659  retval = dap_lookup_cs_component(armv8->debug_ap, ARM_CS_C9_DEVTYPE_CORE_DEBUG,
2660  &armv8->debug_base, target->coreid);
2661  if (retval != ERROR_OK)
2662  return retval;
2663  LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT,
2664  target->coreid, armv8->debug_base);
2665  } else
2666  armv8->debug_base = target->dbgbase;
2667 
2668  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2669  armv8->debug_base + CPUV8_DBG_OSLAR, 0);
2670  if (retval != ERROR_OK) {
2671  LOG_DEBUG("Examine %s failed", "oslock");
2672  return retval;
2673  }
2674 
2675  retval = mem_ap_read_u32(armv8->debug_ap,
2676  armv8->debug_base + CPUV8_DBG_MAINID0, &cpuid);
2677  if (retval != ERROR_OK) {
2678  LOG_DEBUG("Examine %s failed", "CPUID");
2679  return retval;
2680  }
2681 
2682  retval = mem_ap_read_u32(armv8->debug_ap,
2683  armv8->debug_base + CPUV8_DBG_MEMFEATURE0, &tmp0);
2684  retval += mem_ap_read_u32(armv8->debug_ap,
2685  armv8->debug_base + CPUV8_DBG_MEMFEATURE0 + 4, &tmp1);
2686  if (retval != ERROR_OK) {
2687  LOG_DEBUG("Examine %s failed", "Memory Model Type");
2688  return retval;
2689  }
2690  retval = mem_ap_read_u32(armv8->debug_ap,
2691  armv8->debug_base + CPUV8_DBG_DBGFEATURE0, &tmp2);
2692  retval += mem_ap_read_u32(armv8->debug_ap,
2693  armv8->debug_base + CPUV8_DBG_DBGFEATURE0 + 4, &tmp3);
2694  if (retval != ERROR_OK) {
2695  LOG_DEBUG("Examine %s failed", "ID_AA64DFR0_EL1");
2696  return retval;
2697  }
2698 
2699  retval = dap_run(armv8->debug_ap->dap);
2700  if (retval != ERROR_OK) {
2701  LOG_ERROR("%s: examination failed\n", target_name(target));
2702  return retval;
2703  }
2704 
2705  ttypr |= tmp1;
2706  ttypr = (ttypr << 32) | tmp0;
2707  debug |= tmp3;
2708  debug = (debug << 32) | tmp2;
2709 
2710  LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
2711  LOG_DEBUG("ttypr = 0x%08" PRIx64, ttypr);
2712  LOG_DEBUG("debug = 0x%08" PRIx64, debug);
2713 
2714  if (!pc->cti) {
2715  LOG_TARGET_ERROR(target, "CTI not specified");
2716  return ERROR_FAIL;
2717  }
2718 
2719  armv8->cti = pc->cti;
2720 
2721  retval = aarch64_dpm_setup(aarch64, debug);
2722  if (retval != ERROR_OK)
2723  return retval;
2724 
2725  /* Setup Breakpoint Register Pairs */
2726  aarch64->brp_num = (uint32_t)((debug >> 12) & 0x0F) + 1;
2727  aarch64->brp_num_context = (uint32_t)((debug >> 28) & 0x0F) + 1;
2728  aarch64->brp_num_available = aarch64->brp_num;
2729  aarch64->brp_list = calloc(aarch64->brp_num, sizeof(struct aarch64_brp));
2730  for (i = 0; i < aarch64->brp_num; i++) {
2731  aarch64->brp_list[i].used = 0;
2732  if (i < (aarch64->brp_num-aarch64->brp_num_context))
2733  aarch64->brp_list[i].type = BRP_NORMAL;
2734  else
2735  aarch64->brp_list[i].type = BRP_CONTEXT;
2736  aarch64->brp_list[i].value = 0;
2737  aarch64->brp_list[i].control = 0;
2738  aarch64->brp_list[i].brpn = i;
2739  }
2740 
2741  /* Setup Watchpoint Register Pairs */
2742  aarch64->wp_num = (uint32_t)((debug >> 20) & 0x0F) + 1;
2743  aarch64->wp_num_available = aarch64->wp_num;
2744  aarch64->wp_list = calloc(aarch64->wp_num, sizeof(struct aarch64_brp));
2745  for (i = 0; i < aarch64->wp_num; i++) {
2746  aarch64->wp_list[i].used = 0;
2747  aarch64->wp_list[i].type = BRP_NORMAL;
2748  aarch64->wp_list[i].value = 0;
2749  aarch64->wp_list[i].control = 0;
2750  aarch64->wp_list[i].brpn = i;
2751  }
2752 
2753  LOG_DEBUG("Configured %i hw breakpoints, %i watchpoints",
2754  aarch64->brp_num, aarch64->wp_num);
2755 
2756  target->state = TARGET_UNKNOWN;
2757  target->debug_reason = DBG_REASON_NOTHALTED;
2758  aarch64->isrmasking_mode = AARCH64_ISRMASK_ON;
2759  target_set_examined(target);
2760  return ERROR_OK;
2761 }
2762 
2763 static int aarch64_examine(struct target *target)
2764 {
2765  int retval = ERROR_OK;
2766 
2767  /* don't re-probe hardware after each reset */
2768  if (!target_was_examined(target))
2769  retval = aarch64_examine_first(target);
2770 
2771  /* Configure core debug access */
2772  if (retval == ERROR_OK)
2773  retval = aarch64_init_debug_access(target);
2774 
2775  if (retval == ERROR_OK)
2776  retval = aarch64_poll(target);
2777 
2778  return retval;
2779 }
2780 
2781 /*
2782  * Cortex-A8 target creation and initialization
2783  */
2784 
2785 static int aarch64_init_target(struct command_context *cmd_ctx,
2786  struct target *target)
2787 {
2788  /* examine_first() does a bunch of this */
2789  arm_semihosting_init(target);
2790  return ERROR_OK;
2791 }
2792 
2793 static int aarch64_init_arch_info(struct target *target,
2794  struct aarch64_common *aarch64, struct adiv5_dap *dap)
2795 {
2796  struct armv8_common *armv8 = &aarch64->armv8_common;
2797 
2798  /* Setup struct aarch64_common */
2799  aarch64->common_magic = AARCH64_COMMON_MAGIC;
2800  armv8->arm.dap = dap;
2801 
2802  /* register arch-specific functions */
2803  armv8->examine_debug_reason = NULL;
2804  armv8->post_debug_entry = aarch64_post_debug_entry;
2805  armv8->pre_restore_context = NULL;
2806  armv8->armv8_mmu.read_physical_memory = aarch64_read_phys_memory;
2807 
2808  armv8_init_arch_info(target, armv8);
2809  target_register_timer_callback(aarch64_handle_target_request, 1,
2810  TARGET_TIMER_TYPE_PERIODIC, target);
2811 
2812  return ERROR_OK;
2813 }
2814 
2815 static int armv8r_target_create(struct target *target, Jim_Interp *interp)
2816 {
2817  struct aarch64_private_config *pc = target->private_config;
2818  struct aarch64_common *aarch64;
2819 
2820  if (adiv5_verify_config(&pc->adiv5_config) != ERROR_OK)
2821  return ERROR_FAIL;
2822 
2823  aarch64 = calloc(1, sizeof(struct aarch64_common));
2824  if (!aarch64) {
2825  LOG_ERROR("Out of memory");
2826  return ERROR_FAIL;
2827  }
2828 
2829  aarch64->armv8_common.is_armv8r = true;
2830 
2831  return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap);
2832 }
2833 
2834 static int aarch64_target_create(struct target *target, Jim_Interp *interp)
2835 {
2836  struct aarch64_private_config *pc = target->private_config;
2837  struct aarch64_common *aarch64;
2838 
2839  if (adiv5_verify_config(&pc->adiv5_config) != ERROR_OK)
2840  return ERROR_FAIL;
2841 
2842  aarch64 = calloc(1, sizeof(struct aarch64_common));
2843  if (!aarch64) {
2844  LOG_ERROR("Out of memory");
2845  return ERROR_FAIL;
2846  }
2847 
2848  aarch64->armv8_common.is_armv8r = false;
2849 
2850  return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap);
2851 }
2852 
2853 static void aarch64_deinit_target(struct target *target)
2854 {
2855  struct aarch64_common *aarch64 = target_to_aarch64(target);
2856  struct armv8_common *armv8 = &aarch64->armv8_common;
2857  struct arm_dpm *dpm = &armv8->dpm;
2858 
2859  if (armv8->debug_ap)
2860  dap_put_ap(armv8->debug_ap);
2861 
2862  armv8_free_reg_cache(target);
2863  free(aarch64->brp_list);
2864  free(dpm->dbp);
2865  free(dpm->dwp);
2866  free(target->private_config);
2867  free(aarch64);
2868 }
2869 
2870 static int aarch64_mmu(struct target *target, int *enabled)
2871 {
2872  struct aarch64_common *aarch64 = target_to_aarch64(target);
2873  struct armv8_common *armv8 = &aarch64->armv8_common;
2874  if (target->state != TARGET_HALTED) {
2875  LOG_TARGET_ERROR(target, "not halted");
2876  return ERROR_TARGET_NOT_HALTED;
2877  }
2878  if (armv8->is_armv8r)
2879  *enabled = 0;
2880  else
2881  *enabled = target_to_aarch64(target)->armv8_common.armv8_mmu.mmu_enabled;
2882  return ERROR_OK;
2883 }
2884 
2885 static int aarch64_virt2phys(struct target *target, target_addr_t virt,
2886  target_addr_t *phys)
2887 {
2888  return armv8_mmu_translate_va_pa(target, virt, phys, 1);
2889 }
2890 
2891 /*
2892  * private target configuration items
2893  */
2894 enum aarch64_cfg_param {
2895  CFG_CTI,
2896 };
2897 
2898 static const struct jim_nvp nvp_config_opts[] = {
2899  { .name = "-cti", .value = CFG_CTI },
2900  { .name = NULL, .value = -1 }
2901 };
2902 
2903 static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *goi)
2904 {
2905  struct aarch64_private_config *pc;
2906  struct jim_nvp *n;
2907  int e;
2908 
2909  pc = (struct aarch64_private_config *)target->private_config;
2910  if (!pc) {
2911  pc = calloc(1, sizeof(struct aarch64_private_config));
2912  pc->adiv5_config.ap_num = DP_APSEL_INVALID;
2913  target->private_config = pc;
2914  }
2915 
2916  /*
2917  * Call adiv5_jim_configure() to parse the common DAP options
2918  * It will return JIM_CONTINUE if it didn't find any known
2919  * options, JIM_OK if it correctly parsed the topmost option
2920  * and JIM_ERR if an error occurred during parameter evaluation.
2921  * For JIM_CONTINUE, we check our own params.
2922  */
2923  e = adiv5_jim_configure_ext(target, goi, &pc->adiv5_config, ADI_CONFIGURE_DAP_COMPULSORY);
2924  if (e != JIM_CONTINUE)
2925  return e;
2926 
2927  /* parse config or cget options ... */
2928  if (goi->argc > 0) {
2929  Jim_SetEmptyResult(goi->interp);
2930 
2931  /* check first if topmost item is for us */
2932  e = jim_nvp_name2value_obj(goi->interp, nvp_config_opts,
2933  goi->argv[0], &n);
2934  if (e != JIM_OK)
2935  return JIM_CONTINUE;
2936 
2937  e = jim_getopt_obj(goi, NULL);
2938  if (e != JIM_OK)
2939  return e;
2940 
2941  switch (n->value) {
2942  case CFG_CTI: {
2943  if (goi->isconfigure) {
2944  Jim_Obj *o_cti;
2945  struct arm_cti *cti;
2946  e = jim_getopt_obj(goi, &o_cti);
2947  if (e != JIM_OK)
2948  return e;
2949  cti = cti_instance_by_jim_obj(goi->interp, o_cti);
2950  if (!cti) {
2951  Jim_SetResultString(goi->interp, "CTI name invalid!", -1);
2952  return JIM_ERR;
2953  }
2954  pc->cti = cti;
2955  } else {
2956  if (goi->argc != 0) {
2957  Jim_WrongNumArgs(goi->interp,
2958  goi->argc, goi->argv,
2959  "NO PARAMS");
2960  return JIM_ERR;
2961  }
2962 
2963  if (!pc || !pc->cti) {
2964  Jim_SetResultString(goi->interp, "CTI not configured", -1);
2965  return JIM_ERR;
2966  }
2967  Jim_SetResultString(goi->interp, arm_cti_name(pc->cti), -1);
2968  }
2969  break;
2970  }
2971 
2972  default:
2973  return JIM_CONTINUE;
2974  }
2975  }
2976 
2977  return JIM_OK;
2978 }
2979 
2980 COMMAND_HANDLER(aarch64_handle_cache_info_command)
2981 {
2982  struct target *target = get_current_target(CMD_CTX);
2983  struct armv8_common *armv8 = target_to_armv8(target);
2984 
2985  return armv8_handle_cache_info_command(CMD,
2986  &armv8->armv8_mmu.armv8_cache);
2987 }
2988 
2989 COMMAND_HANDLER(aarch64_handle_dbginit_command)
2990 {
2991  struct target *target = get_current_target(CMD_CTX);
2992  if (!target_was_examined(target)) {
2993  LOG_ERROR("target not examined yet");
2994  return ERROR_FAIL;
2995  }
2996 
2997  return aarch64_init_debug_access(target);
2998 }
2999 
3000 COMMAND_HANDLER(aarch64_handle_disassemble_command)
3001 {
3002  struct target *target = get_current_target(CMD_CTX);
3003 
3004  if (!target) {
3005  LOG_ERROR("No target selected");
3006  return ERROR_FAIL;
3007  }
3008 
3009  struct aarch64_common *aarch64 = target_to_aarch64(target);
3010 
3011  if (aarch64->common_magic != AARCH64_COMMON_MAGIC) {
3012  command_print(CMD, "current target isn't an AArch64");
3013  return ERROR_FAIL;
3014  }
3015 
3016  int count = 1;
3017  target_addr_t address;
3018 
3019  switch (CMD_ARGC) {
3020  case 2:
3021  COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
3022  /* FALL THROUGH */
3023  case 1:
3024  COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
3025  break;
3026  default:
3027  return ERROR_COMMAND_SYNTAX_ERROR;
3028  }
3029 
3030  return a64_disassemble(CMD, target, address, count);
3031 }
3032 
3033 COMMAND_HANDLER(aarch64_mask_interrupts_command)
3034 {
3035  struct target *target = get_current_target(CMD_CTX);
3036  struct aarch64_common *aarch64 = target_to_aarch64(target);
3037 
3038  static const struct nvp nvp_maskisr_modes[] = {
3039  { .name = "off", .value = AARCH64_ISRMASK_OFF },
3040  { .name = "on", .value = AARCH64_ISRMASK_ON },
3041  { .name = NULL, .value = -1 },
3042  };
3043  const struct nvp *n;
3044 
3045  if (CMD_ARGC > 0) {
3046  n = nvp_name2value(nvp_maskisr_modes, CMD_ARGV[0]);
3047  if (!n->name) {
3048  LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV[0]);
3049  return ERROR_COMMAND_SYNTAX_ERROR;
3050  }
3051 
3052  aarch64->isrmasking_mode = n->value;
3053  }
3054 
3055  n = nvp_value2name(nvp_maskisr_modes, aarch64->isrmasking_mode);
3056  command_print(CMD, "aarch64 interrupt mask %s", n->name);
3057 
3058  return ERROR_OK;
3059 }
3060 
3061 COMMAND_HANDLER(aarch64_mcrmrc_command)
3062 {
3063  bool is_mcr = false;
3064  unsigned int arg_cnt = 5;
3065 
3066  if (!strcmp(CMD_NAME, "mcr")) {
3067  is_mcr = true;
3068  arg_cnt = 6;
3069  }
3070 
3071  if (arg_cnt != CMD_ARGC)
3072  return ERROR_COMMAND_SYNTAX_ERROR;
3073 
3074  struct target *target = get_current_target(CMD_CTX);
3075  if (!target) {
3076  command_print(CMD, "no current target");
3077  return ERROR_FAIL;
3078  }
3079  if (!target_was_examined(target)) {
3080  command_print(CMD, "%s: not yet examined", target_name(target));
3081  return ERROR_TARGET_NOT_EXAMINED;
3082  }
3083 
3084  struct arm *arm = target_to_arm(target);
3085  if (!is_arm(arm)) {
3086  command_print(CMD, "%s: not an ARM", target_name(target));
3087  return ERROR_FAIL;
3088  }
3089 
3090  if (target->state != TARGET_HALTED) {
3091  command_print(CMD, "Error: [%s] not halted", target_name(target));
3092  return ERROR_TARGET_NOT_HALTED;
3093  }
3094 
3095  if (arm->core_state == ARM_STATE_AARCH64) {
3096  command_print(CMD, "%s: not 32-bit arm target", target_name(target));
3097  return ERROR_FAIL;
3098  }
3099 
3100  int cpnum;
3101  uint32_t op1;
3102  uint32_t op2;
3103  uint32_t crn;
3104  uint32_t crm;
3105  uint32_t value;
3106 
3107  /* NOTE: parameter sequence matches ARM instruction set usage:
3108  * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
3109  * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
3110  * The "rX" is necessarily omitted; it uses Tcl mechanisms.
3111  */
3112  COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cpnum);
3113  if (cpnum & ~0xf) {
3114  command_print(CMD, "coprocessor %d out of range", cpnum);
3115  return ERROR_COMMAND_ARGUMENT_INVALID;
3116  }
3117 
3118  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], op1);
3119  if (op1 & ~0x7) {
3120  command_print(CMD, "op1 %d out of range", op1);
3121  return ERROR_COMMAND_ARGUMENT_INVALID;
3122  }
3123 
3124  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], crn);
3125  if (crn & ~0xf) {
3126  command_print(CMD, "CRn %d out of range", crn);
3127  return ERROR_COMMAND_ARGUMENT_INVALID;
3128  }
3129 
3130  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], crm);
3131  if (crm & ~0xf) {
3132  command_print(CMD, "CRm %d out of range", crm);
3133  return ERROR_COMMAND_ARGUMENT_INVALID;
3134  }
3135 
3136  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], op2);
3137  if (op2 & ~0x7) {
3138  command_print(CMD, "op2 %d out of range", op2);
3139  return ERROR_COMMAND_ARGUMENT_INVALID;
3140  }
3141 
3142  if (is_mcr) {
3143  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[5], value);
3144 
3145  /* NOTE: parameters reordered! */
3146  /* ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2) */
3147  int retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value);
3148  if (retval != ERROR_OK)
3149  return retval;
3150  } else {
3151  value = 0;
3152  /* NOTE: parameters reordered! */
3153  /* ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2) */
3154  int retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value);
3155  if (retval != ERROR_OK)
3156  return retval;
3157 
3158  command_print(CMD, "0x%" PRIx32, value);
3159  }
3160 
3161  return ERROR_OK;
3162 }
3163 
3164 static const struct command_registration aarch64_exec_command_handlers[] = {
3165  {
3166  .name = "cache_info",
3167  .handler = aarch64_handle_cache_info_command,
3168  .mode = COMMAND_EXEC,
3169  .help = "display information about target caches",
3170  .usage = "",
3171  },
3172  {
3173  .name = "dbginit",
3174  .handler = aarch64_handle_dbginit_command,
3175  .mode = COMMAND_EXEC,
3176  .help = "Initialize core debug",
3177  .usage = "",
3178  },
3179  {
3180  .name = "disassemble",
3181  .handler = aarch64_handle_disassemble_command,
3182  .mode = COMMAND_EXEC,
3183  .help = "Disassemble instructions",
3184  .usage = "address [count]",
3185  },
3186  {
3187  .name = "maskisr",
3188  .handler = aarch64_mask_interrupts_command,
3189  .mode = COMMAND_ANY,
3190  .help = "mask aarch64 interrupts during single-step",
3191  .usage = "['on'|'off']",
3192  },
3193  {
3194  .name = "mcr",
3195  .mode = COMMAND_EXEC,
3196  .handler = aarch64_mcrmrc_command,
3197  .help = "write coprocessor register",
3198  .usage = "cpnum op1 CRn CRm op2 value",
3199  },
3200  {
3201  .name = "mrc",
3202  .mode = COMMAND_EXEC,
3203  .handler = aarch64_mcrmrc_command,
3204  .help = "read coprocessor register",
3205  .usage = "cpnum op1 CRn CRm op2",
3206  },
3207  {
3208  .chain = smp_command_handlers,
3209  },
3210 
3211 
3212  COMMAND_REGISTRATION_DONE
3213 };
3214 
3215 static const struct command_registration aarch64_command_handlers[] = {
3216  {
3217  .name = "arm",
3218  .mode = COMMAND_ANY,
3219  .help = "ARM Command Group",
3220  .usage = "",
3221  .chain = semihosting_common_handlers
3222  },
3223  {
3224  .chain = armv8_command_handlers,
3225  },
3226  {
3227  .name = "aarch64",
3228  .mode = COMMAND_ANY,
3229  .help = "Aarch64 command group",
3230  .usage = "",
3231  .chain = aarch64_exec_command_handlers,
3232  },
3233  COMMAND_REGISTRATION_DONE
3234 };
3235 
3236 struct target_type aarch64_target = {
3237  .name = "aarch64",
3238 
3239  .poll = aarch64_poll,
3240  .arch_state = armv8_arch_state,
3241 
3242  .halt = aarch64_halt,
3243  .resume = aarch64_resume,
3244  .step = aarch64_step,
3245 
3246  .assert_reset = aarch64_assert_reset,
3247  .deassert_reset = aarch64_deassert_reset,
3248 
3249  /* REVISIT allow exporting VFP3 registers ... */
3250  .get_gdb_arch = armv8_get_gdb_arch,
3251  .get_gdb_reg_list = armv8_get_gdb_reg_list,
3252 
3253  .read_memory = aarch64_read_memory,
3254  .write_memory = aarch64_write_memory,
3255 
3256  .add_breakpoint = aarch64_add_breakpoint,
3257  .add_context_breakpoint = aarch64_add_context_breakpoint,
3258  .add_hybrid_breakpoint = aarch64_add_hybrid_breakpoint,
3259  .remove_breakpoint = aarch64_remove_breakpoint,
3260  .add_watchpoint = aarch64_add_watchpoint,
3261  .remove_watchpoint = aarch64_remove_watchpoint,
3262  .hit_watchpoint = aarch64_hit_watchpoint,
3263 
3264  .commands = aarch64_command_handlers,
3265  .target_create = aarch64_target_create,
3266  .target_jim_configure = aarch64_jim_configure,
3267  .init_target = aarch64_init_target,
3268  .deinit_target = aarch64_deinit_target,
3269  .examine = aarch64_examine,
3270 
3271  .read_phys_memory = aarch64_read_phys_memory,
3272  .write_phys_memory = aarch64_write_phys_memory,
3273  .mmu = aarch64_mmu,
3274  .virt2phys = aarch64_virt2phys,
3275 };
3276 
3277 struct target_type armv8r_target = {
3278  .name = "armv8r",
3279 
3280  .poll = aarch64_poll,
3281  .arch_state = armv8_arch_state,
3282 
3283  .halt = aarch64_halt,
3284  .resume = aarch64_resume,
3285  .step = aarch64_step,
3286 
3287  .assert_reset = aarch64_assert_reset,
3288  .deassert_reset = aarch64_deassert_reset,
3289 
3290  /* REVISIT allow exporting VFP3 registers ... */
3291  .get_gdb_arch = armv8_get_gdb_arch,
3292  .get_gdb_reg_list = armv8_get_gdb_reg_list,
3293 
3294  .read_memory = aarch64_read_phys_memory,
3295  .write_memory = aarch64_write_phys_memory,
3296 
3297  .add_breakpoint = aarch64_add_breakpoint,
3298  .add_context_breakpoint = aarch64_add_context_breakpoint,
3299  .add_hybrid_breakpoint = aarch64_add_hybrid_breakpoint,
3300  .remove_breakpoint = aarch64_remove_breakpoint,
3301  .add_watchpoint = aarch64_add_watchpoint,
3302  .remove_watchpoint = aarch64_remove_watchpoint,
3303  .hit_watchpoint = aarch64_hit_watchpoint,
3304 
3305  .commands = aarch64_command_handlers,
3306  .target_create = armv8r_target_create,
3307  .target_jim_configure = aarch64_jim_configure,
3308  .init_target = aarch64_init_target,
3309  .deinit_target = aarch64_deinit_target,
3310  .examine = aarch64_examine,
3311 };
a64_disassemble
int a64_disassemble(struct command_invocation *cmd, struct target *target, target_addr_t address, size_t count)
Definition: a64_disassembler.c:127
a64_disassembler.h
aarch64_write_cpu_memory_slow
static int aarch64_write_cpu_memory_slow(struct target *target, uint32_t size, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
Definition: aarch64.c:2070
aarch64_set_breakpoint
static int aarch64_set_breakpoint(struct target *target, struct breakpoint *breakpoint, uint8_t matchmode)
Definition: aarch64.c:1256
aarch64_unset_watchpoint
static int aarch64_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: aarch64.c:1801
aarch64_add_watchpoint
static int aarch64_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: aarch64.c:1845
COMMAND_HANDLER
COMMAND_HANDLER(aarch64_handle_cache_info_command)
Definition: aarch64.c:2980
aarch64_set_dscr_bits
static int aarch64_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
Definition: aarch64.c:288
aarch64_assert_reset
static int aarch64_assert_reset(struct target *target)
Definition: aarch64.c:1959
halt_mode
halt_mode
Definition: aarch64.c:32
HALT_SYNC
@ HALT_SYNC
Definition: aarch64.c:34
HALT_LAZY
@ HALT_LAZY
Definition: aarch64.c:33
aarch64_deinit_target
static void aarch64_deinit_target(struct target *target)
Definition: aarch64.c:2853
aarch64_prep_restart_smp
static int aarch64_prep_restart_smp(struct target *target, int handle_breakpoints, struct target **p_first)
Definition: aarch64.c:756
aarch64_add_context_breakpoint
static int aarch64_add_context_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1663
aarch64_write_phys_memory
static int aarch64_write_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: aarch64.c:2547
aarch64_restore_one
static int aarch64_restore_one(struct target *target, int current, uint64_t *address, int handle_breakpoints, int debug_execution)
Definition: aarch64.c:592
nvp_config_opts
static const struct jim_nvp nvp_config_opts[]
Definition: aarch64.c:2898
aarch64_resume
static int aarch64_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Definition: aarch64.c:867
aarch64_examine
static int aarch64_examine(struct target *target)
Definition: aarch64.c:2763
aarch64_exec_command_handlers
static const struct command_registration aarch64_exec_command_handlers[]
Definition: aarch64.c:3164
aarch64_add_breakpoint
static int aarch64_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1647
aarch64_read_prsr
static int aarch64_read_prsr(struct target *target, uint32_t *prsr)
Definition: aarch64.c:196
aarch64_set_context_breakpoint
static int aarch64_set_context_breakpoint(struct target *target, struct breakpoint *breakpoint, uint8_t matchmode)
Definition: aarch64.c:1377
aarch64_mmu_modify
static int aarch64_mmu_modify(struct target *target, int enable)
Definition: aarch64.c:123
aarch64_read_cpu_memory_fast
static int aarch64_read_cpu_memory_fast(struct target *target, uint32_t count, uint8_t *buffer, uint32_t *dscr)
Definition: aarch64.c:2351
aarch64_examine_first
static int aarch64_examine_first(struct target *target)
Definition: aarch64.c:2616
aarch64_poll
static int aarch64_poll(struct target *target)
Definition: aarch64.c:518
aarch64_init_target
static int aarch64_init_target(struct command_context *cmd_ctx, struct target *target)
Definition: aarch64.c:2785
aarch64_read_cpu_memory
static int aarch64_read_cpu_memory(struct target *target, uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: aarch64.c:2420
aarch64_target_create
static int aarch64_target_create(struct target *target, Jim_Interp *interp)
Definition: aarch64.c:2834
aarch64_prepare_restart_one
static int aarch64_prepare_restart_one(struct target *target)
prepare single target for restart
Definition: aarch64.c:652
aarch64_restore_context
static int aarch64_restore_context(struct target *target, bool bpwp)
Definition: aarch64.c:1229
aarch64_enable_reset_catch
static int aarch64_enable_reset_catch(struct target *target, bool enable)
Definition: aarch64.c:1909
aarch64_jim_configure
static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *goi)
Definition: aarch64.c:2903
aarch64_halt
static int aarch64_halt(struct target *target)
Definition: aarch64.c:581
update_halt_gdb
static int update_halt_gdb(struct target *target, enum target_debug_reason debug_reason)
Definition: aarch64.c:472
aarch64_mmu
static int aarch64_mmu(struct target *target, int *enabled)
Definition: aarch64.c:2870
aarch64_read_phys_memory
static int aarch64_read_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: aarch64.c:2511
aarch64_check_state_one
static int aarch64_check_state_one(struct target *target, uint32_t mask, uint32_t val, int *p_result, uint32_t *p_prsr)
Definition: aarch64.c:294
aarch64_restore_system_control_reg
static int aarch64_restore_system_control_reg(struct target *target)
Definition: aarch64.c:59
aarch64_write_cpu_memory_fast
static int aarch64_write_cpu_memory_fast(struct target *target, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
Definition: aarch64.c:2147
aarch64_set_watchpoint
static int aarch64_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: aarch64.c:1717
aarch64_remove_watchpoint
static int aarch64_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: aarch64.c:1863
aarch64_restart_one
static int aarch64_restart_one(struct target *target, enum restart_mode mode)
Definition: aarch64.c:740
aarch64_step_restart_smp
static int aarch64_step_restart_smp(struct target *target)
Definition: aarch64.c:794
aarch64_dap_write_memap_register_u32
static int aarch64_dap_write_memap_register_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: aarch64.c:261
aarch64_debug_entry
static int aarch64_debug_entry(struct target *target)
Definition: aarch64.c:972
aarch64_prepare_halt_smp
static int aarch64_prepare_halt_smp(struct target *target, bool exc_target, struct target **p_first)
Definition: aarch64.c:335
aarch64_target
struct target_type aarch64_target
Definition: aarch64.c:3236
aarch64_command_handlers
static const struct command_registration aarch64_command_handlers[]
Definition: aarch64.c:3215
aarch64_write_cpu_memory
static int aarch64_write_cpu_memory(struct target *target, uint64_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: aarch64.c:2180
aarch64_unset_breakpoint
static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1514
aarch64_virt2phys
static int aarch64_virt2phys(struct target *target, target_addr_t virt, target_addr_t *phys)
Definition: aarch64.c:2885
aarch64_handle_target_request
static int aarch64_handle_target_request(void *priv)
Definition: aarch64.c:2584
aarch64_clear_reset_catch
static int aarch64_clear_reset_catch(struct target *target)
Definition: aarch64.c:1930
aarch64_halt_one
static int aarch64_halt_one(struct target *target, enum halt_mode mode)
Definition: aarch64.c:380
aarch64_hit_watchpoint
static int aarch64_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
find out which watchpoint hits get exception address and compare the address to watchpoints
Definition: aarch64.c:1880
aarch64_step
static int aarch64_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
Definition: aarch64.c:1116
aarch64_cfg_param
aarch64_cfg_param
Definition: aarch64.c:2894
CFG_CTI
@ CFG_CTI
Definition: aarch64.c:2895
aarch64_deassert_reset
static int aarch64_deassert_reset(struct target *target)
Definition: aarch64.c:2021
armv8r_target_create
static int armv8r_target_create(struct target *target, Jim_Interp *interp)
Definition: aarch64.c:2815
aarch64_write_memory
static int aarch64_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: aarch64.c:2564
armv8r_target
struct target_type armv8r_target
Definition: aarch64.c:3277
aarch64_do_restart_one
static int aarch64_do_restart_one(struct target *target, enum restart_mode mode)
Definition: aarch64.c:698
aarch64_dpm_setup
static int aarch64_dpm_setup(struct aarch64_common *a8, uint64_t debug)
Definition: aarch64.c:273
aarch64_add_hybrid_breakpoint
static int aarch64_add_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1679
aarch64_wait_halt_one
static int aarch64_wait_halt_one(struct target *target)
Definition: aarch64.c:313
aarch64_read_cpu_memory_slow
static int aarch64_read_cpu_memory_slow(struct target *target, uint32_t size, uint32_t count, uint8_t *buffer, uint32_t *dscr)
Definition: aarch64.c:2267
aarch64_init_arch_info
static int aarch64_init_arch_info(struct target *target, struct aarch64_common *aarch64, struct adiv5_dap *dap)
Definition: aarch64.c:2793
aarch64_remove_breakpoint
static int aarch64_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1695
aarch64_set_hybrid_breakpoint
static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: aarch64.c:1427
aarch64_read_memory
static int aarch64_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: aarch64.c:2527
restart_mode
restart_mode
Definition: aarch64.c:27
RESTART_SYNC
@ RESTART_SYNC
Definition: aarch64.c:29
RESTART_LAZY
@ RESTART_LAZY
Definition: aarch64.c:28
aarch64_halt_smp
static int aarch64_halt_smp(struct target *target, bool exc_target)
Definition: aarch64.c:409
aarch64_post_debug_entry
static int aarch64_post_debug_entry(struct target *target)
Definition: aarch64.c:1041
aarch64_init_debug_access
static int aarch64_init_debug_access(struct target *target)
Definition: aarch64.c:213
target_to_aarch64
static struct aarch64_common * target_to_aarch64(struct target *target)
Definition: aarch64.h:64
BRP_CONTEXT
#define BRP_CONTEXT
Definition: aarch64.h:23
AARCH64_ISRMASK_ON
@ AARCH64_ISRMASK_ON
Definition: aarch64.h:29
AARCH64_ISRMASK_OFF
@ AARCH64_ISRMASK_OFF
Definition: aarch64.h:28
BRP_NORMAL
#define BRP_NORMAL
Definition: aarch64.h:22
AARCH64_COMMON_MAGIC
#define AARCH64_COMMON_MAGIC
Definition: aarch64.h:12
armv8_get_gdb_arch
const char * armv8_get_gdb_arch(const struct target *target)
Definition: armv8.c:1952
armv8_reg_current
struct reg * armv8_reg_current(struct arm *arm, unsigned int regnum)
Definition: armv8.c:1884
armv8_get_gdb_reg_list
int armv8_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: armv8.c:1958
is_arm
static bool is_arm(struct arm *arm)
Definition: arm.h:267
arm_mode
arm_mode
Represent state of an ARM core.
Definition: arm.h:82
ARM_MODE_IRQ
@ ARM_MODE_IRQ
Definition: arm.h:85
ARM_MODE_SYS
@ ARM_MODE_SYS
Definition: arm.h:92
ARM_MODE_HYP
@ ARM_MODE_HYP
Definition: arm.h:89
ARMV8_64_EL0T
@ ARMV8_64_EL0T
Definition: arm.h:98
ARMV8_64_EL3H
@ ARMV8_64_EL3H
Definition: arm.h:104
ARM_MODE_MON
@ ARM_MODE_MON
Definition: arm.h:87
ARMV8_64_EL3T
@ ARMV8_64_EL3T
Definition: arm.h:103
ARM_MODE_FIQ
@ ARM_MODE_FIQ
Definition: arm.h:84
ARM_MODE_UND
@ ARM_MODE_UND
Definition: arm.h:90
ARM_MODE_ANY
@ ARM_MODE_ANY
Definition: arm.h:106
ARMV8_64_EL1H
@ ARMV8_64_EL1H
Definition: arm.h:100
ARM_MODE_SVC
@ ARM_MODE_SVC
Definition: arm.h:86
ARMV8_64_EL2H
@ ARMV8_64_EL2H
Definition: arm.h:102
ARMV8_64_EL2T
@ ARMV8_64_EL2T
Definition: arm.h:101
ARMV8_64_EL1T
@ ARMV8_64_EL1T
Definition: arm.h:99
ARM_MODE_ABT
@ ARM_MODE_ABT
Definition: arm.h:88
target_to_arm
static struct arm * target_to_arm(const struct target *target)
Convert target handle to generic ARM target state handle.
Definition: arm.h:261
arm_state
arm_state
The PSR "T" and "J" bits define the mode of "classic ARM" cores.
Definition: arm.h:150
ARM_STATE_JAZELLE
@ ARM_STATE_JAZELLE
Definition: arm.h:153
ARM_STATE_THUMB
@ ARM_STATE_THUMB
Definition: arm.h:152
ARM_STATE_ARM
@ ARM_STATE_ARM
Definition: arm.h:151
ARM_STATE_AARCH64
@ ARM_STATE_AARCH64
Definition: arm.h:155
ARM_STATE_THUMB_EE
@ ARM_STATE_THUMB_EE
Definition: arm.h:154
dap_lookup_cs_component
int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type, target_addr_t *addr, int32_t core_id)
Definition: arm_adi_v5.c:2287
mem_ap_read_buf_noincr
int mem_ap_read_buf_noincr(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:734
adiv5_verify_config
int adiv5_verify_config(struct adiv5_private_config *pc)
Definition: arm_adi_v5.c:2484
mem_ap_read_u32
int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Asynchronous (queued) read of a word from memory or a system register.
Definition: arm_adi_v5.c:237
dap_find_get_ap
int dap_find_get_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
Definition: arm_adi_v5.c:1107
mem_ap_write_buf_noincr
int mem_ap_write_buf_noincr(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:740
adiv5_jim_configure_ext
int adiv5_jim_configure_ext(struct target *target, struct jim_getopt_info *goi, struct adiv5_private_config *pc, enum adiv5_configure_dap_optional optional)
Definition: arm_adi_v5.c:2439
mem_ap_read_atomic_u32
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Synchronous read of a word from memory or a system register.
Definition: arm_adi_v5.c:266
dap_get_ap
struct adiv5_ap * dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1189
dap_put_ap
int dap_put_ap(struct adiv5_ap *ap)
Definition: arm_adi_v5.c:1209
mem_ap_init
int mem_ap_init(struct adiv5_ap *ap)
Initialize a DAP.
Definition: arm_adi_v5.c:888
mem_ap_write_atomic_u32
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Synchronous write of a word to memory or a system register.
Definition: arm_adi_v5.c:318
AP_TYPE_APB_AP
@ AP_TYPE_APB_AP
Definition: arm_adi_v5.h:491
ADI_CONFIGURE_DAP_COMPULSORY
@ ADI_CONFIGURE_DAP_COMPULSORY
Definition: arm_adi_v5.h:793
DP_APSEL_INVALID
#define DP_APSEL_INVALID
Definition: arm_adi_v5.h:110
dap_run
static int dap_run(struct adiv5_dap *dap)
Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they ar...
Definition: arm_adi_v5.h:648
arm_coresight.h
ARM_CS_C9_DEVTYPE_CORE_DEBUG
#define ARM_CS_C9_DEVTYPE_CORE_DEBUG
Definition: arm_coresight.h:88
arm_cti_ack_events
int arm_cti_ack_events(struct arm_cti *self, uint32_t event)
Definition: arm_cti.c:81
arm_cti_write_reg
int arm_cti_write_reg(struct arm_cti *self, unsigned int reg, uint32_t value)
Definition: arm_cti.c:123
arm_cti_gate_channel
int arm_cti_gate_channel(struct arm_cti *self, uint32_t channel)
Definition: arm_cti.c:107
arm_cti_pulse_channel
int arm_cti_pulse_channel(struct arm_cti *self, uint32_t channel)
Definition: arm_cti.c:136
arm_cti_enable
int arm_cti_enable(struct arm_cti *self, bool enable)
Definition: arm_cti.c:74
arm_cti_name
const char * arm_cti_name(struct arm_cti *self)
Definition: arm_cti.c:30
cti_instance_by_jim_obj
struct arm_cti * cti_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o)
Definition: arm_cti.c:35
arm_cti_ungate_channel
int arm_cti_ungate_channel(struct arm_cti *self, uint32_t channel)
Definition: arm_cti.c:115
CTI_CHNL
#define CTI_CHNL(x)
Definition: arm_cti.h:45
CTI_GATE
#define CTI_GATE
Definition: arm_cti.h:41
CTI_TRIG
#define CTI_TRIG(n)
Definition: arm_cti.h:48
CTI_OUTEN0
#define CTI_OUTEN0
Definition: arm_cti.h:27
CTI_OUTEN1
#define CTI_OUTEN1
Definition: arm_cti.h:28
DSCR_DTR_TX_FULL
#define DSCR_DTR_TX_FULL
Definition: arm_dpm.h:194
ARMV4_5_MRC
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:186
ARMV4_5_MCR
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:209
arm_semihosting
int arm_semihosting(struct target *target, int *retval)
Checks for and processes an ARM semihosting request.
Definition: arm_semihosting.c:172
arm_semihosting_init
int arm_semihosting_init(struct target *target)
Initialize ARM semihosting support.
Definition: arm_semihosting.c:150
arm_semihosting.h
mode
enum arm_mode mode
Definition: armv4_5.c:277
armv8_init_arch_info
int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
Definition: armv8.c:1289
armv8_set_dbgreg_bits
int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value)
Definition: armv8.c:2020
armv8_read_mpidr
int armv8_read_mpidr(struct armv8_common *armv8)
Definition: armv8.c:881
armv8_free_reg_cache
void armv8_free_reg_cache(struct target *target)
Definition: armv8.c:1916
armv8_arch_state
int armv8_arch_state(struct target *target)
Definition: armv8.c:1329
armv8_mmu_translate_va_pa
int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va, target_addr_t *val, int meminfo)
Definition: armv8.c:1106
armv8_command_handlers
const struct command_registration armv8_command_handlers[]
Definition: armv8.c:1930
armv8_select_reg_access
void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64)
Definition: armv8.c:864
armv8_mode_name
const char * armv8_mode_name(unsigned int psr_mode)
Map PSR mode bits to the name of an ARM processor operating mode.
Definition: armv8.c:108
armv8_handle_cache_info_command
int armv8_handle_cache_info_command(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache)
Definition: armv8.c:1271
armv8_identify_cache
int armv8_identify_cache(struct armv8_common *armv8)
Definition: armv8_cache.c:297
CPUV8_DBG_DRCR
#define CPUV8_DBG_DRCR
Definition: armv8.h:262
target_to_armv8
static struct armv8_common * target_to_armv8(struct target *target)
Definition: armv8.h:238
CPUV8_DBG_BVR_BASE
#define CPUV8_DBG_BVR_BASE
Definition: armv8.h:272
CPUV8_DBG_OSLAR
#define CPUV8_DBG_OSLAR
Definition: armv8.h:278
CPUV8_DBG_EDWAR0
#define CPUV8_DBG_EDWAR0
Definition: armv8.h:259
ARMV8_RUNCONTROL_HALT
@ ARMV8_RUNCONTROL_HALT
Definition: armv8.h:111
ARMV8_RUNCONTROL_RESUME
@ ARMV8_RUNCONTROL_RESUME
Definition: armv8.h:110
ARMV8_RUNCONTROL_STEP
@ ARMV8_RUNCONTROL_STEP
Definition: armv8.h:112
CPUV8_DBG_MAINID0
#define CPUV8_DBG_MAINID0
Definition: armv8.h:249
CPUV8_DBG_MEMFEATURE0
#define CPUV8_DBG_MEMFEATURE0
Definition: armv8.h:252
CPUV8_DBG_DSCR
#define CPUV8_DBG_DSCR
Definition: armv8.h:261
CPUV8_DBG_DTRTX
#define CPUV8_DBG_DTRTX
Definition: armv8.h:270
CPUV8_DBG_EDWAR1
#define CPUV8_DBG_EDWAR1
Definition: armv8.h:260
CPUV8_DBG_EDESR
#define CPUV8_DBG_EDESR
Definition: armv8.h:257
CPUV8_DBG_PRSR
#define CPUV8_DBG_PRSR
Definition: armv8.h:265
CPUV8_DBG_DBGFEATURE0
#define CPUV8_DBG_DBGFEATURE0
Definition: armv8.h:251
CPUV8_DBG_WVR_BASE
#define CPUV8_DBG_WVR_BASE
Definition: armv8.h:274
CPUV8_DBG_WCR_BASE
#define CPUV8_DBG_WCR_BASE
Definition: armv8.h:275
CPUV8_DBG_EDECR
#define CPUV8_DBG_EDECR
Definition: armv8.h:258
CPUV8_DBG_DTRRX
#define CPUV8_DBG_DTRRX
Definition: armv8.h:267
CPUV8_DBG_BCR_BASE
#define CPUV8_DBG_BCR_BASE
Definition: armv8.h:273
armv8_cache_d_inner_flush_virt
int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va, size_t size)
Definition: armv8_cache.c:104
armv8_cache_i_inner_inval_virt
int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va, size_t size)
Definition: armv8_cache.c:143
armv8_cache.h
armv8_dpm_report_dscr
void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
Definition: armv8_dpm.c:1351
armv8_dpm_write_dirty_registers
int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
Writes all modified core registers for all processor modes.
Definition: armv8_dpm.c:872
armv8_dpm_get_core_state
enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm)
Get core state from EDSCR, without necessity to retrieve CPSR.
Definition: armv8_dpm.c:41
armv8_dpm_read_current_registers
int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
Read basic registers of the current context: R0 to R15, and CPSR in AArch32 state or R0 to R31,...
Definition: armv8_dpm.c:734
armv8_dpm_initialize
int armv8_dpm_initialize(struct arm_dpm *dpm)
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affec...
Definition: armv8_dpm.c:1483
armv8_dpm_modeswitch
int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
Definition: armv8_dpm.c:538
armv8_dpm_handle_exception
void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore)
Definition: armv8_dpm.c:1295
armv8_dpm_setup
int armv8_dpm_setup(struct arm_dpm *dpm)
Hooks up this DPM to its associated target; call only once.
Definition: armv8_dpm.c:1401
PRSR_RESET
#define PRSR_RESET
Definition: armv8_dpm.h:99
PRSR_SDR
#define PRSR_SDR
Definition: armv8_dpm.h:108
ESR_RC
#define ESR_RC
Definition: armv8_dpm.h:94
DSCR_MA
#define DSCR_MA
Definition: armv8_dpm.h:44
PRSR_HALT
#define PRSR_HALT
Definition: armv8_dpm.h:101
DRCR_CSE
#define DRCR_CSE
Definition: armv8_dpm.h:74
DSCR_HDE
#define DSCR_HDE
Definition: armv8_dpm.h:41
ECR_RCE
#define ECR_RCE
Definition: armv8_dpm.h:91
PRSR_SR
#define PRSR_SR
Definition: armv8_dpm.h:100
DSCR_SYS_ERROR_PEND
#define DSCR_SYS_ERROR_PEND
Definition: armv8_dpm.h:38
DSCR_ERR
#define DSCR_ERR
Definition: armv8_dpm.h:37
DSCR_ITE
#define DSCR_ITE
Definition: armv8_dpm.h:47
armv8_select_opcodes
void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)
Definition: armv8_opcodes.c:73
armv8_opcodes.h
ARMV8_HLT_T1
#define ARMV8_HLT_T1(im)
Definition: armv8_opcodes.h:148
SYSTEM_SCTLR_EL1
#define SYSTEM_SCTLR_EL1
Definition: armv8_opcodes.h:37
ARMV8_MSR_GP
#define ARMV8_MSR_GP(system, rt)
Definition: armv8_opcodes.h:134
SYSTEM_SCTLR_EL3
#define SYSTEM_SCTLR_EL3
Definition: armv8_opcodes.h:39
ARMV8_MRS
#define ARMV8_MRS(system, rt)
Definition: armv8_opcodes.h:132
ARMV8_HLT
#define ARMV8_HLT(im)
Definition: armv8_opcodes.h:146
armv8_opcode
armv8_opcode
Definition: armv8_opcodes.h:183
ARMV8_OPC_LDRD_IP
@ ARMV8_OPC_LDRD_IP
Definition: armv8_opcodes.h:209
ARMV8_OPC_LDRW_IP
@ ARMV8_OPC_LDRW_IP
Definition: armv8_opcodes.h:208
ARMV8_OPC_LDRB_IP
@ ARMV8_OPC_LDRB_IP
Definition: armv8_opcodes.h:206
ARMV8_OPC_LDRH_IP
@ ARMV8_OPC_LDRH_IP
Definition: armv8_opcodes.h:207
ARMV8_OPC_STRD_IP
@ ARMV8_OPC_STRD_IP
Definition: armv8_opcodes.h:205
ARMV8_OPC_STRH_IP
@ ARMV8_OPC_STRH_IP
Definition: armv8_opcodes.h:203
ARMV8_OPC_STRW_IP
@ ARMV8_OPC_STRW_IP
Definition: armv8_opcodes.h:204
ARMV8_OPC_STRB_IP
@ ARMV8_OPC_STRB_IP
Definition: armv8_opcodes.h:202
SYSTEM_SCTLR_EL2
#define SYSTEM_SCTLR_EL2
Definition: armv8_opcodes.h:38
SYSTEM_DBG_DTRTX_EL0
#define SYSTEM_DBG_DTRTX_EL0
Definition: armv8_opcodes.h:63
SYSTEM_DBG_DBGDTR_EL0
#define SYSTEM_DBG_DBGDTR_EL0
Definition: armv8_opcodes.h:64
SYSTEM_DBG_DTRRX_EL0
#define SYSTEM_DBG_DTRRX_EL0
Definition: armv8_opcodes.h:62
ARMV8_HLT_A1
#define ARMV8_HLT_A1(im)
Definition: armv8_opcodes.h:147
buf_set_u32
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
buf_get_u64
static uint64_t buf_get_u64(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 64-bit word.
Definition: binarybuffer.h:134
buf_set_u64
static void buf_set_u64(uint8_t *_buffer, unsigned int first, unsigned int num, uint64_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:65
BKPT_HARD
@ BKPT_HARD
Definition: breakpoints.h:18
BKPT_SOFT
@ BKPT_SOFT
Definition: breakpoints.h:19
watchpoint_set
static void watchpoint_set(struct watchpoint *watchpoint, unsigned int number)
Definition: breakpoints.h:83
breakpoint_hw_set
static void breakpoint_hw_set(struct breakpoint *breakpoint, unsigned int hw_number)
Definition: breakpoints.h:66
WPT_ACCESS
@ WPT_ACCESS
Definition: breakpoints.h:23
WPT_READ
@ WPT_READ
Definition: breakpoints.h:23
WPT_WRITE
@ WPT_WRITE
Definition: breakpoints.h:23
command_print
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:443
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
CMD_NAME
#define CMD_NAME
Use this macro to access the name of the command being handled, rather than accessing the variable di...
Definition: command.h:166
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
COMMAND_PARSE_ADDRESS
#define COMMAND_PARSE_ADDRESS(in, out)
Definition: command.h:452
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:402
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
COMMAND_PARSE_NUMBER
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:442
CMD_CTX
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:146
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
ERROR_COMMAND_ARGUMENT_INVALID
#define ERROR_COMMAND_ARGUMENT_INVALID
Definition: command.h:404
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
halted
static int halted(struct target *target, const char *label)
Definition: davinci.c:58
mask
int mask
Definition: esirisc.c:1741
type
uint8_t type
Definition: esp_usb_jtag.c:0
priv
static struct esp_usb_jtag * priv
Definition: esp_usb_jtag.c:219
length
uint8_t length
Definition: esp_usb_jtag.c:1
jim_nvp_name2value_obj
int jim_nvp_name2value_obj(Jim_Interp *interp, const struct jim_nvp *p, Jim_Obj *o, struct jim_nvp **result)
Definition: jim-nvp.c:66
jim_getopt_obj
int jim_getopt_obj(struct jim_getopt_info *goi, Jim_Obj **puthere)
Remove argv[0] from the list.
Definition: jim-nvp.c:169
adapter_deassert_reset
int adapter_deassert_reset(void)
Definition: jtag/core.c:1899
jtag_get_reset_config
enum reset_types jtag_get_reset_config(void)
Definition: jtag/core.c:1734
adapter_assert_reset
int adapter_assert_reset(void)
Definition: jtag/core.c:1879
reset_types
reset_types
Definition: jtag.h:216
RESET_SRST_NO_GATING
@ RESET_SRST_NO_GATING
Definition: jtag.h:225
RESET_HAS_SRST
@ RESET_HAS_SRST
Definition: jtag.h:219
RESET_SRST_PULLS_TRST
@ RESET_SRST_PULLS_TRST
Definition: jtag.h:221
LOG_TARGET_INFO
#define LOG_TARGET_INFO(target, fmt_str,...)
Definition: log.h:152
LOG_WARNING
#define LOG_WARNING(expr ...)
Definition: log.h:129
ERROR_FAIL
#define ERROR_FAIL
Definition: log.h:170
LOG_TARGET_ERROR
#define LOG_TARGET_ERROR(target, fmt_str,...)
Definition: log.h:158
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:132
LOG_INFO
#define LOG_INFO(expr ...)
Definition: log.h:126
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:109
ERROR_OK
#define ERROR_OK
Definition: log.h:164
nvp_name2value
const struct nvp * nvp_name2value(const struct nvp *p, const char *name)
Definition: nvp.c:29
nvp_value2name
const struct nvp * nvp_value2name(const struct nvp *p, int value)
Definition: nvp.c:39
register_cache_invalidate
void register_cache_invalidate(struct reg_cache *cache)
Marks the contents of the register cache as invalid (and clean).
Definition: register.c:94
addr
target_addr_t addr
Start address to search for the control block.
Definition: rtt/rtt.c:28
target
struct target * target
Definition: rtt/rtt.c:26
size
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
semihosting_common_handlers
const struct command_registration semihosting_common_handlers[]
Definition: semihosting_common.c:2115
smp_command_handlers
const struct command_registration smp_command_handlers[]
Definition: smp.c:153
foreach_smp_target
#define foreach_smp_target(pos, head)
Definition: smp.h:15
aarch64_brp
Definition: aarch64.h:32
aarch64_brp::brpn
uint8_t brpn
Definition: aarch64.h:37
aarch64_brp::value
target_addr_t value
Definition: aarch64.h:35
aarch64_brp::type
int type
Definition: aarch64.h:34
aarch64_brp::control
uint32_t control
Definition: aarch64.h:36
aarch64_brp::used
int used
Definition: aarch64.h:33
aarch64_common
Definition: aarch64.h:40
aarch64_common::common_magic
unsigned int common_magic
Definition: aarch64.h:41
aarch64_common::wp_num_available
int wp_num_available
Definition: aarch64.h:57
aarch64_common::wp_list
struct aarch64_brp * wp_list
Definition: aarch64.h:58
aarch64_common::brp_num_available
int brp_num_available
Definition: aarch64.h:52
aarch64_common::brp_num
int brp_num
Definition: aarch64.h:51
aarch64_common::system_control_reg_curr
uint64_t system_control_reg_curr
Definition: aarch64.h:47
aarch64_common::wp_num
int wp_num
Definition: aarch64.h:56
aarch64_common::armv8_common
struct armv8_common armv8_common
Definition: aarch64.h:43
aarch64_common::brp_list
struct aarch64_brp * brp_list
Definition: aarch64.h:53
aarch64_common::isrmasking_mode
enum aarch64_isrmasking_mode isrmasking_mode
Definition: aarch64.h:60
aarch64_common::system_control_reg
uint64_t system_control_reg
Definition: aarch64.h:46
aarch64_common::brp_num_context
int brp_num_context
Definition: aarch64.h:50
aarch64_private_config
Definition: aarch64.c:37
aarch64_private_config::cti
struct arm_cti * cti
Definition: aarch64.c:39
aarch64_private_config::adiv5_config
struct adiv5_private_config adiv5_config
Definition: aarch64.c:38
adiv5_ap::dap
struct adiv5_dap * dap
DAP this AP belongs to.
Definition: arm_adi_v5.h:254
adiv5_ap::memaccess_tck
uint32_t memaccess_tck
Configures how many extra tck clocks are added after starting a MEM-AP access before we try to read i...
Definition: arm_adi_v5.h:306
adiv5_dap
This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
Definition: arm_adi_v5.h:348
adiv5_private_config
Definition: arm_adi_v5.h:785
adiv5_private_config::ap_num
uint64_t ap_num
Definition: arm_adi_v5.h:786
adiv5_private_config::dap
struct adiv5_dap * dap
Definition: arm_adi_v5.h:787
arm_cti
Definition: arm_cti.c:21
arm_dpm
This wraps an implementation of DPM primitives.
Definition: arm_dpm.h:47
arm_dpm::wp_addr
target_addr_t wp_addr
Target dependent watchpoint address.
Definition: arm_dpm.h:147
arm_dpm::didr
uint64_t didr
Cache of DIDR.
Definition: arm_dpm.h:51
arm_dpm::instr_write_data_r0_64
int(* instr_write_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Runs one instruction, writing data to R0 before execution.
Definition: arm_dpm.h:82
arm_dpm::instr_execute
int(* instr_execute)(struct arm_dpm *dpm, uint32_t opcode)
Runs one instruction.
Definition: arm_dpm.h:60
arm_dpm::instr_write_data_dcc_64
int(* instr_write_data_dcc_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Definition: arm_dpm.h:68
arm_dpm::arm
struct arm * arm
Definition: arm_dpm.h:48
arm_dpm::dbp
struct dpm_bp * dbp
Definition: arm_dpm.h:139
arm_dpm::instr_write_data_dcc
int(* instr_write_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
Definition: arm_dpm.h:65
arm_dpm::instr_read_data_r0_64
int(* instr_read_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Definition: arm_dpm.h:108
arm_dpm::dwp
struct dpm_wp * dwp
Definition: arm_dpm.h:140
arm_dpm::instr_cpsr_sync
int(* instr_cpsr_sync)(struct arm_dpm *dpm)
Optional core-specific operation invoked after CPSR writes.
Definition: arm_dpm.h:86
arm_dpm::dscr
uint32_t dscr
Recent value of DSCR.
Definition: arm_dpm.h:150
arm
Represents a generic ARM core, with standard application registers.
Definition: arm.h:175
arm::mrc
int(* mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
Read coprocessor register.
Definition: arm.h:230
arm::core_mode
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
Definition: arm.h:196
arm::dap
struct adiv5_dap * dap
For targets conforming to ARM Debug Interface v5, this handle references the Debug Access Port (DAP) ...
Definition: arm.h:257
arm::pc
struct reg * pc
Handle to the PC; valid in all core modes.
Definition: arm.h:181
arm::core_cache
struct reg_cache * core_cache
Definition: arm.h:178
arm::dpm
struct arm_dpm * dpm
Handle for the debug module, if one is present.
Definition: arm.h:213
arm::mcr
int(* mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
Write coprocessor register.
Definition: arm.h:241
arm::core_state
enum arm_state core_state
Record the current core state: ARM, Thumb, or otherwise.
Definition: arm.h:199
armv8_cache_common::d_u_cache_enabled
int d_u_cache_enabled
Definition: armv8.h:160
armv8_cache_common::info
int info
Definition: armv8.h:154
armv8_cache_common::flush_all_data_cache
int(* flush_all_data_cache)(struct target *target)
Definition: armv8.h:164
armv8_cache_common::i_cache_enabled
int i_cache_enabled
Definition: armv8.h:159
armv8_common
Definition: armv8.h:184
armv8_common::arm
struct arm arm
Definition: armv8.h:187
armv8_common::dpm
struct arm_dpm dpm
Definition: armv8.h:191
armv8_common::is_armv8r
bool is_armv8r
Definition: armv8.h:207
armv8_common::debug_base
target_addr_t debug_base
Definition: armv8.h:192
armv8_common::sticky_reset
bool sticky_reset
Definition: armv8.h:216
armv8_common::last_run_control_op
enum run_control_op last_run_control_op
Definition: armv8.h:219
armv8_common::armv8_mmu
struct armv8_mmu_common armv8_mmu
Definition: armv8.h:209
armv8_common::debug_ap
struct adiv5_ap * debug_ap
Definition: armv8.h:193
armv8_common::cti
struct arm_cti * cti
Definition: armv8.h:211
armv8_common::pre_restore_context
void(* pre_restore_context)(struct target *target)
Definition: armv8.h:234
armv8_common::examine_debug_reason
int(* examine_debug_reason)(struct target *target)
Definition: armv8.h:231
armv8_common::post_debug_entry
int(* post_debug_entry)(struct target *target)
Definition: armv8.h:232
armv8_mmu_common::mmu_enabled
uint32_t mmu_enabled
Definition: armv8.h:181
armv8_mmu_common::read_physical_memory
int(* read_physical_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: armv8.h:178
armv8_mmu_common::armv8_cache
struct armv8_cache_common armv8_cache
Definition: armv8.h:180
breakpoint::linked_brp
int linked_brp
Definition: breakpoints.h:36
breakpoint::length
unsigned int length
Definition: breakpoints.h:29
breakpoint::orig_instr
uint8_t * orig_instr
Definition: breakpoints.h:33
breakpoint::type
enum breakpoint_type type
Definition: breakpoints.h:30
breakpoint::is_set
bool is_set
Definition: breakpoints.h:31
breakpoint::number
unsigned int number
Definition: breakpoints.h:32
breakpoint::asid
uint32_t asid
Definition: breakpoints.h:28
breakpoint::address
target_addr_t address
Definition: breakpoints.h:27
command_context
Definition: command.h:52
command_registration
Definition: command.h:234
command_registration::name
const char * name
Definition: command.h:235
command_registration::chain
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
Definition: command.h:249
gdb_service::target
struct target * target
Definition: target.h:95
jim_getopt_info
A TCL -ish GetOpt like code.
Definition: jim-nvp.h:135
jim_getopt_info::interp
Jim_Interp * interp
Definition: jim-nvp.h:136
jim_getopt_info::argc
int argc
Definition: jim-nvp.h:137
jim_getopt_info::argv
Jim_Obj *const * argv
Definition: jim-nvp.h:138
jim_getopt_info::isconfigure
int isconfigure
Definition: jim-nvp.h:139
jim_nvp
Name Value Pairs, aka: NVP.
Definition: jim-nvp.h:59
jim_nvp::name
const char * name
Definition: jim-nvp.h:60
jim_nvp::value
int value
Definition: jim-nvp.h:61
nvp
Name Value Pairs, aka: NVP.
Definition: nvp.h:61
nvp::value
int value
Definition: nvp.h:63
nvp::name
const char * name
Definition: nvp.h:62
reg_cache::next
struct reg_cache * next
Definition: register.h:146
reg::valid
bool valid
Definition: register.h:126
reg::value
uint8_t * value
Definition: register.h:122
reg::dirty
bool dirty
Definition: register.h:124
target_list
Definition: target.h:212
target_list::target
struct target * target
Definition: target.h:214
target_type
This holds methods shared between all instances of a given target type.
Definition: target_type.h:26
target_type::name
const char * name
Name of this type of target.
Definition: target_type.h:31
target
Definition: target.h:116
target::coreid
int32_t coreid
Definition: target.h:120
target::gdb_service
struct gdb_service * gdb_service
Definition: target.h:199
target::dbgbase_set
bool dbgbase_set
Definition: target.h:174
target::dbg_msg_enabled
bool dbg_msg_enabled
Definition: target.h:163
target::debug_reason
enum target_debug_reason debug_reason
Definition: target.h:154
target::state
enum target_state state
Definition: target.h:157
target::dbgbase
uint32_t dbgbase
Definition: target.h:175
target::private_config
void * private_config
Definition: target.h:165
target::smp_targets
struct list_head * smp_targets
Definition: target.h:188
target::smp
unsigned int smp
Definition: target.h:187
target::watchpoints
struct watchpoint * watchpoints
Definition: target.h:160
target::reset_halt
bool reset_halt
Definition: target.h:144
target::next
struct target * next
Definition: target.h:166
watchpoint::rw
enum watchpoint_rw rw
Definition: breakpoints.h:46
watchpoint::is_set
bool is_set
Definition: breakpoints.h:47
watchpoint::next
struct watchpoint * next
Definition: breakpoints.h:49
watchpoint::length
unsigned int length
Definition: breakpoints.h:43
watchpoint::number
unsigned int number
Definition: breakpoints.h:48
watchpoint::address
target_addr_t address
Definition: breakpoints.h:42
target_buffer_get_u64
uint64_t target_buffer_get_u64(struct target *target, const uint8_t *buffer)
Definition: target.c:307
target_call_event_callbacks
int target_call_event_callbacks(struct target *target, enum target_event event)
Definition: target.c:1764
target_free_all_working_areas
void target_free_all_working_areas(struct target *target)
Definition: target.c:2150
target_buffer_set_u16
void target_buffer_set_u16(struct target *target, uint8_t *buffer, uint16_t value)
Definition: target.c:370
target_buffer_set_u32
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
Definition: target.c:352
target_write_memory
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1265
srst_asserted
static int srst_asserted
Definition: target.c:2849
target_register_timer_callback
int target_register_timer_callback(int(*callback)(void *priv), unsigned int time_ms, enum target_timer_type type, void *priv)
The period is very approximate, the callback can happen much more often or much more rarely than spec...
Definition: target.c:1658
target_buffer_set_u64
void target_buffer_set_u64(struct target *target, uint8_t *buffer, uint64_t value)
Definition: target.c:343
target_buffer_get_u16
uint16_t target_buffer_get_u16(struct target *target, const uint8_t *buffer)
Definition: target.c:334
target_read_memory
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
Definition: target.c:1237
target_has_event_action
bool target_has_event_action(const struct target *target, enum target_event event)
Returns true only if the target has a handler for the specified event.
Definition: target.c:4860
get_current_target
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:458
target_handle_event
void target_handle_event(struct target *target, enum target_event e)
Definition: target.c:4667
target_buffer_get_u32
uint32_t target_buffer_get_u32(struct target *target, const uint8_t *buffer)
Definition: target.c:316
target_debug_reason
target_debug_reason
Definition: target.h:68
DBG_REASON_NOTHALTED
@ DBG_REASON_NOTHALTED
Definition: target.h:74
DBG_REASON_DBGRQ
@ DBG_REASON_DBGRQ
Definition: target.h:69
DBG_REASON_WATCHPOINT
@ DBG_REASON_WATCHPOINT
Definition: target.h:71
ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:790
target_was_examined
static bool target_was_examined(const struct target *target)
Definition: target.h:436
TARGET_TIMER_TYPE_PERIODIC
@ TARGET_TIMER_TYPE_PERIODIC
Definition: target.h:327
TARGET_EVENT_DEBUG_RESUMED
@ TARGET_EVENT_DEBUG_RESUMED
Definition: target.h:272
TARGET_EVENT_HALTED
@ TARGET_EVENT_HALTED
Definition: target.h:252
TARGET_EVENT_RESUMED
@ TARGET_EVENT_RESUMED
Definition: target.h:253
TARGET_EVENT_DEBUG_HALTED
@ TARGET_EVENT_DEBUG_HALTED
Definition: target.h:271
TARGET_EVENT_RESET_ASSERT
@ TARGET_EVENT_RESET_ASSERT
Definition: target.h:264
target_name
static const char * target_name(const struct target *target)
Returns the instance-specific name of the specified target.
Definition: target.h:233
target_state
target_state
Definition: target.h:53
TARGET_RESET
@ TARGET_RESET
Definition: target.h:57
TARGET_DEBUG_RUNNING
@ TARGET_DEBUG_RUNNING
Definition: target.h:58
TARGET_UNKNOWN
@ TARGET_UNKNOWN
Definition: target.h:54
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:56
TARGET_RUNNING
@ TARGET_RUNNING
Definition: target.h:55
ERROR_TARGET_NOT_EXAMINED
#define ERROR_TARGET_NOT_EXAMINED
Definition: target.h:797
ERROR_TARGET_TIMEOUT
#define ERROR_TARGET_TIMEOUT
Definition: target.h:789
ERROR_TARGET_RESOURCE_NOT_AVAILABLE
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:794
target_set_examined
static void target_set_examined(struct target *target)
Sets the examined flag for the given target.
Definition: target.h:443
target_request
int target_request(struct target *target, uint32_t request)
Definition: target_request.c:108
target_request.h
target_type.h
time_support.h
timeval_ms
int64_t timeval_ms(void)
Definition: time_support_common.c:23
TARGET_ADDR_FMT
#define TARGET_ADDR_FMT
Definition: types.h:342
target_addr_t
uint64_t target_addr_t
Definition: types.h:335
TARGET_PRIxADDR
#define TARGET_PRIxADDR
Definition: types.h:340
NULL
#define NULL
Definition: usb.h:16
offset
uint8_t offset[4]
Definition: vdebug.c:9
dummy
uint8_t dummy[96]
Definition: vdebug.c:23
count
uint8_t count[4]
Definition: vdebug.c:22