7 #ifndef OPENOCD_TARGET_ARM_DPM_H
8 #define OPENOCD_TARGET_ARM_DPM_H
66 uint32_t opcode, uint32_t data);
69 uint32_t opcode, uint64_t data);
73 uint32_t opcode, uint32_t data);
79 uint32_t opcode, uint64_t data);
83 uint32_t opcode, uint64_t data);
92 uint32_t opcode, uint32_t *data);
95 uint32_t opcode, uint64_t *data);
99 uint32_t opcode, uint32_t *data);
106 uint32_t opcode, uint64_t *data);
109 uint32_t opcode, uint64_t *data);
111 struct reg *(*arm_reg_current)(
struct arm *
arm,
112 unsigned int regnum);
123 uint32_t
addr, uint32_t control);
172 #define DSCR_CORE_HALTED (0x1 << 0)
173 #define DSCR_CORE_RESTARTED (0x1 << 1)
174 #define DSCR_ENTRY_MASK (0xF << 2)
175 #define DSCR_STICKY_ABORT_PRECISE (0x1 << 6)
176 #define DSCR_STICKY_ABORT_IMPRECISE (0x1 << 7)
177 #define DSCR_STICKY_UNDEFINED (0x1 << 8)
178 #define DSCR_DBG_NOPWRDWN (0x1 << 9)
179 #define DSCR_DBG_ACK (0x1 << 10)
180 #define DSCR_INT_DIS (0x1 << 11)
181 #define DSCR_CP14_USR_COMMS (0x1 << 12)
182 #define DSCR_ITR_EN (0x1 << 13)
183 #define DSCR_HALT_DBG_MODE (0x1 << 14)
184 #define DSCR_MON_DBG_MODE (0x1 << 15)
185 #define DSCR_SEC_PRIV_INVASV_DIS (0x1 << 16)
186 #define DSCR_SEC_PRIV_NINVASV_DIS (0x1 << 17)
187 #define DSCR_NON_SECURE (0x1 << 18)
188 #define DSCR_DSCRD_IMPRECISE_ABORT (0x1 << 19)
189 #define DSCR_EXT_DCC_MASK (0x3 << 20)
190 #define DSCR_INSTR_COMP (0x1 << 24)
191 #define DSCR_PIPE_ADVANCE (0x1 << 25)
192 #define DSCR_DTRTX_FULL_LATCHED (0x1 << 26)
193 #define DSCR_DTRRX_FULL_LATCHED (0x1 << 27)
194 #define DSCR_DTR_TX_FULL (0x1 << 29)
195 #define DSCR_DTR_RX_FULL (0x1 << 30)
197 #define DSCR_ENTRY(dscr) ((dscr) & 0x3f)
198 #define DSCR_RUN_MODE(dscr) ((dscr) & 0x03)
202 #define DSCR_ENTRY_HALT_REQ (0x03)
203 #define DSCR_ENTRY_BREAKPOINT (0x07)
204 #define DSCR_ENTRY_IMPRECISE_WATCHPT (0x0B)
205 #define DSCR_ENTRY_BKPT_INSTR (0x0F)
206 #define DSCR_ENTRY_EXT_DBG_REQ (0x13)
207 #define DSCR_ENTRY_VECT_CATCH (0x17)
208 #define DSCR_ENTRY_D_SIDE_ABORT (0x1B)
209 #define DSCR_ENTRY_I_SIDE_ABORT (0x1F)
210 #define DSCR_ENTRY_OS_UNLOCK (0x23)
211 #define DSCR_ENTRY_PRECISE_WATCHPT (0x2B)
214 #define DSCR_EXT_DCC_NON_BLOCKING (0x0 << 20)
215 #define DSCR_EXT_DCC_STALL_MODE (0x1 << 20)
216 #define DSCR_EXT_DCC_FAST_MODE (0x2 << 20)
223 #define DRCR_HALT (1 << 0)
224 #define DRCR_RESTART (1 << 1)
225 #define DRCR_CLEAR_EXCEPTIONS (1 << 2)
230 #define PRCR_DEBUG_NO_POWER_DOWN (1 << 0)
231 #define PRCR_WARM_RESET (1 << 1)
232 #define PRCR_HOLD_NON_DEBUG_RESET (1 << 2)
235 #define PRSR_POWERUP_STATUS (1 << 0)
236 #define PRSR_STICKY_POWERDOWN_STATUS (1 << 1)
237 #define PRSR_RESET_STATUS (1 << 2)
238 #define PRSR_STICKY_RESET_STATUS (1 << 3)
239 #define PRSR_HALTED (1 << 4)
240 #define PRSR_OSLK (1 << 5)
241 #define PRSR_DLK (1 << 6)
244 #define OSLSR_OSLM0 (1 << 0)
245 #define OSLSR_OSLK (1 << 1)
246 #define OSLSR_NTT (1 << 2)
247 #define OSLSR_OSLM1 (1 << 3)
248 #define OSLSR_OSLM (OSLSR_OSLM0|OSLSR_OSLM1)
arm_mode
Represent state of an ARM core.
int arm_dpm_read_current_registers(struct arm_dpm *dpm)
Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or ...
int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
int arm_dpm_setup(struct arm_dpm *dpm)
Hooks up this DPM to its associated target; call only once.
int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
Writes all modified core registers for all processor modes.
void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t wfar)
void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr)
int arm_dpm_initialize(struct arm_dpm *dpm)
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affec...
target_addr_t addr
Start address to search for the control block.
This wraps an implementation of DPM primitives.
target_addr_t wp_addr
Target dependent watchpoint address.
int(* instr_read_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from dcc after execution.
uint64_t didr
Cache of DIDR.
int(* instr_write_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Runs one instruction, writing data to R0 before execution.
int(* instr_read_data_dcc_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
int(* instr_execute)(struct arm_dpm *dpm, uint32_t opcode)
Runs one instruction.
int(* instr_write_data_dcc_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
int(* bpwp_enable)(struct arm_dpm *dpm, unsigned int index_value, uint32_t addr, uint32_t control)
Enables one breakpoint or watchpoint by writing to the hardware registers.
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
unsigned int last_el
Recent exception level on armv8.
int(* instr_write_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
int(* instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
int(* instr_read_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
int(* instr_read_data_r0_r1)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Runs two instructions, reading data from r0 and r1 after execution.
int(* bpwp_disable)(struct arm_dpm *dpm, unsigned int index_value)
Disables one breakpoint or watchpoint by clearing its hardware control registers.
int(* instr_cpsr_sync)(struct arm_dpm *dpm)
Optional core-specific operation invoked after CPSR writes.
int(* instr_write_data_r0_r1)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Runs two instructions, writing data to R0 and R1 before execution.
uint32_t dscr
Recent value of DSCR.
Represents a generic ARM core, with standard application registers.