OpenOCD
arm_dpm.h
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /*
4  * Copyright (C) 2009 by David Brownell
5  */
6 
7 #ifndef OPENOCD_TARGET_ARM_DPM_H
8 #define OPENOCD_TARGET_ARM_DPM_H
9 
21 struct dpm_bpwp {
22  unsigned int number;
23  uint32_t address;
24  uint32_t control;
25  /* true if hardware state needs flushing */
26  bool dirty;
27 };
28 
29 struct dpm_bp {
30  struct breakpoint *bp;
31  struct dpm_bpwp bpwp;
32 };
33 
34 struct dpm_wp {
35  struct watchpoint *wp;
36  struct dpm_bpwp bpwp;
37 };
38 
47 struct arm_dpm {
48  struct arm *arm;
49 
51  uint64_t didr;
52 
54  int (*prepare)(struct arm_dpm *dpm);
55 
57  int (*finish)(struct arm_dpm *dpm);
58 
60  int (*instr_execute)(struct arm_dpm *dpm, uint32_t opcode);
61 
62  /* WRITE TO CPU */
63 
65  int (*instr_write_data_dcc)(struct arm_dpm *dpm,
66  uint32_t opcode, uint32_t data);
67 
68  int (*instr_write_data_dcc_64)(struct arm_dpm *dpm,
69  uint32_t opcode, uint64_t data);
70 
72  int (*instr_write_data_r0)(struct arm_dpm *dpm,
73  uint32_t opcode, uint32_t data);
74 
78  int (*instr_write_data_r0_r1)(struct arm_dpm *dpm,
79  uint32_t opcode, uint64_t data);
80 
82  int (*instr_write_data_r0_64)(struct arm_dpm *dpm,
83  uint32_t opcode, uint64_t data);
84 
86  int (*instr_cpsr_sync)(struct arm_dpm *dpm);
87 
88  /* READ FROM CPU */
89 
91  int (*instr_read_data_dcc)(struct arm_dpm *dpm,
92  uint32_t opcode, uint32_t *data);
93 
94  int (*instr_read_data_dcc_64)(struct arm_dpm *dpm,
95  uint32_t opcode, uint64_t *data);
96 
98  int (*instr_read_data_r0)(struct arm_dpm *dpm,
99  uint32_t opcode, uint32_t *data);
100 
105  int (*instr_read_data_r0_r1)(struct arm_dpm *dpm,
106  uint32_t opcode, uint64_t *data);
107 
108  int (*instr_read_data_r0_64)(struct arm_dpm *dpm,
109  uint32_t opcode, uint64_t *data);
110 
111  struct reg *(*arm_reg_current)(struct arm *arm,
112  unsigned int regnum);
113 
114  /* BREAKPOINT/WATCHPOINT SUPPORT */
115 
122  int (*bpwp_enable)(struct arm_dpm *dpm, unsigned int index_value,
123  uint32_t addr, uint32_t control);
124 
130  int (*bpwp_disable)(struct arm_dpm *dpm, unsigned int index_value);
131 
132  /* The breakpoint and watchpoint arrays are private to the
133  * DPM infrastructure. There are nbp indices in the dbp
134  * array. There are nwp indices in the dwp array.
135  */
136 
137  unsigned int nbp;
138  unsigned int nwp;
139  struct dpm_bp *dbp;
140  struct dpm_wp *dwp;
141 
148 
150  uint32_t dscr;
151 
153  unsigned int last_el;
154 
155  /* FIXME -- read/write DCSR methods and symbols */
156 };
157 
158 int arm_dpm_setup(struct arm_dpm *dpm);
159 int arm_dpm_initialize(struct arm_dpm *dpm);
160 
161 int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum);
162 int arm_dpm_read_current_registers(struct arm_dpm *dpm);
163 int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
164 
165 int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp);
166 
167 void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t wfar);
168 
169 /* DSCR bits; see ARMv7a arch spec section C10.3.1.
170  * Not all v7 bits are valid in v6.
171  */
172 #define DSCR_CORE_HALTED (0x1 << 0)
173 #define DSCR_CORE_RESTARTED (0x1 << 1)
174 #define DSCR_ENTRY_MASK (0xF << 2)
175 #define DSCR_STICKY_ABORT_PRECISE (0x1 << 6)
176 #define DSCR_STICKY_ABORT_IMPRECISE (0x1 << 7)
177 #define DSCR_STICKY_UNDEFINED (0x1 << 8)
178 #define DSCR_DBG_NOPWRDWN (0x1 << 9) /* v6 only */
179 #define DSCR_DBG_ACK (0x1 << 10)
180 #define DSCR_INT_DIS (0x1 << 11)
181 #define DSCR_CP14_USR_COMMS (0x1 << 12)
182 #define DSCR_ITR_EN (0x1 << 13)
183 #define DSCR_HALT_DBG_MODE (0x1 << 14)
184 #define DSCR_MON_DBG_MODE (0x1 << 15)
185 #define DSCR_SEC_PRIV_INVASV_DIS (0x1 << 16)
186 #define DSCR_SEC_PRIV_NINVASV_DIS (0x1 << 17)
187 #define DSCR_NON_SECURE (0x1 << 18)
188 #define DSCR_DSCRD_IMPRECISE_ABORT (0x1 << 19)
189 #define DSCR_EXT_DCC_MASK (0x3 << 20) /* DTR mode */ /* bits 22, 23 are reserved */
190 #define DSCR_INSTR_COMP (0x1 << 24)
191 #define DSCR_PIPE_ADVANCE (0x1 << 25)
192 #define DSCR_DTRTX_FULL_LATCHED (0x1 << 26)
193 #define DSCR_DTRRX_FULL_LATCHED (0x1 << 27) /* bit 28 is reserved */
194 #define DSCR_DTR_TX_FULL (0x1 << 29)
195 #define DSCR_DTR_RX_FULL (0x1 << 30) /* bit 31 is reserved */
196 
197 #define DSCR_ENTRY(dscr) ((dscr) & 0x3f)
198 #define DSCR_RUN_MODE(dscr) ((dscr) & 0x03)
199 
200 
201 /* Methods of entry into debug mode */
202 #define DSCR_ENTRY_HALT_REQ (0x03)
203 #define DSCR_ENTRY_BREAKPOINT (0x07)
204 #define DSCR_ENTRY_IMPRECISE_WATCHPT (0x0B)
205 #define DSCR_ENTRY_BKPT_INSTR (0x0F)
206 #define DSCR_ENTRY_EXT_DBG_REQ (0x13)
207 #define DSCR_ENTRY_VECT_CATCH (0x17)
208 #define DSCR_ENTRY_D_SIDE_ABORT (0x1B) /* v6 only */
209 #define DSCR_ENTRY_I_SIDE_ABORT (0x1F) /* v6 only */
210 #define DSCR_ENTRY_OS_UNLOCK (0x23)
211 #define DSCR_ENTRY_PRECISE_WATCHPT (0x2B)
212 
213 /* DTR modes */
214 #define DSCR_EXT_DCC_NON_BLOCKING (0x0 << 20)
215 #define DSCR_EXT_DCC_STALL_MODE (0x1 << 20)
216 #define DSCR_EXT_DCC_FAST_MODE (0x2 << 20) /* bits 22, 23 are reserved */
217 
218 
219 
220 
221 
222 /* DRCR (debug run control register) bits */
223 #define DRCR_HALT (1 << 0)
224 #define DRCR_RESTART (1 << 1)
225 #define DRCR_CLEAR_EXCEPTIONS (1 << 2)
226 
227 void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
228 
229 /* PRCR (Device Power-down and Reset Control Register) bits */
230 #define PRCR_DEBUG_NO_POWER_DOWN (1 << 0)
231 #define PRCR_WARM_RESET (1 << 1)
232 #define PRCR_HOLD_NON_DEBUG_RESET (1 << 2)
233 
234 /* PRSR (Device Power-down and Reset Status Register) bits */
235 #define PRSR_POWERUP_STATUS (1 << 0)
236 #define PRSR_STICKY_POWERDOWN_STATUS (1 << 1)
237 #define PRSR_RESET_STATUS (1 << 2)
238 #define PRSR_STICKY_RESET_STATUS (1 << 3)
239 #define PRSR_HALTED (1 << 4) /* v7.1 Debug only */
240 #define PRSR_OSLK (1 << 5) /* v7.1 Debug only */
241 #define PRSR_DLK (1 << 6) /* v7.1 Debug only */
242 
243 /* OSLSR (OS Lock Status Register) bits */
244 #define OSLSR_OSLM0 (1 << 0)
245 #define OSLSR_OSLK (1 << 1)
246 #define OSLSR_NTT (1 << 2)
247 #define OSLSR_OSLM1 (1 << 3)
248 #define OSLSR_OSLM (OSLSR_OSLM0|OSLSR_OSLM1)
249 
250 #endif /* OPENOCD_TARGET_ARM_DPM_H */
arm_mode
Represent state of an ARM core.
Definition: arm.h:82
int arm_dpm_read_current_registers(struct arm_dpm *dpm)
Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or ...
Definition: arm_dpm.c:377
int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
Definition: arm_dpm.c:146
int arm_dpm_setup(struct arm_dpm *dpm)
Hooks up this DPM to its associated target; call only once.
Definition: arm_dpm.c:1093
int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
Definition: arm_dpm.c:208
int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
Writes all modified core registers for all processor modes.
Definition: arm_dpm.c:485
void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t wfar)
Definition: arm_dpm.c:1031
void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr)
Definition: arm_dpm.c:1055
int arm_dpm_initialize(struct arm_dpm *dpm)
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affec...
Definition: arm_dpm.c:1160
enum arm_mode mode
Definition: armv4_5.c:277
target_addr_t addr
Start address to search for the control block.
Definition: rtt/rtt.c:28
This wraps an implementation of DPM primitives.
Definition: arm_dpm.h:47
target_addr_t wp_addr
Target dependent watchpoint address.
Definition: arm_dpm.h:147
int(* instr_read_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from dcc after execution.
Definition: arm_dpm.h:91
uint64_t didr
Cache of DIDR.
Definition: arm_dpm.h:51
int(* instr_write_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Runs one instruction, writing data to R0 before execution.
Definition: arm_dpm.h:82
int(* instr_read_data_dcc_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Definition: arm_dpm.h:94
int(* instr_execute)(struct arm_dpm *dpm, uint32_t opcode)
Runs one instruction.
Definition: arm_dpm.h:60
int(* instr_write_data_dcc_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Definition: arm_dpm.h:68
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
Definition: arm_dpm.h:72
struct arm * arm
Definition: arm_dpm.h:48
int(* bpwp_enable)(struct arm_dpm *dpm, unsigned int index_value, uint32_t addr, uint32_t control)
Enables one breakpoint or watchpoint by writing to the hardware registers.
Definition: arm_dpm.h:122
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
Definition: arm_dpm.h:57
struct dpm_bp * dbp
Definition: arm_dpm.h:139
unsigned int last_el
Recent exception level on armv8.
Definition: arm_dpm.h:153
int(* instr_write_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
Definition: arm_dpm.h:65
unsigned int nwp
Definition: arm_dpm.h:138
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
Definition: arm_dpm.h:54
int(* instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
Definition: arm_dpm.h:98
int(* instr_read_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Definition: arm_dpm.h:108
int(* instr_read_data_r0_r1)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Runs two instructions, reading data from r0 and r1 after execution.
Definition: arm_dpm.h:105
unsigned int nbp
Definition: arm_dpm.h:137
struct dpm_wp * dwp
Definition: arm_dpm.h:140
int(* bpwp_disable)(struct arm_dpm *dpm, unsigned int index_value)
Disables one breakpoint or watchpoint by clearing its hardware control registers.
Definition: arm_dpm.h:130
int(* instr_cpsr_sync)(struct arm_dpm *dpm)
Optional core-specific operation invoked after CPSR writes.
Definition: arm_dpm.h:86
int(* instr_write_data_r0_r1)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Runs two instructions, writing data to R0 and R1 before execution.
Definition: arm_dpm.h:78
uint32_t dscr
Recent value of DSCR.
Definition: arm_dpm.h:150
Represents a generic ARM core, with standard application registers.
Definition: arm.h:175
Definition: arm_dpm.h:29
struct dpm_bpwp bpwp
Definition: arm_dpm.h:31
struct breakpoint * bp
Definition: arm_dpm.h:30
uint32_t control
Definition: arm_dpm.h:24
unsigned int number
Definition: arm_dpm.h:22
bool dirty
Definition: arm_dpm.h:26
uint32_t address
Definition: arm_dpm.h:23
Definition: arm_dpm.h:34
struct watchpoint * wp
Definition: arm_dpm.h:35
struct dpm_bpwp bpwp
Definition: arm_dpm.h:36
Definition: register.h:111
uint64_t target_addr_t
Definition: types.h:335