OpenOCD
armv8.c
Go to the documentation of this file.
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2015 by David Ung *
5  * *
6  * Copyright (C) 2018 by Liviu Ionescu *
7  * <ilg@livius.net> *
8  ***************************************************************************/
9 
10 #ifdef HAVE_CONFIG_H
11 #include "config.h"
12 #endif
13 
14 #include <helper/replacements.h>
15 
16 #include "armv8.h"
17 #include "arm_disassembler.h"
18 
19 #include "register.h"
20 #include <helper/binarybuffer.h>
21 #include <helper/command.h>
22 #include <helper/nvp.h>
23 
24 #include <stdlib.h>
25 #include <string.h>
26 #include <unistd.h>
27 
28 #include "armv8_opcodes.h"
29 #include "target.h"
30 #include "target_type.h"
31 #include "semihosting_common.h"
32 
33 static const char * const armv8_state_strings[] = {
34  "AArch32", "Thumb", "Jazelle", "ThumbEE", "AArch64",
35 };
36 
37 static const struct {
38  const char *name;
39  unsigned int psr;
40 } armv8_mode_data[] = {
41  {
42  .name = "USR",
43  .psr = ARM_MODE_USR,
44  },
45  {
46  .name = "FIQ",
47  .psr = ARM_MODE_FIQ,
48  },
49  {
50  .name = "IRQ",
51  .psr = ARM_MODE_IRQ,
52  },
53  {
54  .name = "SVC",
55  .psr = ARM_MODE_SVC,
56  },
57  {
58  .name = "MON",
59  .psr = ARM_MODE_MON,
60  },
61  {
62  .name = "ABT",
63  .psr = ARM_MODE_ABT,
64  },
65  {
66  .name = "HYP",
67  .psr = ARM_MODE_HYP,
68  },
69  {
70  .name = "UND",
71  .psr = ARM_MODE_UND,
72  },
73  {
74  .name = "SYS",
75  .psr = ARM_MODE_SYS,
76  },
77  {
78  .name = "EL0T",
79  .psr = ARMV8_64_EL0T,
80  },
81  {
82  .name = "EL1T",
83  .psr = ARMV8_64_EL1T,
84  },
85  {
86  .name = "EL1H",
87  .psr = ARMV8_64_EL1H,
88  },
89  {
90  .name = "EL2T",
91  .psr = ARMV8_64_EL2T,
92  },
93  {
94  .name = "EL2H",
95  .psr = ARMV8_64_EL2H,
96  },
97  {
98  .name = "EL3T",
99  .psr = ARMV8_64_EL3T,
100  },
101  {
102  .name = "EL3H",
103  .psr = ARMV8_64_EL3H,
104  },
105 };
106 
108 const char *armv8_mode_name(unsigned int psr_mode)
109 {
110  for (unsigned int i = 0; i < ARRAY_SIZE(armv8_mode_data); i++) {
111  if (armv8_mode_data[i].psr == psr_mode)
112  return armv8_mode_data[i].name;
113  }
114  LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
115  return "UNRECOGNIZED";
116 }
117 
118 static uint8_t armv8_pa_size(uint32_t ps)
119 {
120  uint8_t ret = 0;
121  switch (ps) {
122  case 0:
123  ret = 32;
124  break;
125  case 1:
126  ret = 36;
127  break;
128  case 2:
129  ret = 40;
130  break;
131  case 3:
132  ret = 42;
133  break;
134  case 4:
135  ret = 44;
136  break;
137  case 5:
138  ret = 48;
139  break;
140  default:
141  LOG_INFO("Unknown physical address size");
142  break;
143  }
144  return ret;
145 }
146 
147 static __attribute__((unused)) int armv8_read_ttbcr32(struct target *target)
148 {
149  struct armv8_common *armv8 = target_to_armv8(target);
150  struct arm_dpm *dpm = armv8->arm.dpm;
151  uint32_t ttbcr, ttbcr_n;
152  int retval = dpm->prepare(dpm);
153  if (retval != ERROR_OK)
154  goto done;
155  /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
156  retval = dpm->instr_read_data_r0(dpm,
157  ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
158  &ttbcr);
159  if (retval != ERROR_OK)
160  goto done;
161 
162  LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
163 
164  ttbcr_n = ttbcr & 0x7;
165  armv8->armv8_mmu.ttbcr = ttbcr;
166 
167  /*
168  * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
169  * document # ARM DDI 0406C
170  */
171  armv8->armv8_mmu.ttbr_range[0] = 0xffffffff >> ttbcr_n;
172  armv8->armv8_mmu.ttbr_range[1] = 0xffffffff;
173  armv8->armv8_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
174  armv8->armv8_mmu.ttbr_mask[1] = 0xffffffff << 14;
175 
176  LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
177  (ttbcr_n != 0) ? "used" : "not used",
178  armv8->armv8_mmu.ttbr_mask[0],
179  armv8->armv8_mmu.ttbr_mask[1]);
180 
181 done:
182  dpm->finish(dpm);
183  return retval;
184 }
185 
186 static int armv8_read_ttbcr(struct target *target)
187 {
188  struct armv8_common *armv8 = target_to_armv8(target);
189  struct arm_dpm *dpm = armv8->arm.dpm;
190  struct arm *arm = &armv8->arm;
191  uint32_t ttbcr;
192  uint64_t ttbcr_64;
193 
194  int retval = dpm->prepare(dpm);
195  if (retval != ERROR_OK)
196  goto done;
197 
198  /* clear ttrr1_used and ttbr0_mask */
199  memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
200  memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
201 
203  case SYSTEM_CUREL_EL3:
204  retval = dpm->instr_read_data_r0(dpm,
206  &ttbcr);
207  retval += dpm->instr_read_data_r0_64(dpm,
209  &armv8->ttbr_base);
210  if (retval != ERROR_OK)
211  goto done;
212  armv8->va_size = 64 - (ttbcr & 0x3F);
213  armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
214  armv8->page_size = (ttbcr >> 14) & 3;
215  break;
216  case SYSTEM_CUREL_EL2:
217  retval = dpm->instr_read_data_r0(dpm,
219  &ttbcr);
220  retval += dpm->instr_read_data_r0_64(dpm,
222  &armv8->ttbr_base);
223  if (retval != ERROR_OK)
224  goto done;
225  armv8->va_size = 64 - (ttbcr & 0x3F);
226  armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
227  armv8->page_size = (ttbcr >> 14) & 3;
228  break;
229  case SYSTEM_CUREL_EL0:
231  /* fall through */
232  case SYSTEM_CUREL_EL1:
233  retval = dpm->instr_read_data_r0_64(dpm,
235  &ttbcr_64);
236  armv8->va_size = 64 - (ttbcr_64 & 0x3F);
237  armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7);
238  armv8->page_size = (ttbcr_64 >> 14) & 3;
239  armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0;
240  armv8->armv8_mmu.ttbr0_mask = 0x0000FFFFFFFFFFFFULL;
241  retval += dpm->instr_read_data_r0_64(dpm,
243  &armv8->ttbr_base);
244  if (retval != ERROR_OK)
245  goto done;
246  break;
247  default:
248  LOG_ERROR("unknown core state");
249  retval = ERROR_FAIL;
250  break;
251  }
252  if (retval != ERROR_OK)
253  goto done;
254 
255  if (armv8->armv8_mmu.ttbr1_used == 1)
256  LOG_INFO("TTBR0 access above %" PRIx64, (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
257 
258 done:
260  dpm->finish(dpm);
261  return retval;
262 }
263 
264 static int armv8_get_pauth_mask(struct armv8_common *armv8, uint64_t *mask)
265 {
266  struct arm *arm = &armv8->arm;
267  int retval = ERROR_OK;
268  if (armv8->va_size == 0)
269  retval = armv8_read_ttbcr(arm->target);
270  if (retval != ERROR_OK)
271  return retval;
272 
273  *mask = ~(((uint64_t)1 << armv8->va_size) - 1);
274 
275  return retval;
276 }
277 
278 static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regval)
279 {
280  struct arm_dpm *dpm = &armv8->dpm;
281  unsigned int curel = armv8_curel_from_core_mode(dpm->arm->core_mode);
282  int retval;
283  uint32_t value;
284  uint64_t value_64;
285 
286  if (!regval)
287  return ERROR_FAIL;
288 
289  switch (regnum) {
290  case 0 ... 30:
291  retval = dpm->instr_read_data_dcc_64(dpm,
292  ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, regnum), &value_64);
293  break;
294  case ARMV8_SP:
295  retval = dpm->instr_read_data_r0_64(dpm,
296  ARMV8_MOVFSP_64(0), &value_64);
297  break;
298  case ARMV8_PC:
299  retval = dpm->instr_read_data_r0_64(dpm,
300  ARMV8_MRS_DLR(0), &value_64);
301  break;
302  case ARMV8_XPSR:
303  retval = dpm->instr_read_data_r0(dpm,
304  ARMV8_MRS_DSPSR(0), &value);
305  value_64 = value;
306  break;
307  case ARMV8_FPSR:
308  retval = dpm->instr_read_data_r0(dpm,
309  ARMV8_MRS_FPSR(0), &value);
310  value_64 = value;
311  break;
312  case ARMV8_FPCR:
313  retval = dpm->instr_read_data_r0(dpm,
314  ARMV8_MRS_FPCR(0), &value);
315  value_64 = value;
316  break;
317  case ARMV8_ELR_EL1:
318  if (curel < SYSTEM_CUREL_EL1) {
319  LOG_DEBUG("ELR_EL1 not accessible in EL%u", curel);
320  retval = ERROR_FAIL;
321  break;
322  }
323  retval = dpm->instr_read_data_r0_64(dpm,
324  ARMV8_MRS(SYSTEM_ELR_EL1, 0), &value_64);
325  break;
326  case ARMV8_ELR_EL2:
327  if (curel < SYSTEM_CUREL_EL2) {
328  LOG_DEBUG("ELR_EL2 not accessible in EL%u", curel);
329  retval = ERROR_FAIL;
330  break;
331  }
332  retval = dpm->instr_read_data_r0_64(dpm,
333  ARMV8_MRS(SYSTEM_ELR_EL2, 0), &value_64);
334  break;
335  case ARMV8_ELR_EL3:
336  if (curel < SYSTEM_CUREL_EL3) {
337  LOG_DEBUG("ELR_EL3 not accessible in EL%u", curel);
338  retval = ERROR_FAIL;
339  break;
340  }
341  retval = dpm->instr_read_data_r0_64(dpm,
342  ARMV8_MRS(SYSTEM_ELR_EL3, 0), &value_64);
343  break;
344  case ARMV8_ESR_EL1:
345  if (curel < SYSTEM_CUREL_EL1) {
346  LOG_DEBUG("ESR_EL1 not accessible in EL%u", curel);
347  retval = ERROR_FAIL;
348  break;
349  }
350  retval = dpm->instr_read_data_r0_64(dpm,
351  ARMV8_MRS(SYSTEM_ESR_EL1, 0), &value_64);
352  break;
353  case ARMV8_ESR_EL2:
354  if (curel < SYSTEM_CUREL_EL2) {
355  LOG_DEBUG("ESR_EL2 not accessible in EL%u", curel);
356  retval = ERROR_FAIL;
357  break;
358  }
359  retval = dpm->instr_read_data_r0_64(dpm,
360  ARMV8_MRS(SYSTEM_ESR_EL2, 0), &value_64);
361  break;
362  case ARMV8_ESR_EL3:
363  if (curel < SYSTEM_CUREL_EL3) {
364  LOG_DEBUG("ESR_EL3 not accessible in EL%u", curel);
365  retval = ERROR_FAIL;
366  break;
367  }
368  retval = dpm->instr_read_data_r0_64(dpm,
369  ARMV8_MRS(SYSTEM_ESR_EL3, 0), &value_64);
370  break;
371  case ARMV8_SPSR_EL1:
372  if (curel < SYSTEM_CUREL_EL1) {
373  LOG_DEBUG("SPSR_EL1 not accessible in EL%u", curel);
374  retval = ERROR_FAIL;
375  break;
376  }
377  retval = dpm->instr_read_data_r0_64(dpm,
378  ARMV8_MRS(SYSTEM_SPSR_EL1, 0), &value_64);
379  break;
380  case ARMV8_SPSR_EL2:
381  if (curel < SYSTEM_CUREL_EL2) {
382  LOG_DEBUG("SPSR_EL2 not accessible in EL%u", curel);
383  retval = ERROR_FAIL;
384  break;
385  }
386  retval = dpm->instr_read_data_r0_64(dpm,
387  ARMV8_MRS(SYSTEM_SPSR_EL2, 0), &value_64);
388  break;
389  case ARMV8_SPSR_EL3:
390  if (curel < SYSTEM_CUREL_EL3) {
391  LOG_DEBUG("SPSR_EL3 not accessible in EL%u", curel);
392  retval = ERROR_FAIL;
393  break;
394  }
395  retval = dpm->instr_read_data_r0_64(dpm,
396  ARMV8_MRS(SYSTEM_SPSR_EL3, 0), &value_64);
397  break;
398  case ARMV8_PAUTH_CMASK:
399  case ARMV8_PAUTH_DMASK:
400  retval = armv8_get_pauth_mask(armv8, &value_64);
401  break;
402  default:
403  retval = ERROR_FAIL;
404  break;
405  }
406 
407  if (retval == ERROR_OK)
408  *regval = value_64;
409 
410  return retval;
411 }
412 
413 static int armv8_read_reg_simdfp_aarch64(struct armv8_common *armv8, int regnum, uint64_t *lvalue, uint64_t *hvalue)
414 {
415  int retval = ERROR_FAIL;
416  struct arm_dpm *dpm = &armv8->dpm;
417 
418  switch (regnum) {
419  case ARMV8_V0 ... ARMV8_V31:
420  retval = dpm->instr_read_data_r0_64(dpm,
421  ARMV8_MOV_GPR_VFP(0, (regnum - ARMV8_V0), 1), hvalue);
422  if (retval != ERROR_OK)
423  return retval;
424  retval = dpm->instr_read_data_r0_64(dpm,
425  ARMV8_MOV_GPR_VFP(0, (regnum - ARMV8_V0), 0), lvalue);
426  break;
427 
428  default:
429  retval = ERROR_FAIL;
430  break;
431  }
432 
433  return retval;
434 }
435 
436 static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t value_64)
437 {
438  struct arm_dpm *dpm = &armv8->dpm;
439  unsigned int curel = armv8_curel_from_core_mode(dpm->arm->core_mode);
440  int retval;
441  uint32_t value;
442 
443  switch (regnum) {
444  case 0 ... 30:
445  retval = dpm->instr_write_data_dcc_64(dpm,
447  value_64);
448  break;
449  case ARMV8_SP:
450  retval = dpm->instr_write_data_r0_64(dpm,
451  ARMV8_MOVTSP_64(0),
452  value_64);
453  break;
454  case ARMV8_PC:
455  retval = dpm->instr_write_data_r0_64(dpm,
456  ARMV8_MSR_DLR(0),
457  value_64);
458  break;
459  case ARMV8_XPSR:
460  value = value_64;
461  retval = dpm->instr_write_data_r0(dpm,
462  ARMV8_MSR_DSPSR(0),
463  value);
464  break;
465  case ARMV8_FPSR:
466  value = value_64;
467  retval = dpm->instr_write_data_r0(dpm,
468  ARMV8_MSR_FPSR(0),
469  value);
470  break;
471  case ARMV8_FPCR:
472  value = value_64;
473  retval = dpm->instr_write_data_r0(dpm,
474  ARMV8_MSR_FPCR(0),
475  value);
476  break;
477  /* registers clobbered by taking exception in debug state */
478  case ARMV8_ELR_EL1:
479  if (curel < SYSTEM_CUREL_EL1) {
480  LOG_DEBUG("ELR_EL1 not accessible in EL%u", curel);
481  retval = ERROR_FAIL;
482  break;
483  }
484  retval = dpm->instr_write_data_r0_64(dpm,
485  ARMV8_MSR_GP(SYSTEM_ELR_EL1, 0), value_64);
486  break;
487  case ARMV8_ELR_EL2:
488  if (curel < SYSTEM_CUREL_EL2) {
489  LOG_DEBUG("ELR_EL2 not accessible in EL%u", curel);
490  retval = ERROR_FAIL;
491  break;
492  }
493  retval = dpm->instr_write_data_r0_64(dpm,
494  ARMV8_MSR_GP(SYSTEM_ELR_EL2, 0), value_64);
495  break;
496  case ARMV8_ELR_EL3:
497  if (curel < SYSTEM_CUREL_EL3) {
498  LOG_DEBUG("ELR_EL3 not accessible in EL%u", curel);
499  retval = ERROR_FAIL;
500  break;
501  }
502  retval = dpm->instr_write_data_r0_64(dpm,
503  ARMV8_MSR_GP(SYSTEM_ELR_EL3, 0), value_64);
504  break;
505  case ARMV8_ESR_EL1:
506  if (curel < SYSTEM_CUREL_EL1) {
507  LOG_DEBUG("ESR_EL1 not accessible in EL%u", curel);
508  retval = ERROR_FAIL;
509  break;
510  }
511  retval = dpm->instr_write_data_r0_64(dpm,
512  ARMV8_MSR_GP(SYSTEM_ESR_EL1, 0), value_64);
513  break;
514  case ARMV8_ESR_EL2:
515  if (curel < SYSTEM_CUREL_EL2) {
516  LOG_DEBUG("ESR_EL2 not accessible in EL%u", curel);
517  retval = ERROR_FAIL;
518  break;
519  }
520  retval = dpm->instr_write_data_r0_64(dpm,
521  ARMV8_MSR_GP(SYSTEM_ESR_EL2, 0), value_64);
522  break;
523  case ARMV8_ESR_EL3:
524  if (curel < SYSTEM_CUREL_EL3) {
525  LOG_DEBUG("ESR_EL3 not accessible in EL%u", curel);
526  retval = ERROR_FAIL;
527  break;
528  }
529  retval = dpm->instr_write_data_r0_64(dpm,
530  ARMV8_MSR_GP(SYSTEM_ESR_EL3, 0), value_64);
531  break;
532  case ARMV8_SPSR_EL1:
533  if (curel < SYSTEM_CUREL_EL1) {
534  LOG_DEBUG("SPSR_EL1 not accessible in EL%u", curel);
535  retval = ERROR_FAIL;
536  break;
537  }
538  retval = dpm->instr_write_data_r0_64(dpm,
539  ARMV8_MSR_GP(SYSTEM_SPSR_EL1, 0), value_64);
540  break;
541  case ARMV8_SPSR_EL2:
542  if (curel < SYSTEM_CUREL_EL2) {
543  LOG_DEBUG("SPSR_EL2 not accessible in EL%u", curel);
544  retval = ERROR_FAIL;
545  break;
546  }
547  retval = dpm->instr_write_data_r0_64(dpm,
548  ARMV8_MSR_GP(SYSTEM_SPSR_EL2, 0), value_64);
549  break;
550  case ARMV8_SPSR_EL3:
551  if (curel < SYSTEM_CUREL_EL3) {
552  LOG_DEBUG("SPSR_EL3 not accessible in EL%u", curel);
553  retval = ERROR_FAIL;
554  break;
555  }
556  retval = dpm->instr_write_data_r0_64(dpm,
557  ARMV8_MSR_GP(SYSTEM_SPSR_EL3, 0), value_64);
558  break;
559  default:
560  retval = ERROR_FAIL;
561  break;
562  }
563 
564  return retval;
565 }
566 
567 static int armv8_write_reg_simdfp_aarch64(struct armv8_common *armv8, int regnum, uint64_t lvalue, uint64_t hvalue)
568 {
569  int retval = ERROR_FAIL;
570  struct arm_dpm *dpm = &armv8->dpm;
571 
572  switch (regnum) {
573  case ARMV8_V0 ... ARMV8_V31:
574  retval = dpm->instr_write_data_r0_64(dpm,
575  ARMV8_MOV_VFP_GPR((regnum - ARMV8_V0), 0, 1), hvalue);
576  if (retval != ERROR_OK)
577  return retval;
578  retval = dpm->instr_write_data_r0_64(dpm,
579  ARMV8_MOV_VFP_GPR((regnum - ARMV8_V0), 0, 0), lvalue);
580  break;
581 
582  default:
583  retval = ERROR_FAIL;
584  break;
585  }
586 
587  return retval;
588 }
589 
590 static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *regval)
591 {
592  struct arm_dpm *dpm = &armv8->dpm;
593  uint32_t value = 0;
594  int retval;
595 
596  if (!regval)
597  return ERROR_FAIL;
598 
599  switch (regnum) {
600  case ARMV8_R0 ... ARMV8_R14:
601  /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
602  retval = dpm->instr_read_data_dcc(dpm,
603  ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
604  &value);
605  break;
606  case ARMV8_SP:
607  retval = dpm->instr_read_data_dcc(dpm,
608  ARMV4_5_MCR(14, 0, 13, 0, 5, 0),
609  &value);
610  break;
611  case ARMV8_PC:
612  retval = dpm->instr_read_data_r0(dpm,
613  ARMV8_MRC_DLR(0),
614  &value);
615  break;
616  case ARMV8_XPSR:
617  retval = dpm->instr_read_data_r0(dpm,
618  ARMV8_MRC_DSPSR(0),
619  &value);
620  break;
621  case ARMV8_ELR_EL1: /* mapped to LR_svc */
622  retval = dpm->instr_read_data_dcc(dpm,
623  ARMV4_5_MCR(14, 0, 14, 0, 5, 0),
624  &value);
625  break;
626  case ARMV8_ELR_EL2: /* mapped to ELR_hyp */
627  retval = dpm->instr_read_data_r0(dpm,
628  ARMV8_MRS_T1(0, 14, 0, 1),
629  &value);
630  break;
631  case ARMV8_ELR_EL3: /* mapped to LR_mon */
632  retval = dpm->instr_read_data_dcc(dpm,
633  ARMV4_5_MCR(14, 0, 14, 0, 5, 0),
634  &value);
635  break;
636  case ARMV8_ESR_EL1: /* mapped to DFSR */
637  retval = dpm->instr_read_data_r0(dpm,
638  ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
639  &value);
640  break;
641  case ARMV8_ESR_EL2: /* mapped to HSR */
642  retval = dpm->instr_read_data_r0(dpm,
643  ARMV4_5_MRC(15, 4, 0, 5, 2, 0),
644  &value);
645  break;
646  case ARMV8_ESR_EL3: /* no equivalent in aarch32 */
647  retval = ERROR_FAIL;
648  break;
649  case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
650  retval = dpm->instr_read_data_r0(dpm,
651  ARMV8_MRS_XPSR_T1(1, 0),
652  &value);
653  break;
654  case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
655  retval = dpm->instr_read_data_r0(dpm,
656  ARMV8_MRS_XPSR_T1(1, 0),
657  &value);
658  break;
659  case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
660  retval = dpm->instr_read_data_r0(dpm,
661  ARMV8_MRS_XPSR_T1(1, 0),
662  &value);
663  break;
664  case ARMV8_FPSR:
665  /* "VMRS r0, FPSCR"; then return via DCC */
666  retval = dpm->instr_read_data_r0(dpm,
667  ARMV4_5_VMRS(0), &value);
668  break;
669  default:
670  retval = ERROR_FAIL;
671  break;
672  }
673 
674  if (retval == ERROR_OK)
675  *regval = value;
676 
677  return retval;
678 }
679 
680 static int armv8_read_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum, uint64_t *lvalue, uint64_t *hvalue)
681 {
682  int retval = ERROR_FAIL;
683  struct arm_dpm *dpm = &armv8->dpm;
684  struct reg *reg_r1 = dpm->arm->core_cache->reg_list + ARMV8_R1;
685  uint32_t value_r0 = 0, value_r1 = 0;
686  unsigned int num = (regnum - ARMV8_V0) << 1;
687 
688  switch (regnum) {
689  case ARMV8_V0 ... ARMV8_V15:
690  /* we are going to write R1, mark it dirty */
691  reg_r1->dirty = true;
692  /* move from double word register to r0:r1: "vmov r0, r1, vm"
693  * then read r0 via dcc
694  */
695  retval = dpm->instr_read_data_r0(dpm,
696  ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
697  &value_r0);
698  if (retval != ERROR_OK)
699  return retval;
700  /* read r1 via dcc */
701  retval = dpm->instr_read_data_dcc(dpm,
702  ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
703  &value_r1);
704  if (retval != ERROR_OK)
705  return retval;
706  *lvalue = value_r1;
707  *lvalue = ((*lvalue) << 32) | value_r0;
708 
709  num++;
710  /* repeat above steps for high 64 bits of V register */
711  retval = dpm->instr_read_data_r0(dpm,
712  ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
713  &value_r0);
714  if (retval != ERROR_OK)
715  return retval;
716  retval = dpm->instr_read_data_dcc(dpm,
717  ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
718  &value_r1);
719  if (retval != ERROR_OK)
720  return retval;
721  *hvalue = value_r1;
722  *hvalue = ((*hvalue) << 32) | value_r0;
723  break;
724  default:
725  retval = ERROR_FAIL;
726  break;
727  }
728 
729  return retval;
730 }
731 
732 static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t value)
733 {
734  struct arm_dpm *dpm = &armv8->dpm;
735  int retval;
736 
737  switch (regnum) {
738  case ARMV8_R0 ... ARMV8_R14:
739  /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
740  retval = dpm->instr_write_data_dcc(dpm,
741  ARMV4_5_MRC(14, 0, regnum, 0, 5, 0), value);
742  break;
743  case ARMV8_SP:
744  retval = dpm->instr_write_data_dcc(dpm,
745  ARMV4_5_MRC(14, 0, 13, 0, 5, 0), value);
746  break;
747  case ARMV8_PC:/* PC
748  * read r0 from DCC; then "MOV pc, r0" */
749  retval = dpm->instr_write_data_r0(dpm,
750  ARMV8_MCR_DLR(0), value);
751  break;
752  case ARMV8_XPSR: /* CPSR */
753  /* read r0 from DCC, then "MCR r0, DSPSR" */
754  retval = dpm->instr_write_data_r0(dpm,
755  ARMV8_MCR_DSPSR(0), value);
756  break;
757  case ARMV8_ELR_EL1: /* mapped to LR_svc */
758  retval = dpm->instr_write_data_dcc(dpm,
759  ARMV4_5_MRC(14, 0, 14, 0, 5, 0),
760  value);
761  break;
762  case ARMV8_ELR_EL2: /* mapped to ELR_hyp */
763  retval = dpm->instr_write_data_r0(dpm,
764  ARMV8_MSR_GP_T1(0, 14, 0, 1),
765  value);
766  break;
767  case ARMV8_ELR_EL3: /* mapped to LR_mon */
768  retval = dpm->instr_write_data_dcc(dpm,
769  ARMV4_5_MRC(14, 0, 14, 0, 5, 0),
770  value);
771  break;
772  case ARMV8_ESR_EL1: /* mapped to DFSR */
773  retval = dpm->instr_write_data_r0(dpm,
774  ARMV4_5_MCR(15, 0, 0, 5, 0, 0),
775  value);
776  break;
777  case ARMV8_ESR_EL2: /* mapped to HSR */
778  retval = dpm->instr_write_data_r0(dpm,
779  ARMV4_5_MCR(15, 4, 0, 5, 2, 0),
780  value);
781  break;
782  case ARMV8_ESR_EL3: /* no equivalent in aarch32 */
783  retval = ERROR_FAIL;
784  break;
785  case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
786  retval = dpm->instr_write_data_r0(dpm,
787  ARMV8_MSR_GP_XPSR_T1(1, 0, 15),
788  value);
789  break;
790  case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
791  retval = dpm->instr_write_data_r0(dpm,
792  ARMV8_MSR_GP_XPSR_T1(1, 0, 15),
793  value);
794  break;
795  case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
796  retval = dpm->instr_write_data_r0(dpm,
797  ARMV8_MSR_GP_XPSR_T1(1, 0, 15),
798  value);
799  break;
800  case ARMV8_FPSR:
801  /* move to r0 from DCC, then "VMSR FPSCR, r0" */
802  retval = dpm->instr_write_data_r0(dpm,
803  ARMV4_5_VMSR(0), value);
804  break;
805  default:
806  retval = ERROR_FAIL;
807  break;
808  }
809 
810  return retval;
811 
812 }
813 
814 static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum, uint64_t lvalue, uint64_t hvalue)
815 {
816  int retval = ERROR_FAIL;
817  struct arm_dpm *dpm = &armv8->dpm;
818  struct reg *reg_r1 = dpm->arm->core_cache->reg_list + ARMV8_R1;
819  uint32_t value_r0 = 0, value_r1 = 0;
820  unsigned int num = (regnum - ARMV8_V0) << 1;
821 
822  switch (regnum) {
823  case ARMV8_V0 ... ARMV8_V15:
824  /* we are going to write R1, mark it dirty */
825  reg_r1->dirty = true;
826  value_r1 = lvalue >> 32;
827  value_r0 = lvalue & 0xFFFFFFFF;
828  /* write value_r1 to r1 via dcc */
829  retval = dpm->instr_write_data_dcc(dpm,
830  ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
831  value_r1);
832  if (retval != ERROR_OK)
833  return retval;
834  /* write value_r0 to r0 via dcc then,
835  * move to double word register from r0:r1: "vmov vm, r0, r1"
836  */
837  retval = dpm->instr_write_data_r0(dpm,
838  ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
839  value_r0);
840  if (retval != ERROR_OK)
841  return retval;
842 
843  num++;
844  /* repeat above steps for high 64 bits of V register */
845  value_r1 = hvalue >> 32;
846  value_r0 = hvalue & 0xFFFFFFFF;
847  retval = dpm->instr_write_data_dcc(dpm,
848  ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
849  value_r1);
850  if (retval != ERROR_OK)
851  return retval;
852  retval = dpm->instr_write_data_r0(dpm,
853  ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
854  value_r0);
855  break;
856  default:
857  retval = ERROR_FAIL;
858  break;
859  }
860 
861  return retval;
862 }
863 
864 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64)
865 {
866  if (is_aarch64) {
867  armv8->read_reg_u64 = armv8_read_reg;
871 
872  } else {
877  }
878 }
879 
880 /* retrieve core id cluster id */
881 int armv8_read_mpidr(struct armv8_common *armv8)
882 {
883  int retval = ERROR_FAIL;
884  struct arm *arm = &armv8->arm;
885  struct arm_dpm *dpm = armv8->arm.dpm;
886  uint32_t mpidr;
887 
888  retval = dpm->prepare(dpm);
889  if (retval != ERROR_OK)
890  goto done;
891 
892  /* check if we're in an unprivileged mode */
894  retval = armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H);
895  if (retval != ERROR_OK)
896  return retval;
897  }
898 
899  retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
900  if (retval != ERROR_OK)
901  goto done;
902  if (mpidr & 1U<<31) {
903  armv8->multi_processor_system = (mpidr >> 30) & 1;
904  armv8->cluster_id = (mpidr >> 8) & 0xf;
905  armv8->cpu_id = mpidr & 0x3;
906  LOG_INFO("%s cluster %x core %x %s", target_name(armv8->arm.target),
907  armv8->cluster_id,
908  armv8->cpu_id,
909  armv8->multi_processor_system == 0 ? "multi core" : "single core");
910  } else
911  LOG_ERROR("mpidr not in multiprocessor format");
912 
913 done:
915  dpm->finish(dpm);
916  return retval;
917 }
918 
924 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
925 {
926  uint32_t mode = cpsr & 0x1F;
927 
928  /* NOTE: this may be called very early, before the register
929  * cache is set up. We can't defend against many errors, in
930  * particular against CPSRs that aren't valid *here* ...
931  */
932  if (arm->cpsr) {
933  buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
934  arm->cpsr->valid = true;
935  arm->cpsr->dirty = false;
936  }
937 
938  /* Older ARMs won't have the J bit */
939  enum arm_state state = 0xFF;
940 
941  if ((cpsr & 0x10) != 0) {
942  /* Aarch32 state */
943  if (cpsr & (1 << 5)) { /* T */
944  if (cpsr & (1 << 24)) { /* J */
945  LOG_WARNING("ThumbEE -- incomplete support");
947  } else
949  } else {
950  if (cpsr & (1 << 24)) { /* J */
951  LOG_ERROR("Jazelle state handling is BROKEN!");
953  } else
955  }
956  } else {
957  /* Aarch64 state */
959  }
960 
961  arm->core_state = state;
962  arm->core_mode = mode;
963 
964  LOG_DEBUG("set CPSR %#8.8" PRIx32 ": %s mode, %s state", cpsr,
967 }
968 
969 static void armv8_show_fault_registers32(struct armv8_common *armv8)
970 {
971  uint32_t dfsr, ifsr, dfar, ifar;
972  struct arm_dpm *dpm = armv8->arm.dpm;
973  int retval;
974 
975  retval = dpm->prepare(dpm);
976  if (retval != ERROR_OK)
977  return;
978 
979  /* ARMV4_5_MRC(cpnum, op1, r0, crn, crm, op2) */
980 
981  /* c5/c0 - {data, instruction} fault status registers */
982  retval = dpm->instr_read_data_r0(dpm,
983  ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
984  &dfsr);
985  if (retval != ERROR_OK)
986  goto done;
987 
988  retval = dpm->instr_read_data_r0(dpm,
989  ARMV4_5_MRC(15, 0, 0, 5, 0, 1),
990  &ifsr);
991  if (retval != ERROR_OK)
992  goto done;
993 
994  /* c6/c0 - {data, instruction} fault address registers */
995  retval = dpm->instr_read_data_r0(dpm,
996  ARMV4_5_MRC(15, 0, 0, 6, 0, 0),
997  &dfar);
998  if (retval != ERROR_OK)
999  goto done;
1000 
1001  retval = dpm->instr_read_data_r0(dpm,
1002  ARMV4_5_MRC(15, 0, 0, 6, 0, 2),
1003  &ifar);
1004  if (retval != ERROR_OK)
1005  goto done;
1006 
1007  LOG_USER("Data fault registers DFSR: %8.8" PRIx32
1008  ", DFAR: %8.8" PRIx32, dfsr, dfar);
1009  LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
1010  ", IFAR: %8.8" PRIx32, ifsr, ifar);
1011 
1012 done:
1013  dpm->finish(dpm);
1014 }
1015 
1016 static __attribute__((unused)) void armv8_show_fault_registers(struct target *target)
1017 {
1018  struct armv8_common *armv8 = target_to_armv8(target);
1019 
1020  if (armv8->arm.core_state != ARM_STATE_AARCH64)
1022 }
1023 
1024 /* method adapted to cortex A : reused arm v4 v5 method*/
1026 {
1027  return ERROR_OK;
1028 }
1029 
1030 static void armv8_decode_cacheability(int attr)
1031 {
1032  if (attr == 0) {
1033  LOG_USER_N("UNPREDICTABLE");
1034  return;
1035  }
1036  if (attr == 4) {
1037  LOG_USER_N("Non-cacheable");
1038  return;
1039  }
1040  switch (attr & 0xC) {
1041  case 0:
1042  LOG_USER_N("Write-Through Transient");
1043  break;
1044  case 0x4:
1045  LOG_USER_N("Write-Back Transient");
1046  break;
1047  case 0x8:
1048  LOG_USER_N("Write-Through Non-transient");
1049  break;
1050  case 0xC:
1051  LOG_USER_N("Write-Back Non-transient");
1052  break;
1053  }
1054  if (attr & 2)
1055  LOG_USER_N(" Read-Allocate");
1056  else
1057  LOG_USER_N(" No-Read Allocate");
1058  if (attr & 1)
1059  LOG_USER_N(" Write-Allocate");
1060  else
1061  LOG_USER_N(" No-Write Allocate");
1062 }
1063 
1064 static void armv8_decode_memory_attr(int attr)
1065 {
1066  if (attr == 0x40) {
1067  LOG_USER("Normal Memory, Inner Non-cacheable, "
1068  "Outer Non-cacheable, XS=0");
1069  } else if (attr == 0xA0) {
1070  LOG_USER("Normal Memory, Inner Write-through Cacheable, "
1071  "Outer Write-through Cacheable, Read-Allocate, "
1072  "No-Write Allocate, Non-transient, XS=0");
1073  } else if (attr == 0xF0) {
1074  LOG_USER("Tagged Normal Memory, Inner Write-Back, "
1075  "Outer Write-Back, Read-Allocate, Write-Allocate, "
1076  "Non-transient");
1077  } else if ((attr & 0xF0) == 0) {
1078  switch (attr & 0xC) {
1079  case 0:
1080  LOG_USER_N("Device-nGnRnE Memory");
1081  break;
1082  case 0x4:
1083  LOG_USER_N("Device-nGnRE Memory");
1084  break;
1085  case 0x8:
1086  LOG_USER_N("Device-nGRE Memory");
1087  break;
1088  case 0xC:
1089  LOG_USER_N("Device-GRE Memory");
1090  break;
1091  }
1092  if (attr & 1)
1093  LOG_USER(", XS=0");
1094  else
1095  LOG_USER_N("\n");
1096  } else {
1097  LOG_USER_N("Normal Memory, Inner ");
1098  armv8_decode_cacheability(attr & 0xF);
1099  LOG_USER_N(", Outer ");
1100  armv8_decode_cacheability(attr >> 4);
1101  LOG_USER_N("\n");
1102  }
1103 }
1104 
1105 /* V8 method VA TO PA */
1107  target_addr_t *val, int meminfo)
1108 {
1109  struct armv8_common *armv8 = target_to_armv8(target);
1110  struct arm *arm = target_to_arm(target);
1111  struct arm_dpm *dpm = &armv8->dpm;
1112  enum arm_mode target_mode = ARM_MODE_ANY;
1113  uint32_t retval;
1114  uint32_t instr = 0;
1115  uint64_t par;
1116 
1117  static const char * const shared_name[] = {
1118  "Non-", "UNDEFINED ", "Outer ", "Inner "
1119  };
1120 
1121  static const char * const secure_name[] = {
1122  "Secure", "Not Secure"
1123  };
1124 
1125  if (target->state != TARGET_HALTED) {
1126  LOG_TARGET_ERROR(target, "not halted");
1127  return ERROR_TARGET_NOT_HALTED;
1128  }
1129 
1130  retval = dpm->prepare(dpm);
1131  if (retval != ERROR_OK)
1132  return retval;
1133 
1135  case SYSTEM_CUREL_EL0:
1136  instr = ARMV8_SYS(SYSTEM_ATS12E0R, 0);
1137  /* can only execute instruction at EL2 */
1138  target_mode = ARMV8_64_EL2H;
1139  break;
1140  case SYSTEM_CUREL_EL1:
1141  instr = ARMV8_SYS(SYSTEM_ATS12E1R, 0);
1142  /* can only execute instruction at EL2 */
1143  target_mode = ARMV8_64_EL2H;
1144  break;
1145  case SYSTEM_CUREL_EL2:
1146  instr = ARMV8_SYS(SYSTEM_ATS1E2R, 0);
1147  break;
1148  case SYSTEM_CUREL_EL3:
1149  instr = ARMV8_SYS(SYSTEM_ATS1E3R, 0);
1150  break;
1151 
1152  default:
1153  break;
1154  };
1155 
1156  if (target_mode != ARM_MODE_ANY)
1157  armv8_dpm_modeswitch(dpm, target_mode);
1158 
1159  /* write VA to R0 and execute translation instruction */
1160  retval = dpm->instr_write_data_r0_64(dpm, instr, (uint64_t)va);
1161  /* read result from PAR_EL1 */
1162  if (retval == ERROR_OK)
1163  retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS(SYSTEM_PAR_EL1, 0), &par);
1164 
1165  /* switch back to saved PE mode */
1166  if (target_mode != ARM_MODE_ANY)
1168 
1169  dpm->finish(dpm);
1170 
1171  if (retval != ERROR_OK)
1172  return retval;
1173 
1174  if (par & 1) {
1175  LOG_ERROR("Address translation failed at stage %i, FST=%x, PTW=%i",
1176  ((int)(par >> 9) & 1)+1, (int)(par >> 1) & 0x3f, (int)(par >> 8) & 1);
1177 
1178  *val = 0;
1179  retval = ERROR_FAIL;
1180  } else {
1181  *val = (par & 0xFFFFFFFFF000UL) | (va & 0xFFF);
1182  if (meminfo) {
1183  int SH = (par >> 7) & 3;
1184  int NS = (par >> 9) & 1;
1185  int ATTR = (par >> 56) & 0xFF;
1186 
1187  LOG_USER("%sshareable, %s",
1188  shared_name[SH], secure_name[NS]);
1190  }
1191  }
1192 
1193  return retval;
1194 }
1195 
1196 COMMAND_HANDLER(armv8_handle_exception_catch_command)
1197 {
1199  struct armv8_common *armv8 = target_to_armv8(target);
1200  uint32_t edeccr = 0;
1201  unsigned int argp = 0;
1202  int retval;
1203 
1204  static const struct nvp nvp_ecatch_modes[] = {
1205  { .name = "off", .value = 0 },
1206  { .name = "nsec_el1", .value = (1 << 5) },
1207  { .name = "nsec_el2", .value = (2 << 5) },
1208  { .name = "nsec_el12", .value = (3 << 5) },
1209  { .name = "sec_el1", .value = (1 << 1) },
1210  { .name = "sec_el3", .value = (4 << 1) },
1211  { .name = "sec_el13", .value = (5 << 1) },
1212  { .name = NULL, .value = -1 },
1213  };
1214  const struct nvp *n;
1215 
1216  if (CMD_ARGC == 0) {
1217  const char *sec = NULL, *nsec = NULL;
1218 
1219  retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1220  armv8->debug_base + CPUV8_DBG_ECCR, &edeccr);
1221  if (retval != ERROR_OK)
1222  return retval;
1223 
1224  n = nvp_value2name(nvp_ecatch_modes, edeccr & 0x0f);
1225  if (n->name)
1226  sec = n->name;
1227 
1228  n = nvp_value2name(nvp_ecatch_modes, edeccr & 0xf0);
1229  if (n->name)
1230  nsec = n->name;
1231 
1232  if (!sec || !nsec) {
1233  LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02" PRIx32, edeccr & 0xff);
1234  return ERROR_FAIL;
1235  }
1236 
1237  command_print(CMD, "Exception Catch: Secure: %s, Non-Secure: %s", sec, nsec);
1238  return ERROR_OK;
1239  }
1240 
1241  while (argp < CMD_ARGC) {
1242  n = nvp_name2value(nvp_ecatch_modes, CMD_ARGV[argp]);
1243  if (!n->name) {
1244  LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]);
1245  return ERROR_FAIL;
1246  }
1247 
1248  LOG_DEBUG("found: %s", n->name);
1249 
1250  edeccr |= n->value;
1251  argp++;
1252  }
1253 
1254  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1255  armv8->debug_base + CPUV8_DBG_ECCR, edeccr);
1256  if (retval != ERROR_OK)
1257  return retval;
1258 
1259  return ERROR_OK;
1260 }
1261 
1262 COMMAND_HANDLER(armv8_pauth_command)
1263 {
1265  struct armv8_common *armv8 = target_to_armv8(target);
1266  return CALL_COMMAND_HANDLER(handle_command_parse_bool,
1267  &armv8->enable_pauth,
1268  "pauth feature");
1269 }
1270 
1272  struct armv8_cache_common *armv8_cache)
1273 {
1274  if (armv8_cache->info == -1) {
1275  command_print(cmd, "cache not yet identified");
1276  return ERROR_OK;
1277  }
1278 
1279  if (armv8_cache->display_cache_info)
1280  armv8_cache->display_cache_info(cmd, armv8_cache);
1281  return ERROR_OK;
1282 }
1283 
1284 static int armv8_setup_semihosting(struct target *target, int enable)
1285 {
1286  return ERROR_OK;
1287 }
1288 
1289 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
1290 {
1291  struct arm *arm = &armv8->arm;
1292  arm->arch_info = armv8;
1293  target->arch_info = &armv8->arm;
1295  /* target is useful in all function arm v4 5 compatible */
1296  armv8->arm.target = target;
1299 
1301  armv8->armv8_mmu.armv8_cache.info = -1;
1304  return ERROR_OK;
1305 }
1306 
1307 static int armv8_aarch64_state(struct target *target)
1308 {
1309  struct arm *arm = target_to_arm(target);
1310 
1311  if (arm->common_magic != ARM_COMMON_MAGIC) {
1312  LOG_ERROR("BUG: called for a non-ARM target");
1313  return ERROR_FAIL;
1314  }
1315 
1316  LOG_USER("%s halted in %s state due to %s, current mode: %s\n"
1317  "cpsr: 0x%8.8" PRIx32 " pc: 0x%" PRIx64 "%s",
1322  buf_get_u32(arm->cpsr->value, 0, 32),
1323  buf_get_u64(arm->pc->value, 0, 64),
1324  (target->semihosting && target->semihosting->is_active) ? ", semihosting" : "");
1325 
1326  return ERROR_OK;
1327 }
1328 
1330 {
1331  static const char * const state[] = {
1332  "disabled", "enabled"
1333  };
1334 
1335  struct armv8_common *armv8 = target_to_armv8(target);
1336  struct arm *arm = &armv8->arm;
1337 
1338  if (armv8->common_magic != ARMV8_COMMON_MAGIC) {
1339  LOG_ERROR("BUG: called for a non-Armv8 target");
1341  }
1342 
1345  else
1347 
1348  LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
1349  state[armv8->armv8_mmu.mmu_enabled],
1352 
1353  if (arm->core_mode == ARM_MODE_ABT)
1354  armv8_show_fault_registers(target);
1355 
1357  LOG_USER("Watchpoint triggered at " TARGET_ADDR_FMT, armv8->dpm.wp_addr);
1358 
1359  return ERROR_OK;
1360 }
1361 
1362 static struct reg_data_type aarch64_vector_base_types[] = {
1363  {REG_TYPE_IEEE_DOUBLE, "ieee_double", 0, {NULL} },
1364  {REG_TYPE_UINT64, "uint64", 0, {NULL} },
1365  {REG_TYPE_INT64, "int64", 0, {NULL} },
1366  {REG_TYPE_IEEE_SINGLE, "ieee_single", 0, {NULL} },
1367  {REG_TYPE_UINT32, "uint32", 0, {NULL} },
1368  {REG_TYPE_INT32, "int32", 0, {NULL} },
1369  {REG_TYPE_UINT16, "uint16", 0, {NULL} },
1370  {REG_TYPE_INT16, "int16", 0, {NULL} },
1371  {REG_TYPE_UINT8, "uint8", 0, {NULL} },
1372  {REG_TYPE_INT8, "int8", 0, {NULL} },
1373  {REG_TYPE_UINT128, "uint128", 0, {NULL} },
1374  {REG_TYPE_INT128, "int128", 0, {NULL} }
1375 };
1376 
1377 static struct reg_data_type_vector aarch64_vector_types[] = {
1378  {aarch64_vector_base_types + 0, 2},
1379  {aarch64_vector_base_types + 1, 2},
1380  {aarch64_vector_base_types + 2, 2},
1381  {aarch64_vector_base_types + 3, 4},
1382  {aarch64_vector_base_types + 4, 4},
1383  {aarch64_vector_base_types + 5, 4},
1384  {aarch64_vector_base_types + 6, 8},
1385  {aarch64_vector_base_types + 7, 8},
1386  {aarch64_vector_base_types + 8, 16},
1387  {aarch64_vector_base_types + 9, 16},
1388  {aarch64_vector_base_types + 10, 01},
1389  {aarch64_vector_base_types + 11, 01},
1390 };
1391 
1392 static struct reg_data_type aarch64_fpu_vector[] = {
1405 };
1406 
1410  {"s", aarch64_fpu_vector + 2, NULL},
1411 };
1412 
1416  {"s", aarch64_fpu_vector + 5, NULL},
1417 };
1418 
1421  {"s", aarch64_fpu_vector + 7, NULL},
1422 };
1423 
1426  {"s", aarch64_fpu_vector + 9, NULL},
1427 };
1428 
1431  {"s", aarch64_fpu_vector + 11, NULL},
1432 };
1433 
1434 static struct reg_data_type_union aarch64_union_types[] = {
1440 };
1441 
1442 static struct reg_data_type aarch64_fpu_union[] = {
1443  {REG_TYPE_ARCH_DEFINED, "vnd", REG_TYPE_CLASS_UNION, {.reg_type_union = aarch64_union_types + 0} },
1444  {REG_TYPE_ARCH_DEFINED, "vns", REG_TYPE_CLASS_UNION, {.reg_type_union = aarch64_union_types + 1} },
1445  {REG_TYPE_ARCH_DEFINED, "vnh", REG_TYPE_CLASS_UNION, {.reg_type_union = aarch64_union_types + 2} },
1446  {REG_TYPE_ARCH_DEFINED, "vnb", REG_TYPE_CLASS_UNION, {.reg_type_union = aarch64_union_types + 3} },
1447  {REG_TYPE_ARCH_DEFINED, "vnq", REG_TYPE_CLASS_UNION, {.reg_type_union = aarch64_union_types + 4} },
1448 };
1449 
1451  {"d", aarch64_fpu_union + 0, aarch64v_union_fields + 1},
1452  {"s", aarch64_fpu_union + 1, aarch64v_union_fields + 2},
1453  {"h", aarch64_fpu_union + 2, aarch64v_union_fields + 3},
1454  {"b", aarch64_fpu_union + 3, aarch64v_union_fields + 4},
1455  {"q", aarch64_fpu_union + 4, NULL},
1456 };
1457 
1458 static struct reg_data_type_union aarch64v_union[] = {
1460 };
1461 
1462 static struct reg_data_type aarch64v[] = {
1464  {.reg_type_union = aarch64v_union} },
1465 };
1466 
1467 static struct reg_data_type_bitfield aarch64_cpsr_bits[] = {
1468  { 0, 0, REG_TYPE_UINT8 },
1469  { 2, 3, REG_TYPE_UINT8 },
1470  { 4, 4, REG_TYPE_UINT8 },
1471  { 6, 6, REG_TYPE_BOOL },
1472  { 7, 7, REG_TYPE_BOOL },
1473  { 8, 8, REG_TYPE_BOOL },
1474  { 9, 9, REG_TYPE_BOOL },
1475  { 20, 20, REG_TYPE_BOOL },
1476  { 21, 21, REG_TYPE_BOOL },
1477  { 28, 28, REG_TYPE_BOOL },
1478  { 29, 29, REG_TYPE_BOOL },
1479  { 30, 30, REG_TYPE_BOOL },
1480  { 31, 31, REG_TYPE_BOOL },
1481 };
1482 
1484  { "SP", aarch64_cpsr_bits + 0, aarch64_cpsr_fields + 1 },
1485  { "EL", aarch64_cpsr_bits + 1, aarch64_cpsr_fields + 2 },
1486  { "nRW", aarch64_cpsr_bits + 2, aarch64_cpsr_fields + 3 },
1487  { "F", aarch64_cpsr_bits + 3, aarch64_cpsr_fields + 4 },
1488  { "I", aarch64_cpsr_bits + 4, aarch64_cpsr_fields + 5 },
1489  { "A", aarch64_cpsr_bits + 5, aarch64_cpsr_fields + 6 },
1490  { "D", aarch64_cpsr_bits + 6, aarch64_cpsr_fields + 7 },
1491  { "IL", aarch64_cpsr_bits + 7, aarch64_cpsr_fields + 8 },
1492  { "SS", aarch64_cpsr_bits + 8, aarch64_cpsr_fields + 9 },
1493  { "V", aarch64_cpsr_bits + 9, aarch64_cpsr_fields + 10 },
1494  { "C", aarch64_cpsr_bits + 10, aarch64_cpsr_fields + 11 },
1495  { "Z", aarch64_cpsr_bits + 11, aarch64_cpsr_fields + 12 },
1496  { "N", aarch64_cpsr_bits + 12, NULL }
1497 };
1498 
1499 static struct reg_data_type_flags aarch64_cpsr_flags[] = {
1500  { 4, aarch64_cpsr_fields }
1501 };
1502 
1503 static struct reg_data_type aarch64_flags_cpsr[] = {
1505  {.reg_type_flags = aarch64_cpsr_flags} },
1506 };
1507 
1508 static const struct {
1509  unsigned int id;
1510  const char *name;
1511  unsigned int bits;
1512  enum arm_mode mode;
1513  enum reg_type type;
1514  const char *group;
1515  const char *feature;
1517 } armv8_regs[] = {
1518  { ARMV8_R0, "x0", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1519  { ARMV8_R1, "x1", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1520  { ARMV8_R2, "x2", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1521  { ARMV8_R3, "x3", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1522  { ARMV8_R4, "x4", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1523  { ARMV8_R5, "x5", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1524  { ARMV8_R6, "x6", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1525  { ARMV8_R7, "x7", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1526  { ARMV8_R8, "x8", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1527  { ARMV8_R9, "x9", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1528  { ARMV8_R10, "x10", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1529  { ARMV8_R11, "x11", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1530  { ARMV8_R12, "x12", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1531  { ARMV8_R13, "x13", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1532  { ARMV8_R14, "x14", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1533  { ARMV8_R15, "x15", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1534  { ARMV8_R16, "x16", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1535  { ARMV8_R17, "x17", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1536  { ARMV8_R18, "x18", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1537  { ARMV8_R19, "x19", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1538  { ARMV8_R20, "x20", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1539  { ARMV8_R21, "x21", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1540  { ARMV8_R22, "x22", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1541  { ARMV8_R23, "x23", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1542  { ARMV8_R24, "x24", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1543  { ARMV8_R25, "x25", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1544  { ARMV8_R26, "x26", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1545  { ARMV8_R27, "x27", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1546  { ARMV8_R28, "x28", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1547  { ARMV8_R29, "x29", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1548  { ARMV8_R30, "x30", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core", NULL},
1549 
1550  { ARMV8_SP, "sp", 64, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core", NULL},
1551  { ARMV8_PC, "pc", 64, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core", NULL},
1553  "general", "org.gnu.gdb.aarch64.core", aarch64_flags_cpsr},
1554  { ARMV8_V0, "v0", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1555  { ARMV8_V1, "v1", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1556  { ARMV8_V2, "v2", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1557  { ARMV8_V3, "v3", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1558  { ARMV8_V4, "v4", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1559  { ARMV8_V5, "v5", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1560  { ARMV8_V6, "v6", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1561  { ARMV8_V7, "v7", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1562  { ARMV8_V8, "v8", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1563  { ARMV8_V9, "v9", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1564  { ARMV8_V10, "v10", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1565  { ARMV8_V11, "v11", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1566  { ARMV8_V12, "v12", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1567  { ARMV8_V13, "v13", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1568  { ARMV8_V14, "v14", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1569  { ARMV8_V15, "v15", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1570  { ARMV8_V16, "v16", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1571  { ARMV8_V17, "v17", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1572  { ARMV8_V18, "v18", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1573  { ARMV8_V19, "v19", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1574  { ARMV8_V20, "v20", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1575  { ARMV8_V21, "v21", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1576  { ARMV8_V22, "v22", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1577  { ARMV8_V23, "v23", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1578  { ARMV8_V24, "v24", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1579  { ARMV8_V25, "v25", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1580  { ARMV8_V26, "v26", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1581  { ARMV8_V27, "v27", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1582  { ARMV8_V28, "v28", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1583  { ARMV8_V29, "v29", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1584  { ARMV8_V30, "v30", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1585  { ARMV8_V31, "v31", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
1586  { ARMV8_FPSR, "fpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "simdfp", "org.gnu.gdb.aarch64.fpu", NULL},
1587  { ARMV8_FPCR, "fpcr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "simdfp", "org.gnu.gdb.aarch64.fpu", NULL},
1588 
1589  { ARMV8_ELR_EL1, "ELR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",
1590  NULL},
1591  { ARMV8_ESR_EL1, "ESR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
1592  NULL},
1593  { ARMV8_SPSR_EL1, "SPSR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
1594  NULL},
1595 
1596  { ARMV8_ELR_EL2, "ELR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",
1597  NULL},
1598  { ARMV8_ESR_EL2, "ESR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
1599  NULL},
1600  { ARMV8_SPSR_EL2, "SPSR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
1601  NULL},
1602 
1603  { ARMV8_ELR_EL3, "ELR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",
1604  NULL},
1605  { ARMV8_ESR_EL3, "ESR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
1606  NULL},
1607  { ARMV8_SPSR_EL3, "SPSR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
1608  NULL},
1609  { ARMV8_PAUTH_DMASK, "pauth_dmask", 64, ARM_MODE_ANY, REG_TYPE_UINT64, NULL, "org.gnu.gdb.aarch64.pauth", NULL},
1610  { ARMV8_PAUTH_CMASK, "pauth_cmask", 64, ARM_MODE_ANY, REG_TYPE_UINT64, NULL, "org.gnu.gdb.aarch64.pauth", NULL},
1611 };
1612 
1613 static const struct {
1614  unsigned int id;
1615  unsigned int mapping;
1616  const char *name;
1617  unsigned int bits;
1618  enum arm_mode mode;
1619  enum reg_type type;
1620  const char *group;
1621  const char *feature;
1622 } armv8_regs32[] = {
1623  { ARMV8_R0, 0, "r0", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1624  { ARMV8_R1, 0, "r1", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1625  { ARMV8_R2, 0, "r2", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1626  { ARMV8_R3, 0, "r3", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1627  { ARMV8_R4, 0, "r4", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1628  { ARMV8_R5, 0, "r5", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1629  { ARMV8_R6, 0, "r6", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1630  { ARMV8_R7, 0, "r7", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1631  { ARMV8_R8, 0, "r8", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1632  { ARMV8_R9, 0, "r9", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1633  { ARMV8_R10, 0, "r10", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1634  { ARMV8_R11, 0, "r11", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1635  { ARMV8_R12, 0, "r12", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1636  { ARMV8_R13, 0, "sp", 32, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.core" },
1637  { ARMV8_R14, 0, "lr", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
1638  { ARMV8_PC, 0, "pc", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
1639  { ARMV8_XPSR, 0, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1640  { ARMV8_V0, 0, "d0", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1641  { ARMV8_V0, 8, "d1", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1642  { ARMV8_V1, 0, "d2", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1643  { ARMV8_V1, 8, "d3", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1644  { ARMV8_V2, 0, "d4", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1645  { ARMV8_V2, 8, "d5", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1646  { ARMV8_V3, 0, "d6", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1647  { ARMV8_V3, 8, "d7", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1648  { ARMV8_V4, 0, "d8", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1649  { ARMV8_V4, 8, "d9", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1650  { ARMV8_V5, 0, "d10", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1651  { ARMV8_V5, 8, "d11", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1652  { ARMV8_V6, 0, "d12", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1653  { ARMV8_V6, 8, "d13", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1654  { ARMV8_V7, 0, "d14", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1655  { ARMV8_V7, 8, "d15", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1656  { ARMV8_V8, 0, "d16", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1657  { ARMV8_V8, 8, "d17", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1658  { ARMV8_V9, 0, "d18", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1659  { ARMV8_V9, 8, "d19", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1660  { ARMV8_V10, 0, "d20", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1661  { ARMV8_V10, 8, "d21", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1662  { ARMV8_V11, 0, "d22", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1663  { ARMV8_V11, 8, "d23", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1664  { ARMV8_V12, 0, "d24", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1665  { ARMV8_V12, 8, "d25", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1666  { ARMV8_V13, 0, "d26", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1667  { ARMV8_V13, 8, "d27", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1668  { ARMV8_V14, 0, "d28", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1669  { ARMV8_V14, 8, "d29", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1670  { ARMV8_V15, 0, "d30", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1671  { ARMV8_V15, 8, "d31", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
1672  { ARMV8_FPSR, 0, "fpscr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "float", "org.gnu.gdb.arm.vfp"},
1673 };
1674 
1675 #define ARMV8_NUM_REGS ARRAY_SIZE(armv8_regs)
1676 #define ARMV8_NUM_REGS32 ARRAY_SIZE(armv8_regs32)
1677 
1678 static int armv8_get_core_reg(struct reg *reg)
1679 {
1680  struct arm_reg *armv8_reg = reg->arch_info;
1681  struct target *target = armv8_reg->target;
1682  struct arm *arm = target_to_arm(target);
1683 
1684  if (target->state != TARGET_HALTED)
1685  return ERROR_TARGET_NOT_HALTED;
1686 
1687  return arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
1688 }
1689 
1690 static int armv8_set_core_reg(struct reg *reg, uint8_t *buf)
1691 {
1692  struct arm_reg *armv8_reg = reg->arch_info;
1693  struct target *target = armv8_reg->target;
1694  struct arm *arm = target_to_arm(target);
1695  uint64_t value = buf_get_u64(buf, 0, reg->size);
1696 
1697  if (target->state != TARGET_HALTED)
1698  return ERROR_TARGET_NOT_HALTED;
1699 
1700  if (reg->size <= 64) {
1701  if (reg == arm->cpsr)
1702  armv8_set_cpsr(arm, (uint32_t)value);
1703  else {
1704  buf_set_u64(reg->value, 0, reg->size, value);
1705  reg->valid = true;
1706  }
1707  } else if (reg->size <= 128) {
1708  uint64_t hvalue = buf_get_u64(buf + 8, 0, reg->size - 64);
1709 
1710  buf_set_u64(reg->value, 0, 64, value);
1711  buf_set_u64(reg->value + 8, 0, reg->size - 64, hvalue);
1712  reg->valid = true;
1713  }
1714 
1715  reg->dirty = true;
1716 
1717  return ERROR_OK;
1718 }
1719 
1720 static const struct reg_arch_type armv8_reg_type = {
1722  .set = armv8_set_core_reg,
1723 };
1724 
1725 static int armv8_get_core_reg32(struct reg *reg)
1726 {
1727  struct arm_reg *armv8_reg = reg->arch_info;
1728  struct target *target = armv8_reg->target;
1729  struct arm *arm = target_to_arm(target);
1730  struct reg_cache *cache = arm->core_cache;
1731  struct reg *reg64;
1732  int retval;
1733 
1734  if (target->state != TARGET_HALTED)
1735  return ERROR_TARGET_NOT_HALTED;
1736 
1737  /* get the corresponding Aarch64 register */
1738  reg64 = cache->reg_list + armv8_reg->num;
1739  if (reg64->valid) {
1740  reg->valid = true;
1741  return ERROR_OK;
1742  }
1743 
1744  retval = arm->read_core_reg(target, reg64, armv8_reg->num, arm->core_mode);
1745  if (retval == ERROR_OK)
1746  reg->valid = reg64->valid;
1747 
1748  return retval;
1749 }
1750 
1751 static int armv8_set_core_reg32(struct reg *reg, uint8_t *buf)
1752 {
1753  struct arm_reg *armv8_reg = reg->arch_info;
1754  struct target *target = armv8_reg->target;
1755  struct arm *arm = target_to_arm(target);
1756  struct reg_cache *cache = arm->core_cache;
1757  struct reg *reg64 = cache->reg_list + armv8_reg->num;
1758  uint32_t value = buf_get_u32(buf, 0, 32);
1759 
1760  if (target->state != TARGET_HALTED)
1761  return ERROR_TARGET_NOT_HALTED;
1762 
1763  if (reg64 == arm->cpsr) {
1765  } else {
1766  if (reg->size <= 32)
1767  buf_set_u32(reg->value, 0, 32, value);
1768  else if (reg->size <= 64) {
1769  uint64_t value64 = buf_get_u64(buf, 0, 64);
1770  buf_set_u64(reg->value, 0, 64, value64);
1771  }
1772  reg->valid = true;
1773  reg64->valid = true;
1774  }
1775 
1776  reg64->dirty = true;
1777 
1778  return ERROR_OK;
1779 }
1780 
1781 static const struct reg_arch_type armv8_reg32_type = {
1783  .set = armv8_set_core_reg32,
1784 };
1785 
1788 {
1789  struct armv8_common *armv8 = target_to_armv8(target);
1790  struct arm *arm = &armv8->arm;
1791  int num_regs = ARMV8_NUM_REGS;
1792  int num_regs32 = ARMV8_NUM_REGS32;
1793  struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
1794  struct reg_cache *cache = malloc(sizeof(struct reg_cache));
1795  struct reg_cache *cache32 = malloc(sizeof(struct reg_cache));
1796  struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
1797  struct reg *reg_list32 = calloc(num_regs32, sizeof(struct reg));
1798  struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
1799  struct reg_feature *feature;
1800  int i;
1801 
1802  /* Build the process context cache */
1803  cache->name = "Aarch64 registers";
1804  cache->next = cache32;
1805  cache->reg_list = reg_list;
1806  cache->num_regs = num_regs;
1807 
1808  for (i = 0; i < num_regs; i++) {
1809  arch_info[i].num = armv8_regs[i].id;
1810  arch_info[i].mode = armv8_regs[i].mode;
1811  arch_info[i].target = target;
1812  arch_info[i].arm = arm;
1813 
1814  reg_list[i].name = armv8_regs[i].name;
1815  reg_list[i].size = armv8_regs[i].bits;
1816  reg_list[i].value = &arch_info[i].value[0];
1817  reg_list[i].type = &armv8_reg_type;
1818  reg_list[i].arch_info = &arch_info[i];
1819 
1820  reg_list[i].group = armv8_regs[i].group;
1821  reg_list[i].number = i;
1822  reg_list[i].exist = true;
1823  reg_list[i].caller_save = true; /* gdb defaults to true */
1824 
1825  feature = calloc(1, sizeof(struct reg_feature));
1826  if (feature) {
1827  feature->name = armv8_regs[i].feature;
1828  reg_list[i].feature = feature;
1829  } else
1830  LOG_ERROR("unable to allocate feature list");
1831 
1832  reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
1833  if (reg_list[i].reg_data_type) {
1834  if (!armv8_regs[i].data_type)
1835  reg_list[i].reg_data_type->type = armv8_regs[i].type;
1836  else
1837  *reg_list[i].reg_data_type = *armv8_regs[i].data_type;
1838  } else
1839  LOG_ERROR("unable to allocate reg type list");
1840 
1841  if (i == ARMV8_PAUTH_CMASK || i == ARMV8_PAUTH_DMASK)
1842  reg_list[i].exist = armv8->enable_pauth;
1843  }
1844 
1845  arm->cpsr = reg_list + ARMV8_XPSR;
1846  arm->pc = reg_list + ARMV8_PC;
1847  arm->core_cache = cache;
1848 
1849  /* shadow cache for ARM mode registers */
1850  cache32->name = "Aarch32 registers";
1851  cache32->next = NULL;
1852  cache32->reg_list = reg_list32;
1853  cache32->num_regs = num_regs32;
1854 
1855  for (i = 0; i < num_regs32; i++) {
1856  reg_list32[i].name = armv8_regs32[i].name;
1857  reg_list32[i].size = armv8_regs32[i].bits;
1858  reg_list32[i].value = &arch_info[armv8_regs32[i].id].value[armv8_regs32[i].mapping];
1859  reg_list32[i].type = &armv8_reg32_type;
1860  reg_list32[i].arch_info = &arch_info[armv8_regs32[i].id];
1861  reg_list32[i].group = armv8_regs32[i].group;
1862  reg_list32[i].number = i;
1863  reg_list32[i].exist = true;
1864  reg_list32[i].caller_save = true;
1865 
1866  feature = calloc(1, sizeof(struct reg_feature));
1867  if (feature) {
1868  feature->name = armv8_regs32[i].feature;
1869  reg_list32[i].feature = feature;
1870  } else
1871  LOG_ERROR("unable to allocate feature list");
1872 
1873  reg_list32[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
1874  if (reg_list32[i].reg_data_type)
1875  reg_list32[i].reg_data_type->type = armv8_regs32[i].type;
1876  else
1877  LOG_ERROR("unable to allocate reg type list");
1878  }
1879 
1880  (*cache_p) = cache;
1881  return cache;
1882 }
1883 
1884 struct reg *armv8_reg_current(struct arm *arm, unsigned int regnum)
1885 {
1886  struct reg *r;
1887 
1888  if (regnum > (ARMV8_LAST_REG - 1))
1889  return NULL;
1890 
1891  r = arm->core_cache->reg_list + regnum;
1892  return r;
1893 }
1894 
1895 static void armv8_free_cache(struct reg_cache *cache, bool regs32)
1896 {
1897  struct reg *reg;
1898  unsigned int i;
1899 
1900  if (!cache)
1901  return;
1902 
1903  for (i = 0; i < cache->num_regs; i++) {
1904  reg = &cache->reg_list[i];
1905 
1906  free(reg->feature);
1907  free(reg->reg_data_type);
1908  }
1909 
1910  if (!regs32)
1911  free(cache->reg_list[0].arch_info);
1912  free(cache->reg_list);
1913  free(cache);
1914 }
1915 
1917 {
1918  struct armv8_common *armv8 = target_to_armv8(target);
1919  struct arm *arm = &armv8->arm;
1920  struct reg_cache *cache = NULL, *cache32 = NULL;
1921 
1922  cache = arm->core_cache;
1923  if (cache)
1924  cache32 = cache->next;
1925  armv8_free_cache(cache32, true);
1926  armv8_free_cache(cache, false);
1927  arm->core_cache = NULL;
1928 }
1929 
1931  {
1932  .name = "catch_exc",
1933  .handler = armv8_handle_exception_catch_command,
1934  .mode = COMMAND_EXEC,
1935  .help = "configure exception catch",
1936  .usage = "[(nsec_el1,nsec_el2,sec_el1,sec_el3)+,off]",
1937  },
1938  {
1939  .name = "pauth",
1940  .handler = armv8_pauth_command,
1941  .mode = COMMAND_CONFIG,
1942  .help = "enable or disable providing GDB with an 8-bytes mask to "
1943  "remove signature bits added by pointer authentication."
1944  "Pointer authentication feature is broken until gdb 12.1, going to be fixed. "
1945  "Consider using a newer version of gdb if you want enable "
1946  "pauth feature.",
1947  .usage = "[on|off]",
1948  },
1950 };
1951 
1952 const char *armv8_get_gdb_arch(const struct target *target)
1953 {
1954  struct arm *arm = target_to_arm(target);
1955  return arm->core_state == ARM_STATE_AARCH64 ? "aarch64" : "arm";
1956 }
1957 
1959  struct reg **reg_list[], int *reg_list_size,
1960  enum target_register_class reg_class)
1961 {
1962  struct arm *arm = target_to_arm(target);
1963  int i;
1964 
1965  if (arm->core_state == ARM_STATE_AARCH64) {
1966 
1967  LOG_DEBUG("Creating Aarch64 register list for target %s", target_name(target));
1968 
1969  switch (reg_class) {
1970  case REG_CLASS_GENERAL:
1971  *reg_list_size = ARMV8_V0;
1972  *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1973 
1974  for (i = 0; i < *reg_list_size; i++)
1975  (*reg_list)[i] = armv8_reg_current(arm, i);
1976  return ERROR_OK;
1977 
1978  case REG_CLASS_ALL:
1979  *reg_list_size = ARMV8_LAST_REG;
1980  *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1981 
1982  for (i = 0; i < *reg_list_size; i++)
1983  (*reg_list)[i] = armv8_reg_current(arm, i);
1984 
1985  return ERROR_OK;
1986 
1987  default:
1988  LOG_ERROR("not a valid register class type in query.");
1989  return ERROR_FAIL;
1990  }
1991  } else {
1992  struct reg_cache *cache32 = arm->core_cache->next;
1993 
1994  LOG_DEBUG("Creating Aarch32 register list for target %s", target_name(target));
1995 
1996  switch (reg_class) {
1997  case REG_CLASS_GENERAL:
1998  *reg_list_size = ARMV8_R14 + 3;
1999  *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
2000 
2001  for (i = 0; i < *reg_list_size; i++)
2002  (*reg_list)[i] = cache32->reg_list + i;
2003 
2004  return ERROR_OK;
2005  case REG_CLASS_ALL:
2006  *reg_list_size = cache32->num_regs;
2007  *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
2008 
2009  for (i = 0; i < *reg_list_size; i++)
2010  (*reg_list)[i] = cache32->reg_list + i;
2011 
2012  return ERROR_OK;
2013  default:
2014  LOG_ERROR("not a valid register class type in query.");
2015  return ERROR_FAIL;
2016  }
2017  }
2018 }
2019 
2020 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value)
2021 {
2022  uint32_t tmp;
2023 
2024  /* Read register */
2025  int retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2026  armv8->debug_base + reg, &tmp);
2027  if (retval != ERROR_OK)
2028  return retval;
2029 
2030  /* clear bitfield */
2031  tmp &= ~mask;
2032  /* put new value */
2033  tmp |= value & mask;
2034 
2035  /* write new value */
2036  retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2037  armv8->debug_base + reg, tmp);
2038  return retval;
2039 }
int arm_arch_state(struct target *target)
Definition: armv4_5.c:782
#define ARM_COMMON_MAGIC
Definition: arm.h:166
arm_mode
Represent state of an ARM core.
Definition: arm.h:82
@ ARM_MODE_IRQ
Definition: arm.h:85
@ ARM_MODE_SYS
Definition: arm.h:92
@ ARM_MODE_HYP
Definition: arm.h:89
@ ARMV8_64_EL0T
Definition: arm.h:98
@ ARMV8_64_EL3H
Definition: arm.h:104
@ ARM_MODE_MON
Definition: arm.h:87
@ ARMV8_64_EL3T
Definition: arm.h:103
@ ARM_MODE_FIQ
Definition: arm.h:84
@ ARM_MODE_UND
Definition: arm.h:90
@ ARM_MODE_ANY
Definition: arm.h:106
@ ARMV8_64_EL1H
Definition: arm.h:100
@ ARM_MODE_USR
Definition: arm.h:83
@ ARM_MODE_SVC
Definition: arm.h:86
@ ARMV8_64_EL2H
Definition: arm.h:102
@ ARMV8_64_EL2T
Definition: arm.h:101
@ ARMV8_64_EL1T
Definition: arm.h:99
@ ARM_MODE_ABT
Definition: arm.h:88
static struct arm * target_to_arm(const struct target *target)
Convert target handle to generic ARM target state handle.
Definition: arm.h:261
arm_state
The PSR "T" and "J" bits define the mode of "classic ARM" cores.
Definition: arm.h:150
@ ARM_STATE_JAZELLE
Definition: arm.h:153
@ ARM_STATE_THUMB
Definition: arm.h:152
@ ARM_STATE_ARM
Definition: arm.h:151
@ ARM_STATE_AARCH64
Definition: arm.h:155
@ ARM_STATE_THUMB_EE
Definition: arm.h:154
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Synchronous read of a word from memory or a system register.
Definition: arm_adi_v5.c:266
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Synchronous write of a word to memory or a system register.
Definition: arm_adi_v5.c:318
#define ARMV4_5_VMSR(rt)
Definition: arm_opcodes.h:146
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:186
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:209
#define ARMV4_5_VMOV(op, rt2, rt, m, vm)
Definition: arm_opcodes.h:134
#define ARMV4_5_VMRS(rt)
Definition: arm_opcodes.h:141
static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *regval)
Definition: armv8.c:590
int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
Definition: armv8.c:1289
static int armv8_get_core_reg32(struct reg *reg)
Definition: armv8.c:1725
int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value)
Definition: armv8.c:2020
static int armv8_get_core_reg(struct reg *reg)
Definition: armv8.c:1678
const char * armv8_get_gdb_arch(const struct target *target)
Definition: armv8.c:1952
static struct reg_data_type_flags_field aarch64_cpsr_fields[]
Definition: armv8.c:1483
static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum, uint64_t lvalue, uint64_t hvalue)
Definition: armv8.c:814
int armv8_read_mpidr(struct armv8_common *armv8)
Definition: armv8.c:881
static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t value)
Definition: armv8.c:732
void armv8_free_reg_cache(struct target *target)
Definition: armv8.c:1916
static void armv8_show_fault_registers32(struct armv8_common *armv8)
Definition: armv8.c:969
enum arm_mode mode
Definition: armv8.c:1512
static int armv8_get_pauth_mask(struct armv8_common *armv8, uint64_t *mask)
Definition: armv8.c:264
int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val)
Definition: armv8.c:1025
static struct reg_data_type_vector aarch64_vector_types[]
Definition: armv8.c:1377
static __attribute__((unused))
Definition: armv8.c:147
static int armv8_setup_semihosting(struct target *target, int enable)
Definition: armv8.c:1284
static const struct @83 armv8_regs[]
static struct reg_data_type_bitfield aarch64_cpsr_bits[]
Definition: armv8.c:1467
static int armv8_read_reg_simdfp_aarch64(struct armv8_common *armv8, int regnum, uint64_t *lvalue, uint64_t *hvalue)
Definition: armv8.c:413
static struct reg_data_type aarch64_fpu_union[]
Definition: armv8.c:1442
static int armv8_set_core_reg(struct reg *reg, uint8_t *buf)
Definition: armv8.c:1690
static int armv8_read_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum, uint64_t *lvalue, uint64_t *hvalue)
Definition: armv8.c:680
struct reg * armv8_reg_current(struct arm *arm, unsigned int regnum)
Definition: armv8.c:1884
struct reg_data_type * data_type
Definition: armv8.c:1516
int armv8_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: armv8.c:1958
static const char *const armv8_state_strings[]
Definition: armv8.c:33
static const struct reg_arch_type armv8_reg_type
Definition: armv8.c:1720
const char * group
Definition: armv8.c:1514
static struct reg_data_type_union_field aarch64v_union_fields[]
Definition: armv8.c:1450
int armv8_arch_state(struct target *target)
Definition: armv8.c:1329
static struct reg_data_type aarch64v[]
Definition: armv8.c:1462
static void armv8_decode_cacheability(int attr)
Definition: armv8.c:1030
int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va, target_addr_t *val, int meminfo)
Definition: armv8.c:1106
static const struct @82 armv8_mode_data[]
static struct reg_data_type_union_field aarch64_union_fields_vnh[]
Definition: armv8.c:1419
static int armv8_write_reg_simdfp_aarch64(struct armv8_common *armv8, int regnum, uint64_t lvalue, uint64_t hvalue)
Definition: armv8.c:567
static struct reg_data_type aarch64_flags_cpsr[]
Definition: armv8.c:1503
static void armv8_free_cache(struct reg_cache *cache, bool regs32)
Definition: armv8.c:1895
static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regval)
Definition: armv8.c:278
const struct command_registration armv8_command_handlers[]
Definition: armv8.c:1930
static struct reg_data_type_union aarch64v_union[]
Definition: armv8.c:1458
static struct reg_data_type_union_field aarch64_union_fields_vnd[]
Definition: armv8.c:1407
void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
Configures host-side ARM records to reflect the specified CPSR.
Definition: armv8.c:924
const char * name
Definition: armv8.c:38
#define ARMV8_NUM_REGS
Definition: armv8.c:1675
static struct reg_data_type_union_field aarch64_union_fields_vnq[]
Definition: armv8.c:1429
static int armv8_read_ttbcr(struct target *target)
Definition: armv8.c:186
unsigned int bits
Definition: armv8.c:1511
COMMAND_HANDLER(armv8_handle_exception_catch_command)
Definition: armv8.c:1196
static int armv8_set_core_reg32(struct reg *reg, uint8_t *buf)
Definition: armv8.c:1751
unsigned int psr
Definition: armv8.c:39
struct reg_cache * armv8_build_reg_cache(struct target *target)
Builds cache of architecturally defined registers.
Definition: armv8.c:1787
static uint8_t armv8_pa_size(uint32_t ps)
Definition: armv8.c:118
static struct reg_data_type aarch64_vector_base_types[]
Definition: armv8.c:1362
static struct reg_data_type_flags aarch64_cpsr_flags[]
Definition: armv8.c:1499
static struct reg_data_type_union_field aarch64_union_fields_vnb[]
Definition: armv8.c:1424
static const struct @84 armv8_regs32[]
unsigned int mapping
Definition: armv8.c:1615
static int armv8_aarch64_state(struct target *target)
Definition: armv8.c:1307
void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64)
Definition: armv8.c:864
static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t value_64)
Definition: armv8.c:436
static void armv8_decode_memory_attr(int attr)
Definition: armv8.c:1064
static struct reg_data_type_union_field aarch64_union_fields_vns[]
Definition: armv8.c:1413
const char * feature
Definition: armv8.c:1515
static const struct reg_arch_type armv8_reg32_type
Definition: armv8.c:1781
#define ARMV8_NUM_REGS32
Definition: armv8.c:1676
const char * armv8_mode_name(unsigned int psr_mode)
Map PSR mode bits to the name of an ARM processor operating mode.
Definition: armv8.c:108
int armv8_handle_cache_info_command(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache)
Definition: armv8.c:1271
static struct reg_data_type_union aarch64_union_types[]
Definition: armv8.c:1434
static struct reg_data_type aarch64_fpu_vector[]
Definition: armv8.c:1392
static struct armv8_common * target_to_armv8(struct target *target)
Definition: armv8.h:238
#define CPUV8_DBG_ECCR
Definition: armv8.h:263
@ ARMV8_V27
Definition: armv8.h:81
@ ARMV8_R14
Definition: armv8.h:32
@ ARMV8_ESR_EL2
Definition: armv8.h:94
@ ARMV8_R20
Definition: armv8.h:38
@ ARMV8_V16
Definition: armv8.h:70
@ ARMV8_V1
Definition: armv8.h:55
@ ARMV8_V11
Definition: armv8.h:65
@ ARMV8_R0
Definition: armv8.h:18
@ ARMV8_V23
Definition: armv8.h:77
@ ARMV8_V2
Definition: armv8.h:56
@ ARMV8_R12
Definition: armv8.h:30
@ ARMV8_R21
Definition: armv8.h:39
@ ARMV8_R5
Definition: armv8.h:23
@ ARMV8_V5
Definition: armv8.h:59
@ ARMV8_ESR_EL1
Definition: armv8.h:90
@ ARMV8_V12
Definition: armv8.h:66
@ ARMV8_V4
Definition: armv8.h:58
@ ARMV8_V25
Definition: armv8.h:79
@ ARMV8_R7
Definition: armv8.h:25
@ ARMV8_V14
Definition: armv8.h:68
@ ARMV8_PAUTH_DMASK
Definition: armv8.h:102
@ ARMV8_R9
Definition: armv8.h:27
@ ARMV8_LAST_REG
Definition: armv8.h:105
@ ARMV8_V18
Definition: armv8.h:72
@ ARMV8_R17
Definition: armv8.h:35
@ ARMV8_R23
Definition: armv8.h:41
@ ARMV8_V6
Definition: armv8.h:60
@ ARMV8_R18
Definition: armv8.h:36
@ ARMV8_R1
Definition: armv8.h:19
@ ARMV8_SPSR_EL3
Definition: armv8.h:99
@ ARMV8_SPSR_EL2
Definition: armv8.h:95
@ ARMV8_R24
Definition: armv8.h:42
@ ARMV8_V19
Definition: armv8.h:73
@ ARMV8_R22
Definition: armv8.h:40
@ ARMV8_SP
Definition: armv8.h:50
@ ARMV8_R6
Definition: armv8.h:24
@ ARMV8_R29
Definition: armv8.h:47
@ ARMV8_V3
Definition: armv8.h:57
@ ARMV8_V7
Definition: armv8.h:61
@ ARMV8_V31
Definition: armv8.h:85
@ ARMV8_V17
Definition: armv8.h:71
@ ARMV8_V13
Definition: armv8.h:67
@ ARMV8_R25
Definition: armv8.h:43
@ ARMV8_V28
Definition: armv8.h:82
@ ARMV8_V9
Definition: armv8.h:63
@ ARMV8_V22
Definition: armv8.h:76
@ ARMV8_ELR_EL3
Definition: armv8.h:97
@ ARMV8_XPSR
Definition: armv8.h:52
@ ARMV8_R30
Definition: armv8.h:48
@ ARMV8_PAUTH_CMASK
Definition: armv8.h:103
@ ARMV8_V8
Definition: armv8.h:62
@ ARMV8_R27
Definition: armv8.h:45
@ ARMV8_R4
Definition: armv8.h:22
@ ARMV8_FPCR
Definition: armv8.h:87
@ ARMV8_V24
Definition: armv8.h:78
@ ARMV8_R8
Definition: armv8.h:26
@ ARMV8_PC
Definition: armv8.h:51
@ ARMV8_V0
Definition: armv8.h:54
@ ARMV8_SPSR_EL1
Definition: armv8.h:91
@ ARMV8_R13
Definition: armv8.h:31
@ ARMV8_ELR_EL2
Definition: armv8.h:93
@ ARMV8_V29
Definition: armv8.h:83
@ ARMV8_ESR_EL3
Definition: armv8.h:98
@ ARMV8_R10
Definition: armv8.h:28
@ ARMV8_V26
Definition: armv8.h:80
@ ARMV8_V10
Definition: armv8.h:64
@ ARMV8_R28
Definition: armv8.h:46
@ ARMV8_R3
Definition: armv8.h:21
@ ARMV8_R26
Definition: armv8.h:44
@ ARMV8_V21
Definition: armv8.h:75
@ ARMV8_V15
Definition: armv8.h:69
@ ARMV8_V20
Definition: armv8.h:74
@ ARMV8_R16
Definition: armv8.h:34
@ ARMV8_V30
Definition: armv8.h:84
@ ARMV8_R11
Definition: armv8.h:29
@ ARMV8_FPSR
Definition: armv8.h:86
@ ARMV8_ELR_EL1
Definition: armv8.h:89
@ ARMV8_R15
Definition: armv8.h:33
@ ARMV8_R2
Definition: armv8.h:20
@ ARMV8_R19
Definition: armv8.h:37
static unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
Definition: armv8.h:308
#define ARMV8_COMMON_MAGIC
Definition: armv8.h:115
int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
Definition: armv8_dpm.c:538
#define ARMV8_MRC_DLR(rt)
#define SYSTEM_ESR_EL3
#define ARMV8_MCR_DLR(rt)
#define SYSTEM_CUREL_EL1
Definition: armv8_opcodes.h:15
#define ARMV8_MSR_GP(system, rt)
#define ARMV8_MSR_DLR(rt)
#define ARMV8_MCR_DSPSR(rt)
#define ARMV8_MOVTSP_64(rt)
#define SYSTEM_TTBR0_EL2
Definition: armv8_opcodes.h:85
#define SYSTEM_TTBR0_EL3
Definition: armv8_opcodes.h:86
#define SYSTEM_ELR_EL3
Definition: armv8_opcodes.h:35
#define SYSTEM_TCR_EL2
Definition: armv8_opcodes.h:81
#define SYSTEM_ESR_EL2
#define SYSTEM_CUREL_EL3
Definition: armv8_opcodes.h:17
#define SYSTEM_ATS12E0R
Definition: armv8_opcodes.h:91
#define ARMV8_MOV_VFP_GPR(rd, rn, index)
#define SYSTEM_ELR_EL1
Definition: armv8_opcodes.h:33
#define SYSTEM_CUREL_EL2
Definition: armv8_opcodes.h:16
#define ARMV8_MRS_DSPSR(rt)
#define ARMV8_MSR_FPCR(rt)
#define SYSTEM_TTBR0_EL1
Definition: armv8_opcodes.h:84
#define SYSTEM_SPSR_EL3
Definition: armv8_opcodes.h:56
#define ARMV8_MRS(system, rt)
#define SYSTEM_ATS12E1R
Definition: armv8_opcodes.h:92
#define ARMV8_MSR_FPSR(rt)
#define ARMV8_MRS_DLR(rt)
#define SYSTEM_ATS1E3R
Definition: armv8_opcodes.h:94
#define SYSTEM_PAR_EL1
Definition: armv8_opcodes.h:90
#define SYSTEM_ESR_EL1
#define SYSTEM_SPSR_EL2
Definition: armv8_opcodes.h:55
#define ARMV8_MRS_FPCR(rt)
#define SYSTEM_TCR_EL3
Definition: armv8_opcodes.h:82
#define ARMV8_MOV_GPR_VFP(rd, rn, index)
#define ARMV8_SYS(system, rt)
#define ARMV8_MRS_XPSR_T1(r, rd)
#define ARMV8_MSR_GP_XPSR_T1(r, rn, mask)
#define SYSTEM_SPSR_EL1
Definition: armv8_opcodes.h:54
#define ARMV8_MSR_GP_T1(r, m1, rd, m)
#define ARMV8_MSR_DSPSR(rt)
#define SYSTEM_CUREL_EL0
Definition: armv8_opcodes.h:14
armv8_opcode
@ READ_REG_MPIDR
#define SYSTEM_ATS1E2R
Definition: armv8_opcodes.h:93
#define SYSTEM_ELR_EL2
Definition: armv8_opcodes.h:34
#define SYSTEM_TCR_EL1
Definition: armv8_opcodes.h:80
#define ARMV8_MRS_FPSR(rt)
#define ARMV8_MRS_T1(r, m1, rd, m)
#define ARMV8_MRC_DSPSR(rt)
#define SYSTEM_DBG_DBGDTR_EL0
Definition: armv8_opcodes.h:64
#define ARMV8_MOVFSP_64(rt)
Support functions to access arbitrary bits in a byte array.
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:104
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
static uint64_t buf_get_u64(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 64-bit word.
Definition: binarybuffer.h:134
static void buf_set_u64(uint8_t *_buffer, unsigned int first, unsigned int num, uint64_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:65
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:443
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
Definition: command.h:118
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:402
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:146
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
@ COMMAND_CONFIG
Definition: command.h:41
@ COMMAND_EXEC
Definition: command.h:40
int mask
Definition: esirisc.c:1741
#define LOG_USER(expr ...)
Definition: log.h:135
#define LOG_WARNING(expr ...)
Definition: log.h:129
#define ERROR_FAIL
Definition: log.h:170
#define LOG_TARGET_ERROR(target, fmt_str,...)
Definition: log.h:158
#define LOG_USER_N(expr ...)
Definition: log.h:138
#define LOG_ERROR(expr ...)
Definition: log.h:132
#define LOG_INFO(expr ...)
Definition: log.h:126
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:164
const struct nvp * nvp_name2value(const struct nvp *p, const char *name)
Definition: nvp.c:29
const struct nvp * nvp_value2name(const struct nvp *p, int value)
Definition: nvp.c:39
struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
Definition: register.c:72
reg_type
Definition: register.h:19
@ REG_TYPE_UINT16
Definition: register.h:29
@ REG_TYPE_BOOL
Definition: register.h:20
@ REG_TYPE_IEEE_DOUBLE
Definition: register.h:37
@ REG_TYPE_INT64
Definition: register.h:25
@ REG_TYPE_INT16
Definition: register.h:23
@ REG_TYPE_UINT32
Definition: register.h:30
@ REG_TYPE_CODE_PTR
Definition: register.h:33
@ REG_TYPE_DATA_PTR
Definition: register.h:34
@ REG_TYPE_INT32
Definition: register.h:24
@ REG_TYPE_INT128
Definition: register.h:26
@ REG_TYPE_UINT128
Definition: register.h:32
@ REG_TYPE_UINT64
Definition: register.h:31
@ REG_TYPE_INT8
Definition: register.h:22
@ REG_TYPE_ARCH_DEFINED
Definition: register.h:38
@ REG_TYPE_IEEE_SINGLE
Definition: register.h:36
@ REG_TYPE_UINT8
Definition: register.h:28
@ REG_TYPE_CLASS_VECTOR
Definition: register.h:93
@ REG_TYPE_CLASS_FLAGS
Definition: register.h:96
@ REG_TYPE_CLASS_UNION
Definition: register.h:94
struct target * target
Definition: rtt/rtt.c:26
This wraps an implementation of DPM primitives.
Definition: arm_dpm.h:47
target_addr_t wp_addr
Target dependent watchpoint address.
Definition: arm_dpm.h:147
int(* instr_read_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from dcc after execution.
Definition: arm_dpm.h:91
int(* instr_write_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Runs one instruction, writing data to R0 before execution.
Definition: arm_dpm.h:82
int(* instr_read_data_dcc_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Definition: arm_dpm.h:94
int(* instr_write_data_dcc_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Definition: arm_dpm.h:68
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
Definition: arm_dpm.h:72
struct arm * arm
Definition: arm_dpm.h:48
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
Definition: arm_dpm.h:57
int(* instr_write_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
Definition: arm_dpm.h:65
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
Definition: arm_dpm.h:54
int(* instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
Definition: arm_dpm.h:98
int(* instr_read_data_r0_64)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Definition: arm_dpm.h:108
Definition: arm.h:280
int num
Definition: arm.h:281
struct arm * arm
Definition: arm.h:284
uint8_t value[16]
Definition: arm.h:285
enum arm_mode mode
Definition: arm.h:282
struct target * target
Definition: arm.h:283
Represents a generic ARM core, with standard application registers.
Definition: arm.h:175
void * arch_info
Definition: arm.h:251
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
Definition: arm.h:196
struct reg * cpsr
Handle to the CPSR/xPSR; valid in all core modes.
Definition: arm.h:184
struct reg * pc
Handle to the PC; valid in all core modes.
Definition: arm.h:181
int(* setup_semihosting)(struct target *target, int enable)
Definition: arm.h:207
int(* read_core_reg)(struct target *target, struct reg *reg, int num, enum arm_mode mode)
Retrieve a single core register.
Definition: arm.h:224
struct reg_cache * core_cache
Definition: arm.h:178
struct arm_dpm * dpm
Handle for the debug module, if one is present.
Definition: arm.h:213
unsigned int common_magic
Definition: arm.h:176
struct target * target
Backpointer to the target.
Definition: arm.h:210
enum arm_state core_state
Record the current core state: ARM, Thumb, or otherwise.
Definition: arm.h:199
void * l2_cache
Definition: armv8.h:163
int d_u_cache_enabled
Definition: armv8.h:160
int(* display_cache_info)(struct command_invocation *cmd, struct armv8_cache_common *armv8_cache)
Definition: armv8.h:165
int(* flush_all_data_cache)(struct target *target)
Definition: armv8.h:164
int i_cache_enabled
Definition: armv8.h:159
struct arm arm
Definition: armv8.h:187
uint8_t va_size
Definition: armv8.h:203
uint32_t page_size
Definition: armv8.h:205
struct arm_dpm dpm
Definition: armv8.h:191
uint64_t ttbr_base
Definition: armv8.h:206
target_addr_t debug_base
Definition: armv8.h:192
uint8_t cpu_id
Definition: armv8.h:200
struct armv8_mmu_common armv8_mmu
Definition: armv8.h:209
int(* read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value)
Definition: armv8.h:222
int(* write_reg_u128)(struct armv8_common *armv8, int num, uint64_t lvalue, uint64_t hvalue)
Definition: armv8.h:228
struct adiv5_ap * debug_ap
Definition: armv8.h:193
int(* read_reg_u128)(struct armv8_common *armv8, int num, uint64_t *lvalue, uint64_t *hvalue)
Definition: armv8.h:226
unsigned int common_magic
Definition: armv8.h:185
int(* write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value)
Definition: armv8.h:223
uint8_t cluster_id
Definition: armv8.h:199
bool enable_pauth
Definition: armv8.h:214
uint8_t pa_size
Definition: armv8.h:204
uint8_t multi_processor_system
Definition: armv8.h:198
int32_t ttbr1_used
Definition: armv8.h:171
uint64_t ttbr0_mask
Definition: armv8.h:172
uint32_t mmu_enabled
Definition: armv8.h:181
uint32_t ttbr_mask[2]
Definition: armv8.h:175
uint32_t ttbcr
Definition: armv8.h:174
struct armv8_cache_common armv8_cache
Definition: armv8.h:180
uint32_t ttbr_range[2]
Definition: armv8.h:176
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
const char * name
Definition: command.h:235
Name Value Pairs, aka: NVP.
Definition: nvp.h:61
int value
Definition: nvp.h:63
const char * name
Definition: nvp.h:62
int(* get)(struct reg *reg)
Definition: register.h:152
const char * name
Definition: register.h:145
unsigned int num_regs
Definition: register.h:148
struct reg * reg_list
Definition: register.h:147
struct reg_cache * next
Definition: register.h:146
enum reg_type type
Definition: register.h:100
const char * id
Definition: register.h:101
Definition: register.h:111
bool caller_save
Definition: register.h:119
bool valid
Definition: register.h:126
bool exist
Definition: register.h:128
uint32_t size
Definition: register.h:132
const char * group
Definition: register.h:138
uint8_t * value
Definition: register.h:122
struct reg_feature * feature
Definition: register.h:117
struct reg_data_type * reg_data_type
Definition: register.h:135
uint32_t number
Definition: register.h:115
void * arch_info
Definition: register.h:140
bool dirty
Definition: register.h:124
const struct reg_arch_type * type
Definition: register.h:141
const char * name
Definition: register.h:113
bool is_active
A flag reporting whether semihosting is active.
Definition: target.h:116
struct semihosting * semihosting
Definition: target.h:209
enum target_debug_reason debug_reason
Definition: target.h:154
enum target_state state
Definition: target.h:157
struct reg_cache * reg_cache
Definition: target.h:158
void * arch_info
Definition: target.h:164
const char * debug_reason_name(const struct target *t)
Definition: target.c:247
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:458
@ DBG_REASON_WATCHPOINT
Definition: target.h:71
target_register_class
Definition: target.h:110
@ REG_CLASS_GENERAL
Definition: target.h:112
@ REG_CLASS_ALL
Definition: target.h:111
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:790
static const char * target_name(const struct target *target)
Returns the instance-specific name of the specified target.
Definition: target.h:233
@ TARGET_HALTED
Definition: target.h:56
#define TARGET_ADDR_FMT
Definition: types.h:342
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57
uint64_t target_addr_t
Definition: types.h:335
#define NULL
Definition: usb.h:16
uint8_t cmd
Definition: vdebug.c:1
uint8_t state[4]
Definition: vdebug.c:21