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arm_adi_v5.c File Reference

This file implements support for the ARM Debug Interface version 5 (ADIv5) debugging architecture. More...

Include dependency graph for arm_adi_v5.c:

Go to the source code of this file.

Data Structures

struct  cs_component_vals
 Holds registers and coordinates of a CoreSight component. More...
 
struct  dap_lookup_data
 
struct  dap_part_nums
 
struct  rtp_ops
 Actions/operations to be executed while parsing ROM tables. More...
 

Macros

#define ARCH_ID(architect, archid)
 
#define CORESIGHT_COMPONENT_FOUND   (1)
 Value used only during lookup of a CoreSight component in ROM table. More...
 
#define DAP_POWER_DOMAIN_TIMEOUT   (10)
 
#define DEVARCH_ID_MASK   (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
 
#define DEVARCH_MEM_AP   ARCH_ID(ARM_ID, 0x0A17)
 
#define DEVARCH_ROM_C_0X9   ARCH_ID(ARM_ID, 0x0AF7)
 
#define DEVARCH_UNKNOWN_V2   ARCH_ID(ARM_ID, 0x0A47)
 
#define ROM_TABLE_MAX_DEPTH   (16)
 

Enumerations

enum  adiv5_cfg_param { CFG_DAP , CFG_AP_NUM , CFG_BASEADDR , CFG_CTIBASE }
 
enum  coresight_access_mode { CS_ACCESS_AP , CS_ACCESS_MEM_AP }
 Method to access the CoreSight component. More...
 

Functions

static struct adiv5_ap_dap_get_ap (struct adiv5_dap *dap, uint64_t ap_num)
 
int adiv5_jim_configure (struct target *target, struct jim_getopt_info *goi)
 
int adiv5_jim_configure_ext (struct target *target, struct jim_getopt_info *goi, struct adiv5_private_config *pc, enum adiv5_configure_dap_optional optional)
 
int adiv5_jim_mem_ap_spot_configure (struct adiv5_mem_ap_spot *cfg, struct jim_getopt_info *goi)
 
static int adiv5_jim_spot_configure (struct jim_getopt_info *goi, struct adiv5_dap **dap_p, uint64_t *ap_num_p, uint32_t *base_p)
 
int adiv5_mem_ap_spot_init (struct adiv5_mem_ap_spot *p)
 
int adiv5_verify_config (struct adiv5_private_config *pc)
 
int adiv6_dap_read_baseptr (struct command_invocation *cmd, struct adiv5_dap *dap, uint64_t *baseptr)
 
static const char * ap_type_to_description (enum ap_type type)
 
static const char * class0x9_devarch_description (uint32_t devarch)
 
 COMMAND_HANDLER (dap_apcsw_command)
 
 COMMAND_HANDLER (dap_apid_command)
 
 COMMAND_HANDLER (dap_apreg_command)
 
 COMMAND_HANDLER (dap_apsel_command)
 
 COMMAND_HANDLER (dap_baseaddr_command)
 
 COMMAND_HANDLER (dap_dpreg_command)
 
 COMMAND_HANDLER (dap_memaccess_command)
 
 COMMAND_HANDLER (dap_nu_npcx_quirks_command)
 
 COMMAND_HANDLER (dap_ti_be_32_quirks_command)
 
 COMMAND_HANDLER (handle_dap_info_command)
 
static int dap_devtype_display (struct command_invocation *cmd, uint32_t devtype)
 
int dap_dp_init (struct adiv5_dap *dap)
 Initialize a DAP. More...
 
int dap_dp_init_or_reconnect (struct adiv5_dap *dap)
 Initialize a DAP or do reconnect if DAP is not accessible. More...
 
int dap_find_get_ap (struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
 
struct adiv5_apdap_get_ap (struct adiv5_dap *dap, uint64_t ap_num)
 
struct adiv5_apdap_get_config_ap (struct adiv5_dap *dap, uint64_t ap_num)
 
static int dap_get_debugbase (struct adiv5_ap *ap, target_addr_t *dbgbase, uint32_t *apid)
 
static int dap_info_ap_header (struct adiv5_ap *ap, int depth, void *priv)
 
int dap_info_command (struct command_invocation *cmd, struct adiv5_ap *ap)
 
static int dap_info_cs_component (int retval, struct cs_component_vals *v, int depth, void *priv)
 
static int dap_info_mem_ap_header (int retval, struct adiv5_ap *ap, target_addr_t dbgbase, uint32_t apid, int depth, void *priv)
 
static int dap_info_rom_table_entry (int retval, int depth, unsigned int offset, uint64_t romentry, void *priv)
 
void dap_invalidate_cache (struct adiv5_dap *dap)
 Invalidate cached DP select and cached TAR and CSW of all APs. More...
 
int dap_lookup_cs_component (struct adiv5_ap *ap, uint8_t type, target_addr_t *addr, int32_t core_id)
 
static int dap_lookup_cs_component_cs_component (int retval, struct cs_component_vals *v, int depth, void *priv)
 
int dap_put_ap (struct adiv5_ap *ap)
 
static int dap_queue_read_reg (enum coresight_access_mode mode, struct adiv5_ap *ap, uint64_t component_base, unsigned int reg, uint32_t *value)
 Helper to read CoreSight component's registers, either on the bus behind a MEM-AP or directly in the AP. More...
 
int dap_to_jtag (struct adiv5_dap *dap)
 Put the debug link into JTAG mode, if the target supports it. More...
 
int dap_to_swd (struct adiv5_dap *dap)
 Put the debug link into SWD mode, if the target supports it. More...
 
static bool is_ap_in_use (struct adiv5_ap *ap)
 
bool is_ap_num_valid (struct adiv5_dap *dap, uint64_t ap_num)
 
static uint32_t max_tar_block_size (uint32_t tar_autoincr_block, target_addr_t address)
 
static uint32_t mem_ap_get_tar_increment (struct adiv5_ap *ap)
 
int mem_ap_init (struct adiv5_ap *ap)
 Initialize a DAP. More...
 
static int mem_ap_read (struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t adr, bool addrinc)
 Synchronous read of a block of memory, using a specific access size. More...
 
int mem_ap_read_atomic_u32 (struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
 Synchronous read of a word from memory or a system register. More...
 
int mem_ap_read_buf (struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
 
int mem_ap_read_buf_noincr (struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
 
static int mem_ap_read_tar (struct adiv5_ap *ap, target_addr_t *tar)
 
int mem_ap_read_u32 (struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
 Asynchronous (queued) read of a word from memory or a system register. More...
 
static int mem_ap_setup_csw (struct adiv5_ap *ap, uint32_t csw)
 
static int mem_ap_setup_tar (struct adiv5_ap *ap, target_addr_t tar)
 
static int mem_ap_setup_transfer (struct adiv5_ap *ap, uint32_t csw, target_addr_t tar)
 Queue transactions setting up transfer parameters for the currently selected MEM-AP. More...
 
static int mem_ap_setup_transfer_verify_size_packing (struct adiv5_ap *ap, unsigned int size, target_addr_t address, bool addrinc, bool pack, unsigned int *this_size)
 Queue transactions setting up transfer parameters for the currently selected MEM-AP. More...
 
static int mem_ap_setup_transfer_verify_size_packing_fallback (struct adiv5_ap *ap, unsigned int size, target_addr_t address, bool addrinc, bool pack, unsigned int *this_size)
 Queue transactions setting up transfer parameters for the currently selected MEM-AP. More...
 
static void mem_ap_update_tar_cache (struct adiv5_ap *ap)
 
static int mem_ap_write (struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address, bool addrinc)
 Synchronous write of a block of memory, using a specific access size. More...
 
int mem_ap_write_atomic_u32 (struct adiv5_ap *ap, target_addr_t address, uint32_t value)
 Synchronous write of a word to memory or a system register. More...
 
int mem_ap_write_buf (struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
 
int mem_ap_write_buf_noincr (struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
 
int mem_ap_write_u32 (struct adiv5_ap *ap, target_addr_t address, uint32_t value)
 Asynchronous (queued) write of a word to memory or a system register. More...
 
static const struct dap_part_numspidr_to_part_num (unsigned int designer_id, unsigned int part_num)
 
static int rtp_ap (const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
 
static int rtp_cs_component (enum coresight_access_mode mode, const struct rtp_ops *ops, struct adiv5_ap *ap, target_addr_t dbgbase, bool *is_mem_ap, int depth)
 
static int rtp_ops_ap_header (const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
 Wrapper around struct rtp_ops::ap_header. More...
 
static int rtp_ops_cs_component (const struct rtp_ops *ops, int retval, struct cs_component_vals *v, int depth)
 Wrapper around struct rtp_ops::cs_component. More...
 
static int rtp_ops_mem_ap_header (const struct rtp_ops *ops, int retval, struct adiv5_ap *ap, uint64_t dbgbase, uint32_t apid, int depth)
 Wrapper around struct rtp_ops::mem_ap_header. More...
 
static int rtp_ops_rom_table_entry (const struct rtp_ops *ops, int retval, int depth, unsigned int offset, uint64_t romentry)
 Wrapper around struct rtp_ops::rom_table_entry. More...
 
static int rtp_read_cs_regs (enum coresight_access_mode mode, struct adiv5_ap *ap, target_addr_t component_base, struct cs_component_vals *v)
 Read the CoreSight registers needed during ROM Table Parsing (RTP). More...
 
static int rtp_rom_loop (enum coresight_access_mode mode, const struct rtp_ops *ops, struct adiv5_ap *ap, target_addr_t base_address, int depth, unsigned int width, unsigned int max_entries)
 

Variables

struct {
   const char *   description
 
   enum ap_type   type
 
ap_types []
 
struct {
   uint32_t   arch_id
 
   const char *   description
 
class0x9_devarch []
 
static const char * class_description [16]
 
const struct command_registration dap_instance_commands []
 
static const struct dap_part_nums dap_part_nums []
 
static const struct jim_nvp nvp_config_opts []
 

Detailed Description

This file implements support for the ARM Debug Interface version 5 (ADIv5) debugging architecture.

Compared with previous versions, this includes a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message transport, and focuses on memory mapped resources as defined by the CoreSight architecture.

A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two basic components: a Debug Port (DP) transporting messages to and from a debugger, and an Access Port (AP) accessing resources. Three types of DP are defined. One uses only JTAG for communication, and is called JTAG-DP. One uses only SWD for communication, and is called SW-DP. The third can use either SWD or JTAG, and is called SWJ-DP. The most common type of AP is used to access memory mapped resources and is called a MEM-AP. Also a JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.

This programming interface allows DAP pipelined operations through a transaction queue. This primarily affects AP operations (such as using a MEM-AP to access memory or registers). If the current transaction has not finished by the time the next one must begin, and the ORUNDETECT bit is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and further AP operations will fail. There are two basic methods to avoid such overrun errors. One involves polling for status instead of using transaction pipelining. The other involves adding delays to ensure the AP has enough time to complete one operation before starting the next one. (For JTAG these delays are controlled by memaccess_tck.)

Definition in file arm_adi_v5.c.

Macro Definition Documentation

◆ ARCH_ID

#define ARCH_ID (   architect,
  archid 
)
Value:
( \
)
#define ARM_CS_C9_DEVARCH_ARCHID_MASK
Definition: arm_coresight.h:59
#define ARM_CS_C9_DEVARCH_ARCHITECT_MASK
Definition: arm_coresight.h:64
#define ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT
Definition: arm_coresight.h:65
#define ARM_CS_C9_DEVARCH_ARCHID_SHIFT
Definition: arm_coresight.h:60

Definition at line 1003 of file arm_adi_v5.c.

◆ CORESIGHT_COMPONENT_FOUND

#define CORESIGHT_COMPONENT_FOUND   (1)

Value used only during lookup of a CoreSight component in ROM table.

Return CORESIGHT_COMPONENT_FOUND when component is found. Return ERROR_OK when component is not found yet. Return any other ERROR_* in case of error.

Definition at line 1848 of file arm_adi_v5.c.

◆ DAP_POWER_DOMAIN_TIMEOUT

#define DAP_POWER_DOMAIN_TIMEOUT   (10)

Definition at line 749 of file arm_adi_v5.c.

◆ DEVARCH_ID_MASK

Definition at line 1037 of file arm_adi_v5.c.

◆ DEVARCH_MEM_AP

#define DEVARCH_MEM_AP   ARCH_ID(ARM_ID, 0x0A17)

Definition at line 1038 of file arm_adi_v5.c.

◆ DEVARCH_ROM_C_0X9

#define DEVARCH_ROM_C_0X9   ARCH_ID(ARM_ID, 0x0AF7)

Definition at line 1039 of file arm_adi_v5.c.

◆ DEVARCH_UNKNOWN_V2

#define DEVARCH_UNKNOWN_V2   ARCH_ID(ARM_ID, 0x0A47)

Definition at line 1040 of file arm_adi_v5.c.

◆ ROM_TABLE_MAX_DEPTH

#define ROM_TABLE_MAX_DEPTH   (16)

Definition at line 1840 of file arm_adi_v5.c.

Enumeration Type Documentation

◆ adiv5_cfg_param

Enumerator
CFG_DAP 
CFG_AP_NUM 
CFG_BASEADDR 
CFG_CTIBASE 

Definition at line 2321 of file arm_adi_v5.c.

◆ coresight_access_mode

Method to access the CoreSight component.

On ADIv5, CoreSight components are on the bus behind a MEM-AP. On ADIv6, CoreSight components can either be on the bus behind a MEM-AP or directly in the AP.

Enumerator
CS_ACCESS_AP 
CS_ACCESS_MEM_AP 

Definition at line 1298 of file arm_adi_v5.c.

Function Documentation

◆ _dap_get_ap()

static struct adiv5_ap* _dap_get_ap ( struct adiv5_dap dap,
uint64_t  ap_num 
)
static

◆ adiv5_jim_configure()

int adiv5_jim_configure ( struct target target,
struct jim_getopt_info goi 
)

Definition at line 2479 of file arm_adi_v5.c.

References ADI_CONFIGURE_DAP_COMPULSORY, adiv5_jim_configure_ext(), and NULL.

◆ adiv5_jim_configure_ext()

◆ adiv5_jim_mem_ap_spot_configure()

int adiv5_jim_mem_ap_spot_configure ( struct adiv5_mem_ap_spot cfg,
struct jim_getopt_info goi 
)

◆ adiv5_jim_spot_configure()

◆ adiv5_mem_ap_spot_init()

int adiv5_mem_ap_spot_init ( struct adiv5_mem_ap_spot p)

◆ adiv5_verify_config()

◆ adiv6_dap_read_baseptr()

int adiv6_dap_read_baseptr ( struct command_invocation cmd,
struct adiv5_dap dap,
uint64_t *  baseptr 
)

◆ ap_type_to_description()

static const char* ap_type_to_description ( enum ap_type  type)
static

Definition at line 1069 of file arm_adi_v5.c.

References ap_types, ARRAY_SIZE, and type.

Referenced by dap_find_get_ap(), and dap_info_mem_ap_header().

◆ class0x9_devarch_description()

static const char* class0x9_devarch_description ( uint32_t  devarch)
static

◆ COMMAND_HANDLER() [1/10]

◆ COMMAND_HANDLER() [2/10]

◆ COMMAND_HANDLER() [3/10]

◆ COMMAND_HANDLER() [4/10]

◆ COMMAND_HANDLER() [5/10]

◆ COMMAND_HANDLER() [6/10]

◆ COMMAND_HANDLER() [7/10]

◆ COMMAND_HANDLER() [8/10]

COMMAND_HANDLER ( dap_nu_npcx_quirks_command  )

◆ COMMAND_HANDLER() [9/10]

COMMAND_HANDLER ( dap_ti_be_32_quirks_command  )

◆ COMMAND_HANDLER() [10/10]

◆ dap_devtype_display()

static int dap_devtype_display ( struct command_invocation cmd,
uint32_t  devtype 
)
static

◆ dap_dp_init()

int dap_dp_init ( struct adiv5_dap dap)

◆ dap_dp_init_or_reconnect()

int dap_dp_init_or_reconnect ( struct adiv5_dap dap)

Initialize a DAP or do reconnect if DAP is not accessible.

Parameters
dapThe DAP being initialized.

Definition at line 857 of file arm_adi_v5.c.

References adiv5_dap_name(), CDBGPWRUPREQ, dap_ops::connect, CSYSPWRUPREQ, dap_dp_init(), dap_dp_read_atomic(), adiv5_dap::do_reconnect, DP_CTRL_STAT, adiv5_dap::dp_ctrl_stat, LOG_DEBUG, NULL, and adiv5_dap::ops.

Referenced by cortex_m_assert_reset(), and cortex_m_deassert_reset().

◆ dap_find_get_ap()

◆ dap_get_ap()

◆ dap_get_config_ap()

struct adiv5_ap* dap_get_config_ap ( struct adiv5_dap dap,
uint64_t  ap_num 
)

◆ dap_get_debugbase()

static int dap_get_debugbase ( struct adiv5_ap ap,
target_addr_t dbgbase,
uint32_t *  apid 
)
static

◆ dap_info_ap_header()

static int dap_info_ap_header ( struct adiv5_ap ap,
int  depth,
void *  priv 
)
static

Definition at line 2048 of file arm_adi_v5.c.

References adiv5_ap::ap_num, cmd, command_print(), ERROR_FAIL, ERROR_OK, priv, and ROM_TABLE_MAX_DEPTH.

Referenced by dap_info_command().

◆ dap_info_command()

int dap_info_command ( struct command_invocation cmd,
struct adiv5_ap ap 
)

◆ dap_info_cs_component()

◆ dap_info_mem_ap_header()

static int dap_info_mem_ap_header ( int  retval,
struct adiv5_ap ap,
target_addr_t  dbgbase,
uint32_t  apid,
int  depth,
void *  priv 
)
static

◆ dap_info_rom_table_entry()

static int dap_info_rom_table_entry ( int  retval,
int  depth,
unsigned int  offset,
uint64_t  romentry,
void *  priv 
)
static

Definition at line 2201 of file arm_adi_v5.c.

References ARM_CS_ROMENTRY_PRESENT, cmd, command_print(), ERROR_OK, offset, and priv.

Referenced by dap_info_command().

◆ dap_invalidate_cache()

void dap_invalidate_cache ( struct adiv5_dap dap)

◆ dap_lookup_cs_component()

◆ dap_lookup_cs_component_cs_component()

◆ dap_put_ap()

◆ dap_queue_read_reg()

static int dap_queue_read_reg ( enum coresight_access_mode  mode,
struct adiv5_ap ap,
uint64_t  component_base,
unsigned int  reg,
uint32_t *  value 
)
static

Helper to read CoreSight component's registers, either on the bus behind a MEM-AP or directly in the AP.

Parameters
modeMethod to access the component (AP or MEM-AP).
apPointer to AP containing the component.
component_baseOn MEM-AP access method, base address of the component.
regOffset of the component's register to read.
valuePointer to the store the read value.
Returns
ERROR_OK on success, else a fault code.

Definition at line 1327 of file arm_adi_v5.c.

References CS_ACCESS_AP, dap_queue_ap_read(), mem_ap_read_u32(), and mode.

Referenced by rtp_read_cs_regs(), and rtp_rom_loop().

◆ dap_to_jtag()

int dap_to_jtag ( struct adiv5_dap dap)

Put the debug link into JTAG mode, if the target supports it.

The link's initial mode may be either SWD or JTAG.

Note that targets implemented with SW-DP do not support JTAG, and that some targets which could otherwise support it may have been configured to disable JTAG signaling

Parameters
dapThe DAP used
Returns
ERROR_OK or else a fault code.

Definition at line 970 of file arm_adi_v5.c.

References dap_send_sequence(), LOG_DEBUG, and SWD_TO_JTAG.

Referenced by COMMAND_HANDLER().

◆ dap_to_swd()

int dap_to_swd ( struct adiv5_dap dap)

Put the debug link into SWD mode, if the target supports it.

The link's initial mode may be either JTAG (for example, with SWJ-DP after reset) or SWD.

Note that targets using the JTAG-DP do not support SWD, and that some targets which could otherwise support it may have been configured to disable SWD signaling

Parameters
dapThe DAP used
Returns
ERROR_OK or else a fault code.

Definition at line 952 of file arm_adi_v5.c.

References dap_send_sequence(), JTAG_TO_SWD, and LOG_DEBUG.

Referenced by COMMAND_HANDLER().

◆ is_ap_in_use()

static bool is_ap_in_use ( struct adiv5_ap ap)
inlinestatic

Definition at line 1150 of file arm_adi_v5.c.

References adiv5_ap::config_ap_never_release, and adiv5_ap::refcount.

Referenced by _dap_get_ap(), and dap_put_ap().

◆ is_ap_num_valid()

bool is_ap_num_valid ( struct adiv5_dap dap,
uint64_t  ap_num 
)

Definition at line 1078 of file arm_adi_v5.c.

References adiv5_dap::asize, DP_APSEL_MAX, and is_adiv6().

Referenced by _dap_get_ap(), and COMMAND_HANDLER().

◆ max_tar_block_size()

static uint32_t max_tar_block_size ( uint32_t  tar_autoincr_block,
target_addr_t  address 
)
static

◆ mem_ap_get_tar_increment()

static uint32_t mem_ap_get_tar_increment ( struct adiv5_ap ap)
static

◆ mem_ap_init()

int mem_ap_init ( struct adiv5_ap ap)

◆ mem_ap_read()

static int mem_ap_read ( struct adiv5_ap ap,
uint8_t *  buffer,
uint32_t  size,
uint32_t  count,
target_addr_t  adr,
bool  addrinc 
)
static

Synchronous read of a block of memory, using a specific access size.

Parameters
apThe MEM-AP to access.
bufferThe data buffer to receive the data. No particular alignment is assumed.
sizeWhich access size to use, in bytes. 1, 2, or 4. If large data extension is available also accepts sizes 8, 16, 32.
countThe number of reads to do (in size units, not bytes).
adrAddress to be read; it must be readable by the currently selected MEM-AP.
addrincWhether the target address should be increased after each read or not. This should normally be true, except when reading from e.g. a FIFO.
Returns
ERROR_OK on success, otherwise an error code.

Definition at line 604 of file arm_adi_v5.c.

References adiv5_dap::ap, buffer, count, adiv5_ap::dap, dap_queue_ap_read(), dap_run(), DIV_ROUND_UP, ERROR_FAIL, ERROR_OK, ERROR_TARGET_SIZE_NOT_SUPPORTED, ERROR_TARGET_UNALIGNED_ACCESS, LOG_ERROR, MAX, max_tar_block_size(), mem_ap_read_tar(), MEM_AP_REG_DRW, mem_ap_setup_transfer_verify_size_packing_fallback(), mem_ap_update_tar_cache(), MIN, size, adiv5_ap::tar_autoincr_block, TARGET_ADDR_FMT, adiv5_dap::ti_be_32_quirks, and adiv5_ap::unaligned_access_bad.

Referenced by mem_ap_read_buf(), and mem_ap_read_buf_noincr().

◆ mem_ap_read_atomic_u32()

int mem_ap_read_atomic_u32 ( struct adiv5_ap ap,
target_addr_t  address,
uint32_t *  value 
)

Synchronous read of a word from memory or a system register.

As a side effect, this flushes any queued transactions.

Parameters
apThe MEM-AP to access.
addressAddress of the 32-bit word to read; it must be readable by the currently selected MEM-AP.
valuepoints to where the result will be stored.
Returns
ERROR_OK for success; *value holds the result. Otherwise a fault code.

Definition at line 266 of file arm_adi_v5.c.

References adiv5_ap::dap, dap_run(), ERROR_OK, and mem_ap_read_u32().

Referenced by aarch64_clear_reset_catch(), aarch64_debug_entry(), aarch64_enable_reset_catch(), aarch64_handle_target_request(), aarch64_prepare_restart_one(), aarch64_read_cpu_memory(), aarch64_read_cpu_memory_fast(), aarch64_read_cpu_memory_slow(), aarch64_read_prsr(), aarch64_step(), aarch64_write_cpu_memory(), arm_cti_ack_events(), arm_cti_mod_reg_bits(), arm_cti_read_reg(), armv7a_setup_semihosting(), armv8_set_dbgreg_bits(), COMMAND_HANDLER(), cortex_a_debug_entry(), cortex_a_deinit_target(), cortex_a_examine_first(), cortex_a_handle_target_request(), cortex_a_init_debug_access(), cortex_a_internal_restart(), cortex_a_poll(), cortex_a_read_copro(), cortex_a_read_cpu_memory(), cortex_a_read_cpu_memory_fast(), cortex_a_read_cpu_memory_slow(), cortex_a_read_dcc(), cortex_a_set_dscr_bits(), cortex_a_wait_dscr_bits(), cortex_a_wait_instrcmpl(), cortex_a_write_cpu_memory(), cortex_m_assert_reset(), cortex_m_clear_halt(), cortex_m_endreset_event(), cortex_m_examine_exception_reason(), cortex_m_load_core_reg_u32(), cortex_m_read_dhcsr_atomic_sticky(), cortex_m_soft_reset_halt(), dpmv8_dpm_prepare(), dpmv8_exec_opcode(), dpmv8_read_dcc(), and dpmv8_read_dcc_64().

◆ mem_ap_read_buf()

int mem_ap_read_buf ( struct adiv5_ap ap,
uint8_t *  buffer,
uint32_t  size,
uint32_t  count,
target_addr_t  address 
)

◆ mem_ap_read_buf_noincr()

int mem_ap_read_buf_noincr ( struct adiv5_ap ap,
uint8_t *  buffer,
uint32_t  size,
uint32_t  count,
target_addr_t  address 
)

◆ mem_ap_read_tar()

static int mem_ap_read_tar ( struct adiv5_ap ap,
target_addr_t tar 
)
static

◆ mem_ap_read_u32()

int mem_ap_read_u32 ( struct adiv5_ap ap,
target_addr_t  address,
uint32_t *  value 
)

Asynchronous (queued) read of a word from memory or a system register.

Parameters
apThe MEM-AP to access.
addressAddress of the 32-bit word to read; it must be readable by the currently selected MEM-AP.
valuepoints to where the word will be stored when the transaction queue is flushed (assuming no errors).
Returns
ERROR_OK for success. Otherwise a fault code.

Definition at line 237 of file arm_adi_v5.c.

References CSW_32BIT, CSW_ADDRINC_MASK, adiv5_ap::csw_value, adiv5_ap::dap, dap_queue_ap_read(), ERROR_OK, MEM_AP_REG_BD0, and mem_ap_setup_transfer().

Referenced by aarch64_examine_first(), COMMAND_HANDLER(), cortex_m_debug_entry(), cortex_m_examine_exception_reason(), cortex_m_fast_read_all_regs(), cortex_m_load_core_reg_u32(), cortex_m_queue_reg_read(), cortex_m_store_core_reg_u32(), dap_queue_read_reg(), dpmv8_dpm_prepare(), and mem_ap_read_atomic_u32().

◆ mem_ap_setup_csw()

static int mem_ap_setup_csw ( struct adiv5_ap ap,
uint32_t  csw 
)
static

◆ mem_ap_setup_tar()

◆ mem_ap_setup_transfer()

static int mem_ap_setup_transfer ( struct adiv5_ap ap,
uint32_t  csw,
target_addr_t  tar 
)
static

Queue transactions setting up transfer parameters for the currently selected MEM-AP.

Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2 initiate data reads or writes using memory or peripheral addresses. If the CSW is configured for it, the TAR may be automatically incremented after each transfer.

Parameters
apThe MEM-AP.
cswMEM-AP Control/Status Word (CSW) register to assign. If this matches the cached value, the register is not changed.
tarMEM-AP Transfer Address Register (TAR) to assign. If this matches the cached address, the register is not changed.
Returns
ERROR_OK if the transaction was properly queued, else a fault code.

Definition at line 214 of file arm_adi_v5.c.

References ERROR_OK, mem_ap_setup_csw(), and mem_ap_setup_tar().

Referenced by mem_ap_read_u32(), and mem_ap_write_u32().

◆ mem_ap_setup_transfer_verify_size_packing()

static int mem_ap_setup_transfer_verify_size_packing ( struct adiv5_ap ap,
unsigned int  size,
target_addr_t  address,
bool  addrinc,
bool  pack,
unsigned int *  this_size 
)
static

Queue transactions setting up transfer parameters for the currently selected MEM-AP.

If transfer size or packing has not been probed, run the queue, read back CSW and check if the requested transfer mode is supported.

Parameters
apThe MEM-AP.
sizeTransfer width in bytes. Corresponding CSW.Size will be set.
addressTransfer address, MEM-AP TAR will be set to this value.
addrincTAR will be autoincremented.
packTry to setup packed transfer.
this_sizePoints to a variable set to the size of single transfer or to 4 when transferring packed bytes or halfwords
Returns
ERROR_OK if the transaction was properly queued, else a fault code.

Definition at line 345 of file arm_adi_v5.c.

References adiv5_ap::ap_num, CSW_128BIT, CSW_16BIT, CSW_256BIT, CSW_32BIT, CSW_64BIT, CSW_8BIT, CSW_ADDRINC_MASK, CSW_ADDRINC_OFF, CSW_ADDRINC_PACKED, CSW_ADDRINC_SINGLE, CSW_SIZE_MASK, adiv5_ap::csw_size_probed_mask, adiv5_ap::csw_size_supported_mask, adiv5_ap::dap, dap_queue_ap_read(), dap_run(), ERROR_OK, ERROR_TARGET_PACKING_NOT_SUPPORTED, ERROR_TARGET_SIZE_NOT_SUPPORTED, LOG_DEBUG, LOG_ERROR, max_tar_block_size(), MEM_AP_REG_CSW, mem_ap_setup_csw(), mem_ap_setup_tar(), adiv5_ap::packed_transfers_probed, adiv5_ap::packed_transfers_supported, size, and adiv5_ap::tar_autoincr_block.

Referenced by mem_ap_setup_transfer_verify_size_packing_fallback().

◆ mem_ap_setup_transfer_verify_size_packing_fallback()

static int mem_ap_setup_transfer_verify_size_packing_fallback ( struct adiv5_ap ap,
unsigned int  size,
target_addr_t  address,
bool  addrinc,
bool  pack,
unsigned int *  this_size 
)
static

Queue transactions setting up transfer parameters for the currently selected MEM-AP.

If transfer size or packing has not been probed, run the queue, read back CSW and check if the requested transfer mode is supported. If packing is not supported fallback and prepare CSW for unpacked transfer.

Parameters
apThe MEM-AP.
sizeTransfer width in bytes. Corresponding CSW.Size will be set.
addressTransfer address, MEM-AP TAR will be set to this value.
addrincTAR will be autoincremented.
packTry to setup packed transfer.
this_sizePoints to a variable set to the size of single transfer or to 4 when transferring packed bytes or halfwords
Returns
ERROR_OK if the transaction was properly queued, else a fault code.

Definition at line 445 of file arm_adi_v5.c.

References ERROR_TARGET_PACKING_NOT_SUPPORTED, mem_ap_setup_transfer_verify_size_packing(), and size.

Referenced by mem_ap_read(), and mem_ap_write().

◆ mem_ap_update_tar_cache()

static void mem_ap_update_tar_cache ( struct adiv5_ap ap)
static

◆ mem_ap_write()

static int mem_ap_write ( struct adiv5_ap ap,
const uint8_t *  buffer,
uint32_t  size,
uint32_t  count,
target_addr_t  address,
bool  addrinc 
)
static

Synchronous write of a block of memory, using a specific access size.

Parameters
apThe MEM-AP to access.
bufferThe data buffer to write. No particular alignment is assumed.
sizeWhich access size to use, in bytes. 1, 2, or 4. If large data extension is available also accepts sizes 8, 16, 32.
countThe number of writes to do (in size units, not bytes).
addressAddress to be written; it must be writable by the currently selected MEM-AP.
addrincWhether the target address should be increased for each write or not. This should normally be true, except when writing to e.g. a FIFO.
Returns
ERROR_OK on success, otherwise an error code.

Definition at line 474 of file arm_adi_v5.c.

References adiv5_dap::ap, buffer, count, adiv5_ap::dap, dap_queue_ap_write(), dap_run(), DIV_ROUND_UP, ERROR_OK, ERROR_TARGET_SIZE_NOT_SUPPORTED, ERROR_TARGET_UNALIGNED_ACCESS, LOG_ERROR, low, mem_ap_read_tar(), MEM_AP_REG_DRW, mem_ap_setup_transfer_verify_size_packing_fallback(), mem_ap_update_tar_cache(), MIN, adiv5_dap::nu_npcx_quirks, size, TARGET_ADDR_FMT, adiv5_dap::ti_be_32_quirks, and adiv5_ap::unaligned_access_bad.

Referenced by mem_ap_write_buf(), and mem_ap_write_buf_noincr().

◆ mem_ap_write_atomic_u32()

int mem_ap_write_atomic_u32 ( struct adiv5_ap ap,
target_addr_t  address,
uint32_t  value 
)

Synchronous write of a word to memory or a system register.

As a side effect, this flushes any queued transactions.

Parameters
apThe MEM-AP to access.
addressAddress to be written; it must be writable by the currently selected MEM-AP.
valueWord that will be written.
Returns
ERROR_OK for success; the data was written. Otherwise a fault code.

Definition at line 318 of file arm_adi_v5.c.

References adiv5_ap::dap, dap_run(), ERROR_OK, and mem_ap_write_u32().

Referenced by aarch64_assert_reset(), aarch64_clear_reset_catch(), aarch64_dap_write_memap_register_u32(), aarch64_debug_entry(), aarch64_enable_reset_catch(), aarch64_examine_first(), aarch64_init_debug_access(), aarch64_prepare_restart_one(), aarch64_read_cpu_memory(), aarch64_read_cpu_memory_fast(), aarch64_read_cpu_memory_slow(), aarch64_step(), aarch64_write_cpu_memory(), aarch64_write_cpu_memory_fast(), aarch64_write_cpu_memory_slow(), arm_cti_ack_events(), arm_cti_enable(), arm_cti_mod_reg_bits(), arm_cti_write_reg(), armv7a_setup_semihosting(), armv8_set_dbgreg_bits(), COMMAND_HANDLER(), cortex_a_bpwp_disable(), cortex_a_bpwp_enable(), cortex_a_deassert_reset(), cortex_a_debug_entry(), cortex_a_deinit_target(), cortex_a_examine_first(), cortex_a_halt(), cortex_a_init_debug_access(), cortex_a_internal_restart(), cortex_a_read_cpu_memory(), cortex_a_read_cpu_memory_fast(), cortex_a_set_breakpoint(), cortex_a_set_context_breakpoint(), cortex_a_set_dcc_mode(), cortex_a_set_dscr_bits(), cortex_a_set_hybrid_breakpoint(), cortex_a_set_watchpoint(), cortex_a_unset_breakpoint(), cortex_a_unset_watchpoint(), cortex_a_write_copro(), cortex_a_write_cpu_memory(), cortex_a_write_cpu_memory_fast(), cortex_a_write_cpu_memory_slow(), cortex_m_assert_reset(), cortex_m_clear_halt(), cortex_m_fast_read_all_regs(), cortex_m_load_core_reg_u32(), cortex_m_soft_reset_halt(), cortex_m_store_core_reg_u32(), cortex_m_write_debug_halt_mask(), dpmv8_bpwp_disable(), handle_reset_halt(), and wrap_write_u32().

◆ mem_ap_write_buf()

int mem_ap_write_buf ( struct adiv5_ap ap,
const uint8_t *  buffer,
uint32_t  size,
uint32_t  count,
target_addr_t  address 
)

Definition at line 728 of file arm_adi_v5.c.

References adiv5_dap::ap, buffer, count, mem_ap_write(), and size.

Referenced by COMMAND_HANDLER(), and cortex_m_write_memory().

◆ mem_ap_write_buf_noincr()

int mem_ap_write_buf_noincr ( struct adiv5_ap ap,
const uint8_t *  buffer,
uint32_t  size,
uint32_t  count,
target_addr_t  address 
)

◆ mem_ap_write_u32()

int mem_ap_write_u32 ( struct adiv5_ap ap,
target_addr_t  address,
uint32_t  value 
)

Asynchronous (queued) write of a word to memory or a system register.

Parameters
apThe MEM-AP to access.
addressAddress to be written; it must be writable by the currently selected MEM-AP.
valueWord that will be written to the address when transaction queue is flushed (assuming no errors).
Returns
ERROR_OK for success. Otherwise a fault code.

Definition at line 289 of file arm_adi_v5.c.

References CSW_32BIT, CSW_ADDRINC_MASK, adiv5_ap::csw_value, adiv5_ap::dap, dap_queue_ap_write(), ERROR_OK, MEM_AP_REG_BD0, and mem_ap_setup_transfer().

Referenced by armv8_dpm_handle_exception(), COMMAND_HANDLER(), cortex_a_exec_opcode(), cortex_a_init_debug_access(), cortex_a_write_dcc(), cortex_m_assert_reset(), cortex_m_endreset_event(), cortex_m_load_core_reg_u32(), cortex_m_queue_reg_read(), cortex_m_soft_reset_halt(), cortex_m_store_core_reg_u32(), dpmv8_exec_opcode(), dpmv8_write_dcc(), dpmv8_write_dcc_64(), mem_ap_write_atomic_u32(), xtensa_dm_queue_pwr_reg_read(), xtensa_dm_queue_pwr_reg_write(), and xtensa_dm_queue_reg_write().

◆ pidr_to_part_num()

static const struct dap_part_nums* pidr_to_part_num ( unsigned int  designer_id,
unsigned int  part_num 
)
static

◆ rtp_ap()

◆ rtp_cs_component()

◆ rtp_ops_ap_header()

static int rtp_ops_ap_header ( const struct rtp_ops ops,
struct adiv5_ap ap,
int  depth 
)
static

Wrapper around struct rtp_ops::ap_header.

Definition at line 1782 of file arm_adi_v5.c.

References cs_component_vals::ap, rtp_ops::ap_header, ERROR_OK, and rtp_ops::priv.

Referenced by rtp_ap().

◆ rtp_ops_cs_component()

static int rtp_ops_cs_component ( const struct rtp_ops ops,
int  retval,
struct cs_component_vals v,
int  depth 
)
static

Wrapper around struct rtp_ops::cs_component.

Input parameter retval is propagated.

Definition at line 1811 of file arm_adi_v5.c.

References rtp_ops::cs_component, ERROR_OK, and rtp_ops::priv.

Referenced by rtp_cs_component().

◆ rtp_ops_mem_ap_header()

static int rtp_ops_mem_ap_header ( const struct rtp_ops ops,
int  retval,
struct adiv5_ap ap,
uint64_t  dbgbase,
uint32_t  apid,
int  depth 
)
static

Wrapper around struct rtp_ops::mem_ap_header.

Input parameter retval is propagated.

Definition at line 1795 of file arm_adi_v5.c.

References cs_component_vals::ap, ERROR_OK, rtp_ops::mem_ap_header, and rtp_ops::priv.

Referenced by rtp_ap().

◆ rtp_ops_rom_table_entry()

static int rtp_ops_rom_table_entry ( const struct rtp_ops ops,
int  retval,
int  depth,
unsigned int  offset,
uint64_t  romentry 
)
static

Wrapper around struct rtp_ops::rom_table_entry.

Input parameter retval is propagated.

Definition at line 1827 of file arm_adi_v5.c.

References ERROR_OK, offset, rtp_ops::priv, and rtp_ops::rom_table_entry.

Referenced by rtp_rom_loop().

◆ rtp_read_cs_regs()

static int rtp_read_cs_regs ( enum coresight_access_mode  mode,
struct adiv5_ap ap,
target_addr_t  component_base,
struct cs_component_vals v 
)
static

Read the CoreSight registers needed during ROM Table Parsing (RTP).

Parameters
modeMethod to access the component (AP or MEM-AP).
apPointer to AP containing the component.
component_baseOn MEM-AP access method, base address of the component.
vPointer to the struct holding the value of registers.
Returns
ERROR_OK on success, else a fault code.

Definition at line 1347 of file arm_adi_v5.c.

References cs_component_vals::ap, ARM_CS_ALIGN, ARM_CS_C9_DEVARCH, ARM_CS_C9_DEVID, ARM_CS_C9_DEVTYPE, ARM_CS_CIDR0, ARM_CS_CIDR1, ARM_CS_CIDR2, ARM_CS_CIDR3, ARM_CS_PIDR0, ARM_CS_PIDR1, ARM_CS_PIDR2, ARM_CS_PIDR3, ARM_CS_PIDR4, cs_component_vals::cid, cs_component_vals::component_base, adiv5_ap::dap, dap_queue_read_reg(), dap_run(), cs_component_vals::devarch, cs_component_vals::devid, cs_component_vals::devtype_memtype, ERROR_OK, IS_ALIGNED, LOG_DEBUG, cs_component_vals::mode, mode, and cs_component_vals::pid.

Referenced by rtp_cs_component().

◆ rtp_rom_loop()

Variable Documentation

◆ 

const { ... } ap_types[]
Initial value:
= {
{ AP_TYPE_JTAG_AP, "JTAG-AP" },
{ AP_TYPE_COM_AP, "COM-AP" },
{ AP_TYPE_AHB3_AP, "MEM-AP AHB3" },
{ AP_TYPE_APB_AP, "MEM-AP APB2 or APB3" },
{ AP_TYPE_AXI_AP, "MEM-AP AXI3 or AXI4" },
{ AP_TYPE_AHB5_AP, "MEM-AP AHB5" },
{ AP_TYPE_APB4_AP, "MEM-AP APB4" },
{ AP_TYPE_AXI5_AP, "MEM-AP AXI5" },
{ AP_TYPE_AHB5H_AP, "MEM-AP AHB5 with enhanced HPROT" },
}
@ AP_TYPE_APB_AP
Definition: arm_adi_v5.h:491
@ AP_TYPE_AXI_AP
Definition: arm_adi_v5.h:492
@ AP_TYPE_APB4_AP
Definition: arm_adi_v5.h:494
@ AP_TYPE_AHB3_AP
Definition: arm_adi_v5.h:490
@ AP_TYPE_COM_AP
Definition: arm_adi_v5.h:489
@ AP_TYPE_AHB5H_AP
Definition: arm_adi_v5.h:496
@ AP_TYPE_JTAG_AP
Definition: arm_adi_v5.h:488
@ AP_TYPE_AXI5_AP
Definition: arm_adi_v5.h:495
@ AP_TYPE_AHB5_AP
Definition: arm_adi_v5.h:493

Referenced by ap_type_to_description().

◆ arch_id

uint32_t arch_id

Definition at line 1009 of file arm_adi_v5.c.

◆ 

const { ... } class0x9_devarch[]
Initial value:
= {
{ ARCH_ID(ARM_ID, 0x0A00), "RAS architecture" },
{ ARCH_ID(ARM_ID, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" },
{ ARCH_ID(ARM_ID, 0x1A02), "DWT architecture" },
{ ARCH_ID(ARM_ID, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" },
{ ARCH_ID(ARM_ID, 0x2A04), "Processor debug architecture (ARMv8-M)" },
{ ARCH_ID(ARM_ID, 0x6A05), "Processor debug architecture (ARMv8-R)" },
{ ARCH_ID(ARM_ID, 0x0A10), "PC sample-based profiling" },
{ ARCH_ID(ARM_ID, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },
{ ARCH_ID(ARM_ID, 0x1A14), "Cross Trigger Interface (CTI) architecture" },
{ ARCH_ID(ARM_ID, 0x6A15), "Processor debug architecture (v8.0-A)" },
{ ARCH_ID(ARM_ID, 0x7A15), "Processor debug architecture (v8.1-A)" },
{ ARCH_ID(ARM_ID, 0x8A15), "Processor debug architecture (v8.2-A)" },
{ ARCH_ID(ARM_ID, 0x2A16), "Processor Performance Monitor (PMU) architecture" },
{ ARCH_ID(ARM_ID, 0x0A17), "Memory Access Port v2 architecture" },
{ ARCH_ID(ARM_ID, 0x0A27), "JTAG Access Port v2 architecture" },
{ ARCH_ID(ARM_ID, 0x0A31), "Basic trace router" },
{ ARCH_ID(ARM_ID, 0x0A37), "Power requestor" },
{ ARCH_ID(ARM_ID, 0x0A47), "Unknown Access Port v2 architecture" },
{ ARCH_ID(ARM_ID, 0x0A50), "HSSTP architecture" },
{ ARCH_ID(ARM_ID, 0x0A63), "System Trace Macrocell (STM) architecture" },
{ ARCH_ID(ARM_ID, 0x0A75), "CoreSight ELA architecture" },
{ ARCH_ID(ARM_ID, 0x0AF7), "CoreSight ROM architecture" },
}
#define ARCH_ID(architect, archid)
Definition: arm_adi_v5.c:1003
#define ARM_ID
Definition: arm_adi_v5.h:28

Referenced by class0x9_devarch_description().

◆ class_description

const char* class_description[16]
static
Initial value:
= {
[0x0] = "Generic verification component",
[0x1] = "ROM table",
[0x2] = "Reserved",
[0x3] = "Reserved",
[0x4] = "Reserved",
[0x5] = "Reserved",
[0x6] = "Reserved",
[0x7] = "Reserved",
[0x8] = "Reserved",
[0x9] = "CoreSight component",
[0xA] = "Reserved",
[0xB] = "Peripheral Test Block",
[0xC] = "Reserved",
[0xD] = "OptimoDE DESS",
[0xE] = "Generic IP component",
[0xF] = "CoreLink, PrimeCell or System component",
}

Definition at line 984 of file arm_adi_v5.c.

Referenced by dap_info_cs_component().

◆ dap_instance_commands

const struct command_registration dap_instance_commands[]

Definition at line 2896 of file arm_adi_v5.c.

Referenced by dap_create().

◆ dap_part_nums

const struct dap_part_nums dap_part_nums[]
static

◆ description

const char* description

Definition at line 1010 of file arm_adi_v5.c.

Referenced by class0x9_devarch_description(), decode_dmi(), and mpsse_open().

◆ nvp_config_opts

const struct jim_nvp nvp_config_opts[]
static
Initial value:
= {
{ .name = "-dap", .value = CFG_DAP },
{ .name = "-ap-num", .value = CFG_AP_NUM },
{ .name = "-baseaddr", .value = CFG_BASEADDR },
{ .name = "-ctibase", .value = CFG_CTIBASE },
{ .name = NULL, .value = -1 }
}
@ CFG_AP_NUM
Definition: arm_adi_v5.c:2323
@ CFG_CTIBASE
Definition: arm_adi_v5.c:2325
@ CFG_BASEADDR
Definition: arm_adi_v5.c:2324
@ CFG_DAP
Definition: arm_adi_v5.c:2322
#define NULL
Definition: usb.h:16

Definition at line 2287 of file arm_adi_v5.c.

Referenced by adiv5_jim_spot_configure().

◆ type

enum ap_type type

Definition at line 1010 of file arm_adi_v5.c.

Referenced by ap_type_to_description(), and dap_lookup_cs_component().