OpenOCD
kinetis.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2011 by Mathias Kuester *
5  * kesmtp@freenet.de *
6  * *
7  * Copyright (C) 2011 sleep(5) ltd *
8  * tomas@sleepfive.com *
9  * *
10  * Copyright (C) 2012 by Christopher D. Kilgour *
11  * techie at whiterocker.com *
12  * *
13  * Copyright (C) 2013 Nemui Trinomius *
14  * nemuisan_kawausogasuki@live.jp *
15  * *
16  * Copyright (C) 2015 Tomas Vanek *
17  * vanekt@fbl.cz *
18  ***************************************************************************/
19 
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23 
24 #include "jtag/interface.h"
25 #include "imp.h"
26 #include <helper/binarybuffer.h>
27 #include <helper/time_support.h>
28 #include <target/target_type.h>
29 #include <target/algorithm.h>
30 #include <target/arm_adi_v5.h>
31 #include <target/armv7m.h>
32 #include <target/cortex_m.h>
33 
34 /*
35  * Implementation Notes
36  *
37  * The persistent memories in the Kinetis chip families K10 through
38  * K70 are all manipulated with the Flash Memory Module. Some
39  * variants call this module the FTFE, others call it the FTFL. To
40  * indicate that both are considered here, we use FTFX.
41  *
42  * Within the module, according to the chip variant, the persistent
43  * memory is divided into what Freescale terms Program Flash, FlexNVM,
44  * and FlexRAM. All chip variants have Program Flash. Some chip
45  * variants also have FlexNVM and FlexRAM, which always appear
46  * together.
47  *
48  * A given Kinetis chip may have 1, 2 or 4 blocks of flash. Here we map
49  * each block to a separate bank. Each block size varies by chip and
50  * may be determined by the read-only SIM_FCFG1 register. The sector
51  * size within each bank/block varies by chip, and may be 1, 2 or 4k.
52  * The sector size may be different for flash and FlexNVM.
53  *
54  * The first half of the flash (1 or 2 blocks) is always Program Flash
55  * and always starts at address 0x00000000. The "PFLSH" flag, bit 23
56  * of the read-only SIM_FCFG2 register, determines whether the second
57  * half of the flash is also Program Flash or FlexNVM+FlexRAM. When
58  * PFLSH is set, the second from the first half. When PFLSH is clear,
59  * the second half of flash is FlexNVM and always starts at address
60  * 0x10000000. FlexRAM, which is also present when PFLSH is clear,
61  * always starts at address 0x14000000.
62  *
63  * The Flash Memory Module provides a register set where flash
64  * commands are loaded to perform flash operations like erase and
65  * program. Different commands are available depending on whether
66  * Program Flash or FlexNVM/FlexRAM is being manipulated. Although
67  * the commands used are quite consistent between flash blocks, the
68  * parameters they accept differ according to the flash sector size.
69  *
70  */
71 
72 /* Addresses */
73 #define FCF_ADDRESS 0x00000400
74 #define FCF_FPROT 0x8
75 #define FCF_FSEC 0xc
76 #define FCF_FOPT 0xd
77 #define FCF_FDPROT 0xf
78 #define FCF_SIZE 0x10
79 
80 #define FLEXRAM 0x14000000
81 
82 #define MSCM_OCMDR0 0x40001400
83 #define MSCM_OCMDR1 0x40001404
84 #define FMC_PFB01CR 0x4001f004
85 #define FTFX_FSTAT 0x40020000
86 #define FTFX_FCNFG 0x40020001
87 #define FTFX_FCCOB3 0x40020004
88 #define FTFX_FPROT3 0x40020010
89 #define FTFX_FDPROT 0x40020017
90 #define SIM_BASE 0x40047000
91 #define SIM_BASE_KL28 0x40074000
92 #define SIM_COPC 0x40048100
93  /* SIM_COPC does not exist on devices with changed SIM_BASE */
94 #define WDOG_BASE 0x40052000
95 #define WDOG32_KE1X 0x40052000
96 #define WDOG32_KL28 0x40076000
97 #define SMC_PMCTRL 0x4007E001
98 #define SMC_PMSTAT 0x4007E003
99 #define SMC32_PMCTRL 0x4007E00C
100 #define SMC32_PMSTAT 0x4007E014
101 #define PMC_REGSC 0x4007D002
102 #define MC_PMCTRL 0x4007E003
103 #define MCM_PLACR 0xF000300C
104 
105 /* Offsets */
106 #define SIM_SOPT1_OFFSET 0x0000
107 #define SIM_SDID_OFFSET 0x1024
108 #define SIM_FCFG1_OFFSET 0x104c
109 #define SIM_FCFG2_OFFSET 0x1050
110 
111 #define WDOG_STCTRLH_OFFSET 0
112 #define WDOG32_CS_OFFSET 0
113 
114 /* Values */
115 #define PM_STAT_RUN 0x01
116 #define PM_STAT_VLPR 0x04
117 #define PM_CTRL_RUNM_RUN 0x00
118 
119 /* Commands */
120 #define FTFX_CMD_BLOCKSTAT 0x00
121 #define FTFX_CMD_SECTSTAT 0x01
122 #define FTFX_CMD_LWORDPROG 0x06
123 #define FTFX_CMD_SECTERASE 0x09
124 #define FTFX_CMD_SECTWRITE 0x0b
125 #define FTFX_CMD_MASSERASE 0x44
126 #define FTFX_CMD_PGMPART 0x80
127 #define FTFX_CMD_SETFLEXRAM 0x81
128 
129 /* The older Kinetis K series uses the following SDID layout :
130  * Bit 31-16 : 0
131  * Bit 15-12 : REVID
132  * Bit 11-7 : DIEID
133  * Bit 6-4 : FAMID
134  * Bit 3-0 : PINID
135  *
136  * The newer Kinetis series uses the following SDID layout :
137  * Bit 31-28 : FAMID
138  * Bit 27-24 : SUBFAMID
139  * Bit 23-20 : SERIESID
140  * Bit 19-16 : SRAMSIZE
141  * Bit 15-12 : REVID
142  * Bit 6-4 : Reserved (0)
143  * Bit 3-0 : PINID
144  *
145  * We assume that if bits 31-16 are 0 then it's an older
146  * K-series MCU.
147  */
148 
149 #define KINETIS_SOPT1_RAMSIZE_MASK 0x0000F000
150 #define KINETIS_SOPT1_RAMSIZE_K24FN1M 0x0000B000
151 
152 #define KINETIS_SDID_K_SERIES_MASK 0x0000FFFF
153 
154 #define KINETIS_SDID_DIEID_MASK 0x00000F80
155 
156 #define KINETIS_SDID_DIEID_K22FN128 0x00000680 /* smaller pflash with FTFA */
157 #define KINETIS_SDID_DIEID_K22FN256 0x00000A80
158 #define KINETIS_SDID_DIEID_K22FN512 0x00000E80
159 #define KINETIS_SDID_DIEID_K24FN256 0x00000700
160 
161 #define KINETIS_SDID_DIEID_K24FN1M 0x00000300 /* Detect Errata 7534 */
162 
163 /* We can't rely solely on the FAMID field to determine the MCU
164  * type since some FAMID values identify multiple MCUs with
165  * different flash sector sizes (K20 and K22 for instance).
166  * Therefore we combine it with the DIEID bits which may possibly
167  * break if Freescale bumps the DIEID for a particular MCU. */
168 #define KINETIS_K_SDID_TYPE_MASK 0x00000FF0
169 #define KINETIS_K_SDID_K10_M50 0x00000000
170 #define KINETIS_K_SDID_K10_M72 0x00000080
171 #define KINETIS_K_SDID_K10_M100 0x00000100
172 #define KINETIS_K_SDID_K10_M120 0x00000180
173 #define KINETIS_K_SDID_K11 0x00000220
174 #define KINETIS_K_SDID_K12 0x00000200
175 #define KINETIS_K_SDID_K20_M50 0x00000010
176 #define KINETIS_K_SDID_K20_M72 0x00000090
177 #define KINETIS_K_SDID_K20_M100 0x00000110
178 #define KINETIS_K_SDID_K20_M120 0x00000190
179 #define KINETIS_K_SDID_K21_M50 0x00000230
180 #define KINETIS_K_SDID_K21_M120 0x00000330
181 #define KINETIS_K_SDID_K22_M50 0x00000210
182 #define KINETIS_K_SDID_K22_M120 0x00000310
183 #define KINETIS_K_SDID_K30_M72 0x000000A0
184 #define KINETIS_K_SDID_K30_M100 0x00000120
185 #define KINETIS_K_SDID_K40_M72 0x000000B0
186 #define KINETIS_K_SDID_K40_M100 0x00000130
187 #define KINETIS_K_SDID_K50_M72 0x000000E0
188 #define KINETIS_K_SDID_K51_M72 0x000000F0
189 #define KINETIS_K_SDID_K53 0x00000170
190 #define KINETIS_K_SDID_K60_M100 0x00000140
191 #define KINETIS_K_SDID_K60_M150 0x000001C0
192 #define KINETIS_K_SDID_K70_M150 0x000001D0
193 
194 #define KINETIS_K_REVID_MASK 0x0000F000
195 #define KINETIS_K_REVID_SHIFT 12
196 
197 #define KINETIS_SDID_SERIESID_MASK 0x00F00000
198 #define KINETIS_SDID_SERIESID_K 0x00000000
199 #define KINETIS_SDID_SERIESID_KL 0x00100000
200 #define KINETIS_SDID_SERIESID_KE 0x00200000
201 #define KINETIS_SDID_SERIESID_KW 0x00500000
202 #define KINETIS_SDID_SERIESID_KV 0x00600000
203 
204 #define KINETIS_SDID_SUBFAMID_SHIFT 24
205 #define KINETIS_SDID_SUBFAMID_MASK 0x0F000000
206 #define KINETIS_SDID_SUBFAMID_KX0 0x00000000
207 #define KINETIS_SDID_SUBFAMID_KX1 0x01000000
208 #define KINETIS_SDID_SUBFAMID_KX2 0x02000000
209 #define KINETIS_SDID_SUBFAMID_KX3 0x03000000
210 #define KINETIS_SDID_SUBFAMID_KX4 0x04000000
211 #define KINETIS_SDID_SUBFAMID_KX5 0x05000000
212 #define KINETIS_SDID_SUBFAMID_KX6 0x06000000
213 #define KINETIS_SDID_SUBFAMID_KX7 0x07000000
214 #define KINETIS_SDID_SUBFAMID_KX8 0x08000000
215 
216 #define KINETIS_SDID_FAMILYID_SHIFT 28
217 #define KINETIS_SDID_FAMILYID_MASK 0xF0000000
218 #define KINETIS_SDID_FAMILYID_K0X 0x00000000
219 #define KINETIS_SDID_FAMILYID_K1X 0x10000000
220 #define KINETIS_SDID_FAMILYID_K2X 0x20000000
221 #define KINETIS_SDID_FAMILYID_K3X 0x30000000
222 #define KINETIS_SDID_FAMILYID_K4X 0x40000000
223 #define KINETIS_SDID_FAMILYID_K5X 0x50000000
224 #define KINETIS_SDID_FAMILYID_K6X 0x60000000
225 #define KINETIS_SDID_FAMILYID_K7X 0x70000000
226 #define KINETIS_SDID_FAMILYID_K8X 0x80000000
227 #define KINETIS_SDID_FAMILYID_KL8X 0x90000000
228 
229 /* The field originally named DIEID has new name/meaning on KE1x */
230 #define KINETIS_SDID_PROJECTID_MASK KINETIS_SDID_DIEID_MASK
231 #define KINETIS_SDID_PROJECTID_KE1XF 0x00000080
232 #define KINETIS_SDID_PROJECTID_KE1XZ 0x00000100
233 
234 /* The S32K series uses a different, incompatible SDID layout :
235  * Bit 31-28 : GENERATION
236  * Bit 27-24 : SUBSERIES
237  * Bit 23-20 : DERIVATE
238  * Bit 19-16 : RAMSIZE
239  * Bit 15-12 : REVID
240  * Bit 11-8 : PACKAGE
241  * Bit 7-0 : FEATURES
242  */
243 
244 #define KINETIS_SDID_S32K_SERIES_MASK 0xFF000000 /* GENERATION + SUBSERIES */
245 #define KINETIS_SDID_S32K_SERIES_K11X 0x11000000
246 #define KINETIS_SDID_S32K_SERIES_K14X 0x14000000
247 
248 #define KINETIS_SDID_S32K_DERIVATE_MASK 0x00F00000
249 #define KINETIS_SDID_S32K_DERIVATE_KXX2 0x00200000
250 #define KINETIS_SDID_S32K_DERIVATE_KXX3 0x00300000
251 #define KINETIS_SDID_S32K_DERIVATE_KXX4 0x00400000
252 #define KINETIS_SDID_S32K_DERIVATE_KXX5 0x00500000
253 #define KINETIS_SDID_S32K_DERIVATE_KXX6 0x00600000
254 #define KINETIS_SDID_S32K_DERIVATE_KXX8 0x00800000
255 
258  bool probed;
259  unsigned int bank_number; /* bank number in particular chip */
260  struct flash_bank *bank;
261 
262  uint32_t sector_size;
263  uint32_t protection_size;
264  uint32_t prog_base; /* base address for FTFx operations */
265  /* usually same as bank->base for pflash, differs for FlexNVM */
266  uint32_t protection_block; /* number of first protection block in this bank */
267 
268  enum {
269  FC_AUTO = 0,
274 };
275 
276 #define KINETIS_MAX_BANKS 4u
277 
278 struct kinetis_chip {
279  struct target *target;
280  bool probed;
281 
282  uint32_t sim_sdid;
283  uint32_t sim_fcfg1;
284  uint32_t sim_fcfg2;
287 
290  unsigned int max_flash_prog_size;
291 
292  uint32_t pflash_base;
293  uint32_t pflash_size;
294  uint32_t nvm_base;
295  uint32_t nvm_size; /* whole FlexNVM */
296  uint32_t dflash_size; /* accessible rest of FlexNVM if EEPROM backup uses part of FlexNVM */
297 
298  uint32_t progr_accel_ram;
299  uint32_t sim_base;
300 
301  enum {
305 
306  enum {
309  FS_PROGRAM_PHRASE = 4, /* Unsupported */
310 
313  FS_ECC = 0x100,
315 
316  enum {
318  KINETIS_CACHE_K, /* invalidate using FMC->PFB0CR/PFB01CR */
319  KINETIS_CACHE_L, /* invalidate using MCM->PLACR */
320  KINETIS_CACHE_MSCM, /* devices like KE1xF, invalidate MSCM->OCMDR0 */
321  KINETIS_CACHE_MSCM2, /* devices like S32K, invalidate MSCM->OCMDR0 and MSCM->OCMDR1 */
323 
324  enum {
331 
332  enum {
337 
338  char name[40];
339 
340  unsigned int num_banks;
342 };
343 
344 struct kinetis_type {
345  uint32_t sdid;
346  char *name;
347 };
348 
349 static const struct kinetis_type kinetis_types_old[] = {
350  { KINETIS_K_SDID_K10_M50, "MK10D%s5" },
351  { KINETIS_K_SDID_K10_M72, "MK10D%s7" },
352  { KINETIS_K_SDID_K10_M100, "MK10D%s10" },
353  { KINETIS_K_SDID_K10_M120, "MK10F%s12" },
354  { KINETIS_K_SDID_K11, "MK11D%s5" },
355  { KINETIS_K_SDID_K12, "MK12D%s5" },
356 
357  { KINETIS_K_SDID_K20_M50, "MK20D%s5" },
358  { KINETIS_K_SDID_K20_M72, "MK20D%s7" },
359  { KINETIS_K_SDID_K20_M100, "MK20D%s10" },
360  { KINETIS_K_SDID_K20_M120, "MK20F%s12" },
361  { KINETIS_K_SDID_K21_M50, "MK21D%s5" },
362  { KINETIS_K_SDID_K21_M120, "MK21F%s12" },
363  { KINETIS_K_SDID_K22_M50, "MK22D%s5" },
364  { KINETIS_K_SDID_K22_M120, "MK22F%s12" },
365 
366  { KINETIS_K_SDID_K30_M72, "MK30D%s7" },
367  { KINETIS_K_SDID_K30_M100, "MK30D%s10" },
368 
369  { KINETIS_K_SDID_K40_M72, "MK40D%s7" },
370  { KINETIS_K_SDID_K40_M100, "MK40D%s10" },
371 
372  { KINETIS_K_SDID_K50_M72, "MK50D%s7" },
373  { KINETIS_K_SDID_K51_M72, "MK51D%s7" },
374  { KINETIS_K_SDID_K53, "MK53D%s10" },
375 
376  { KINETIS_K_SDID_K60_M100, "MK60D%s10" },
377  { KINETIS_K_SDID_K60_M150, "MK60F%s15" },
378 
379  { KINETIS_K_SDID_K70_M150, "MK70F%s15" },
380 };
381 
382 
383 #define MDM_AP 1
384 
385 #define MDM_REG_STAT 0x00
386 #define MDM_REG_CTRL 0x04
387 #define MDM_REG_ID 0xfc
388 
389 #define MDM_STAT_FMEACK (1<<0)
390 #define MDM_STAT_FREADY (1<<1)
391 #define MDM_STAT_SYSSEC (1<<2)
392 #define MDM_STAT_SYSRES (1<<3)
393 #define MDM_STAT_FMEEN (1<<5)
394 #define MDM_STAT_BACKDOOREN (1<<6)
395 #define MDM_STAT_LPEN (1<<7)
396 #define MDM_STAT_VLPEN (1<<8)
397 #define MDM_STAT_LLSMODEXIT (1<<9)
398 #define MDM_STAT_VLLSXMODEXIT (1<<10)
399 #define MDM_STAT_CORE_HALTED (1<<16)
400 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
401 #define MDM_STAT_CORESLEEPING (1<<18)
402 
403 #define MDM_CTRL_FMEIP (1<<0)
404 #define MDM_CTRL_DBG_DIS (1<<1)
405 #define MDM_CTRL_DBG_REQ (1<<2)
406 #define MDM_CTRL_SYS_RES_REQ (1<<3)
407 #define MDM_CTRL_CORE_HOLD_RES (1<<4)
408 #define MDM_CTRL_VLLSX_DBG_REQ (1<<5)
409 #define MDM_CTRL_VLLSX_DBG_ACK (1<<6)
410 #define MDM_CTRL_VLLSX_STAT_ACK (1<<7)
411 
412 #define MDM_ACCESS_TIMEOUT 500 /* msec */
413 
414 
415 static bool allow_fcf_writes;
416 static uint8_t fcf_fopt = 0xff;
417 static bool create_banks;
418 
419 
420 const struct flash_driver kinetis_flash;
421 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
422  uint32_t offset, uint32_t count);
423 static int kinetis_probe_chip(struct kinetis_chip *k_chip);
424 static int kinetis_probe_chip_s32k(struct kinetis_chip *k_chip);
425 static int kinetis_auto_probe(struct flash_bank *bank);
426 
427 
428 static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned int reg, uint32_t value)
429 {
430  LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
431 
432  struct adiv5_ap *ap = dap_get_ap(dap, MDM_AP);
433  if (!ap) {
434  LOG_DEBUG("MDM: failed to get AP");
435  return ERROR_FAIL;
436  }
437 
438  int retval = dap_queue_ap_write(ap, reg, value);
439  if (retval != ERROR_OK) {
440  LOG_DEBUG("MDM: failed to queue a write request");
441  dap_put_ap(ap);
442  return retval;
443  }
444 
445  retval = dap_run(dap);
446  dap_put_ap(ap);
447  if (retval != ERROR_OK) {
448  LOG_DEBUG("MDM: dap_run failed");
449  return retval;
450  }
451 
452 
453  return ERROR_OK;
454 }
455 
456 static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned int reg, uint32_t *result)
457 {
458  struct adiv5_ap *ap = dap_get_ap(dap, MDM_AP);
459  if (!ap) {
460  LOG_DEBUG("MDM: failed to get AP");
461  return ERROR_FAIL;
462  }
463 
464  int retval = dap_queue_ap_read(ap, reg, result);
465  if (retval != ERROR_OK) {
466  LOG_DEBUG("MDM: failed to queue a read request");
467  dap_put_ap(ap);
468  return retval;
469  }
470 
471  retval = dap_run(dap);
472  dap_put_ap(ap);
473  if (retval != ERROR_OK) {
474  LOG_DEBUG("MDM: dap_run failed");
475  return retval;
476  }
477 
478  LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32, reg, *result);
479  return ERROR_OK;
480 }
481 
482 static int kinetis_mdm_poll_register(struct adiv5_dap *dap, unsigned int reg,
483  uint32_t mask, uint32_t value, uint32_t timeout_ms)
484 {
485  uint32_t val;
486  int retval;
487  int64_t ms_timeout = timeval_ms() + timeout_ms;
488 
489  do {
490  retval = kinetis_mdm_read_register(dap, reg, &val);
491  if (retval != ERROR_OK || (val & mask) == value)
492  return retval;
493 
494  alive_sleep(1);
495  } while (timeval_ms() < ms_timeout);
496 
497  LOG_DEBUG("MDM: polling timed out");
498  return ERROR_FAIL;
499 }
500 
501 /*
502  * This command can be used to break a watchdog reset loop when
503  * connecting to an unsecured target. Unlike other commands, halt will
504  * automatically retry as it does not know how far into the boot process
505  * it is when the command is called.
506  */
507 COMMAND_HANDLER(kinetis_mdm_halt)
508 {
510  struct cortex_m_common *cortex_m = target_to_cm(target);
511  struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
512  int retval;
513  int tries = 0;
514  uint32_t stat;
515  int64_t ms_timeout = timeval_ms() + MDM_ACCESS_TIMEOUT;
516 
517  if (!dap) {
518  LOG_ERROR("Cannot perform halt with a high-level adapter");
519  return ERROR_FAIL;
520  }
521 
522  while (true) {
523  tries++;
524 
526 
527  alive_sleep(1);
528 
529  retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
530  if (retval != ERROR_OK) {
531  LOG_DEBUG("MDM: failed to read MDM_REG_STAT");
532  continue;
533  }
534 
535  /* Repeat setting MDM_CTRL_CORE_HOLD_RES until system is out of
536  * reset with flash ready and without security
537  */
540  break;
541 
542  if (timeval_ms() >= ms_timeout) {
543  LOG_ERROR("MDM: halt timed out");
544  return ERROR_FAIL;
545  }
546  }
547 
548  LOG_DEBUG("MDM: halt succeeded after %d attempts.", tries);
549 
551  /* enable polling in case kinetis_check_flash_security_status disabled it */
552  jtag_poll_set_enabled(true);
553 
554  alive_sleep(100);
555 
556  target->reset_halt = true;
558 
559  retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
560  if (retval != ERROR_OK) {
561  LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
562  return retval;
563  }
564 
566 
567  return ERROR_OK;
568 }
569 
570 COMMAND_HANDLER(kinetis_mdm_reset)
571 {
573  struct cortex_m_common *cortex_m = target_to_cm(target);
574  struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
575  int retval;
576 
577  if (!dap) {
578  LOG_ERROR("Cannot perform reset with a high-level adapter");
579  return ERROR_FAIL;
580  }
581 
583  if (retval != ERROR_OK) {
584  LOG_ERROR("MDM: failed to write MDM_REG_CTRL");
585  return retval;
586  }
587 
589  if (retval != ERROR_OK) {
590  LOG_ERROR("MDM: failed to assert reset");
591  return retval;
592  }
593 
594  retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
595  if (retval != ERROR_OK) {
596  LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
597  return retval;
598  }
599 
600  return ERROR_OK;
601 }
602 
603 /*
604  * This function implements the procedure to mass erase the flash via
605  * SWD/JTAG on Kinetis K and L series of devices as it is described in
606  * AN4835 "Production Flash Programming Best Practices for Kinetis K-
607  * and L-series MCUs" Section 4.2.1. To prevent a watchdog reset loop,
608  * the core remains halted after this function completes as suggested
609  * by the application note.
610  */
611 COMMAND_HANDLER(kinetis_mdm_mass_erase)
612 {
614  struct cortex_m_common *cortex_m = target_to_cm(target);
615  struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
616 
617  if (!dap) {
618  LOG_ERROR("Cannot perform mass erase with a high-level adapter");
619  return ERROR_FAIL;
620  }
621 
622  int retval;
623 
624  /*
625  * ... Power on the processor, or if power has already been
626  * applied, assert the RESET pin to reset the processor. For
627  * devices that do not have a RESET pin, write the System
628  * Reset Request bit in the MDM-AP control register after
629  * establishing communication...
630  */
631 
632  /* assert SRST if configured */
633  bool has_srst = jtag_get_reset_config() & RESET_HAS_SRST;
634  if (has_srst)
636 
638  if (retval != ERROR_OK && !has_srst) {
639  LOG_ERROR("MDM: failed to assert reset");
640  goto deassert_reset_and_exit;
641  }
642 
643  /*
644  * ... Read the MDM-AP status register repeatedly and wait for
645  * stable conditions suitable for mass erase:
646  * - mass erase is enabled
647  * - flash is ready
648  * - reset is finished
649  *
650  * Mass erase is started as soon as all conditions are met in 32
651  * subsequent status reads.
652  *
653  * In case of not stable conditions (RESET/WDOG loop in secured device)
654  * the user is asked for manual pressing of RESET button
655  * as a last resort.
656  */
657  int cnt_mass_erase_disabled = 0;
658  int cnt_ready = 0;
659  int64_t ms_start = timeval_ms();
660  bool man_reset_requested = false;
661 
662  do {
663  uint32_t stat = 0;
664  int64_t ms_elapsed = timeval_ms() - ms_start;
665 
666  if (!man_reset_requested && ms_elapsed > 100) {
667  LOG_INFO("MDM: Press RESET button now if possible.");
668  man_reset_requested = true;
669  }
670 
671  if (ms_elapsed > 3000) {
672  LOG_ERROR("MDM: waiting for mass erase conditions timed out.");
673  LOG_INFO("Mass erase of a secured MCU is not possible without hardware reset.");
674  LOG_INFO("Connect SRST, use 'reset_config srst_only' and retry.");
675  goto deassert_reset_and_exit;
676  }
677  retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
678  if (retval != ERROR_OK) {
679  cnt_ready = 0;
680  continue;
681  }
682 
683  if (!(stat & MDM_STAT_FMEEN)) {
684  cnt_ready = 0;
685  cnt_mass_erase_disabled++;
686  if (cnt_mass_erase_disabled > 10) {
687  LOG_ERROR("MDM: mass erase is disabled");
688  goto deassert_reset_and_exit;
689  }
690  continue;
691  }
692 
693  if ((stat & (MDM_STAT_FREADY | MDM_STAT_SYSRES)) == MDM_STAT_FREADY)
694  cnt_ready++;
695  else
696  cnt_ready = 0;
697 
698  } while (cnt_ready < 32);
699 
700  /*
701  * ... Write the MDM-AP control register to set the Flash Mass
702  * Erase in Progress bit. This will start the mass erase
703  * process...
704  */
706  if (retval != ERROR_OK) {
707  LOG_ERROR("MDM: failed to start mass erase");
708  goto deassert_reset_and_exit;
709  }
710 
711  /*
712  * ... Read the MDM-AP control register until the Flash Mass
713  * Erase in Progress bit clears...
714  * Data sheed defines erase time <3.6 sec/512kB flash block.
715  * The biggest device has 4 pflash blocks => timeout 16 sec.
716  */
717  retval = kinetis_mdm_poll_register(dap, MDM_REG_CTRL, MDM_CTRL_FMEIP, 0, 16000);
718  if (retval != ERROR_OK) {
719  LOG_ERROR("MDM: mass erase timeout");
720  goto deassert_reset_and_exit;
721  }
722 
724  /* enable polling in case kinetis_check_flash_security_status disabled it */
725  jtag_poll_set_enabled(true);
726 
727  alive_sleep(100);
728 
729  target->reset_halt = true;
731 
732  /*
733  * ... Negate the RESET signal or clear the System Reset Request
734  * bit in the MDM-AP control register.
735  */
736  retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
737  if (retval != ERROR_OK)
738  LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
739 
741 
742  return retval;
743 
744 deassert_reset_and_exit:
746  if (has_srst)
748  return retval;
749 }
750 
751 static const uint32_t kinetis_known_mdm_ids[] = {
752  0x001C0000, /* Kinetis-K Series */
753  0x001C0020, /* Kinetis-L/M/V/E Series */
754  0x001C0030, /* Kinetis with a Cortex-M7, in time of writing KV58 */
755 };
756 
757 /*
758  * This function implements the procedure to connect to
759  * SWD/JTAG on Kinetis K and L series of devices as it is described in
760  * AN4835 "Production Flash Programming Best Practices for Kinetis K-
761  * and L-series MCUs" Section 4.1.1
762  */
763 COMMAND_HANDLER(kinetis_check_flash_security_status)
764 {
766  struct cortex_m_common *cortex_m = target_to_cm(target);
767  struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
768 
769  if (!dap) {
770  LOG_WARNING("Cannot check flash security status with a high-level adapter");
771  return ERROR_OK;
772  }
773 
774  if (!dap->ops)
775  return ERROR_OK; /* too early to check, in JTAG mode ops may not be initialised */
776 
777  uint32_t val;
778  int retval;
779 
780  /*
781  * ... The MDM-AP ID register can be read to verify that the
782  * connection is working correctly...
783  */
784  retval = kinetis_mdm_read_register(dap, MDM_REG_ID, &val);
785  if (retval != ERROR_OK) {
786  LOG_ERROR("MDM: failed to read ID register");
787  return ERROR_OK;
788  }
789 
790  if (val == 0)
791  return ERROR_OK; /* dap not yet initialised */
792 
793  bool found = false;
794  for (size_t i = 0; i < ARRAY_SIZE(kinetis_known_mdm_ids); i++) {
795  if (val == kinetis_known_mdm_ids[i]) {
796  found = true;
797  break;
798  }
799  }
800 
801  if (!found)
802  LOG_WARNING("MDM: unknown ID %08" PRIX32, val);
803 
804  /*
805  * ... Read the System Security bit to determine if security is enabled.
806  * If System Security = 0, then proceed. If System Security = 1, then
807  * communication with the internals of the processor, including the
808  * flash, will not be possible without issuing a mass erase command or
809  * unsecuring the part through other means (backdoor key unlock)...
810  */
811  retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &val);
812  if (retval != ERROR_OK) {
813  LOG_ERROR("MDM: failed to read MDM_REG_STAT");
814  return ERROR_OK;
815  }
816 
817  /*
818  * System Security bit is also active for short time during reset.
819  * If a MCU has blank flash and runs in RESET/WDOG loop,
820  * System Security bit is active most of time!
821  * We should observe Flash Ready bit and read status several times
822  * to avoid false detection of secured MCU
823  */
824  int secured_score = 0, flash_not_ready_score = 0;
825 
826  if ((val & (MDM_STAT_SYSSEC | MDM_STAT_FREADY)) != MDM_STAT_FREADY) {
827  uint32_t stats[32];
828  struct adiv5_ap *ap = dap_get_ap(dap, MDM_AP);
829  if (!ap) {
830  LOG_ERROR("MDM: failed to get AP");
831  return ERROR_OK;
832  }
833 
834  for (unsigned int i = 0; i < 32; i++) {
835  stats[i] = MDM_STAT_FREADY;
836  dap_queue_ap_read(ap, MDM_REG_STAT, &stats[i]);
837  }
838  retval = dap_run(dap);
839  dap_put_ap(ap);
840  if (retval != ERROR_OK) {
841  LOG_DEBUG("MDM: dap_run failed when validating secured state");
842  return ERROR_OK;
843  }
844  for (unsigned int i = 0; i < 32; i++) {
845  if (stats[i] & MDM_STAT_SYSSEC)
846  secured_score++;
847  if (!(stats[i] & MDM_STAT_FREADY))
848  flash_not_ready_score++;
849  }
850  }
851 
852  if (flash_not_ready_score <= 8 && secured_score > 24) {
853  jtag_poll_set_enabled(false);
854 
855  LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
856  LOG_WARNING("**** ****");
857  LOG_WARNING("**** Your Kinetis MCU is in secured state, which means that, ****");
858  LOG_WARNING("**** with exception for very basic communication, JTAG/SWD ****");
859  LOG_WARNING("**** interface will NOT work. In order to restore its ****");
860  LOG_WARNING("**** functionality please issue 'kinetis mdm mass_erase' ****");
861  LOG_WARNING("**** command, power cycle the MCU and restart OpenOCD. ****");
862  LOG_WARNING("**** ****");
863  LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
864 
865  } else if (flash_not_ready_score > 24) {
866  jtag_poll_set_enabled(false);
867  LOG_WARNING("**** Your Kinetis MCU is probably locked-up in RESET/WDOG loop. ****");
868  LOG_WARNING("**** Common reason is a blank flash (at least a reset vector). ****");
869  LOG_WARNING("**** Issue 'kinetis mdm halt' command or if SRST is connected ****");
870  LOG_WARNING("**** and configured, use 'reset halt' ****");
871  LOG_WARNING("**** If MCU cannot be halted, it is likely secured and running ****");
872  LOG_WARNING("**** in RESET/WDOG loop. Issue 'kinetis mdm mass_erase' ****");
873 
874  } else {
875  LOG_INFO("MDM: Chip is unsecured. Continuing.");
876  jtag_poll_set_enabled(true);
877  }
878 
879  return ERROR_OK;
880 }
881 
882 
884 {
885  struct flash_bank *bank_iter;
886  struct kinetis_flash_bank *k_bank;
887 
888  /* iterate over all kinetis banks */
889  for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
890  if (bank_iter->driver != &kinetis_flash
891  || bank_iter->target != target)
892  continue;
893 
894  k_bank = bank_iter->driver_priv;
895  if (!k_bank)
896  continue;
897 
898  if (k_bank->k_chip)
899  return k_bank->k_chip;
900  }
901  return NULL;
902 }
903 
904 static int kinetis_chip_options(struct kinetis_chip *k_chip, int argc, const char *argv[])
905 {
906  for (int i = 0; i < argc; i++) {
907  if (strcmp(argv[i], "-sim-base") == 0) {
908  if (i + 1 < argc)
909  k_chip->sim_base = strtoul(argv[++i], NULL, 0);
910  } else if (strcmp(argv[i], "-s32k") == 0) {
911  k_chip->chip_type = CT_S32K;
912  } else
913  LOG_ERROR("Unsupported flash bank option %s", argv[i]);
914  }
915  return ERROR_OK;
916 }
917 
918 FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
919 {
920  struct target *target = bank->target;
921  struct kinetis_chip *k_chip;
922  struct kinetis_flash_bank *k_bank;
923  int retval;
924 
925  if (CMD_ARGC < 6)
927 
928  LOG_INFO("add flash_bank kinetis %s", bank->name);
929 
931 
932  if (!k_chip) {
933  k_chip = calloc(1, sizeof(struct kinetis_chip));
934  if (!k_chip) {
935  LOG_ERROR("No memory");
936  return ERROR_FAIL;
937  }
938 
939  k_chip->target = target;
940 
941  /* only the first defined bank can define chip options */
942  retval = kinetis_chip_options(k_chip, CMD_ARGC - 6, CMD_ARGV + 6);
943  if (retval != ERROR_OK)
944  return retval;
945  }
946 
948  LOG_ERROR("Only %u Kinetis flash banks are supported", KINETIS_MAX_BANKS);
949  return ERROR_FAIL;
950  }
951 
952  bank->driver_priv = k_bank = &(k_chip->banks[k_chip->num_banks]);
953  k_bank->k_chip = k_chip;
954  k_bank->bank_number = k_chip->num_banks;
955  k_bank->bank = bank;
956  k_chip->num_banks++;
957 
958  return ERROR_OK;
959 }
960 
961 
963 {
964  struct kinetis_flash_bank *k_bank = bank->driver_priv;
965  if (!k_bank)
966  return;
967 
968  struct kinetis_chip *k_chip = k_bank->k_chip;
969  if (!k_chip)
970  return;
971 
972  k_chip->num_banks--;
973  if (k_chip->num_banks == 0)
974  free(k_chip);
975 }
976 
977 
978 static int kinetis_create_missing_banks(struct kinetis_chip *k_chip)
979 {
980  unsigned int num_blocks;
981  struct kinetis_flash_bank *k_bank;
982  struct flash_bank *bank;
983  char base_name[69], name[87], num[11];
984  char *class, *p;
985 
986  num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
987  if (num_blocks > KINETIS_MAX_BANKS) {
988  LOG_ERROR("Only %u Kinetis flash banks are supported", KINETIS_MAX_BANKS);
989  return ERROR_FAIL;
990  }
991 
992  bank = k_chip->banks[0].bank;
993  if (bank && bank->name) {
994  strncpy(base_name, bank->name, sizeof(base_name) - 1);
995  base_name[sizeof(base_name) - 1] = '\0';
996  p = strstr(base_name, ".pflash");
997  if (p) {
998  *p = '\0';
999  if (k_chip->num_pflash_blocks > 1) {
1000  /* rename first bank if numbering is needed */
1001  snprintf(name, sizeof(name), "%s.pflash0", base_name);
1002  free(bank->name);
1003  bank->name = strdup(name);
1004  }
1005  }
1006  } else {
1007  strncpy(base_name, target_name(k_chip->target), sizeof(base_name) - 1);
1008  base_name[sizeof(base_name) - 1] = '\0';
1009  p = strstr(base_name, ".cpu");
1010  if (p)
1011  *p = '\0';
1012  }
1013 
1014  for (unsigned int bank_idx = 1; bank_idx < num_blocks; bank_idx++) {
1015  k_bank = &(k_chip->banks[bank_idx]);
1016  bank = k_bank->bank;
1017 
1018  if (bank)
1019  continue;
1020 
1021  num[0] = '\0';
1022 
1023  if (bank_idx < k_chip->num_pflash_blocks) {
1024  class = "pflash";
1025  if (k_chip->num_pflash_blocks > 1)
1026  snprintf(num, sizeof(num), "%u", bank_idx);
1027  } else {
1028  class = "flexnvm";
1029  if (k_chip->num_nvm_blocks > 1)
1030  snprintf(num, sizeof(num), "%u",
1031  bank_idx - k_chip->num_pflash_blocks);
1032  }
1033 
1034  bank = calloc(1, sizeof(struct flash_bank));
1035  if (!bank)
1036  return ERROR_FAIL;
1037 
1038  bank->target = k_chip->target;
1039  bank->driver = &kinetis_flash;
1040  bank->default_padded_value = bank->erased_value = 0xff;
1041  bank->minimal_write_gap = FLASH_WRITE_GAP_SECTOR;
1042 
1043  snprintf(name, sizeof(name), "%s.%s%s",
1044  base_name, class, num);
1045  bank->name = strdup(name);
1046 
1047  bank->driver_priv = k_bank = &(k_chip->banks[k_chip->num_banks]);
1048  k_bank->k_chip = k_chip;
1049  k_bank->bank_number = bank_idx;
1050  k_bank->bank = bank;
1051  if (k_chip->num_banks <= bank_idx)
1052  k_chip->num_banks = bank_idx + 1;
1053 
1055  }
1056  return ERROR_OK;
1057 }
1058 
1059 
1060 static int kinetis_disable_wdog_algo(struct target *target, size_t code_size, const uint8_t *code, uint32_t wdog_base)
1061 {
1062  struct working_area *wdog_algorithm;
1063  struct armv7m_algorithm armv7m_info;
1064  struct reg_param reg_params[1];
1065  int retval;
1066 
1067  if (target->state != TARGET_HALTED) {
1068  LOG_ERROR("Target not halted");
1069  return ERROR_TARGET_NOT_HALTED;
1070  }
1071 
1072  retval = target_alloc_working_area(target, code_size, &wdog_algorithm);
1073  if (retval != ERROR_OK)
1074  return retval;
1075 
1076  retval = target_write_buffer(target, wdog_algorithm->address,
1077  code_size, code);
1078  if (retval == ERROR_OK) {
1079  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1080  armv7m_info.core_mode = ARM_MODE_THREAD;
1081 
1082  init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1083  buf_set_u32(reg_params[0].value, 0, 32, wdog_base);
1084 
1085  retval = target_run_algorithm(target, 0, NULL, 1, reg_params,
1086  wdog_algorithm->address,
1087  wdog_algorithm->address + code_size - 2,
1088  500, &armv7m_info);
1089 
1090  destroy_reg_param(&reg_params[0]);
1091 
1092  if (retval != ERROR_OK)
1093  LOG_ERROR("Error executing Kinetis WDOG unlock algorithm");
1094  }
1095 
1096  target_free_working_area(target, wdog_algorithm);
1097 
1098  return retval;
1099 }
1100 
1101 /* Disable the watchdog on Kinetis devices
1102  * Standard Kx WDOG peripheral checks timing and therefore requires to run algo.
1103  */
1105 {
1106  const uint32_t wdog_base = WDOG_BASE;
1107  uint16_t wdog;
1108  int retval;
1109 
1110  static const uint8_t kinetis_unlock_wdog_code[] = {
1111 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog.inc"
1112  };
1113 
1114  retval = target_read_u16(target, wdog_base + WDOG_STCTRLH_OFFSET, &wdog);
1115  if (retval != ERROR_OK)
1116  return retval;
1117 
1118  if ((wdog & 0x1) == 0) {
1119  /* watchdog already disabled */
1120  return ERROR_OK;
1121  }
1122  LOG_INFO("Disabling Kinetis watchdog (initial WDOG_STCTRLH = 0x%04" PRIx16 ")", wdog);
1123 
1124  retval = kinetis_disable_wdog_algo(target, sizeof(kinetis_unlock_wdog_code), kinetis_unlock_wdog_code, wdog_base);
1125  if (retval != ERROR_OK)
1126  return retval;
1127 
1128  retval = target_read_u16(target, wdog_base + WDOG_STCTRLH_OFFSET, &wdog);
1129  if (retval != ERROR_OK)
1130  return retval;
1131 
1132  LOG_INFO("WDOG_STCTRLH = 0x%04" PRIx16, wdog);
1133  return (wdog & 0x1) ? ERROR_FAIL : ERROR_OK;
1134 }
1135 
1136 static int kinetis_disable_wdog32(struct target *target, uint32_t wdog_base)
1137 {
1138  uint32_t wdog_cs;
1139  int retval;
1140 
1141  static const uint8_t kinetis_unlock_wdog_code[] = {
1142 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog32.inc"
1143  };
1144 
1145  retval = target_read_u32(target, wdog_base + WDOG32_CS_OFFSET, &wdog_cs);
1146  if (retval != ERROR_OK)
1147  return retval;
1148 
1149  if ((wdog_cs & 0x80) == 0)
1150  return ERROR_OK; /* watchdog already disabled */
1151 
1152  LOG_INFO("Disabling Kinetis watchdog (initial WDOG_CS 0x%08" PRIx32 ")", wdog_cs);
1153 
1154  retval = kinetis_disable_wdog_algo(target, sizeof(kinetis_unlock_wdog_code), kinetis_unlock_wdog_code, wdog_base);
1155  if (retval != ERROR_OK)
1156  return retval;
1157 
1158  retval = target_read_u32(target, wdog_base + WDOG32_CS_OFFSET, &wdog_cs);
1159  if (retval != ERROR_OK)
1160  return retval;
1161 
1162  if ((wdog_cs & 0x80) == 0)
1163  return ERROR_OK; /* watchdog disabled successfully */
1164 
1165  LOG_ERROR("Cannot disable Kinetis watchdog (WDOG_CS 0x%08" PRIx32 "), issue 'reset init'", wdog_cs);
1166  return ERROR_FAIL;
1167 }
1168 
1169 static int kinetis_disable_wdog(struct kinetis_chip *k_chip)
1170 {
1171  struct target *target = k_chip->target;
1172  uint8_t sim_copc;
1173  int retval;
1174 
1175  if (!k_chip->probed) {
1176  switch (k_chip->chip_type) {
1177  case CT_S32K:
1178  retval = kinetis_probe_chip_s32k(k_chip);
1179  break;
1180  default:
1181  retval = kinetis_probe_chip(k_chip);
1182  }
1183  if (retval != ERROR_OK)
1184  return retval;
1185  }
1186 
1187  switch (k_chip->watchdog_type) {
1188  case KINETIS_WDOG_K:
1190 
1191  case KINETIS_WDOG_COP:
1192  retval = target_read_u8(target, SIM_COPC, &sim_copc);
1193  if (retval != ERROR_OK)
1194  return retval;
1195 
1196  if ((sim_copc & 0xc) == 0)
1197  return ERROR_OK; /* watchdog already disabled */
1198 
1199  LOG_INFO("Disabling Kinetis watchdog (initial SIM_COPC 0x%02" PRIx8 ")", sim_copc);
1200  retval = target_write_u8(target, SIM_COPC, sim_copc & ~0xc);
1201  if (retval != ERROR_OK)
1202  return retval;
1203 
1204  retval = target_read_u8(target, SIM_COPC, &sim_copc);
1205  if (retval != ERROR_OK)
1206  return retval;
1207 
1208  if ((sim_copc & 0xc) == 0)
1209  return ERROR_OK; /* watchdog disabled successfully */
1210 
1211  LOG_ERROR("Cannot disable Kinetis watchdog (SIM_COPC 0x%02" PRIx8 "), issue 'reset init'", sim_copc);
1212  return ERROR_FAIL;
1213 
1214  case KINETIS_WDOG32_KE1X:
1216 
1217  case KINETIS_WDOG32_KL28:
1219 
1220  default:
1221  return ERROR_OK;
1222  }
1223 }
1224 
1225 COMMAND_HANDLER(kinetis_disable_wdog_handler)
1226 {
1227  int result;
1229  struct kinetis_chip *k_chip = kinetis_get_chip(target);
1230 
1231  if (!k_chip)
1232  return ERROR_FAIL;
1233 
1234  if (CMD_ARGC > 0)
1236 
1237  result = kinetis_disable_wdog(k_chip);
1238  return result;
1239 }
1240 
1241 
1242 static int kinetis_ftfx_decode_error(uint8_t fstat)
1243 {
1244  if (fstat & 0x20) {
1245  LOG_ERROR("Flash operation failed, illegal command");
1247 
1248  } else if (fstat & 0x10)
1249  LOG_ERROR("Flash operation failed, protection violated");
1250 
1251  else if (fstat & 0x40)
1252  LOG_ERROR("Flash operation failed, read collision");
1253 
1254  else if (fstat & 0x80)
1255  return ERROR_OK;
1256 
1257  else
1258  LOG_ERROR("Flash operation timed out");
1259 
1261 }
1262 
1264 {
1265  /* reset error flags */
1266  return target_write_u8(target, FTFX_FSTAT, 0x70);
1267 }
1268 
1269 
1271 {
1272  int result;
1273  uint8_t fstat;
1274 
1275  /* wait until busy */
1276  for (unsigned int i = 0; i < 50; i++) {
1277  result = target_read_u8(target, FTFX_FSTAT, &fstat);
1278  if (result != ERROR_OK)
1279  return result;
1280 
1281  if (fstat & 0x80)
1282  break;
1283  }
1284 
1285  if ((fstat & 0x80) == 0) {
1286  LOG_ERROR("Flash controller is busy");
1288  }
1289  if (fstat != 0x80) {
1290  /* reset error flags */
1291  result = kinetis_ftfx_clear_error(target);
1292  }
1293  return result;
1294 }
1295 
1296 /* Kinetis Program-LongWord Microcodes */
1297 static const uint8_t kinetis_flash_write_code[] = {
1298 #include "../../../contrib/loaders/flash/kinetis/kinetis_flash.inc"
1299 };
1300 
1301 /* Program LongWord Block Write */
1302 static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
1303  uint32_t offset, uint32_t wcount)
1304 {
1305  struct target *target = bank->target;
1306  uint32_t buffer_size;
1307  struct working_area *write_algorithm;
1308  struct working_area *source;
1309  struct kinetis_flash_bank *k_bank = bank->driver_priv;
1310  uint32_t address = k_bank->prog_base + offset;
1311  uint32_t end_address;
1312  struct reg_param reg_params[5];
1313  struct armv7m_algorithm armv7m_info;
1314  int retval;
1315  uint8_t fstat;
1316 
1317  /* allocate working area with flash programming code */
1319  &write_algorithm) != ERROR_OK) {
1320  LOG_WARNING("no working area available, can't do block memory writes");
1322  }
1323 
1324  retval = target_write_buffer(target, write_algorithm->address,
1326  if (retval != ERROR_OK)
1327  return retval;
1328 
1329  /* memory buffer, size *must* be multiple of word */
1330  buffer_size = target_get_working_area_avail(target) & ~(sizeof(uint32_t) - 1);
1331  if (buffer_size < 256) {
1332  LOG_WARNING("large enough working area not available, can't do block memory writes");
1334  } else if (buffer_size > 16384) {
1335  /* probably won't benefit from more than 16k ... */
1336  buffer_size = 16384;
1337  }
1338 
1339  if (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
1340  LOG_ERROR("allocating working area failed");
1342  }
1343 
1344  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1345  armv7m_info.core_mode = ARM_MODE_THREAD;
1346 
1347  init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* address */
1348  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* word count */
1349  init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1350  init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1351  init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1352 
1353  buf_set_u32(reg_params[0].value, 0, 32, address);
1354  buf_set_u32(reg_params[1].value, 0, 32, wcount);
1355  buf_set_u32(reg_params[2].value, 0, 32, source->address);
1356  buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
1357  buf_set_u32(reg_params[4].value, 0, 32, FTFX_FSTAT);
1358 
1359  retval = target_run_flash_async_algorithm(target, buffer, wcount, 4,
1360  0, NULL,
1361  5, reg_params,
1362  source->address, source->size,
1363  write_algorithm->address, 0,
1364  &armv7m_info);
1365 
1366  if (retval == ERROR_FLASH_OPERATION_FAILED) {
1367  end_address = buf_get_u32(reg_params[0].value, 0, 32);
1368 
1369  LOG_ERROR("Error writing flash at %08" PRIx32, end_address);
1370 
1371  retval = target_read_u8(target, FTFX_FSTAT, &fstat);
1372  if (retval == ERROR_OK) {
1373  retval = kinetis_ftfx_decode_error(fstat);
1374 
1375  /* reset error flags */
1377  }
1378  } else if (retval != ERROR_OK)
1379  LOG_ERROR("Error executing kinetis Flash programming algorithm");
1380 
1382  target_free_working_area(target, write_algorithm);
1383 
1384  destroy_reg_param(&reg_params[0]);
1385  destroy_reg_param(&reg_params[1]);
1386  destroy_reg_param(&reg_params[2]);
1387  destroy_reg_param(&reg_params[3]);
1388  destroy_reg_param(&reg_params[4]);
1389 
1390  return retval;
1391 }
1392 
1393 static int kinetis_protect(struct flash_bank *bank, int set, unsigned int first,
1394  unsigned int last)
1395 {
1396  if (allow_fcf_writes) {
1397  LOG_ERROR("Protection setting is possible with 'kinetis fcf_source protection' only!");
1398  return ERROR_FAIL;
1399  }
1400 
1401  if (!bank->prot_blocks || bank->num_prot_blocks == 0) {
1402  LOG_ERROR("No protection possible for current bank!");
1403  return ERROR_FLASH_BANK_INVALID;
1404  }
1405 
1406  for (unsigned int i = first; i < bank->num_prot_blocks && i <= last; i++)
1407  bank->prot_blocks[i].is_protected = set;
1408 
1409  LOG_INFO("Protection bits will be written at the next FCF sector erase or write.");
1410  LOG_INFO("Do not issue 'flash info' command until protection is written,");
1411  LOG_INFO("doing so would re-read protection status from MCU.");
1412 
1413  return ERROR_OK;
1414 }
1415 
1417 {
1418  struct kinetis_flash_bank *k_bank = bank->driver_priv;
1419  int result;
1420  int b;
1421  uint32_t fprot;
1422 
1423  if (k_bank->flash_class == FC_PFLASH) {
1424 
1425  /* read protection register */
1426  result = target_read_u32(bank->target, FTFX_FPROT3, &fprot);
1427  if (result != ERROR_OK)
1428  return result;
1429 
1430  /* Every bit protects 1/32 of the full flash (not necessarily just this bank) */
1431 
1432  } else if (k_bank->flash_class == FC_FLEX_NVM) {
1433  uint8_t fdprot;
1434 
1435  /* read protection register */
1436  result = target_read_u8(bank->target, FTFX_FDPROT, &fdprot);
1437  if (result != ERROR_OK)
1438  return result;
1439 
1440  fprot = fdprot;
1441 
1442  } else {
1443  LOG_ERROR("Protection checks for FlexRAM not supported");
1444  return ERROR_FLASH_BANK_INVALID;
1445  }
1446 
1447  b = k_bank->protection_block;
1448  for (unsigned int i = 0; i < bank->num_prot_blocks; i++) {
1449  if ((fprot >> b) & 1)
1450  bank->prot_blocks[i].is_protected = 0;
1451  else
1452  bank->prot_blocks[i].is_protected = 1;
1453 
1454  b++;
1455  }
1456 
1457  return ERROR_OK;
1458 }
1459 
1460 
1461 static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf)
1462 {
1463  uint32_t fprot = 0xffffffff;
1464  uint8_t fsec = 0xfe; /* set MCU unsecure */
1465  uint8_t fdprot = 0xff;
1466  unsigned int num_blocks;
1467  uint32_t pflash_bit;
1468  uint8_t dflash_bit;
1469  struct flash_bank *bank_iter;
1470  struct kinetis_flash_bank *k_bank = bank->driver_priv;
1471  struct kinetis_chip *k_chip = k_bank->k_chip;
1472 
1473  memset(fcf, 0xff, FCF_SIZE);
1474 
1475  pflash_bit = 1;
1476  dflash_bit = 1;
1477 
1478  /* iterate over all kinetis banks */
1479  /* current bank is bank 0, it contains FCF */
1480  num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
1481  for (unsigned int bank_idx = 0; bank_idx < num_blocks; bank_idx++) {
1482  k_bank = &(k_chip->banks[bank_idx]);
1483  bank_iter = k_bank->bank;
1484 
1485  if (!bank_iter) {
1486  LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplete", bank_idx);
1487  continue;
1488  }
1489 
1490  kinetis_auto_probe(bank_iter);
1491 
1492  assert(bank_iter->prot_blocks);
1493 
1494  if (k_bank->flash_class == FC_PFLASH) {
1495  for (unsigned int i = 0; i < bank_iter->num_prot_blocks; i++) {
1496  if (bank_iter->prot_blocks[i].is_protected == 1)
1497  fprot &= ~pflash_bit;
1498 
1499  pflash_bit <<= 1;
1500  }
1501 
1502  } else if (k_bank->flash_class == FC_FLEX_NVM) {
1503  for (unsigned int i = 0; i < bank_iter->num_prot_blocks; i++) {
1504  if (bank_iter->prot_blocks[i].is_protected == 1)
1505  fdprot &= ~dflash_bit;
1506 
1507  dflash_bit <<= 1;
1508  }
1509 
1510  }
1511  }
1512 
1513  target_buffer_set_u32(bank->target, fcf + FCF_FPROT, fprot);
1514  fcf[FCF_FSEC] = fsec;
1515  fcf[FCF_FOPT] = fcf_fopt;
1516  fcf[FCF_FDPROT] = fdprot;
1517  return ERROR_OK;
1518 }
1519 
1520 static int kinetis_ftfx_command(struct target *target, uint8_t fcmd, uint32_t faddr,
1521  uint8_t fccob4, uint8_t fccob5, uint8_t fccob6, uint8_t fccob7,
1522  uint8_t fccob8, uint8_t fccob9, uint8_t fccoba, uint8_t fccobb,
1523  uint8_t *ftfx_fstat)
1524 {
1525  uint8_t command[12] = {faddr & 0xff, (faddr >> 8) & 0xff, (faddr >> 16) & 0xff, fcmd,
1526  fccob7, fccob6, fccob5, fccob4,
1527  fccobb, fccoba, fccob9, fccob8};
1528  int result;
1529  uint8_t fstat;
1530  int64_t ms_timeout = timeval_ms() + 250;
1531 
1532  result = target_write_memory(target, FTFX_FCCOB3, 4, 3, command);
1533  if (result != ERROR_OK)
1534  return result;
1535 
1536  /* start command */
1537  result = target_write_u8(target, FTFX_FSTAT, 0x80);
1538  if (result != ERROR_OK)
1539  return result;
1540 
1541  /* wait for done */
1542  do {
1543  result = target_read_u8(target, FTFX_FSTAT, &fstat);
1544 
1545  if (result != ERROR_OK)
1546  return result;
1547 
1548  if (fstat & 0x80)
1549  break;
1550 
1551  } while (timeval_ms() < ms_timeout);
1552 
1553  if (ftfx_fstat)
1554  *ftfx_fstat = fstat;
1555 
1556  if ((fstat & 0xf0) != 0x80) {
1557  LOG_DEBUG("ftfx command failed FSTAT: %02X FCCOB: %02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X",
1558  fstat, command[3], command[2], command[1], command[0],
1559  command[7], command[6], command[5], command[4],
1560  command[11], command[10], command[9], command[8]);
1561 
1562  return kinetis_ftfx_decode_error(fstat);
1563  }
1564 
1565  return ERROR_OK;
1566 }
1567 
1568 
1569 static int kinetis_read_pmstat(struct kinetis_chip *k_chip, uint8_t *pmstat)
1570 {
1571  int result;
1572  uint32_t stat32;
1573  struct target *target = k_chip->target;
1574 
1575  switch (k_chip->sysmodectrlr_type) {
1576  case KINETIS_SMC:
1577  result = target_read_u8(target, SMC_PMSTAT, pmstat);
1578  return result;
1579 
1580  case KINETIS_SMC32:
1581  result = target_read_u32(target, SMC32_PMSTAT, &stat32);
1582  if (result == ERROR_OK)
1583  *pmstat = stat32 & 0xff;
1584  return result;
1585 
1586  case KINETIS_MC:
1587  /* emulate SMC by reading PMC_REGSC bit 3 (VLPRS) */
1588  result = target_read_u8(target, PMC_REGSC, pmstat);
1589  if (result == ERROR_OK) {
1590  if (*pmstat & 0x08)
1591  *pmstat = PM_STAT_VLPR;
1592  else
1593  *pmstat = PM_STAT_RUN;
1594  }
1595  return result;
1596  }
1597  return ERROR_FAIL;
1598 }
1599 
1600 static int kinetis_check_run_mode(struct kinetis_chip *k_chip)
1601 {
1602  int result;
1603  uint8_t pmstat;
1604  struct target *target;
1605 
1606  if (!k_chip) {
1607  LOG_ERROR("Chip not probed.");
1608  return ERROR_FAIL;
1609  }
1610  target = k_chip->target;
1611 
1612  if (target->state != TARGET_HALTED) {
1613  LOG_ERROR("Target not halted");
1614  return ERROR_TARGET_NOT_HALTED;
1615  }
1616 
1617  result = kinetis_read_pmstat(k_chip, &pmstat);
1618  if (result != ERROR_OK)
1619  return result;
1620 
1621  if (pmstat == PM_STAT_RUN)
1622  return ERROR_OK;
1623 
1624  if (pmstat == PM_STAT_VLPR) {
1625  /* It is safe to switch from VLPR to RUN mode without changing clock */
1626  LOG_INFO("Switching from VLPR to RUN mode.");
1627 
1628  switch (k_chip->sysmodectrlr_type) {
1629  case KINETIS_SMC:
1631  break;
1632 
1633  case KINETIS_SMC32:
1635  break;
1636 
1637  case KINETIS_MC:
1639  break;
1640  }
1641  if (result != ERROR_OK)
1642  return result;
1643 
1644  for (unsigned int i = 100; i > 0; i--) {
1645  result = kinetis_read_pmstat(k_chip, &pmstat);
1646  if (result != ERROR_OK)
1647  return result;
1648 
1649  if (pmstat == PM_STAT_RUN)
1650  return ERROR_OK;
1651  }
1652  }
1653 
1654  LOG_ERROR("Flash operation not possible in current run mode: SMC_PMSTAT: 0x%x", pmstat);
1655  LOG_ERROR("Issue a 'reset init' command.");
1656  return ERROR_TARGET_NOT_HALTED;
1657 }
1658 
1659 
1661 {
1662  struct target *target = k_chip->target;
1663 
1664  switch (k_chip->cache_type) {
1665  case KINETIS_CACHE_K:
1666  target_write_u8(target, FMC_PFB01CR + 2, 0xf0);
1667  /* Set CINV_WAY bits - request invalidate of all cache ways */
1668  /* FMC_PFB0CR has same address and CINV_WAY bits as FMC_PFB01CR */
1669  break;
1670 
1671  case KINETIS_CACHE_L:
1672  target_write_u8(target, MCM_PLACR + 1, 0x04);
1673  /* set bit CFCC - Clear Flash Controller Cache */
1674  break;
1675 
1676  case KINETIS_CACHE_MSCM:
1678  /* disable data prefetch and flash speculate */
1679  break;
1680 
1681  case KINETIS_CACHE_MSCM2:
1684  /* disable data prefetch and flash speculate */
1685  break;
1686 
1687  default:
1688  break;
1689  }
1690 }
1691 
1692 
1693 static int kinetis_erase(struct flash_bank *bank, unsigned int first,
1694  unsigned int last)
1695 {
1696  int result;
1697  struct kinetis_flash_bank *k_bank = bank->driver_priv;
1698  struct kinetis_chip *k_chip = k_bank->k_chip;
1699 
1700  result = kinetis_check_run_mode(k_chip);
1701  if (result != ERROR_OK)
1702  return result;
1703 
1704  /* reset error flags */
1705  result = kinetis_ftfx_prepare(bank->target);
1706  if (result != ERROR_OK)
1707  return result;
1708 
1709  if ((first > bank->num_sectors) || (last > bank->num_sectors))
1711 
1712  /*
1713  * FIXME: TODO: use the 'Erase Flash Block' command if the
1714  * requested erase is PFlash or NVM and encompasses the entire
1715  * block. Should be quicker.
1716  */
1717  for (unsigned int i = first; i <= last; i++) {
1718  /* set command and sector address */
1719  result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTERASE, k_bank->prog_base + bank->sectors[i].offset,
1720  0, 0, 0, 0, 0, 0, 0, 0, NULL);
1721 
1722  if (result != ERROR_OK) {
1723  LOG_WARNING("erase sector %u failed", i);
1725  }
1726 
1727  if (k_bank->prog_base == 0
1728  && bank->sectors[i].offset <= FCF_ADDRESS
1729  && bank->sectors[i].offset + bank->sectors[i].size > FCF_ADDRESS + FCF_SIZE) {
1730  if (allow_fcf_writes) {
1731  LOG_WARNING("Flash Configuration Field erased, DO NOT reset or power off the device");
1732  LOG_WARNING("until correct FCF is programmed or MCU gets security lock.");
1733  } else {
1734  uint8_t fcf_buffer[FCF_SIZE];
1735 
1736  kinetis_fill_fcf(bank, fcf_buffer);
1737  result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
1738  if (result != ERROR_OK)
1739  LOG_WARNING("Flash Configuration Field write failed");
1740  else
1741  LOG_DEBUG("Generated FCF written");
1742  }
1743  }
1744  }
1745 
1747 
1748  return ERROR_OK;
1749 }
1750 
1752 {
1753  int result;
1754  uint8_t ftfx_fcnfg;
1755 
1756  /* check if ram ready */
1757  result = target_read_u8(target, FTFX_FCNFG, &ftfx_fcnfg);
1758  if (result != ERROR_OK)
1759  return result;
1760 
1761  if (ftfx_fcnfg & (1 << 1))
1762  return ERROR_OK; /* ram ready */
1763 
1764  /* make flex ram available */
1765  result = kinetis_ftfx_command(target, FTFX_CMD_SETFLEXRAM, 0x00ff0000,
1766  0, 0, 0, 0, 0, 0, 0, 0, NULL);
1767  if (result != ERROR_OK)
1769 
1770  /* check again */
1771  result = target_read_u8(target, FTFX_FCNFG, &ftfx_fcnfg);
1772  if (result != ERROR_OK)
1773  return result;
1774 
1775  if (ftfx_fcnfg & (1 << 1))
1776  return ERROR_OK; /* ram ready */
1777 
1779 }
1780 
1781 
1782 static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer,
1783  uint32_t offset, uint32_t count)
1784 {
1785  int result = ERROR_OK;
1786  struct kinetis_flash_bank *k_bank = bank->driver_priv;
1787  struct kinetis_chip *k_chip = k_bank->k_chip;
1788  uint8_t *buffer_aligned = NULL;
1789  /*
1790  * Kinetis uses different terms for the granularity of
1791  * sector writes, e.g. "phrase" or "128 bits". We use
1792  * the generic term "chunk". The largest possible
1793  * Kinetis "chunk" is 16 bytes (128 bits).
1794  */
1795  uint32_t prog_section_chunk_bytes = k_bank->sector_size >> 8;
1796  uint32_t prog_size_bytes = k_chip->max_flash_prog_size;
1797 
1798  while (count > 0) {
1799  uint32_t size = prog_size_bytes - offset % prog_size_bytes;
1800  uint32_t align_begin = offset % prog_section_chunk_bytes;
1801  uint32_t align_end;
1802  uint32_t size_aligned;
1803  uint16_t chunk_count;
1804  uint8_t ftfx_fstat;
1805 
1806  if (size > count)
1807  size = count;
1808 
1809  align_end = (align_begin + size) % prog_section_chunk_bytes;
1810  if (align_end)
1811  align_end = prog_section_chunk_bytes - align_end;
1812 
1813  size_aligned = align_begin + size + align_end;
1814  chunk_count = size_aligned / prog_section_chunk_bytes;
1815 
1816  if (size != size_aligned) {
1817  /* aligned section: the first, the last or the only */
1818  if (!buffer_aligned)
1819  buffer_aligned = malloc(prog_size_bytes);
1820 
1821  memset(buffer_aligned, 0xff, size_aligned);
1822  memcpy(buffer_aligned + align_begin, buffer, size);
1823 
1824  result = target_write_memory(bank->target, k_chip->progr_accel_ram,
1825  4, size_aligned / 4, buffer_aligned);
1826 
1827  LOG_DEBUG("section @ " TARGET_ADDR_FMT " aligned begin %" PRIu32
1828  ", end %" PRIu32,
1829  bank->base + offset, align_begin, align_end);
1830  } else
1831  result = target_write_memory(bank->target, k_chip->progr_accel_ram,
1832  4, size_aligned / 4, buffer);
1833 
1834  LOG_DEBUG("write section @ " TARGET_ADDR_FMT " with length %" PRIu32
1835  " bytes",
1836  bank->base + offset, size);
1837 
1838  if (result != ERROR_OK) {
1839  LOG_ERROR("target_write_memory failed");
1840  break;
1841  }
1842 
1843  /* execute section-write command */
1844  result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTWRITE,
1845  k_bank->prog_base + offset - align_begin,
1846  chunk_count>>8, chunk_count, 0, 0,
1847  0, 0, 0, 0, &ftfx_fstat);
1848 
1849  if (result != ERROR_OK) {
1850  LOG_ERROR("Error writing section at " TARGET_ADDR_FMT,
1851  bank->base + offset);
1852  break;
1853  }
1854 
1855  if (ftfx_fstat & 0x01) {
1856  LOG_ERROR("Flash write error at " TARGET_ADDR_FMT,
1857  bank->base + offset);
1858  if (k_bank->prog_base == 0 && offset == FCF_ADDRESS + FCF_SIZE
1859  && (k_chip->flash_support & FS_WIDTH_256BIT)) {
1860  LOG_ERROR("Flash write immediately after the end of Flash Config Field shows error");
1861  LOG_ERROR("because the flash memory is 256 bits wide (data were written correctly).");
1862  LOG_ERROR("Either change the linker script to add a gap of 16 bytes after FCF");
1863  LOG_ERROR("or set 'kinetis fcf_source write'");
1864  }
1865  }
1866 
1867  buffer += size;
1868  offset += size;
1869  count -= size;
1870 
1871  keep_alive();
1872  }
1873 
1874  free(buffer_aligned);
1875  return result;
1876 }
1877 
1878 
1879 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
1880  uint32_t offset, uint32_t count)
1881 {
1882  int result;
1883  bool fallback = false;
1884  struct kinetis_flash_bank *k_bank = bank->driver_priv;
1885  struct kinetis_chip *k_chip = k_bank->k_chip;
1886 
1887  if (!(k_chip->flash_support & FS_PROGRAM_SECTOR)) {
1888  /* fallback to longword write */
1889  fallback = true;
1890  LOG_INFO("This device supports Program Longword execution only.");
1891  } else {
1892  result = kinetis_make_ram_ready(bank->target);
1893  if (result != ERROR_OK) {
1894  fallback = true;
1895  LOG_WARNING("FlexRAM not ready, fallback to slow longword write.");
1896  }
1897  }
1898 
1899  LOG_DEBUG("flash write @ " TARGET_ADDR_FMT, bank->base + offset);
1900 
1901  if (!fallback) {
1902  /* program section command */
1904  } else if (k_chip->flash_support & FS_PROGRAM_LONGWORD) {
1905  /* program longword command, not supported in FTFE */
1906  uint8_t *new_buffer = NULL;
1907 
1908  /* check word alignment */
1909  if (offset & 0x3) {
1910  LOG_ERROR("offset 0x%" PRIx32 " breaks the required alignment", offset);
1912  }
1913 
1914  if (count & 0x3) {
1915  uint32_t old_count = count;
1916  count = (old_count | 3) + 1;
1917  new_buffer = malloc(count);
1918  if (!new_buffer) {
1919  LOG_ERROR("odd number of bytes to write and no memory "
1920  "for padding buffer");
1921  return ERROR_FAIL;
1922  }
1923  LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
1924  "and padding with 0xff", old_count, count);
1925  memset(new_buffer + old_count, 0xff, count - old_count);
1926  buffer = memcpy(new_buffer, buffer, old_count);
1927  }
1928 
1929  uint32_t words_remaining = count / 4;
1930 
1931  kinetis_disable_wdog(k_chip);
1932 
1933  /* try using a block write */
1934  result = kinetis_write_block(bank, buffer, offset, words_remaining);
1935 
1936  if (result == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1937  /* if block write failed (no sufficient working area),
1938  * we use normal (slow) single word accesses */
1939  LOG_WARNING("couldn't use block writes, falling back to single "
1940  "memory accesses");
1941 
1942  while (words_remaining) {
1943  uint8_t ftfx_fstat;
1944 
1945  LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));
1946 
1947  result = kinetis_ftfx_command(bank->target, FTFX_CMD_LWORDPROG, k_bank->prog_base + offset,
1948  buffer[3], buffer[2], buffer[1], buffer[0],
1949  0, 0, 0, 0, &ftfx_fstat);
1950 
1951  if (result != ERROR_OK) {
1952  LOG_ERROR("Error writing longword at " TARGET_ADDR_FMT,
1953  bank->base + offset);
1954  break;
1955  }
1956 
1957  if (ftfx_fstat & 0x01)
1958  LOG_ERROR("Flash write error at " TARGET_ADDR_FMT,
1959  bank->base + offset);
1960 
1961  buffer += 4;
1962  offset += 4;
1963  words_remaining--;
1964 
1965  keep_alive();
1966  }
1967  }
1968  free(new_buffer);
1969  } else {
1970  LOG_ERROR("Flash write strategy not implemented");
1972  }
1973 
1975  return result;
1976 }
1977 
1978 
1979 static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
1980  uint32_t offset, uint32_t count)
1981 {
1982  int result;
1983  bool set_fcf = false;
1984  bool fcf_in_data_valid = false;
1985  bool fcf_differs = false;
1986  int sect = 0;
1987  struct kinetis_flash_bank *k_bank = bank->driver_priv;
1988  struct kinetis_chip *k_chip = k_bank->k_chip;
1989  uint8_t fcf_buffer[FCF_SIZE];
1990  uint8_t fcf_current[FCF_SIZE];
1991  uint8_t fcf_in_data[FCF_SIZE];
1992 
1993  result = kinetis_check_run_mode(k_chip);
1994  if (result != ERROR_OK)
1995  return result;
1996 
1997  /* reset error flags */
1998  result = kinetis_ftfx_prepare(bank->target);
1999  if (result != ERROR_OK)
2000  return result;
2001 
2002  if (k_bank->prog_base == 0 && !allow_fcf_writes) {
2003  if (bank->sectors[1].offset <= FCF_ADDRESS)
2004  sect = 1; /* 1kb sector, FCF in 2nd sector */
2005 
2006  if (offset < bank->sectors[sect].offset + bank->sectors[sect].size
2007  && offset + count > bank->sectors[sect].offset)
2008  set_fcf = true; /* write to any part of sector with FCF */
2009  }
2010 
2011  if (set_fcf) {
2012  kinetis_fill_fcf(bank, fcf_buffer);
2013 
2014  fcf_in_data_valid = offset <= FCF_ADDRESS
2015  && offset + count >= FCF_ADDRESS + FCF_SIZE;
2016  if (fcf_in_data_valid) {
2017  memcpy(fcf_in_data, buffer + FCF_ADDRESS - offset, FCF_SIZE);
2018  if (memcmp(fcf_in_data, fcf_buffer, 8)) {
2019  fcf_differs = true;
2020  LOG_INFO("Setting of backdoor key is not supported in mode 'kinetis fcf_source protection'.");
2021  }
2022  if (memcmp(fcf_in_data + FCF_FPROT, fcf_buffer + FCF_FPROT, 4)) {
2023  fcf_differs = true;
2024  LOG_INFO("Flash protection requested in the programmed file differs from current setting.");
2025  }
2026  if (fcf_in_data[FCF_FDPROT] != fcf_buffer[FCF_FDPROT]) {
2027  fcf_differs = true;
2028  LOG_INFO("Data flash protection requested in the programmed file differs from current setting.");
2029  }
2030  if ((fcf_in_data[FCF_FSEC] & 3) != 2) {
2031  fcf_in_data_valid = false;
2032  LOG_INFO("Device security requested in the programmed file! Write denied.");
2033  } else if (fcf_in_data[FCF_FSEC] != fcf_buffer[FCF_FSEC]) {
2034  fcf_differs = true;
2035  LOG_INFO("Strange unsecure mode 0x%02" PRIx8
2036  " requested in the programmed file, set FSEC = 0x%02" PRIx8
2037  " in the startup code!",
2038  fcf_in_data[FCF_FSEC], fcf_buffer[FCF_FSEC]);
2039  }
2040  if (fcf_in_data[FCF_FOPT] != fcf_buffer[FCF_FOPT]) {
2041  fcf_differs = true;
2042  LOG_INFO("FOPT requested in the programmed file differs from current setting, set 'kinetis fopt 0x%02"
2043  PRIx8 "'.", fcf_in_data[FCF_FOPT]);
2044  }
2045 
2046  /* If the device has ECC flash, then we cannot re-program FCF */
2047  if (fcf_differs) {
2048  if (k_chip->flash_support & FS_ECC) {
2049  fcf_in_data_valid = false;
2050  LOG_INFO("Cannot re-program FCF. Expect verify errors at FCF (0x400-0x40f).");
2051  } else {
2052  LOG_INFO("Trying to re-program FCF.");
2053  if (!(k_chip->flash_support & FS_PROGRAM_LONGWORD))
2054  LOG_INFO("Flash re-programming may fail on this device!");
2055  }
2056  }
2057  }
2058  }
2059 
2060  if (set_fcf && !fcf_in_data_valid) {
2061  if (offset < FCF_ADDRESS) {
2062  /* write part preceding FCF */
2064  if (result != ERROR_OK)
2065  return result;
2066  }
2067 
2068  result = target_read_memory(bank->target, bank->base + FCF_ADDRESS, 4, FCF_SIZE / 4, fcf_current);
2069  if (result == ERROR_OK && memcmp(fcf_current, fcf_buffer, FCF_SIZE) == 0)
2070  set_fcf = false;
2071 
2072  if (set_fcf) {
2073  /* write FCF if differs from flash - eliminate multiple writes */
2074  result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
2075  if (result != ERROR_OK)
2076  return result;
2077  }
2078 
2079  LOG_WARNING("Flash Configuration Field written.");
2080  LOG_WARNING("Reset or power off the device to make settings effective.");
2081 
2082  if (offset + count > FCF_ADDRESS + FCF_SIZE) {
2083  uint32_t delta = FCF_ADDRESS + FCF_SIZE - offset;
2084  /* write part after FCF */
2085  result = kinetis_write_inner(bank, buffer + delta, FCF_ADDRESS + FCF_SIZE, count - delta);
2086  }
2087  return result;
2088 
2089  } else {
2090  /* no FCF fiddling, normal write */
2092  }
2093 }
2094 
2095 
2096 static int kinetis_probe_chip_s32k(struct kinetis_chip *k_chip)
2097 {
2098  int result;
2099  uint8_t fcfg1_eesize, fcfg1_depart;
2100  uint32_t ee_size = 0;
2101  uint32_t pflash_size_k, nvm_size_k, dflash_size_k;
2102  unsigned int generation = 0, subseries = 0, derivate = 0;
2103 
2104  struct target *target = k_chip->target;
2105  k_chip->probed = false;
2106  k_chip->pflash_sector_size = 0;
2107  k_chip->pflash_base = 0;
2108  k_chip->nvm_base = 0x10000000;
2109  k_chip->progr_accel_ram = FLEXRAM;
2110  k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2111  k_chip->watchdog_type = KINETIS_WDOG32_KE1X;
2112 
2113  if (k_chip->sim_base == 0)
2114  k_chip->sim_base = SIM_BASE;
2115 
2116  result = target_read_u32(target, k_chip->sim_base + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2117  if (result != ERROR_OK)
2118  return result;
2119 
2120  generation = (k_chip->sim_sdid) >> 28 & 0x0f;
2121  subseries = (k_chip->sim_sdid) >> 24 & 0x0f;
2122  derivate = (k_chip->sim_sdid) >> 20 & 0x0f;
2123 
2124  switch (k_chip->sim_sdid & KINETIS_SDID_S32K_SERIES_MASK) {
2126  k_chip->cache_type = KINETIS_CACHE_L;
2127  k_chip->num_pflash_blocks = 1;
2128  k_chip->num_nvm_blocks = 1;
2129  /* Non-interleaved */
2130  k_chip->max_flash_prog_size = 512;
2131 
2132  switch (k_chip->sim_sdid & KINETIS_SDID_S32K_DERIVATE_MASK) {
2134  /* S32K116 CPU 48Mhz Flash 128KB RAM 17KB+2KB */
2135  /* Non-Interleaved */
2136  k_chip->pflash_size = 128 << 10;
2137  k_chip->pflash_sector_size = 2 << 10;
2138  /* Non-Interleaved */
2139  k_chip->nvm_size = 32 << 10;
2140  k_chip->nvm_sector_size = 2 << 10;
2141  break;
2143  /* S32K118 CPU 80Mhz Flash 256KB+32KB RAM 32KB+4KB */
2144  /* Non-Interleaved */
2145  k_chip->pflash_size = 256 << 10;
2146  k_chip->pflash_sector_size = 2 << 10;
2147  /* Non-Interleaved */
2148  k_chip->nvm_size = 32 << 10;
2149  k_chip->nvm_sector_size = 2 << 10;
2150  break;
2151  }
2152  break;
2153 
2155  k_chip->cache_type = KINETIS_CACHE_MSCM2;
2156  k_chip->num_pflash_blocks = 1;
2157  k_chip->num_nvm_blocks = 1;
2158  /* Non-interleaved */
2159  k_chip->max_flash_prog_size = 512;
2160  switch (k_chip->sim_sdid & KINETIS_SDID_S32K_DERIVATE_MASK) {
2163  /* S32K142/S32K142W CPU 80Mhz Flash 256KB+64KB RAM 32KB+4KB */
2164  /* Non-Interleaved */
2165  k_chip->pflash_size = 256 << 10;
2166  k_chip->pflash_sector_size = 2 << 10;
2167  /* Non-Interleaved */
2168  k_chip->nvm_size = 64 << 10;
2169  k_chip->nvm_sector_size = 2 << 10;
2170  break;
2173  /* S32K144/S32K144W CPU 80Mhz Flash 512KB+64KB RAM 64KB+4KB */
2174  /* Interleaved */
2175  k_chip->pflash_size = 512 << 10;
2176  k_chip->pflash_sector_size = 4 << 10;
2177  /* Non-Interleaved */
2178  k_chip->nvm_size = 64 << 10;
2179  k_chip->nvm_sector_size = 2 << 10;
2180  break;
2182  /* S32K146 CPU 80Mhz Flash 1024KB+64KB RAM 128KB+4KB */
2183  /* Interleaved */
2184  k_chip->pflash_size = 1024 << 10;
2185  k_chip->pflash_sector_size = 4 << 10;
2186  k_chip->num_pflash_blocks = 2;
2187  /* Non-Interleaved */
2188  k_chip->nvm_size = 64 << 10;
2189  k_chip->nvm_sector_size = 2 << 10;
2190  break;
2192  /* S32K148 CPU 80Mhz Flash 1536KB+512KB RAM 256KB+4KB */
2193  /* Interleaved */
2194  k_chip->pflash_size = 1536 << 10;
2195  k_chip->pflash_sector_size = 4 << 10;
2196  k_chip->num_pflash_blocks = 3;
2197  /* Interleaved */
2198  k_chip->nvm_size = 512 << 10;
2199  k_chip->nvm_sector_size = 4 << 10;
2200  /* Interleaved */
2201  k_chip->max_flash_prog_size = 1 << 10;
2202  break;
2203  }
2204  break;
2205 
2206  default:
2207  LOG_ERROR("Unsupported S32K1xx-series");
2208  }
2209 
2210  if (k_chip->pflash_sector_size == 0) {
2211  LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32, k_chip->sim_sdid);
2213  }
2214 
2215  result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &k_chip->sim_fcfg1);
2216  if (result != ERROR_OK)
2217  return result;
2218  k_chip->sim_fcfg2 = 0; /* S32K1xx does not implement FCFG2 register. */
2219 
2220  fcfg1_depart = (k_chip->sim_fcfg1 >> 12) & 0x0f;
2221  fcfg1_eesize = (k_chip->sim_fcfg1 >> 16) & 0x0f;
2222  if (fcfg1_eesize <= 9)
2223  ee_size = (16 << (10 - fcfg1_eesize));
2224  if ((fcfg1_depart & 0x8) == 0) {
2225  /* Binary 0xxx values encode the amount reserved for EEPROM emulation. */
2226  if (fcfg1_depart)
2227  k_chip->dflash_size = k_chip->nvm_size - (4096 << fcfg1_depart);
2228  else
2229  k_chip->dflash_size = k_chip->nvm_size;
2230  } else {
2231  /* Binary 1xxx valued encode the DFlash size. */
2232  if (fcfg1_depart & 0x7)
2233  k_chip->dflash_size = 4096 << (fcfg1_depart & 0x7);
2234  else
2235  k_chip->dflash_size = 0;
2236  }
2237 
2238  snprintf(k_chip->name, sizeof(k_chip->name), "S32K%u%u%u",
2239  generation, subseries, derivate);
2240 
2241  pflash_size_k = k_chip->pflash_size / 1024;
2242  dflash_size_k = k_chip->dflash_size / 1024;
2243 
2244  LOG_INFO("%s detected: %u flash blocks", k_chip->name, k_chip->num_pflash_blocks + k_chip->num_nvm_blocks);
2245  LOG_INFO("%u PFlash banks: %" PRIu32 " KiB total", k_chip->num_pflash_blocks, pflash_size_k);
2246 
2247  nvm_size_k = k_chip->nvm_size / 1024;
2248 
2249  if (k_chip->num_nvm_blocks) {
2250  LOG_INFO("%u FlexNVM banks: %" PRIu32 " KiB total, %" PRIu32 " KiB available as data flash, %"
2251  PRIu32 " bytes FlexRAM",
2252  k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size);
2253  }
2254 
2255  k_chip->probed = true;
2256 
2257  if (create_banks)
2259 
2260  return ERROR_OK;
2261 }
2262 
2263 
2264 static int kinetis_probe_chip(struct kinetis_chip *k_chip)
2265 {
2266  int result;
2267  uint8_t fcfg1_nvmsize, fcfg1_pfsize, fcfg1_eesize, fcfg1_depart;
2268  uint8_t fcfg2_pflsh;
2269  uint32_t ee_size = 0;
2270  uint32_t pflash_size_k, nvm_size_k, dflash_size_k;
2271  uint32_t pflash_size_m;
2272  unsigned int num_blocks = 0;
2273  unsigned int maxaddr_shift = 13;
2274  struct target *target = k_chip->target;
2275 
2276  unsigned int familyid = 0, subfamid = 0;
2277  unsigned int cpu_mhz = 120;
2278  bool use_nvm_marking = false;
2279  char flash_marking[12], nvm_marking[2];
2280  char name[40];
2281 
2282  k_chip->probed = false;
2283  k_chip->pflash_sector_size = 0;
2284  k_chip->pflash_base = 0;
2285  k_chip->nvm_base = 0x10000000;
2286  k_chip->progr_accel_ram = FLEXRAM;
2287 
2288  name[0] = '\0';
2289 
2290  if (k_chip->sim_base)
2291  result = target_read_u32(target, k_chip->sim_base + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2292  else {
2293  result = target_read_u32(target, SIM_BASE + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2294  if (result == ERROR_OK)
2295  k_chip->sim_base = SIM_BASE;
2296  else {
2298  if (result == ERROR_OK)
2299  k_chip->sim_base = SIM_BASE_KL28;
2300  }
2301  }
2302  if (result != ERROR_OK)
2303  return result;
2304 
2305  if ((k_chip->sim_sdid & (~KINETIS_SDID_K_SERIES_MASK)) == 0) {
2306  /* older K-series MCU */
2307  uint32_t mcu_type = k_chip->sim_sdid & KINETIS_K_SDID_TYPE_MASK;
2308  k_chip->cache_type = KINETIS_CACHE_K;
2309  k_chip->watchdog_type = KINETIS_WDOG_K;
2310 
2311  switch (mcu_type) {
2314  /* 1kB sectors */
2315  k_chip->pflash_sector_size = 1<<10;
2316  k_chip->nvm_sector_size = 1<<10;
2317  num_blocks = 2;
2318  k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2319  break;
2327  /* 2kB sectors, 1kB FlexNVM sectors */
2328  k_chip->pflash_sector_size = 2<<10;
2329  k_chip->nvm_sector_size = 1<<10;
2330  num_blocks = 2;
2331  k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2332  k_chip->max_flash_prog_size = 1<<10;
2333  break;
2336  case KINETIS_K_SDID_K11:
2337  case KINETIS_K_SDID_K12:
2341  case KINETIS_K_SDID_K53:
2343  /* 2kB sectors */
2344  k_chip->pflash_sector_size = 2<<10;
2345  k_chip->nvm_sector_size = 2<<10;
2346  num_blocks = 2;
2347  k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2348  break;
2351  /* 4kB sectors (MK21FN1M0, MK21FX512, MK22FN1M0, MK22FX512) */
2352  k_chip->pflash_sector_size = 4<<10;
2353  k_chip->max_flash_prog_size = 1<<10;
2354  k_chip->nvm_sector_size = 4<<10;
2355  num_blocks = 2;
2356  k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2357  break;
2362  /* 4kB sectors */
2363  k_chip->pflash_sector_size = 4<<10;
2364  k_chip->nvm_sector_size = 4<<10;
2365  num_blocks = 4;
2366  k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2367  break;
2368  default:
2369  LOG_ERROR("Unsupported K-family FAMID");
2370  }
2371 
2372  for (size_t idx = 0; idx < ARRAY_SIZE(kinetis_types_old); idx++) {
2373  if (kinetis_types_old[idx].sdid == mcu_type) {
2374  strcpy(name, kinetis_types_old[idx].name);
2375  use_nvm_marking = true;
2376  break;
2377  }
2378  }
2379 
2380  /* first revision of some devices has no SMC */
2381  switch (mcu_type) {
2387  {
2388  uint32_t revid = (k_chip->sim_sdid & KINETIS_K_REVID_MASK) >> KINETIS_K_REVID_SHIFT;
2389  /* highest bit set corresponds to rev 2.x */
2390  if (revid <= 7) {
2391  k_chip->sysmodectrlr_type = KINETIS_MC;
2392  strcat(name, " Rev 1.x");
2393  }
2394  }
2395  break;
2396  }
2397 
2398  } else {
2399  /* Newer K-series or KL series MCU */
2402 
2403  switch (k_chip->sim_sdid & KINETIS_SDID_SERIESID_MASK) {
2405  use_nvm_marking = true;
2406  k_chip->cache_type = KINETIS_CACHE_K;
2407  k_chip->watchdog_type = KINETIS_WDOG_K;
2408 
2411  /* K02FN64, K02FN128: FTFA, 2kB sectors */
2412  k_chip->pflash_sector_size = 2<<10;
2413  num_blocks = 1;
2414  k_chip->flash_support = FS_PROGRAM_LONGWORD;
2415  cpu_mhz = 100;
2416  break;
2417 
2419  /* MK24FN1M reports as K22, this should detect it (according to errata note 1N83J) */
2420  uint32_t sopt1;
2421  result = target_read_u32(target, k_chip->sim_base + SIM_SOPT1_OFFSET, &sopt1);
2422  if (result != ERROR_OK)
2423  return result;
2424 
2427  /* MK24FN1M */
2428  k_chip->pflash_sector_size = 4<<10;
2429  num_blocks = 2;
2430  k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2431  k_chip->max_flash_prog_size = 1<<10;
2432  subfamid = 4; /* errata 1N83J fix */
2433  break;
2434  }
2438  /* K22 with new-style SDID - smaller pflash with FTFA, 2kB sectors */
2439  k_chip->pflash_sector_size = 2<<10;
2440  /* autodetect 1 or 2 blocks */
2441  k_chip->flash_support = FS_PROGRAM_LONGWORD;
2442  break;
2443  }
2444  LOG_ERROR("Unsupported Kinetis K22 DIEID");
2445  break;
2446  }
2448  k_chip->pflash_sector_size = 4<<10;
2450  /* K24FN256 - smaller pflash with FTFA */
2451  num_blocks = 1;
2452  k_chip->flash_support = FS_PROGRAM_LONGWORD;
2453  break;
2454  }
2455  /* K24FN1M without errata 7534 */
2456  num_blocks = 2;
2457  k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2458  k_chip->max_flash_prog_size = 1<<10;
2459  break;
2460 
2461  case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX1: /* errata 7534 - should be K63 */
2462  case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX2: /* errata 7534 - should be K64 */
2463  subfamid += 2; /* errata 7534 fix */
2464  /* fallthrough */
2466  /* K63FN1M0 */
2468  /* K64FN1M0, K64FX512 */
2469  k_chip->pflash_sector_size = 4<<10;
2470  k_chip->nvm_sector_size = 4<<10;
2471  k_chip->max_flash_prog_size = 1<<10;
2472  num_blocks = 2;
2473  k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2474  break;
2475 
2477  /* K26FN2M0 */
2479  /* K66FN2M0, K66FX1M0 */
2480  k_chip->pflash_sector_size = 4<<10;
2481  k_chip->nvm_sector_size = 4<<10;
2482  k_chip->max_flash_prog_size = 1<<10;
2483  num_blocks = 4;
2484  k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_ECC;
2485  cpu_mhz = 180;
2486  break;
2487 
2489  /* K27FN2M0 */
2491  /* K28FN2M0 */
2492  k_chip->pflash_sector_size = 4<<10;
2493  k_chip->max_flash_prog_size = 1<<10;
2494  num_blocks = 4;
2495  k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_ECC;
2496  cpu_mhz = 150;
2497  break;
2498 
2502  /* K80FN256, K81FN256, K82FN256 */
2503  k_chip->pflash_sector_size = 4<<10;
2504  num_blocks = 1;
2505  k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_NO_CMD_BLOCKSTAT;
2506  cpu_mhz = 150;
2507  break;
2508 
2511  /* KL81Z128, KL82Z128 */
2512  k_chip->pflash_sector_size = 2<<10;
2513  num_blocks = 1;
2514  k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_NO_CMD_BLOCKSTAT;
2515  k_chip->cache_type = KINETIS_CACHE_L;
2516 
2517  use_nvm_marking = false;
2518  snprintf(name, sizeof(name), "MKL8%uZ%%s7",
2519  subfamid);
2520  break;
2521 
2522  default:
2523  LOG_ERROR("Unsupported Kinetis FAMILYID SUBFAMID");
2524  }
2525 
2526  if (name[0] == '\0')
2527  snprintf(name, sizeof(name), "MK%u%uF%%s%u",
2528  familyid, subfamid, cpu_mhz / 10);
2529  break;
2530 
2532  /* KL-series */
2533  k_chip->pflash_sector_size = 1<<10;
2534  k_chip->nvm_sector_size = 1<<10;
2535  /* autodetect 1 or 2 blocks */
2536  k_chip->flash_support = FS_PROGRAM_LONGWORD;
2537  k_chip->cache_type = KINETIS_CACHE_L;
2538  k_chip->watchdog_type = KINETIS_WDOG_COP;
2539 
2540  cpu_mhz = 48;
2544  subfamid = 7;
2545  break;
2546 
2548  cpu_mhz = 72;
2549  k_chip->pflash_sector_size = 2<<10;
2550  num_blocks = 2;
2551  k_chip->watchdog_type = KINETIS_WDOG32_KL28;
2552  k_chip->sysmodectrlr_type = KINETIS_SMC32;
2553  break;
2554  }
2555 
2556  snprintf(name, sizeof(name), "MKL%u%uZ%%s%u",
2557  familyid, subfamid, cpu_mhz / 10);
2558  break;
2559 
2561  /* Newer KW-series (all KW series except KW2xD, KW01Z) */
2562  cpu_mhz = 48;
2565  /* KW40Z */
2567  /* KW30Z */
2569  /* KW20Z */
2570  /* FTFA, 1kB sectors */
2571  k_chip->pflash_sector_size = 1<<10;
2572  k_chip->nvm_sector_size = 1<<10;
2573  /* autodetect 1 or 2 blocks */
2574  k_chip->flash_support = FS_PROGRAM_LONGWORD;
2575  k_chip->cache_type = KINETIS_CACHE_L;
2576  k_chip->watchdog_type = KINETIS_WDOG_COP;
2577  break;
2579  /* KW41Z */
2581  /* KW31Z */
2583  /* KW21Z */
2584  /* FTFA, 2kB sectors */
2585  k_chip->pflash_sector_size = 2<<10;
2586  k_chip->nvm_sector_size = 2<<10;
2587  /* autodetect 1 or 2 blocks */
2588  k_chip->flash_support = FS_PROGRAM_LONGWORD;
2589  k_chip->cache_type = KINETIS_CACHE_L;
2590  k_chip->watchdog_type = KINETIS_WDOG_COP;
2591  break;
2592  default:
2593  LOG_ERROR("Unsupported KW FAMILYID SUBFAMID");
2594  }
2595  snprintf(name, sizeof(name), "MKW%u%uZ%%s%u",
2596  familyid, subfamid, cpu_mhz / 10);
2597  break;
2598 
2600  /* KV-series */
2601  k_chip->watchdog_type = KINETIS_WDOG_K;
2604  /* KV10: FTFA, 1kB sectors */
2605  k_chip->pflash_sector_size = 1<<10;
2606  num_blocks = 1;
2607  k_chip->flash_support = FS_PROGRAM_LONGWORD;
2608  k_chip->cache_type = KINETIS_CACHE_L;
2609  strcpy(name, "MKV10Z%s7");
2610  break;
2611 
2613  /* KV11: FTFA, 2kB sectors */
2614  k_chip->pflash_sector_size = 2<<10;
2615  num_blocks = 1;
2616  k_chip->flash_support = FS_PROGRAM_LONGWORD;
2617  k_chip->cache_type = KINETIS_CACHE_L;
2618  strcpy(name, "MKV11Z%s7");
2619  break;
2620 
2622  /* KV30: FTFA, 2kB sectors, 1 block */
2624  /* KV31: FTFA, 2kB sectors, 2 blocks */
2625  k_chip->pflash_sector_size = 2<<10;
2626  /* autodetect 1 or 2 blocks */
2627  k_chip->flash_support = FS_PROGRAM_LONGWORD;
2628  k_chip->cache_type = KINETIS_CACHE_K;
2629  break;
2630 
2634  /* KV4x: FTFA, 4kB sectors */
2635  k_chip->pflash_sector_size = 4<<10;
2636  num_blocks = 1;
2637  k_chip->flash_support = FS_PROGRAM_LONGWORD;
2638  k_chip->cache_type = KINETIS_CACHE_K;
2639  cpu_mhz = 168;
2640  break;
2641 
2644  /* KV5x: FTFE, 8kB sectors */
2645  k_chip->pflash_sector_size = 8<<10;
2646  k_chip->max_flash_prog_size = 1<<10;
2647  num_blocks = 1;
2648  maxaddr_shift = 14;
2649  k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_WIDTH_256BIT | FS_ECC;
2650  k_chip->pflash_base = 0x10000000;
2651  k_chip->progr_accel_ram = 0x18000000;
2652  cpu_mhz = 240;
2653  break;
2654 
2655  default:
2656  LOG_ERROR("Unsupported KV FAMILYID SUBFAMID");
2657  }
2658 
2659  if (name[0] == '\0')
2660  snprintf(name, sizeof(name), "MKV%u%uF%%s%u",
2661  familyid, subfamid, cpu_mhz / 10);
2662  break;
2663 
2665  /* KE1x-series */
2666  k_chip->watchdog_type = KINETIS_WDOG32_KE1X;
2667  switch (k_chip->sim_sdid &
2671  /* KE1xZ: FTFE, 2kB sectors */
2672  k_chip->pflash_sector_size = 2<<10;
2673  k_chip->nvm_sector_size = 2<<10;
2674  k_chip->max_flash_prog_size = 1<<9;
2675  num_blocks = 2;
2676  k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2677  k_chip->cache_type = KINETIS_CACHE_L;
2678 
2679  cpu_mhz = 72;
2680  snprintf(name, sizeof(name), "MKE%u%uZ%%s%u",
2681  familyid, subfamid, cpu_mhz / 10);
2682  break;
2683 
2687  /* KE1xF: FTFE, 4kB sectors */
2688  k_chip->pflash_sector_size = 4<<10;
2689  k_chip->nvm_sector_size = 2<<10;
2690  k_chip->max_flash_prog_size = 1<<10;
2691  num_blocks = 2;
2692  k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2693  k_chip->cache_type = KINETIS_CACHE_MSCM;
2694 
2695  cpu_mhz = 168;
2696  snprintf(name, sizeof(name), "MKE%u%uF%%s%u",
2697  familyid, subfamid, cpu_mhz / 10);
2698  break;
2699 
2700  default:
2701  LOG_ERROR("Unsupported KE FAMILYID SUBFAMID");
2702  }
2703  break;
2704 
2705  default:
2706  LOG_ERROR("Unsupported K-series");
2707  }
2708  }
2709 
2710  if (k_chip->pflash_sector_size == 0) {
2711  LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32, k_chip->sim_sdid);
2713  }
2714 
2715  result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &k_chip->sim_fcfg1);
2716  if (result != ERROR_OK)
2717  return result;
2718 
2719  result = target_read_u32(target, k_chip->sim_base + SIM_FCFG2_OFFSET, &k_chip->sim_fcfg2);
2720  if (result != ERROR_OK)
2721  return result;
2722 
2723  LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08" PRIX32, k_chip->sim_sdid,
2724  k_chip->sim_fcfg1, k_chip->sim_fcfg2);
2725 
2726  fcfg1_nvmsize = (uint8_t)((k_chip->sim_fcfg1 >> 28) & 0x0f);
2727  fcfg1_pfsize = (uint8_t)((k_chip->sim_fcfg1 >> 24) & 0x0f);
2728  fcfg1_eesize = (uint8_t)((k_chip->sim_fcfg1 >> 16) & 0x0f);
2729  fcfg1_depart = (uint8_t)((k_chip->sim_fcfg1 >> 8) & 0x0f);
2730 
2731  fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
2732  k_chip->fcfg2_maxaddr0_shifted = ((k_chip->sim_fcfg2 >> 24) & 0x7f) << maxaddr_shift;
2733  k_chip->fcfg2_maxaddr1_shifted = ((k_chip->sim_fcfg2 >> 16) & 0x7f) << maxaddr_shift;
2734 
2735  if (num_blocks == 0)
2736  num_blocks = k_chip->fcfg2_maxaddr1_shifted ? 2 : 1;
2737  else if (k_chip->fcfg2_maxaddr1_shifted == 0 && num_blocks >= 2 && fcfg2_pflsh) {
2738  /* fcfg2_maxaddr1 may be zero due to partitioning whole NVM as EEPROM backup
2739  * Do not adjust block count in this case! */
2740  num_blocks = 1;
2741  LOG_WARNING("MAXADDR1 is zero, number of flash banks adjusted to 1");
2742  } else if (k_chip->fcfg2_maxaddr1_shifted != 0 && num_blocks == 1) {
2743  num_blocks = 2;
2744  LOG_WARNING("MAXADDR1 is non zero, number of flash banks adjusted to 2");
2745  }
2746 
2747  /* when the PFLSH bit is set, there is no FlexNVM/FlexRAM */
2748  if (!fcfg2_pflsh) {
2749  switch (fcfg1_nvmsize) {
2750  case 0x03:
2751  case 0x05:
2752  case 0x07:
2753  case 0x09:
2754  case 0x0b:
2755  k_chip->nvm_size = 1 << (14 + (fcfg1_nvmsize >> 1));
2756  break;
2757  case 0x0f:
2758  if (k_chip->pflash_sector_size >= 4<<10)
2759  k_chip->nvm_size = 512<<10;
2760  else
2761  /* K20_100 */
2762  k_chip->nvm_size = 256<<10;
2763  break;
2764  default:
2765  k_chip->nvm_size = 0;
2766  break;
2767  }
2768 
2769  switch (fcfg1_eesize) {
2770  case 0x00:
2771  case 0x01:
2772  case 0x02:
2773  case 0x03:
2774  case 0x04:
2775  case 0x05:
2776  case 0x06:
2777  case 0x07:
2778  case 0x08:
2779  case 0x09:
2780  ee_size = (16 << (10 - fcfg1_eesize));
2781  break;
2782  default:
2783  ee_size = 0;
2784  break;
2785  }
2786 
2787  switch (fcfg1_depart) {
2788  case 0x01:
2789  case 0x02:
2790  case 0x03:
2791  case 0x04:
2792  case 0x05:
2793  case 0x06:
2794  k_chip->dflash_size = k_chip->nvm_size - (4096 << fcfg1_depart);
2795  break;
2796  case 0x07:
2797  case 0x08:
2798  k_chip->dflash_size = 0;
2799  break;
2800  case 0x09:
2801  case 0x0a:
2802  case 0x0b:
2803  case 0x0c:
2804  case 0x0d:
2805  k_chip->dflash_size = 4096 << (fcfg1_depart & 0x7);
2806  break;
2807  default:
2808  k_chip->dflash_size = k_chip->nvm_size;
2809  break;
2810  }
2811  }
2812 
2813  switch (fcfg1_pfsize) {
2814  case 0x00:
2815  k_chip->pflash_size = 8192;
2816  break;
2817  case 0x01:
2818  case 0x03:
2819  case 0x05:
2820  case 0x07:
2821  case 0x09:
2822  case 0x0b:
2823  case 0x0d:
2824  k_chip->pflash_size = 1 << (14 + (fcfg1_pfsize >> 1));
2825  break;
2826  case 0x0f:
2827  /* a peculiar case: Freescale states different sizes for 0xf
2828  * KL03P24M48SF0RM 32 KB .... duplicate of code 0x3
2829  * K02P64M100SFARM 128 KB ... duplicate of code 0x7
2830  * K22P121M120SF8RM 256 KB ... duplicate of code 0x9
2831  * K22P121M120SF7RM 512 KB ... duplicate of code 0xb
2832  * K22P100M120SF5RM 1024 KB ... duplicate of code 0xd
2833  * K26P169M180SF5RM 2048 KB ... the only unique value
2834  * fcfg2_maxaddr0 seems to be the only clue to pflash_size
2835  * Checking fcfg2_maxaddr0 in bank probe is pointless then
2836  */
2837  if (fcfg2_pflsh)
2838  k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks;
2839  else
2840  k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks / 2;
2841  if (k_chip->pflash_size != 2048<<10)
2842  LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %" PRIu32 " KB", k_chip->pflash_size>>10);
2843 
2844  break;
2845  default:
2846  k_chip->pflash_size = 0;
2847  break;
2848  }
2849 
2850  if (k_chip->flash_support & FS_PROGRAM_SECTOR && k_chip->max_flash_prog_size == 0) {
2851  k_chip->max_flash_prog_size = k_chip->pflash_sector_size;
2852  /* Program section size is equal to sector size by default */
2853  }
2854 
2855  if (fcfg2_pflsh) {
2856  k_chip->num_pflash_blocks = num_blocks;
2857  k_chip->num_nvm_blocks = 0;
2858  } else {
2859  k_chip->num_pflash_blocks = (num_blocks + 1) / 2;
2860  k_chip->num_nvm_blocks = num_blocks - k_chip->num_pflash_blocks;
2861  }
2862 
2863  if (use_nvm_marking) {
2864  nvm_marking[0] = k_chip->num_nvm_blocks ? 'X' : 'N';
2865  nvm_marking[1] = '\0';
2866  } else
2867  nvm_marking[0] = '\0';
2868 
2869  pflash_size_k = k_chip->pflash_size / 1024;
2870  pflash_size_m = pflash_size_k / 1024;
2871  if (pflash_size_m)
2872  snprintf(flash_marking, sizeof(flash_marking), "%s%" PRIu32 "M0xxx", nvm_marking, pflash_size_m);
2873  else
2874  snprintf(flash_marking, sizeof(flash_marking), "%s%" PRIu32 "xxx", nvm_marking, pflash_size_k);
2875 
2876  snprintf(k_chip->name, sizeof(k_chip->name), name, flash_marking);
2877  LOG_INFO("Kinetis %s detected: %u flash blocks", k_chip->name, num_blocks);
2878  LOG_INFO("%u PFlash banks: %" PRIu32 " KiB total", k_chip->num_pflash_blocks, pflash_size_k);
2879  if (k_chip->num_nvm_blocks) {
2880  nvm_size_k = k_chip->nvm_size / 1024;
2881  dflash_size_k = k_chip->dflash_size / 1024;
2882  LOG_INFO("%u FlexNVM banks: %" PRIu32 " KiB total, %" PRIu32 " KiB available as data flash, %"
2883  PRIu32 " bytes FlexRAM", k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size);
2884  }
2885 
2886  k_chip->probed = true;
2887 
2888  if (create_banks)
2890 
2891  return ERROR_OK;
2892 }
2893 
2894 static int kinetis_probe(struct flash_bank *bank)
2895 {
2896  int result;
2897  uint8_t fcfg2_maxaddr0, fcfg2_pflsh, fcfg2_maxaddr1;
2898  unsigned int num_blocks, first_nvm_bank;
2899  uint32_t size_k;
2900  struct kinetis_flash_bank *k_bank = bank->driver_priv;
2901  struct kinetis_chip *k_chip;
2902 
2903  assert(k_bank);
2904  k_chip = k_bank->k_chip;
2905 
2906  k_bank->probed = false;
2907 
2908  if (!k_chip->probed) {
2909  switch (k_chip->chip_type) {
2910  case CT_S32K:
2911  result = kinetis_probe_chip_s32k(k_chip);
2912  break;
2913  default:
2914  result = kinetis_probe_chip(k_chip);
2915  }
2916  if (result != ERROR_OK)
2917  return result;
2918  }
2919 
2920  num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
2921  first_nvm_bank = k_chip->num_pflash_blocks;
2922 
2923  if (k_bank->bank_number < k_chip->num_pflash_blocks) {
2924  /* pflash, banks start at address zero */
2925  k_bank->flash_class = FC_PFLASH;
2926  bank->size = (k_chip->pflash_size / k_chip->num_pflash_blocks);
2927  bank->base = k_chip->pflash_base + bank->size * k_bank->bank_number;
2928  k_bank->prog_base = 0x00000000 + bank->size * k_bank->bank_number;
2929  k_bank->sector_size = k_chip->pflash_sector_size;
2930  /* pflash is divided into 32 protection areas for
2931  * parts with more than 32K of PFlash. For parts with
2932  * less the protection unit is set to 1024 bytes */
2933  k_bank->protection_size = MAX(k_chip->pflash_size / 32, 1024);
2934  bank->num_prot_blocks = bank->size / k_bank->protection_size;
2935  k_bank->protection_block = bank->num_prot_blocks * k_bank->bank_number;
2936 
2937  size_k = bank->size / 1024;
2938  LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k PFlash, FTFx base 0x%08" PRIx32 ", sect %" PRIu32,
2939  k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
2940 
2941  } else if (k_bank->bank_number < num_blocks) {
2942  /* nvm, banks start at address 0x10000000 */
2943  unsigned int nvm_ord = k_bank->bank_number - first_nvm_bank;
2944  uint32_t limit;
2945 
2946  k_bank->flash_class = FC_FLEX_NVM;
2947  bank->size = k_chip->nvm_size / k_chip->num_nvm_blocks;
2948  bank->base = k_chip->nvm_base + bank->size * nvm_ord;
2949  k_bank->prog_base = 0x00800000 + bank->size * nvm_ord;
2950  k_bank->sector_size = k_chip->nvm_sector_size;
2951  if (k_chip->dflash_size == 0) {
2952  k_bank->protection_size = 0;
2953  } else {
2954  int i;
2955  for (i = k_chip->dflash_size; ~i & 1; i >>= 1)
2956  ;
2957  if (i == 1)
2958  k_bank->protection_size = k_chip->dflash_size / 8; /* data flash size = 2^^n */
2959  else
2960  k_bank->protection_size = k_chip->nvm_size / 8; /* TODO: verify on SF1, not documented in RM */
2961  }
2962  bank->num_prot_blocks = 8 / k_chip->num_nvm_blocks;
2963  k_bank->protection_block = bank->num_prot_blocks * nvm_ord;
2964 
2965  /* EEPROM backup part of FlexNVM is not accessible, use dflash_size as a limit */
2966  if (k_chip->dflash_size > bank->size * nvm_ord)
2967  limit = k_chip->dflash_size - bank->size * nvm_ord;
2968  else
2969  limit = 0;
2970 
2971  if (bank->size > limit) {
2972  bank->size = limit;
2973  LOG_DEBUG("FlexNVM bank %u limited to 0x%08" PRIx32 " due to active EEPROM backup",
2974  k_bank->bank_number, limit);
2975  }
2976 
2977  size_k = bank->size / 1024;
2978  LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k FlexNVM, FTFx base 0x%08" PRIx32 ", sect %" PRIu32,
2979  k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
2980 
2981  } else {
2982  LOG_ERROR("Cannot determine parameters for bank %u, only %u banks on device",
2983  k_bank->bank_number, num_blocks);
2984  return ERROR_FLASH_BANK_INVALID;
2985  }
2986 
2987  /* S32K1xx does not implement FCFG2 register. Skip checks. */
2988  if (k_chip->chip_type != CT_S32K) {
2989  fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
2990  fcfg2_maxaddr0 = (uint8_t)((k_chip->sim_fcfg2 >> 24) & 0x7f);
2991  fcfg2_maxaddr1 = (uint8_t)((k_chip->sim_fcfg2 >> 16) & 0x7f);
2992 
2993  if (k_bank->bank_number == 0 && k_chip->fcfg2_maxaddr0_shifted != bank->size)
2994  LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed,"
2995  " please report to OpenOCD mailing list", fcfg2_maxaddr0);
2996 
2997  if (fcfg2_pflsh) {
2998  if (k_bank->bank_number == 1 && k_chip->fcfg2_maxaddr1_shifted != bank->size)
2999  LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed,"
3000  " please report to OpenOCD mailing list", fcfg2_maxaddr1);
3001  } else {
3002  if (k_bank->bank_number == first_nvm_bank
3003  && k_chip->fcfg2_maxaddr1_shifted != k_chip->dflash_size)
3004  LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check failed,"
3005  " please report to OpenOCD mailing list", fcfg2_maxaddr1);
3006  }
3007  }
3008 
3009  free(bank->sectors);
3010  bank->sectors = NULL;
3011 
3012  free(bank->prot_blocks);
3013  bank->prot_blocks = NULL;
3014 
3015  if (k_bank->sector_size == 0) {
3016  LOG_ERROR("Unknown sector size for bank %u", bank->bank_number);
3017  return ERROR_FLASH_BANK_INVALID;
3018  }
3019 
3020  bank->num_sectors = bank->size / k_bank->sector_size;
3021 
3022  if (bank->num_sectors > 0) {
3023  /* FlexNVM bank can be used for EEPROM backup therefore zero sized */
3024  bank->sectors = alloc_block_array(0, k_bank->sector_size, bank->num_sectors);
3025  if (!bank->sectors)
3026  return ERROR_FAIL;
3027 
3028  bank->prot_blocks = alloc_block_array(0, k_bank->protection_size, bank->num_prot_blocks);
3029  if (!bank->prot_blocks)
3030  return ERROR_FAIL;
3031 
3032  } else {
3033  bank->num_prot_blocks = 0;
3034  }
3035 
3036  k_bank->probed = true;
3037 
3038  return ERROR_OK;
3039 }
3040 
3042 {
3043  struct kinetis_flash_bank *k_bank = bank->driver_priv;
3044 
3045  if (k_bank && k_bank->probed)
3046  return ERROR_OK;
3047 
3048  return kinetis_probe(bank);
3049 }
3050 
3051 static int kinetis_info(struct flash_bank *bank, struct command_invocation *cmd)
3052 {
3053  const char *bank_class_names[] = {
3054  "(ANY)", "PFlash", "FlexNVM", "FlexRAM"
3055  };
3056 
3057  struct kinetis_flash_bank *k_bank = bank->driver_priv;
3058  struct kinetis_chip *k_chip = k_bank->k_chip;
3059  uint32_t size_k = bank->size / 1024;
3060 
3062  "%s %s: %" PRIu32 "k %s bank %s at " TARGET_ADDR_FMT,
3063  bank->driver->name, k_chip->name,
3064  size_k, bank_class_names[k_bank->flash_class],
3065  bank->name, bank->base);
3066 
3067  return ERROR_OK;
3068 }
3069 
3071 {
3072  struct kinetis_flash_bank *k_bank = bank->driver_priv;
3073  struct kinetis_chip *k_chip = k_bank->k_chip;
3074  int result;
3075 
3076  /* surprisingly blank check does not work in VLPR and HSRUN modes */
3077  result = kinetis_check_run_mode(k_chip);
3078  if (result != ERROR_OK)
3079  return result;
3080 
3081  /* reset error flags */
3082  result = kinetis_ftfx_prepare(bank->target);
3083  if (result != ERROR_OK)
3084  return result;
3085 
3086  if (k_bank->flash_class == FC_PFLASH || k_bank->flash_class == FC_FLEX_NVM) {
3087  bool block_dirty = true;
3088  bool use_block_cmd = !(k_chip->flash_support & FS_NO_CMD_BLOCKSTAT);
3089  uint8_t ftfx_fstat;
3090 
3091  if (use_block_cmd && k_bank->flash_class == FC_FLEX_NVM) {
3092  uint8_t fcfg1_depart = (uint8_t)((k_chip->sim_fcfg1 >> 8) & 0x0f);
3093  /* block operation cannot be used on FlexNVM when EEPROM backup partition is set */
3094  if (fcfg1_depart != 0xf && fcfg1_depart != 0)
3095  use_block_cmd = false;
3096  }
3097 
3098  if (use_block_cmd) {
3099  /* check if whole bank is blank */
3100  result = kinetis_ftfx_command(bank->target, FTFX_CMD_BLOCKSTAT, k_bank->prog_base,
3101  0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
3102 
3103  if (result != ERROR_OK)
3104  kinetis_ftfx_clear_error(bank->target);
3105  else if ((ftfx_fstat & 0x01) == 0)
3106  block_dirty = false;
3107  }
3108 
3109  if (block_dirty) {
3110  /* the whole bank is not erased, check sector-by-sector */
3111  for (unsigned int i = 0; i < bank->num_sectors; i++) {
3112  /* normal margin */
3113  result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTSTAT,
3114  k_bank->prog_base + bank->sectors[i].offset,
3115  1, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
3116 
3117  if (result == ERROR_OK) {
3118  bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);
3119  } else {
3120  LOG_DEBUG("Ignoring error on PFlash sector blank-check");
3121  kinetis_ftfx_clear_error(bank->target);
3122  bank->sectors[i].is_erased = -1;
3123  }
3124  }
3125  } else {
3126  /* the whole bank is erased, update all sectors */
3127  for (unsigned int i = 0; i < bank->num_sectors; i++)
3128  bank->sectors[i].is_erased = 1;
3129  }
3130  } else {
3131  LOG_WARNING("kinetis_blank_check not supported yet for FlexRAM");
3133  }
3134 
3135  return ERROR_OK;
3136 }
3137 
3138 
3139 COMMAND_HANDLER(kinetis_nvm_partition)
3140 {
3141  int result;
3142  unsigned int bank_idx;
3143  unsigned int num_blocks, first_nvm_bank;
3144  unsigned long par, log2 = 0, ee1 = 0, ee2 = 0;
3145  enum { SHOW_INFO, DF_SIZE, EEBKP_SIZE } sz_type = SHOW_INFO;
3146  bool enable;
3147  uint8_t load_flex_ram = 1;
3148  uint8_t ee_size_code = 0x3f;
3149  uint8_t flex_nvm_partition_code = 0;
3150  uint8_t ee_split = 3;
3152  struct kinetis_chip *k_chip;
3153  uint32_t sim_fcfg1;
3154 
3155  k_chip = kinetis_get_chip(target);
3156 
3157  if (k_chip->chip_type == CT_S32K) {
3158  LOG_ERROR("NVM partition not supported on S32K1xx (yet).");
3159  return ERROR_FAIL;
3160  }
3161 
3162  if (CMD_ARGC >= 2) {
3163  if (strcmp(CMD_ARGV[0], "dataflash") == 0)
3164  sz_type = DF_SIZE;
3165  else if (strcmp(CMD_ARGV[0], "eebkp") == 0)
3166  sz_type = EEBKP_SIZE;
3167 
3168  COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], par);
3169  while (par >> (log2 + 3))
3170  log2++;
3171  }
3172  switch (sz_type) {
3173  case SHOW_INFO:
3174  if (!k_chip) {
3175  LOG_ERROR("Chip not probed.");
3176  return ERROR_FAIL;
3177  }
3178  result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &sim_fcfg1);
3179  if (result != ERROR_OK)
3180  return result;
3181 
3182  flex_nvm_partition_code = (uint8_t)((sim_fcfg1 >> 8) & 0x0f);
3183  switch (flex_nvm_partition_code) {
3184  case 0:
3185  command_print(CMD, "No EEPROM backup, data flash only");
3186  break;
3187  case 1:
3188  case 2:
3189  case 3:
3190  case 4:
3191  case 5:
3192  case 6:
3193  command_print(CMD, "EEPROM backup %d KB", 4 << flex_nvm_partition_code);
3194  break;
3195  case 8:
3196  command_print(CMD, "No data flash, EEPROM backup only");
3197  break;
3198  case 0x9:
3199  case 0xA:
3200  case 0xB:
3201  case 0xC:
3202  case 0xD:
3203  case 0xE:
3204  command_print(CMD, "data flash %d KB", 4 << (flex_nvm_partition_code & 7));
3205  break;
3206  case 0xf:
3207  command_print(CMD, "No EEPROM backup, data flash only (DEPART not set)");
3208  break;
3209  default:
3210  command_print(CMD, "Unsupported EEPROM backup size code 0x%02" PRIx8, flex_nvm_partition_code);
3211  }
3212  return ERROR_OK;
3213 
3214  case DF_SIZE:
3215  flex_nvm_partition_code = 0x8 | log2;
3216  break;
3217 
3218  case EEBKP_SIZE:
3219  flex_nvm_partition_code = log2;
3220  break;
3221  }
3222 
3223  if (CMD_ARGC == 3) {
3224  unsigned long eex;
3225  COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], eex);
3226  ee1 = ee2 = eex / 2;
3227  } else if (CMD_ARGC >= 4) {
3228  COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], ee1);
3229  COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[3], ee2);
3230  }
3231 
3232  enable = ee1 + ee2 > 0;
3233  if (enable) {
3234  for (log2 = 2; ; log2++) {
3235  if (ee1 + ee2 == (16u << 10) >> log2)
3236  break;
3237  if (ee1 + ee2 > (16u << 10) >> log2 || log2 >= 9) {
3238  LOG_ERROR("Unsupported EEPROM size");
3240  }
3241  }
3242 
3243  if (ee1 * 3 == ee2)
3244  ee_split = 1;
3245  else if (ee1 * 7 == ee2)
3246  ee_split = 0;
3247  else if (ee1 != ee2) {
3248  LOG_ERROR("Unsupported EEPROM sizes ratio");
3250  }
3251 
3252  ee_size_code = log2 | ee_split << 4;
3253  }
3254 
3255  if (CMD_ARGC >= 5)
3256  COMMAND_PARSE_ON_OFF(CMD_ARGV[4], enable);
3257  if (enable)
3258  load_flex_ram = 0;
3259 
3260  LOG_INFO("DEPART 0x%" PRIx8 ", EEPROM size code 0x%" PRIx8,
3261  flex_nvm_partition_code, ee_size_code);
3262 
3263  result = kinetis_check_run_mode(k_chip);
3264  if (result != ERROR_OK)
3265  return result;
3266 
3267  /* reset error flags */
3268  result = kinetis_ftfx_prepare(target);
3269  if (result != ERROR_OK)
3270  return result;
3271 
3272  result = kinetis_ftfx_command(target, FTFX_CMD_PGMPART, load_flex_ram,
3273  ee_size_code, flex_nvm_partition_code, 0, 0,
3274  0, 0, 0, 0, NULL);
3275  if (result != ERROR_OK)
3276  return result;
3277 
3278  command_print(CMD, "FlexNVM partition set. Please reset MCU.");
3279 
3280  if (k_chip) {
3281  first_nvm_bank = k_chip->num_pflash_blocks;
3282  num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
3283  for (bank_idx = first_nvm_bank; bank_idx < num_blocks; bank_idx++)
3284  k_chip->banks[bank_idx].probed = false; /* re-probe before next use */
3285  k_chip->probed = false;
3286  }
3287 
3288  command_print(CMD, "FlexNVM banks will be re-probed to set new data flash size.");
3289  return ERROR_OK;
3290 }
3291 
3292 COMMAND_HANDLER(kinetis_fcf_source_handler)
3293 {
3294  if (CMD_ARGC > 1)
3296 
3297  if (CMD_ARGC == 1) {
3298  if (strcmp(CMD_ARGV[0], "write") == 0)
3299  allow_fcf_writes = true;
3300  else if (strcmp(CMD_ARGV[0], "protection") == 0)
3301  allow_fcf_writes = false;
3302  else
3304  }
3305 
3306  if (allow_fcf_writes) {
3307  command_print(CMD, "Arbitrary Flash Configuration Field writes enabled.");
3308  command_print(CMD, "Protection info writes to FCF disabled.");
3309  LOG_WARNING("BEWARE: incorrect flash configuration may permanently lock the device.");
3310  } else {
3311  command_print(CMD, "Protection info writes to Flash Configuration Field enabled.");
3312  command_print(CMD, "Arbitrary FCF writes disabled. Mode safe from unwanted locking of the device.");
3313  }
3314 
3315  return ERROR_OK;
3316 }
3317 
3318 COMMAND_HANDLER(kinetis_fopt_handler)
3319 {
3320  if (CMD_ARGC > 1)
3322 
3323  if (CMD_ARGC == 1) {
3325  } else {
3326  command_print(CMD, "FCF_FOPT 0x%02" PRIx8, fcf_fopt);
3327  }
3328 
3329  return ERROR_OK;
3330 }
3331 
3332 COMMAND_HANDLER(kinetis_create_banks_handler)
3333 {
3334  if (CMD_ARGC > 0)
3336 
3337  create_banks = true;
3338 
3339  return ERROR_OK;
3340 }
3341 
3342 
3344  {
3345  .name = "check_security",
3346  .mode = COMMAND_EXEC,
3347  .help = "Check status of device security lock",
3348  .usage = "",
3349  .handler = kinetis_check_flash_security_status,
3350  },
3351  {
3352  .name = "halt",
3353  .mode = COMMAND_EXEC,
3354  .help = "Issue a halt via the MDM-AP",
3355  .usage = "",
3356  .handler = kinetis_mdm_halt,
3357  },
3358  {
3359  .name = "mass_erase",
3360  .mode = COMMAND_EXEC,
3361  .help = "Issue a complete flash erase via the MDM-AP",
3362  .usage = "",
3363  .handler = kinetis_mdm_mass_erase,
3364  },
3365  {
3366  .name = "reset",
3367  .mode = COMMAND_EXEC,
3368  .help = "Issue a reset via the MDM-AP",
3369  .usage = "",
3370  .handler = kinetis_mdm_reset,
3371  },
3373 };
3374 
3375 static const struct command_registration kinetis_exec_command_handlers[] = {
3376  {
3377  .name = "mdm",
3378  .mode = COMMAND_ANY,
3379  .help = "MDM-AP command group",
3380  .usage = "",
3382  },
3383  {
3384  .name = "disable_wdog",
3385  .mode = COMMAND_EXEC,
3386  .help = "Disable the watchdog timer",
3387  .usage = "",
3388  .handler = kinetis_disable_wdog_handler,
3389  },
3390  {
3391  .name = "nvm_partition",
3392  .mode = COMMAND_EXEC,
3393  .help = "Show/set data flash or EEPROM backup size in kilobytes,"
3394  " set two EEPROM sizes in bytes and FlexRAM loading during reset",
3395  .usage = "('info'|'dataflash' size|'eebkp' size) [eesize1 eesize2] ['on'|'off']",
3396  .handler = kinetis_nvm_partition,
3397  },
3398  {
3399  .name = "fcf_source",
3400  .mode = COMMAND_EXEC,
3401  .help = "Use protection as a source for Flash Configuration Field or allow writing arbitrary values to the FCF"
3402  " Mode 'protection' is safe from unwanted locking of the device.",
3403  .usage = "['protection'|'write']",
3404  .handler = kinetis_fcf_source_handler,
3405  },
3406  {
3407  .name = "fopt",
3408  .mode = COMMAND_EXEC,
3409  .help = "FCF_FOPT value source in 'kinetis fcf_source protection' mode",
3410  .usage = "[num]",
3411  .handler = kinetis_fopt_handler,
3412  },
3413  {
3414  .name = "create_banks",
3415  .mode = COMMAND_CONFIG,
3416  .help = "Driver creates additional banks if device with two/four flash blocks is probed",
3417  .handler = kinetis_create_banks_handler,
3418  .usage = "",
3419  },
3421 };
3422 
3423 static const struct command_registration kinetis_command_handler[] = {
3424  {
3425  .name = "kinetis",
3426  .mode = COMMAND_ANY,
3427  .help = "Kinetis flash controller commands",
3428  .usage = "",
3430  },
3432 };
3433 
3434 
3435 
3436 const struct flash_driver kinetis_flash = {
3437  .name = "kinetis",
3438  .commands = kinetis_command_handler,
3439  .flash_bank_command = kinetis_flash_bank_command,
3440  .erase = kinetis_erase,
3441  .protect = kinetis_protect,
3442  .write = kinetis_write,
3443  .read = default_flash_read,
3444  .probe = kinetis_probe,
3445  .auto_probe = kinetis_auto_probe,
3446  .erase_check = kinetis_blank_check,
3447  .protect_check = kinetis_protect_check,
3448  .info = kinetis_info,
3449  .free_driver_priv = kinetis_free_driver_priv,
3450 };
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
Definition: algorithm.c:29
void destroy_reg_param(struct reg_param *param)
Definition: algorithm.c:37
@ PARAM_OUT
Definition: algorithm.h:16
@ PARAM_IN_OUT
Definition: algorithm.h:17
@ ARM_MODE_THREAD
Definition: arm.h:94
struct adiv5_ap * dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1189
int dap_put_ap(struct adiv5_ap *ap)
Definition: arm_adi_v5.c:1209
This defines formats and data structures used to talk to ADIv5 entities.
static int dap_queue_ap_read(struct adiv5_ap *ap, unsigned int reg, uint32_t *data)
Queue an AP register read.
Definition: arm_adi_v5.h:590
static int dap_queue_ap_write(struct adiv5_ap *ap, unsigned int reg, uint32_t data)
Queue an AP register write.
Definition: arm_adi_v5.h:610
static int dap_run(struct adiv5_dap *dap)
Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they ar...
Definition: arm_adi_v5.h:648
const char * name
Definition: armv4_5.c:76
#define ARMV7M_COMMON_MAGIC
Definition: armv7m.h:220
Support functions to access arbitrary bits in a byte array.
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:104
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:420
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:443
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
#define COMMAND_PARSE_ON_OFF(in, out)
parses an on/off command argument
Definition: command.h:530
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:402
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:442
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:146
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
@ COMMAND_CONFIG
Definition: command.h:41
@ COMMAND_ANY
Definition: command.h:42
@ COMMAND_EXEC
Definition: command.h:40
static struct cortex_m_common * target_to_cm(struct target *target)
Definition: cortex_m.h:287
uint8_t bank
Definition: esirisc.c:135
int mask
Definition: esirisc.c:1741
#define ERROR_FLASH_OPER_UNSUPPORTED
Definition: flash/common.h:36
#define ERROR_FLASH_BANK_INVALID
Definition: flash/common.h:28
#define ERROR_FLASH_OPERATION_FAILED
Definition: flash/common.h:30
#define ERROR_FLASH_DST_BREAKS_ALIGNMENT
Definition: flash/common.h:32
struct flash_sector * alloc_block_array(uint32_t offset, uint32_t size, unsigned int num_blocks)
Allocate and fill an array of sectors or protection blocks.
void flash_bank_add(struct flash_bank *bank)
Adds a new NOR bank to the global list of banks.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
struct flash_bank * flash_bank_list(void)
void jtag_poll_set_enabled(bool value)
Assign flag reporting whether JTAG polling is disallowed.
Definition: jtag/core.c:165
int adapter_deassert_reset(void)
Definition: jtag/core.c:1899
enum reset_types jtag_get_reset_config(void)
Definition: jtag/core.c:1734
int adapter_assert_reset(void)
Definition: jtag/core.c:1879
@ RESET_HAS_SRST
Definition: jtag.h:219
#define KINETIS_SOPT1_RAMSIZE_K24FN1M
Definition: kinetis.c:150
#define KINETIS_K_SDID_K60_M100
Definition: kinetis.c:190
#define KINETIS_SDID_DIEID_K22FN256
Definition: kinetis.c:157
#define PM_STAT_RUN
Definition: kinetis.c:115
#define KINETIS_SDID_SERIESID_MASK
Definition: kinetis.c:197
static int kinetis_probe_chip_s32k(struct kinetis_chip *k_chip)
Definition: kinetis.c:2096
static int kinetis_protect_check(struct flash_bank *bank)
Definition: kinetis.c:1416
#define KINETIS_K_SDID_K22_M50
Definition: kinetis.c:181
#define WDOG_BASE
Definition: kinetis.c:94
#define WDOG32_KE1X
Definition: kinetis.c:95
#define KINETIS_SDID_PROJECTID_KE1XF
Definition: kinetis.c:231
#define KINETIS_SDID_FAMILYID_SHIFT
Definition: kinetis.c:216
#define FTFX_CMD_SECTERASE
Definition: kinetis.c:123
static int kinetis_create_missing_banks(struct kinetis_chip *k_chip)
Definition: kinetis.c:978
#define PM_CTRL_RUNM_RUN
Definition: kinetis.c:117
#define FCF_FPROT
Definition: kinetis.c:74
#define SIM_FCFG1_OFFSET
Definition: kinetis.c:108
#define KINETIS_SDID_SUBFAMID_MASK
Definition: kinetis.c:205
static int kinetis_info(struct flash_bank *bank, struct command_invocation *cmd)
Definition: kinetis.c:3051
#define KINETIS_SDID_SERIESID_KL
Definition: kinetis.c:199
#define MDM_AP
Definition: kinetis.c:383
#define KINETIS_SDID_S32K_SERIES_MASK
Definition: kinetis.c:244
static int kinetis_blank_check(struct flash_bank *bank)
Definition: kinetis.c:3070
#define KINETIS_K_SDID_K21_M120
Definition: kinetis.c:180
#define SIM_SDID_OFFSET
Definition: kinetis.c:107
#define FCF_SIZE
Definition: kinetis.c:78
#define MDM_STAT_SYSSEC
Definition: kinetis.c:391
static bool create_banks
Definition: kinetis.c:417
#define KINETIS_K_SDID_K30_M100
Definition: kinetis.c:184
#define KINETIS_K_SDID_K12
Definition: kinetis.c:174
#define KINETIS_K_SDID_K40_M72
Definition: kinetis.c:185
static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t wcount)
Definition: kinetis.c:1302
#define FTFX_CMD_SETFLEXRAM
Definition: kinetis.c:127
static int kinetis_probe(struct flash_bank *bank)
Definition: kinetis.c:2894
#define KINETIS_SDID_FAMILYID_K1X
Definition: kinetis.c:219
#define KINETIS_SDID_SUBFAMID_KX6
Definition: kinetis.c:212
#define KINETIS_MAX_BANKS
Definition: kinetis.c:276
#define MDM_CTRL_CORE_HOLD_RES
Definition: kinetis.c:407
static int kinetis_chip_options(struct kinetis_chip *k_chip, int argc, const char *argv[])
Definition: kinetis.c:904
#define SMC32_PMSTAT
Definition: kinetis.c:100
#define KINETIS_SDID_S32K_SERIES_K14X
Definition: kinetis.c:246
#define FTFX_FCNFG
Definition: kinetis.c:86
static int kinetis_disable_wdog32(struct target *target, uint32_t wdog_base)
Definition: kinetis.c:1136
#define KINETIS_SDID_FAMILYID_K3X
Definition: kinetis.c:221
#define KINETIS_K_SDID_K60_M150
Definition: kinetis.c:191
#define MDM_STAT_FMEEN
Definition: kinetis.c:393
#define SMC_PMCTRL
Definition: kinetis.c:97
#define MDM_REG_ID
Definition: kinetis.c:387
#define KINETIS_SDID_DIEID_K24FN1M
Definition: kinetis.c:161
#define KINETIS_SDID_FAMILYID_MASK
Definition: kinetis.c:217
#define KINETIS_K_REVID_MASK
Definition: kinetis.c:194
#define KINETIS_K_SDID_K20_M100
Definition: kinetis.c:177
static int kinetis_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
Definition: kinetis.c:1393
#define WDOG32_KL28
Definition: kinetis.c:96
#define KINETIS_K_SDID_K22_M120
Definition: kinetis.c:182
#define KINETIS_SDID_PROJECTID_MASK
Definition: kinetis.c:230
static const uint8_t kinetis_flash_write_code[]
Definition: kinetis.c:1297
static const struct kinetis_type kinetis_types_old[]
Definition: kinetis.c:349
#define KINETIS_SDID_FAMILYID_KL8X
Definition: kinetis.c:227
#define KINETIS_SDID_FAMILYID_K5X
Definition: kinetis.c:223
COMMAND_HANDLER(kinetis_mdm_halt)
Definition: kinetis.c:507
static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: kinetis.c:1979
static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf)
Definition: kinetis.c:1461
#define KINETIS_K_SDID_K40_M100
Definition: kinetis.c:186
#define SMC_PMSTAT
Definition: kinetis.c:98
#define KINETIS_SDID_SERIESID_K
Definition: kinetis.c:198
#define KINETIS_SDID_SERIESID_KV
Definition: kinetis.c:202
#define FCF_ADDRESS
Definition: kinetis.c:73
#define KINETIS_SDID_S32K_DERIVATE_KXX8
Definition: kinetis.c:254
static const struct command_registration kinetis_exec_command_handlers[]
Definition: kinetis.c:3375
#define KINETIS_SDID_SUBFAMID_KX2
Definition: kinetis.c:208
static uint8_t fcf_fopt
Definition: kinetis.c:416
#define FTFX_CMD_BLOCKSTAT
Definition: kinetis.c:120
#define KINETIS_K_SDID_TYPE_MASK
Definition: kinetis.c:168
#define KINETIS_K_SDID_K70_M150
Definition: kinetis.c:192
static int kinetis_make_ram_ready(struct target *target)
Definition: kinetis.c:1751
#define KINETIS_SDID_FAMILYID_K4X
Definition: kinetis.c:222
#define KINETIS_K_SDID_K53
Definition: kinetis.c:189
static int kinetis_probe_chip(struct kinetis_chip *k_chip)
Definition: kinetis.c:2264
#define KINETIS_SDID_DIEID_MASK
Definition: kinetis.c:154
#define KINETIS_K_REVID_SHIFT
Definition: kinetis.c:195
#define KINETIS_SDID_PROJECTID_KE1XZ
Definition: kinetis.c:232
static int kinetis_disable_wdog_kx(struct target *target)
Definition: kinetis.c:1104
static int kinetis_ftfx_clear_error(struct target *target)
Definition: kinetis.c:1263
#define KINETIS_SDID_S32K_DERIVATE_KXX5
Definition: kinetis.c:252
#define KINETIS_SDID_SERIESID_KW
Definition: kinetis.c:201
#define FCF_FOPT
Definition: kinetis.c:76
static int kinetis_check_run_mode(struct kinetis_chip *k_chip)
Definition: kinetis.c:1600
#define KINETIS_SDID_K_SERIES_MASK
Definition: kinetis.c:152
#define KINETIS_SDID_SUBFAMID_KX8
Definition: kinetis.c:214
#define KINETIS_SDID_S32K_DERIVATE_KXX4
Definition: kinetis.c:251
#define SIM_FCFG2_OFFSET
Definition: kinetis.c:109
#define KINETIS_SDID_S32K_DERIVATE_KXX3
Definition: kinetis.c:250
#define KINETIS_K_SDID_K10_M100
Definition: kinetis.c:171
#define KINETIS_SDID_SUBFAMID_KX7
Definition: kinetis.c:213
#define PM_STAT_VLPR
Definition: kinetis.c:116
static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: kinetis.c:1879
#define KINETIS_SDID_FAMILYID_K8X
Definition: kinetis.c:226
static int kinetis_auto_probe(struct flash_bank *bank)
Definition: kinetis.c:3041
#define KINETIS_K_SDID_K20_M120
Definition: kinetis.c:178
#define KINETIS_SDID_SUBFAMID_SHIFT
Definition: kinetis.c:204
#define KINETIS_SDID_SUBFAMID_KX0
Definition: kinetis.c:206
#define MDM_REG_STAT
Definition: kinetis.c:385
static int kinetis_ftfx_command(struct target *target, uint8_t fcmd, uint32_t faddr, uint8_t fccob4, uint8_t fccob5, uint8_t fccob6, uint8_t fccob7, uint8_t fccob8, uint8_t fccob9, uint8_t fccoba, uint8_t fccobb, uint8_t *ftfx_fstat)
Definition: kinetis.c:1520
#define FMC_PFB01CR
Definition: kinetis.c:84
#define MDM_CTRL_FMEIP
Definition: kinetis.c:403
#define MSCM_OCMDR0
Definition: kinetis.c:82
#define MCM_PLACR
Definition: kinetis.c:103
#define SIM_BASE_KL28
Definition: kinetis.c:91
#define KINETIS_SDID_SUBFAMID_KX3
Definition: kinetis.c:209
#define KINETIS_K_SDID_K10_M120
Definition: kinetis.c:172
#define KINETIS_SDID_FAMILYID_K0X
Definition: kinetis.c:218
#define SIM_COPC
Definition: kinetis.c:92
static void kinetis_invalidate_flash_cache(struct kinetis_chip *k_chip)
Definition: kinetis.c:1660
#define KINETIS_SDID_FAMILYID_K2X
Definition: kinetis.c:220
static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: kinetis.c:1782
const struct flash_driver kinetis_flash
Definition: kinetis.c:420
#define KINETIS_K_SDID_K30_M72
Definition: kinetis.c:183
static const uint32_t kinetis_known_mdm_ids[]
Definition: kinetis.c:751
#define KINETIS_SDID_SUBFAMID_KX5
Definition: kinetis.c:211
FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
Definition: kinetis.c:918
static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned int reg, uint32_t *result)
Definition: kinetis.c:456
static void kinetis_free_driver_priv(struct flash_bank *bank)
Definition: kinetis.c:962
#define SIM_SOPT1_OFFSET
Definition: kinetis.c:106
#define KINETIS_SDID_SUBFAMID_KX1
Definition: kinetis.c:207
#define KINETIS_K_SDID_K11
Definition: kinetis.c:173
#define KINETIS_K_SDID_K20_M72
Definition: kinetis.c:176
#define KINETIS_SDID_S32K_SERIES_K11X
Definition: kinetis.c:245
static int kinetis_ftfx_prepare(struct target *target)
Definition: kinetis.c:1270
#define KINETIS_SDID_DIEID_K22FN128
Definition: kinetis.c:156
#define KINETIS_K_SDID_K10_M50
Definition: kinetis.c:169
#define FTFX_CMD_SECTSTAT
Definition: kinetis.c:121
#define SMC32_PMCTRL
Definition: kinetis.c:99
#define FTFX_CMD_PGMPART
Definition: kinetis.c:126
#define KINETIS_SDID_S32K_DERIVATE_MASK
Definition: kinetis.c:248
static bool allow_fcf_writes
Definition: kinetis.c:415
static struct kinetis_chip * kinetis_get_chip(struct target *target)
Definition: kinetis.c:883
#define FTFX_FDPROT
Definition: kinetis.c:89
static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned int reg, uint32_t value)
Definition: kinetis.c:428
#define FTFX_CMD_LWORDPROG
Definition: kinetis.c:122
#define SIM_BASE
Definition: kinetis.c:90
#define FTFX_FPROT3
Definition: kinetis.c:88
#define KINETIS_K_SDID_K10_M72
Definition: kinetis.c:170
#define FCF_FSEC
Definition: kinetis.c:75
#define FLEXRAM
Definition: kinetis.c:80
static int kinetis_disable_wdog(struct kinetis_chip *k_chip)
Definition: kinetis.c:1169
#define KINETIS_SDID_DIEID_K22FN512
Definition: kinetis.c:158
#define KINETIS_SDID_S32K_DERIVATE_KXX2
Definition: kinetis.c:249
#define KINETIS_SDID_DIEID_K24FN256
Definition: kinetis.c:159
#define PMC_REGSC
Definition: kinetis.c:101
#define KINETIS_SDID_SERIESID_KE
Definition: kinetis.c:200
#define MDM_ACCESS_TIMEOUT
Definition: kinetis.c:412
#define MDM_STAT_FREADY
Definition: kinetis.c:390
static int kinetis_mdm_poll_register(struct adiv5_dap *dap, unsigned int reg, uint32_t mask, uint32_t value, uint32_t timeout_ms)
Definition: kinetis.c:482
#define FTFX_FCCOB3
Definition: kinetis.c:87
#define MDM_REG_CTRL
Definition: kinetis.c:386
#define MDM_STAT_SYSRES
Definition: kinetis.c:392
static int kinetis_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: kinetis.c:1693
#define KINETIS_K_SDID_K51_M72
Definition: kinetis.c:188
#define WDOG32_CS_OFFSET
Definition: kinetis.c:112
static const struct command_registration kinetis_command_handler[]
Definition: kinetis.c:3423
static int kinetis_read_pmstat(struct kinetis_chip *k_chip, uint8_t *pmstat)
Definition: kinetis.c:1569
#define KINETIS_SOPT1_RAMSIZE_MASK
Definition: kinetis.c:149
static int kinetis_disable_wdog_algo(struct target *target, size_t code_size, const uint8_t *code, uint32_t wdog_base)
Definition: kinetis.c:1060
#define KINETIS_SDID_FAMILYID_K6X
Definition: kinetis.c:224
static int kinetis_ftfx_decode_error(uint8_t fstat)
Definition: kinetis.c:1242
#define KINETIS_K_SDID_K50_M72
Definition: kinetis.c:187
#define FTFX_FSTAT
Definition: kinetis.c:85
#define KINETIS_SDID_S32K_DERIVATE_KXX6
Definition: kinetis.c:253
#define FTFX_CMD_SECTWRITE
Definition: kinetis.c:124
#define FCF_FDPROT
Definition: kinetis.c:77
#define MSCM_OCMDR1
Definition: kinetis.c:83
#define KINETIS_K_SDID_K21_M50
Definition: kinetis.c:179
static const struct command_registration kinetis_security_command_handlers[]
Definition: kinetis.c:3343
#define KINETIS_K_SDID_K20_M50
Definition: kinetis.c:175
#define MDM_CTRL_SYS_RES_REQ
Definition: kinetis.c:406
#define WDOG_STCTRLH_OFFSET
Definition: kinetis.c:111
#define MC_PMCTRL
Definition: kinetis.c:102
#define KINETIS_SDID_SUBFAMID_KX4
Definition: kinetis.c:210
void alive_sleep(uint64_t ms)
Definition: log.c:456
void keep_alive(void)
Definition: log.c:415
#define LOG_WARNING(expr ...)
Definition: log.h:129
#define ERROR_FAIL
Definition: log.h:170
#define LOG_ERROR(expr ...)
Definition: log.h:132
#define LOG_INFO(expr ...)
Definition: log.h:126
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:164
#define FLASH_WRITE_GAP_SECTOR
Definition: nor/core.h:63
#define MAX(a, b)
Definition: replacements.h:25
struct target * target
Definition: rtt/rtt.c:26
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
struct rtt_source source
Definition: rtt/rtt.c:23
This represents an ARM Debug Interface (v5) Access Port (AP).
Definition: arm_adi_v5.h:250
struct adiv5_dap * dap
DAP this AP belongs to.
Definition: arm_adi_v5.h:254
This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
Definition: arm_adi_v5.h:348
const struct dap_ops * ops
Definition: arm_adi_v5.h:349
struct adiv5_dap * dap
For targets conforming to ARM Debug Interface v5, this handle references the Debug Access Port (DAP) ...
Definition: arm.h:257
unsigned int common_magic
Definition: armv7m.h:295
enum arm_mode core_mode
Definition: armv7m.h:297
struct arm arm
Definition: armv7m.h:225
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
const char * name
Definition: command.h:235
struct armv7m_common armv7m
Definition: cortex_m.h:224
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
unsigned int num_prot_blocks
The number of protection blocks in this bank.
Definition: nor/core.h:124
const struct flash_driver * driver
Driver for this bank.
Definition: nor/core.h:80
void * driver_priv
Private driver storage pointer.
Definition: nor/core.h:81
struct flash_sector * prot_blocks
Array of protection blocks, allocated and initialized by the flash driver.
Definition: nor/core.h:126
struct flash_bank * next
The next flash bank on this chip.
Definition: nor/core.h:128
struct target * target
Target to which this bank belongs.
Definition: nor/core.h:78
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
int is_protected
Indication of protection status: 0 = unprotected/unlocked, 1 = protected/locked, other = unknown.
Definition: nor/core.h:55
uint32_t nvm_base
Definition: kinetis.c:294
enum kinetis_chip::@10 watchdog_type
uint32_t sim_sdid
Definition: kinetis.c:282
unsigned int nvm_sector_size
Definition: kinetis.c:289
struct kinetis_flash_bank banks[KINETIS_MAX_BANKS]
Definition: kinetis.c:341
char name[40]
Definition: kinetis.c:338
uint32_t pflash_size
Definition: kinetis.c:293
uint32_t sim_fcfg2
Definition: kinetis.c:284
uint32_t sim_fcfg1
Definition: kinetis.c:283
uint32_t nvm_size
Definition: kinetis.c:295
struct target * target
Definition: kinetis.c:279
@ KINETIS_SMC32
Definition: kinetis.c:334
unsigned int num_nvm_blocks
Definition: kinetis.c:288
enum kinetis_chip::@7 chip_type
enum kinetis_chip::@8 flash_support
unsigned int pflash_sector_size
Definition: kinetis.c:289
enum kinetis_chip::@9 cache_type
uint32_t sim_base
Definition: kinetis.c:299
@ FS_PROGRAM_PHRASE
Definition: kinetis.c:309
@ FS_PROGRAM_LONGWORD
Definition: kinetis.c:308
@ FS_WIDTH_256BIT
Definition: kinetis.c:312
@ FS_NO_CMD_BLOCKSTAT
Definition: kinetis.c:311
@ FS_PROGRAM_SECTOR
Definition: kinetis.c:307
enum kinetis_chip::@11 sysmodectrlr_type
@ KINETIS_WDOG_K
Definition: kinetis.c:326
@ KINETIS_WDOG32_KL28
Definition: kinetis.c:329
@ KINETIS_WDOG_NONE
Definition: kinetis.c:325
@ KINETIS_WDOG32_KE1X
Definition: kinetis.c:328
@ KINETIS_WDOG_COP
Definition: kinetis.c:327
uint32_t progr_accel_ram
Definition: kinetis.c:298
unsigned int max_flash_prog_size
Definition: kinetis.c:290
bool probed
Definition: kinetis.c:280
unsigned int num_pflash_blocks
Definition: kinetis.c:288
uint32_t dflash_size
Definition: kinetis.c:296
@ KINETIS_CACHE_K
Definition: kinetis.c:318
@ KINETIS_CACHE_L
Definition: kinetis.c:319
@ KINETIS_CACHE_MSCM
Definition: kinetis.c:320
@ KINETIS_CACHE_MSCM2
Definition: kinetis.c:321
@ KINETIS_CACHE_NONE
Definition: kinetis.c:317
unsigned int num_banks
Definition: kinetis.c:340
uint32_t fcfg2_maxaddr0_shifted
Definition: kinetis.c:285
uint32_t pflash_base
Definition: kinetis.c:292
uint32_t fcfg2_maxaddr1_shifted
Definition: kinetis.c:286
uint32_t sector_size
Definition: kinetis.c:262
uint32_t prog_base
Definition: kinetis.c:264
uint32_t protection_size
Definition: kinetis.c:263
struct flash_bank * bank
Definition: kinetis.c:260
struct kinetis_chip * k_chip
Definition: kinetis.c:257
unsigned int bank_number
Definition: kinetis.c:259
enum kinetis_flash_bank::@6 flash_class
uint32_t protection_block
Definition: kinetis.c:266
char * name
Definition: kinetis.c:346
uint32_t sdid
Definition: kinetis.c:345
uint8_t * value
Definition: algorithm.h:30
Definition: register.h:111
int(* deassert_reset)(struct target *target)
The implementation is responsible for polling the target such that target->state reflects the state c...
Definition: target_type.h:76
int(* assert_reset)(struct target *target)
Definition: target_type.h:64
Definition: target.h:116
enum target_state state
Definition: target.h:157
struct target_type * type
Definition: target.h:117
bool reset_halt
Definition: target.h:144
target_addr_t address
Definition: target.h:86
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
Definition: target.c:352
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2342
int target_write_u8(struct target *target, target_addr_t address, uint8_t value)
Definition: target.c:2683
int target_read_u8(struct target *target, target_addr_t address, uint8_t *value)
Definition: target.c:2598
int target_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Downloads a target-specific native code algorithm to the target, and executes it.
Definition: target.c:773
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1265
uint32_t target_get_working_area_avail(struct target *target)
Definition: target.c:2164
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2060
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2641
int target_poll(struct target *target)
Definition: target.c:477
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2118
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
Definition: target.c:2574
int target_run_flash_async_algorithm(struct target *target, const uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
Streams data to a circular buffer on target intended for consumption by code running asynchronously o...
Definition: target.c:930
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2550
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
Definition: target.c:1237
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:458
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:790
static const char * target_name(const struct target *target)
Returns the instance-specific name of the specified target.
Definition: target.h:233
@ TARGET_HALTED
Definition: target.h:56
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:794
int64_t timeval_ms(void)
#define TARGET_ADDR_FMT
Definition: types.h:342
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57
#define NULL
Definition: usb.h:16
uint8_t cmd
Definition: vdebug.c:1
uint8_t offset[4]
Definition: vdebug.c:9
uint8_t count[4]
Definition: vdebug.c:22