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cortex_m.h File Reference
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Data Structures

struct  cortex_m_common
 
struct  cortex_m_dwt_comparator
 
struct  cortex_m_fp_comparator
 
struct  cortex_m_part_info
 

Macros

#define AIRCR_SYSRESETREQ   BIT(2)
 
#define AIRCR_VECTCLRACTIVE   BIT(1)
 
#define AIRCR_VECTKEY   (0x5FAul << 16)
 
#define AIRCR_VECTRESET   BIT(0)
 
#define ARM_CPUID_IMPLEMENTER_MASK   (0xFF << ARM_CPUID_IMPLEMENTER_POS)
 
#define ARM_CPUID_IMPLEMENTER_POS   24
 
#define ARM_CPUID_PARTNO_MASK   (0xFFF << ARM_CPUID_PARTNO_POS)
 
#define ARM_CPUID_PARTNO_POS   4
 
#define ARM_MAKE_CPUID(impl, partno)
 
#define C_DEBUGEN   BIT(0)
 
#define C_HALT   BIT(1)
 
#define C_MASKINTS   BIT(3)
 
#define C_STEP   BIT(2)
 
#define CORTEX_M_COMMON_MAGIC   0x1A451A45U
 
#define CORTEX_M_F_HAS_FPV4   BIT(0)
 
#define CORTEX_M_F_HAS_FPV5   BIT(1)
 
#define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K   BIT(2)
 
#define CPUID   0xE000ED00
 
#define DAUTHSTATUS   0xE000EFB8
 
#define DAUTHSTATUS_SID_MASK   0x00000030
 
#define DBGKEY   (0xA05Ful << 16)
 
#define DCB_DCRDR   0xE000EDF8
 
#define DCB_DCRSR   0xE000EDF4
 
#define DCB_DEMCR   0xE000EDFC
 
#define DCB_DHCSR   0xE000EDF0
 
#define DCB_DSCSR   0xE000EE08
 
#define DCRSR_WNR   BIT(16)
 
#define DFSR_BKPT   2
 
#define DFSR_DWTTRAP   4
 
#define DFSR_EXTERNAL   16
 
#define DFSR_HALTED   1
 
#define DFSR_VCATCH   8
 
#define DSCSR_CDS   BIT(16)
 
#define DSCSR_CDSKEY   BIT(17)
 
#define DWT_COMP0   0xE0001020
 
#define DWT_CTRL   0xE0001000
 
#define DWT_CYCCNT   0xE0001004
 
#define DWT_DEVARCH   0xE0001FBC
 
#define DWT_DEVARCH_ARMV8M_V2_0   0x101A02
 
#define DWT_DEVARCH_ARMV8M_V2_1   0x111A02
 
#define DWT_FUNCTION0   0xE0001028
 
#define DWT_MASK0   0xE0001024
 
#define DWT_PCSR   0xE000101C
 
#define FP_COMP0   0xE0002008
 
#define FP_COMP1   0xE000200C
 
#define FP_COMP2   0xE0002010
 
#define FP_COMP3   0xE0002014
 
#define FP_COMP4   0xE0002018
 
#define FP_COMP5   0xE000201C
 
#define FP_COMP6   0xE0002020
 
#define FP_COMP7   0xE0002024
 
#define FP_CTRL   0xE0002000
 
#define FP_REMAP   0xE0002004
 
#define FPCR_CODE   0
 
#define FPCR_LITERAL   1
 
#define FPCR_REPLACE_BKPT_BOTH   (3ul << 30)
 
#define FPCR_REPLACE_BKPT_HIGH   (2ul << 30)
 
#define FPCR_REPLACE_BKPT_LOW   (1ul << 30)
 
#define FPCR_REPLACE_REMAP   (0ul << 30)
 
#define FPU_CPACR   0xE000ED88
 
#define FPU_FPCAR   0xE000EF38
 
#define FPU_FPCCR   0xE000EF34
 
#define FPU_FPDSCR   0xE000EF3C
 
#define ITM_LAR   0xE0000FB0
 
#define ITM_LAR_KEY   0xC5ACCE55
 
#define ITM_TCR   0xE0000E80
 
#define ITM_TCR_BUSY_BIT   BIT(23)
 
#define ITM_TCR_ITMENA_BIT   BIT(0)
 
#define ITM_TER0   0xE0000E00
 
#define ITM_TPR   0xE0000E40
 
#define NVIC_AIRCR   0xE000ED0C
 
#define NVIC_BFAR   0xE000ED38
 
#define NVIC_BFSRB   0xE000ED29
 
#define NVIC_CFSR   0xE000ED28
 
#define NVIC_DFSR   0xE000ED30
 
#define NVIC_HFSR   0xE000ED2C
 
#define NVIC_ICSR   0xE000ED04
 
#define NVIC_ICTR   0xE000E004
 
#define NVIC_ISE0   0xE000E100
 
#define NVIC_MMFAR   0xE000ED34
 
#define NVIC_MMFSRB   0xE000ED28
 
#define NVIC_SFAR   0xE000EDE8
 
#define NVIC_SFSR   0xE000EDE4
 
#define NVIC_SHCSR   0xE000ED24
 
#define NVIC_USFSRH   0xE000ED2A
 
#define S_HALT   BIT(17)
 
#define S_LOCKUP   BIT(19)
 
#define S_REGRDY   BIT(16)
 
#define S_RESET_ST   BIT(25)
 
#define S_RETIRE_ST   BIT(24)
 
#define S_SLEEP   BIT(18)
 
#define SHCSR_BUSFAULTENA   BIT(17)
 
#define SYSTEM_CONTROL_BASE   0x400FE000
 
#define TPIU_ACPR   0xE0040010
 
#define TPIU_ACPR_MAX_SWOSCALER   0x1fff
 
#define TPIU_CSPSR   0xE0040004
 
#define TPIU_FFCR   0xE0040304
 
#define TPIU_FFSR   0xE0040300
 
#define TPIU_FSCR   0xE0040308
 
#define TPIU_SPPR   0xE00400F0
 
#define TPIU_SSPSR   0xE0040000
 
#define TRCENA   BIT(24)
 
#define VC_BUSERR   BIT(8)
 
#define VC_CHKERR   BIT(6)
 
#define VC_CORERESET   BIT(0)
 
#define VC_HARDERR   BIT(10)
 
#define VC_INTERR   BIT(9)
 
#define VC_MMERR   BIT(4)
 
#define VC_NOCPERR   BIT(5)
 
#define VC_STATERR   BIT(7)
 

Enumerations

enum  cortex_m_impl_part {
  CORTEX_M_PARTNO_INVALID , STAR_MC1_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM_CHINA, 0x132) , CORTEX_M0_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xC20) , CORTEX_M1_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xC21) ,
  CORTEX_M3_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xC23) , CORTEX_M4_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xC24) , CORTEX_M7_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xC27) , CORTEX_M0P_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xC60) ,
  CORTEX_M23_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xD20) , CORTEX_M33_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xD21) , CORTEX_M35P_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xD31) , CORTEX_M52_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM_CHINA, 0xD24) ,
  CORTEX_M55_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xD22) , CORTEX_M85_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_ARM, 0xD23) , INFINEON_SLX2_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_INFINEON, 0xDB0) , REALTEK_M200_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_REALTEK, 0xd20) ,
  REALTEK_M300_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTER_REALTEK, 0xd22)
}
 Known Arm Cortex masked CPU Ids This includes the implementer and part number, but not the revision or patch fields. More...
 
enum  cortex_m_isrmasking_mode { CORTEX_M_ISRMASK_AUTO , CORTEX_M_ISRMASK_OFF , CORTEX_M_ISRMASK_ON , CORTEX_M_ISRMASK_STEPONLY }
 
enum  cortex_m_soft_reset_config { CORTEX_M_RESET_SYSRESETREQ , CORTEX_M_RESET_VECTRESET }
 

Functions

int cortex_m_add_breakpoint (struct target *target, struct breakpoint *breakpoint)
 
int cortex_m_add_watchpoint (struct target *target, struct watchpoint *watchpoint)
 
void cortex_m_deinit_target (struct target *target)
 
void cortex_m_enable_breakpoints (struct target *target)
 
void cortex_m_enable_watchpoints (struct target *target)
 
int cortex_m_examine (struct target *target)
 
static enum cortex_m_impl_part cortex_m_get_impl_part (struct target *target)
 
int cortex_m_profiling (struct target *target, uint32_t *samples, uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
 
int cortex_m_remove_breakpoint (struct target *target, struct breakpoint *breakpoint)
 
int cortex_m_remove_watchpoint (struct target *target, struct watchpoint *watchpoint)
 
int cortex_m_set_breakpoint (struct target *target, struct breakpoint *breakpoint)
 
int cortex_m_unset_breakpoint (struct target *target, struct breakpoint *breakpoint)
 
static bool is_cortex_m_or_hla (const struct cortex_m_common *cortex_m)
 
static bool is_cortex_m_with_dap_access (const struct cortex_m_common *cortex_m)
 
static struct cortex_m_commontarget_to_cm (struct target *target)
 
static struct cortex_m_commontarget_to_cortex_m_safe (struct target *target)
 

Macro Definition Documentation

◆ AIRCR_SYSRESETREQ

#define AIRCR_SYSRESETREQ   BIT(2)

Definition at line 175 of file cortex_m.h.

◆ AIRCR_VECTCLRACTIVE

#define AIRCR_VECTCLRACTIVE   BIT(1)

Definition at line 176 of file cortex_m.h.

◆ AIRCR_VECTKEY

#define AIRCR_VECTKEY   (0x5FAul << 16)

Definition at line 174 of file cortex_m.h.

◆ AIRCR_VECTRESET

#define AIRCR_VECTRESET   BIT(0)

Definition at line 177 of file cortex_m.h.

◆ ARM_CPUID_IMPLEMENTER_MASK

#define ARM_CPUID_IMPLEMENTER_MASK   (0xFF << ARM_CPUID_IMPLEMENTER_POS)

Definition at line 35 of file cortex_m.h.

◆ ARM_CPUID_IMPLEMENTER_POS

#define ARM_CPUID_IMPLEMENTER_POS   24

Definition at line 34 of file cortex_m.h.

◆ ARM_CPUID_PARTNO_MASK

#define ARM_CPUID_PARTNO_MASK   (0xFFF << ARM_CPUID_PARTNO_POS)

Definition at line 37 of file cortex_m.h.

◆ ARM_CPUID_PARTNO_POS

#define ARM_CPUID_PARTNO_POS   4

Definition at line 36 of file cortex_m.h.

◆ ARM_MAKE_CPUID

#define ARM_MAKE_CPUID (   impl,
  partno 
)
Value:
uint8_t partno
Definition: ambiqmicro.c:99
#define ARM_CPUID_IMPLEMENTER_POS
Definition: cortex_m.h:34
#define ARM_CPUID_PARTNO_POS
Definition: cortex_m.h:36
#define ARM_CPUID_IMPLEMENTER_MASK
Definition: cortex_m.h:35
#define ARM_CPUID_PARTNO_MASK
Definition: cortex_m.h:37

Definition at line 39 of file cortex_m.h.

◆ C_DEBUGEN

#define C_DEBUGEN   BIT(0)

Definition at line 130 of file cortex_m.h.

◆ C_HALT

#define C_HALT   BIT(1)

Definition at line 131 of file cortex_m.h.

◆ C_MASKINTS

#define C_MASKINTS   BIT(3)

Definition at line 133 of file cortex_m.h.

◆ C_STEP

#define C_STEP   BIT(2)

Definition at line 132 of file cortex_m.h.

◆ CORTEX_M_COMMON_MAGIC

#define CORTEX_M_COMMON_MAGIC   0x1A451A45U

Definition at line 20 of file cortex_m.h.

◆ CORTEX_M_F_HAS_FPV4

#define CORTEX_M_F_HAS_FPV4   BIT(0)

Definition at line 67 of file cortex_m.h.

◆ CORTEX_M_F_HAS_FPV5

#define CORTEX_M_F_HAS_FPV5   BIT(1)

Definition at line 68 of file cortex_m.h.

◆ CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K

#define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K   BIT(2)

Definition at line 69 of file cortex_m.h.

◆ CPUID

#define CPUID   0xE000ED00

Definition at line 32 of file cortex_m.h.

◆ DAUTHSTATUS

#define DAUTHSTATUS   0xE000EFB8

Definition at line 85 of file cortex_m.h.

◆ DAUTHSTATUS_SID_MASK

#define DAUTHSTATUS_SID_MASK   0x00000030

Definition at line 86 of file cortex_m.h.

◆ DBGKEY

#define DBGKEY   (0xA05Ful << 16)

Definition at line 129 of file cortex_m.h.

◆ DCB_DCRDR

#define DCB_DCRDR   0xE000EDF8

Definition at line 81 of file cortex_m.h.

◆ DCB_DCRSR

#define DCB_DCRSR   0xE000EDF4

Definition at line 80 of file cortex_m.h.

◆ DCB_DEMCR

#define DCB_DEMCR   0xE000EDFC

Definition at line 82 of file cortex_m.h.

◆ DCB_DHCSR

#define DCB_DHCSR   0xE000EDF0

Definition at line 79 of file cortex_m.h.

◆ DCB_DSCSR

#define DCB_DSCSR   0xE000EE08

Definition at line 83 of file cortex_m.h.

◆ DCRSR_WNR

#define DCRSR_WNR   BIT(16)

Definition at line 88 of file cortex_m.h.

◆ DFSR_BKPT

#define DFSR_BKPT   2

Definition at line 182 of file cortex_m.h.

◆ DFSR_DWTTRAP

#define DFSR_DWTTRAP   4

Definition at line 183 of file cortex_m.h.

◆ DFSR_EXTERNAL

#define DFSR_EXTERNAL   16

Definition at line 185 of file cortex_m.h.

◆ DFSR_HALTED

#define DFSR_HALTED   1

Definition at line 181 of file cortex_m.h.

◆ DFSR_VCATCH

#define DFSR_VCATCH   8

Definition at line 184 of file cortex_m.h.

◆ DSCSR_CDS

#define DSCSR_CDS   BIT(16)

Definition at line 154 of file cortex_m.h.

◆ DSCSR_CDSKEY

#define DSCSR_CDSKEY   BIT(17)

Definition at line 153 of file cortex_m.h.

◆ DWT_COMP0

#define DWT_COMP0   0xE0001020

Definition at line 93 of file cortex_m.h.

◆ DWT_CTRL

#define DWT_CTRL   0xE0001000

Definition at line 90 of file cortex_m.h.

◆ DWT_CYCCNT

#define DWT_CYCCNT   0xE0001004

Definition at line 91 of file cortex_m.h.

◆ DWT_DEVARCH

#define DWT_DEVARCH   0xE0001FBC

Definition at line 96 of file cortex_m.h.

◆ DWT_DEVARCH_ARMV8M_V2_0

#define DWT_DEVARCH_ARMV8M_V2_0   0x101A02

Definition at line 98 of file cortex_m.h.

◆ DWT_DEVARCH_ARMV8M_V2_1

#define DWT_DEVARCH_ARMV8M_V2_1   0x111A02

Definition at line 99 of file cortex_m.h.

◆ DWT_FUNCTION0

#define DWT_FUNCTION0   0xE0001028

Definition at line 95 of file cortex_m.h.

◆ DWT_MASK0

#define DWT_MASK0   0xE0001024

Definition at line 94 of file cortex_m.h.

◆ DWT_PCSR

#define DWT_PCSR   0xE000101C

Definition at line 92 of file cortex_m.h.

◆ FP_COMP0

#define FP_COMP0   0xE0002008

Definition at line 103 of file cortex_m.h.

◆ FP_COMP1

#define FP_COMP1   0xE000200C

Definition at line 104 of file cortex_m.h.

◆ FP_COMP2

#define FP_COMP2   0xE0002010

Definition at line 105 of file cortex_m.h.

◆ FP_COMP3

#define FP_COMP3   0xE0002014

Definition at line 106 of file cortex_m.h.

◆ FP_COMP4

#define FP_COMP4   0xE0002018

Definition at line 107 of file cortex_m.h.

◆ FP_COMP5

#define FP_COMP5   0xE000201C

Definition at line 108 of file cortex_m.h.

◆ FP_COMP6

#define FP_COMP6   0xE0002020

Definition at line 109 of file cortex_m.h.

◆ FP_COMP7

#define FP_COMP7   0xE0002024

Definition at line 110 of file cortex_m.h.

◆ FP_CTRL

#define FP_CTRL   0xE0002000

Definition at line 101 of file cortex_m.h.

◆ FP_REMAP

#define FP_REMAP   0xE0002004

Definition at line 102 of file cortex_m.h.

◆ FPCR_CODE

#define FPCR_CODE   0

Definition at line 187 of file cortex_m.h.

◆ FPCR_LITERAL

#define FPCR_LITERAL   1

Definition at line 188 of file cortex_m.h.

◆ FPCR_REPLACE_BKPT_BOTH

#define FPCR_REPLACE_BKPT_BOTH   (3ul << 30)

Definition at line 192 of file cortex_m.h.

◆ FPCR_REPLACE_BKPT_HIGH

#define FPCR_REPLACE_BKPT_HIGH   (2ul << 30)

Definition at line 191 of file cortex_m.h.

◆ FPCR_REPLACE_BKPT_LOW

#define FPCR_REPLACE_BKPT_LOW   (1ul << 30)

Definition at line 190 of file cortex_m.h.

◆ FPCR_REPLACE_REMAP

#define FPCR_REPLACE_REMAP   (0ul << 30)

Definition at line 189 of file cortex_m.h.

◆ FPU_CPACR

#define FPU_CPACR   0xE000ED88

Definition at line 112 of file cortex_m.h.

◆ FPU_FPCAR

#define FPU_FPCAR   0xE000EF38

Definition at line 114 of file cortex_m.h.

◆ FPU_FPCCR

#define FPU_FPCCR   0xE000EF34

Definition at line 113 of file cortex_m.h.

◆ FPU_FPDSCR

#define FPU_FPDSCR   0xE000EF3C

Definition at line 115 of file cortex_m.h.

◆ ITM_LAR

#define ITM_LAR   0xE0000FB0

Definition at line 29 of file cortex_m.h.

◆ ITM_LAR_KEY

#define ITM_LAR_KEY   0xC5ACCE55

Definition at line 30 of file cortex_m.h.

◆ ITM_TCR

#define ITM_TCR   0xE0000E80

Definition at line 26 of file cortex_m.h.

◆ ITM_TCR_BUSY_BIT

#define ITM_TCR_BUSY_BIT   BIT(23)

Definition at line 28 of file cortex_m.h.

◆ ITM_TCR_ITMENA_BIT

#define ITM_TCR_ITMENA_BIT   BIT(0)

Definition at line 27 of file cortex_m.h.

◆ ITM_TER0

#define ITM_TER0   0xE0000E00

Definition at line 24 of file cortex_m.h.

◆ ITM_TPR

#define ITM_TPR   0xE0000E40

Definition at line 25 of file cortex_m.h.

◆ NVIC_AIRCR

#define NVIC_AIRCR   0xE000ED0C

Definition at line 160 of file cortex_m.h.

◆ NVIC_BFAR

#define NVIC_BFAR   0xE000ED38

Definition at line 169 of file cortex_m.h.

◆ NVIC_BFSRB

#define NVIC_BFSRB   0xE000ED29

Definition at line 164 of file cortex_m.h.

◆ NVIC_CFSR

#define NVIC_CFSR   0xE000ED28

Definition at line 162 of file cortex_m.h.

◆ NVIC_DFSR

#define NVIC_DFSR   0xE000ED30

Definition at line 167 of file cortex_m.h.

◆ NVIC_HFSR

#define NVIC_HFSR   0xE000ED2C

Definition at line 166 of file cortex_m.h.

◆ NVIC_ICSR

#define NVIC_ICSR   0xE000ED04

Definition at line 159 of file cortex_m.h.

◆ NVIC_ICTR

#define NVIC_ICTR   0xE000E004

Definition at line 157 of file cortex_m.h.

◆ NVIC_ISE0

#define NVIC_ISE0   0xE000E100

Definition at line 158 of file cortex_m.h.

◆ NVIC_MMFAR

#define NVIC_MMFAR   0xE000ED34

Definition at line 168 of file cortex_m.h.

◆ NVIC_MMFSRB

#define NVIC_MMFSRB   0xE000ED28

Definition at line 163 of file cortex_m.h.

◆ NVIC_SFAR

#define NVIC_SFAR   0xE000EDE8

Definition at line 171 of file cortex_m.h.

◆ NVIC_SFSR

#define NVIC_SFSR   0xE000EDE4

Definition at line 170 of file cortex_m.h.

◆ NVIC_SHCSR

#define NVIC_SHCSR   0xE000ED24

Definition at line 161 of file cortex_m.h.

◆ NVIC_USFSRH

#define NVIC_USFSRH   0xE000ED2A

Definition at line 165 of file cortex_m.h.

◆ S_HALT

#define S_HALT   BIT(17)

Definition at line 135 of file cortex_m.h.

◆ S_LOCKUP

#define S_LOCKUP   BIT(19)

Definition at line 137 of file cortex_m.h.

◆ S_REGRDY

#define S_REGRDY   BIT(16)

Definition at line 134 of file cortex_m.h.

◆ S_RESET_ST

#define S_RESET_ST   BIT(25)

Definition at line 139 of file cortex_m.h.

◆ S_RETIRE_ST

#define S_RETIRE_ST   BIT(24)

Definition at line 138 of file cortex_m.h.

◆ S_SLEEP

#define S_SLEEP   BIT(18)

Definition at line 136 of file cortex_m.h.

◆ SHCSR_BUSFAULTENA

#define SHCSR_BUSFAULTENA   BIT(17)

Definition at line 179 of file cortex_m.h.

◆ SYSTEM_CONTROL_BASE

#define SYSTEM_CONTROL_BASE   0x400FE000

Definition at line 22 of file cortex_m.h.

◆ TPIU_ACPR

#define TPIU_ACPR   0xE0040010

Definition at line 119 of file cortex_m.h.

◆ TPIU_ACPR_MAX_SWOSCALER

#define TPIU_ACPR_MAX_SWOSCALER   0x1fff

Definition at line 126 of file cortex_m.h.

◆ TPIU_CSPSR

#define TPIU_CSPSR   0xE0040004

Definition at line 118 of file cortex_m.h.

◆ TPIU_FFCR

#define TPIU_FFCR   0xE0040304

Definition at line 122 of file cortex_m.h.

◆ TPIU_FFSR

#define TPIU_FFSR   0xE0040300

Definition at line 121 of file cortex_m.h.

◆ TPIU_FSCR

#define TPIU_FSCR   0xE0040308

Definition at line 123 of file cortex_m.h.

◆ TPIU_SPPR

#define TPIU_SPPR   0xE00400F0

Definition at line 120 of file cortex_m.h.

◆ TPIU_SSPSR

#define TPIU_SSPSR   0xE0040000

Definition at line 117 of file cortex_m.h.

◆ TRCENA

#define TRCENA   BIT(24)

Definition at line 142 of file cortex_m.h.

◆ VC_BUSERR

#define VC_BUSERR   BIT(8)

Definition at line 145 of file cortex_m.h.

◆ VC_CHKERR

#define VC_CHKERR   BIT(6)

Definition at line 147 of file cortex_m.h.

◆ VC_CORERESET

#define VC_CORERESET   BIT(0)

Definition at line 150 of file cortex_m.h.

◆ VC_HARDERR

#define VC_HARDERR   BIT(10)

Definition at line 143 of file cortex_m.h.

◆ VC_INTERR

#define VC_INTERR   BIT(9)

Definition at line 144 of file cortex_m.h.

◆ VC_MMERR

#define VC_MMERR   BIT(4)

Definition at line 149 of file cortex_m.h.

◆ VC_NOCPERR

#define VC_NOCPERR   BIT(5)

Definition at line 148 of file cortex_m.h.

◆ VC_STATERR

#define VC_STATERR   BIT(7)

Definition at line 146 of file cortex_m.h.

Enumeration Type Documentation

◆ cortex_m_impl_part

Known Arm Cortex masked CPU Ids This includes the implementer and part number, but not the revision or patch fields.

Enumerator
CORTEX_M_PARTNO_INVALID 
STAR_MC1_PARTNO 
CORTEX_M0_PARTNO 
CORTEX_M1_PARTNO 
CORTEX_M3_PARTNO 
CORTEX_M4_PARTNO 
CORTEX_M7_PARTNO 
CORTEX_M0P_PARTNO 
CORTEX_M23_PARTNO 
CORTEX_M33_PARTNO 
CORTEX_M35P_PARTNO 
CORTEX_M52_PARTNO 
CORTEX_M55_PARTNO 
CORTEX_M85_PARTNO 
INFINEON_SLX2_PARTNO 
REALTEK_M200_PARTNO 
REALTEK_M300_PARTNO 

Definition at line 46 of file cortex_m.h.

◆ cortex_m_isrmasking_mode

Enumerator
CORTEX_M_ISRMASK_AUTO 
CORTEX_M_ISRMASK_OFF 
CORTEX_M_ISRMASK_ON 
CORTEX_M_ISRMASK_STEPONLY 

Definition at line 214 of file cortex_m.h.

◆ cortex_m_soft_reset_config

Enumerator
CORTEX_M_RESET_SYSRESETREQ 
CORTEX_M_RESET_VECTRESET 

Definition at line 209 of file cortex_m.h.

Function Documentation

◆ cortex_m_add_breakpoint()

int cortex_m_add_breakpoint ( struct target target,
struct breakpoint breakpoint 
)

◆ cortex_m_add_watchpoint()

◆ cortex_m_deinit_target()

◆ cortex_m_enable_breakpoints()

void cortex_m_enable_breakpoints ( struct target target)

◆ cortex_m_enable_watchpoints()

void cortex_m_enable_watchpoints ( struct target target)

◆ cortex_m_examine()

int cortex_m_examine ( struct target target)

Definition at line 2583 of file cortex_m.c.

References cortex_m_common::apsel, arm::arch, cortex_m_part_info::arch, armv7m_common::arm, ARM_ARCH_V7M, ARM_CPUID_IMPLEMENTER_MASK, ARM_CPUID_PARTNO_MASK, cortex_m_common::armv7m, ARMV7M_FPU_FIRST_REG, ARMV7M_FPU_LAST_REG, armv7m_trace_itm_config(), ARMV8M_FIRST_REG, ARMV8M_LAST_REG, ARRAY_SIZE, C_DEBUGEN, C_HALT, C_MASKINTS, C_STEP, arm::core_cache, cortex_m_common::core_info, CORTEX_M7_PARTNO, cortex_m_cumulate_dhcsr_sticky(), cortex_m_dwt_free(), cortex_m_dwt_setup(), CORTEX_M_F_HAS_FPV4, CORTEX_M_F_HAS_FPV5, CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K, cortex_m_find_mem_ap(), cortex_m_has_tz(), cortex_m_parts, CPUID, arm::dap, dap_get_ap(), DBGKEY, DCB_DEMCR, DCB_DHCSR, cortex_m_common::dcb_dhcsr, cortex_m_common::dcb_dhcsr_sticky_is_recent, armv7m_common::debug_ap, armv7m_common::demcr, DP_APSEL_INVALID, cortex_m_common::dwt_num_comp, ERROR_FAIL, ERROR_OK, reg::exist, cortex_m_part_info::flags, FP_COMP0, cortex_m_common::fp_comparator_list, FP_CTRL, armv7m_common::fp_feature, FP_NONE, cortex_m_common::fp_num_code, cortex_m_common::fp_num_lit, cortex_m_common::fp_rev, cortex_m_common::fpb_enabled, cortex_m_fp_comparator::fpcr_address, FPCR_CODE, FPCR_LITERAL, FPV4_SP, FPV5_DP, FPV5_MVE_F, FPV5_MVE_I, FPV5_SP, cortex_m_common::incorrect_halt_erratum, armv7m_common::is_hla_target, LOG_ERROR, LOG_INFO, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, LOG_TARGET_INFO, LOG_TARGET_WARNING, LOG_WARNING, cortex_m_common::maskints_erratum, mem_ap_init(), adiv5_ap::memaccess_tck, MVFR0, MVFR0_DP, MVFR0_DP_MASK, MVFR0_SP, MVFR0_SP_MASK, MVFR1, MVFR1_MVE_F, MVFR1_MVE_I, MVFR1_MVE_MASK, cortex_m_part_info::name, reg_cache::reg_list, S_RESET_ST, adiv5_ap::tar_autoincr_block, target_read_u32(), target_set_examined(), target_to_armv7m(), target_to_cm(), target_was_examined(), target_write_u32(), TRCENA, cortex_m_fp_comparator::type, and cortex_m_common::vectreset_supported.

◆ cortex_m_get_impl_part()

static enum cortex_m_impl_part cortex_m_get_impl_part ( struct target target)
inlinestatic
Returns
cached value of the cpuid, masked for implementation and part. or CORTEX_M_PARTNO_INVALID if the magic number does not match or core_info is not initialised.

Definition at line 300 of file cortex_m.h.

References is_cortex_m_or_hla(), NULL, target_to_armv7m_safe(), and target_to_cm().

Referenced by stm32l4_read_idcode(), stm32x_get_device_id(), stm32x_get_property_addr(), and stm32x_probe().

◆ cortex_m_profiling()

int cortex_m_profiling ( struct target target,
uint32_t *  samples,
uint32_t  max_num_samples,
uint32_t *  num_samples,
uint32_t  seconds 
)

◆ cortex_m_remove_breakpoint()

int cortex_m_remove_breakpoint ( struct target target,
struct breakpoint breakpoint 
)

Definition at line 2012 of file cortex_m.c.

References cortex_m_unset_breakpoint(), ERROR_OK, and breakpoint::is_set.

◆ cortex_m_remove_watchpoint()

int cortex_m_remove_watchpoint ( struct target target,
struct watchpoint watchpoint 
)

◆ cortex_m_set_breakpoint()

◆ cortex_m_unset_breakpoint()

◆ is_cortex_m_or_hla()

static bool is_cortex_m_or_hla ( const struct cortex_m_common cortex_m)
inlinestatic

◆ is_cortex_m_with_dap_access()

static bool is_cortex_m_with_dap_access ( const struct cortex_m_common cortex_m)
inlinestatic

◆ target_to_cm()

◆ target_to_cortex_m_safe()

static struct cortex_m_common* target_to_cortex_m_safe ( struct target target)
inlinestatic
Returns
the pointer to the target specific struct or NULL if the magic number does not match. Use in a flash driver or any place where mismatch of the arch_info type can happen.

Definition at line 300 of file cortex_m.h.