OpenOCD
arm_opcodes.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /*
4  * Copyright (C) 2005 by Dominic Rath
5  * Dominic.Rath@gmx.de
6  *
7  * Copyright (C) 2006 by Magnus Lundin
8  * lundin@mlu.mine.nu
9  *
10  * Copyright (C) 2008 by Spencer Oliver
11  * spen@spen-soft.co.uk
12  *
13  * Copyright (C) 2009 by Øyvind Harboe
14  * oyvind.harboe@zylin.com
15  */
16 
17 #ifndef OPENOCD_TARGET_ARM_OPCODES_H
18 #define OPENOCD_TARGET_ARM_OPCODES_H
19 
25 /* ARM mode instructions */
26 
27 /* Store multiple increment after
28  * rn: base register
29  * list: for each bit in list: store register
30  * s: in privileged mode: store user-mode registers
31  * w = 1: update the base register. w = 0: leave the base register untouched
32  */
33 #define ARMV4_5_STMIA(rn, list, s, w) \
34  (0xe8800000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
35 
36 /* Load multiple increment after
37  * rn: base register
38  * list: for each bit in list: store register
39  * s: in privileged mode: store user-mode registers
40  * w = 1: update the base register. w = 0: leave the base register untouched
41  */
42 #define ARMV4_5_LDMIA(rn, list, s, w) \
43  (0xe8900000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
44 
45 /* MOV r8, r8 */
46 #define ARMV4_5_NOP (0xe1a08008)
47 
48 /* Move PSR to general purpose register
49  * r = 1: SPSR r = 0: CPSR
50  * rn: target register
51  */
52 #define ARMV4_5_MRS(rn, r) (0xe10f0000 | ((r) << 22) | ((rn) << 12))
53 
54 /* Store register
55  * rd: register to store
56  * rn: base register
57  */
58 #define ARMV4_5_STR(rd, rn) (0xe5800000 | ((rd) << 12) | ((rn) << 16))
59 
60 /* Load register
61  * rd: register to load
62  * rn: base register
63  */
64 #define ARMV4_5_LDR(rd, rn) (0xe5900000 | ((rd) << 12) | ((rn) << 16))
65 
66 /* Move general purpose register to PSR
67  * r = 1: SPSR r = 0: CPSR
68  * field: Field mask
69  * 1: control field 2: extension field 4: status field 8: flags field
70  * rm: source register
71  */
72 #define ARMV4_5_MSR_GP(rm, field, r) \
73  (0xe120f000 | (rm) | ((field) << 16) | ((r) << 22))
74 #define ARMV4_5_MSR_IM(im, rotate, field, r) \
75  (0xe320f000 | (im) | ((rotate) << 8) | ((field) << 16) | ((r) << 22))
76 
77 /* Load Register Word Immediate Post-Index
78  * rd: register to load
79  * rn: base register
80  */
81 #define ARMV4_5_LDRW_IP(rd, rn) (0xe4900004 | ((rd) << 12) | ((rn) << 16))
82 
83 /* Load Register Halfword Immediate Post-Index
84  * rd: register to load
85  * rn: base register
86  */
87 #define ARMV4_5_LDRH_IP(rd, rn) (0xe0d000b2 | ((rd) << 12) | ((rn) << 16))
88 
89 /* Load Register Byte Immediate Post-Index
90  * rd: register to load
91  * rn: base register
92  */
93 #define ARMV4_5_LDRB_IP(rd, rn) (0xe4d00001 | ((rd) << 12) | ((rn) << 16))
94 
95 /* Store register Word Immediate Post-Index
96  * rd: register to store
97  * rn: base register
98  */
99 #define ARMV4_5_STRW_IP(rd, rn) (0xe4800004 | ((rd) << 12) | ((rn) << 16))
100 
101 /* Store register Halfword Immediate Post-Index
102  * rd: register to store
103  * rn: base register
104  */
105 #define ARMV4_5_STRH_IP(rd, rn) (0xe0c000b2 | ((rd) << 12) | ((rn) << 16))
106 
107 /* Store register Byte Immediate Post-Index
108  * rd: register to store
109  * rn: base register
110  */
111 #define ARMV4_5_STRB_IP(rd, rn) (0xe4c00001 | ((rd) << 12) | ((rn) << 16))
112 
113 /* Branch (and Link)
114  * im: Branch target (left-shifted by 2 bits, added to PC)
115  * l: 1: branch and link 0: branch only
116  */
117 #define ARMV4_5_B(im, l) (0xea000000 | (im) | ((l) << 24))
118 
119 /* Branch and exchange (ARM state)
120  * rm: register holding branch target address
121  */
122 #define ARMV4_5_BX(rm) (0xe12fff10 | (rm))
123 
124 /* Copies two words from two ARM core registers
125  * into a doubleword extension register, or
126  * from a doubleword extension register to two ARM core registers.
127  * See Armv7-A arch reference manual section A8.8.345
128  * rt: Arm core register 1
129  * rt2: Arm core register 2
130  * vm: The doubleword extension register
131  * m: m = UInt(m:vm);
132  * op: to_arm_registers = (op == ‘1’);
133  */
134 #define ARMV4_5_VMOV(op, rt2, rt, m, vm) \
135  (0xec400b10 | ((op) << 20) | ((rt2) << 16) | \
136  ((rt) << 12) | ((m) << 5) | (vm))
137 
138 /* Moves the value of the FPSCR to an ARM core register
139  * rt: Arm core register
140  */
141 #define ARMV4_5_VMRS(rt) (0xeef10a10 | ((rt) << 12))
142 
143 /* Moves the value of an ARM core register to the FPSCR.
144  * rt: Arm core register
145  */
146 #define ARMV4_5_VMSR(rt) (0xeee10a10 | ((rt) << 12))
147 
148 /* Store data from coprocessor to consecutive memory
149  * See Armv7-A arch doc section A8.6.187
150  * p: 1=index mode (offset from rn)
151  * u: 1=add, 0=subtract rn address with imm
152  * d: Opcode D encoding
153  * w: write back the offset start address to the rn register
154  * cp: Coprocessor number (4 bits)
155  * crd: Coprocessor source register (4 bits)
156  * rn: Base register for memory address (4 bits)
157  * imm: Immediate value (0 - 1020, must be divisible by 4)
158  */
159 #define ARMV4_5_STC(p, u, d, w, cp, crd, rn, imm) \
160  (0xec000000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
161  ((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm)>>2))
162 
163 /* Loads data from consecutive memory to coprocessor
164  * See Armv7-A arch doc section A8.6.51
165  * p: 1=index mode (offset from rn)
166  * u: 1=add, 0=subtract rn address with imm
167  * d: Opcode D encoding
168  * w: write back the offset start address to the rn register
169  * cp: Coprocessor number (4 bits)
170  * crd: Coprocessor dest register (4 bits)
171  * rn: Base register for memory address (4 bits)
172  * imm: Immediate value (0 - 1020, must be divisible by 4)
173  */
174 #define ARMV4_5_LDC(p, u, d, w, cp, crd, rn, imm) \
175  (0xec100000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
176  ((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm) >> 2))
177 
178 /* Move to ARM register from coprocessor
179  * cp: Coprocessor number
180  * op1: Coprocessor opcode
181  * rd: destination register
182  * crn: first coprocessor operand
183  * crm: second coprocessor operand
184  * op2: Second coprocessor opcode
185  */
186 #define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2) \
187  (0xee100010 | (crm) | ((op2) << 5) | ((cp) << 8) \
188  | ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
189 
190 /* Move to two ARM registers from coprocessor
191  * cp: Coprocessor number
192  * op: Coprocessor opcode
193  * rt: destination register 1
194  * rt2: destination register 2
195  * crm: coprocessor source register
196  */
197 #define ARMV5_T_MRRC(cp, op, rt, rt2, crm) \
198  (0xec500000 | (crm) | ((op) << 4) | ((cp) << 8) \
199  | ((rt) << 12) | ((rt2) << 16))
200 
201 /* Move to coprocessor from ARM register
202  * cp: Coprocessor number
203  * op1: Coprocessor opcode
204  * rd: destination register
205  * crn: first coprocessor operand
206  * crm: second coprocessor operand
207  * op2: Second coprocessor opcode
208  */
209 #define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2) \
210  (0xee000010 | (crm) | ((op2) << 5) | ((cp) << 8) \
211  | ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
212 
213 /* Move to coprocessor from two ARM registers
214  * cp: Coprocessor number
215  * op: Coprocessor opcode
216  * rt: destination register 1
217  * rt2: destination register 2
218  * crm: coprocessor source register
219  */
220 #define ARMV5_T_MCRR(cp, op, rt, rt2, crm) \
221  (0xec400000 | (crm) | ((op) << 4) | ((cp) << 8) \
222  | ((rt) << 12) | ((rt2) << 16))
223 
224 /* Breakpoint instruction (ARMv5)
225  * im: 16-bit immediate
226  */
227 #define ARMV5_BKPT(im) (0xe1200070 | ((im & 0xfff0) << 4) | (im & 0xf))
228 
229 
230 /* Thumb mode instructions
231  *
232  * NOTE: these 16-bit opcodes fill both halves of a word with the same
233  * value. The reason for this is that when we need to execute Thumb
234  * opcodes on ARM7/ARM9 cores (to switch to ARM state on debug entry),
235  * we must shift 32 bits to the bus using scan chain 1 ... if we write
236  * both halves, we don't need to track which half matters. On ARMv6 and
237  * ARMv7 we don't execute Thumb instructions in debug mode; the ITR
238  * register does not accept Thumb (or Thumb2) opcodes.
239  */
240 
241 /* Store register (Thumb mode)
242  * rd: source register
243  * rn: base register
244  */
245 #define ARMV4_5_T_STR(rd, rn) \
246  ((0x6000 | (rd) | ((rn) << 3)) | \
247  ((0x6000 | (rd) | ((rn) << 3)) << 16))
248 
249 /* Load register (Thumb state)
250  * rd: destination register
251  * rn: base register
252  */
253 #define ARMV4_5_T_LDR(rd, rn) \
254  ((0x6800 | ((rn) << 3) | (rd)) \
255  | ((0x6800 | ((rn) << 3) | (rd)) << 16))
256 
257 /* Load multiple (Thumb state)
258  * rn: base register
259  * list: for each bit in list: store register
260  */
261 #define ARMV4_5_T_LDMIA(rn, list) \
262  ((0xc800 | ((rn) << 8) | (list)) \
263  | ((0xc800 | ((rn) << 8) | (list)) << 16))
264 
265 /* Load register with PC relative addressing
266  * rd: register to load
267  */
268 #define ARMV4_5_T_LDR_PCREL(rd) \
269  ((0x4800 | ((rd) << 8)) \
270  | ((0x4800 | ((rd) << 8)) << 16))
271 
272 /* Move hi register (Thumb mode)
273  * rd: destination register
274  * rm: source register
275  */
276 #define ARMV4_5_T_MOV(rd, rm) \
277  ((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
278  (((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) \
279  | ((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
280  (((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) << 16))
281 
282 /* No operation (Thumb mode)
283  * NOTE: this is "MOV r8, r8" ... Thumb2 adds two
284  * architected NOPs, 16-bit and 32-bit.
285  */
286 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
287 
288 /* Move immediate to register (Thumb state)
289  * rd: destination register
290  * im: 8-bit immediate value
291  */
292 #define ARMV4_5_T_MOV_IM(rd, im) \
293  ((0x2000 | ((rd) << 8) | (im)) \
294  | ((0x2000 | ((rd) << 8) | (im)) << 16))
295 
296 /* Branch and Exchange
297  * rm: register containing branch target
298  */
299 #define ARMV4_5_T_BX(rm) \
300  ((0x4700 | ((rm) << 3)) \
301  | ((0x4700 | ((rm) << 3)) << 16))
302 
303 /* Branch (Thumb state)
304  * imm: Branch target
305  */
306 #define ARMV4_5_T_B(imm) \
307  ((0xe000 | (imm)) \
308  | ((0xe000 | (imm)) << 16))
309 
310 /* Breakpoint instruction (ARMv5) (Thumb state)
311  * Im: 8-bit immediate
312  */
313 #define ARMV5_T_BKPT(im) \
314  ((0xbe00 | (im)) \
315  | ((0xbe00 | (im)) << 16))
316 
317 /* Move to Register from Special Register
318  * 32 bit Thumb2 instruction
319  * rd: destination register
320  * sysm: source special register
321  */
322 #define ARM_T2_MRS(rd, sysm) \
323  ((0xF3EF) | ((0x8000 | (rd << 8) | sysm) << 16))
324 
325 /* Move from Register from Special Register
326  * 32 bit Thumb2 instruction
327  * rd: source register
328  * sysm: destination special register
329  */
330 #define ARM_T2_MSR(sysm, rn) \
331  ((0xF380 | (rn << 8)) | ((0x8800 | sysm) << 16))
332 
333 /* Change Processor State.
334  * 16 bit Thumb2 instruction
335  * rd: source register
336  * IF: A_FLAG and/or I_FLAG and/or F_FLAG
337  */
338 #define A_FLAG 4
339 #define I_FLAG 2
340 #define F_FLAG 1
341 #define ARM_T2_CPSID(_if) \
342  ((0xB660 | (1 << 8) | ((_if)&0x3)) \
343  | ((0xB660 | (1 << 8) | ((_if)&0x3)) << 16))
344 #define ARM_T2_CPSIE(_if) \
345  ((0xB660 | (0 << 8) | ((_if)&0x3)) \
346  | ((0xB660 | (0 << 8) | ((_if)&0x3)) << 16))
347 
348 #endif /* OPENOCD_TARGET_ARM_OPCODES_H */