131 #define FLASH_ERASE_TIMEOUT 250
132 #define FLASH_WRITE_TIMEOUT 50
138 #define F_HAS_DUAL_BANK BIT(0)
141 #define F_USE_ALL_WRPXX BIT(1)
143 #define F_HAS_TZ BIT(2)
145 #define F_HAS_L5_FLASH_REGS BIT(3)
148 #define F_QUAD_WORD_PROG BIT(4)
284 { 0x1000,
"1" }, { 0x1001,
"2" }, { 0x1003,
"3" }, { 0x1007,
"4" }
288 { 0x1000,
"A" }, { 0x1001,
"Z" }, { 0x2001,
"Y" },
293 { 0x1000,
"A" }, { 0x1001,
"Z" },
297 { 0x1000,
"A" }, { 0x1001,
"Z" },
305 { 0x1000,
"A/Z" } , { 0x2000,
"B" },
309 { 0x1000,
"A" }, { 0x2000,
"B" },
313 { 0x1000,
"A" }, { 0x1001,
"Z" }, { 0x2001,
"Y" },
317 { 0x1000,
"A" }, { 0x1001,
"Z" }, { 0x2001,
"Y" },
321 { 0x1000,
"A" }, { 0x1001,
"Z" }, { 0x2000,
"B" },
329 { 0x1000,
"A" }, { 0x2000,
"B" }, { 0x2001,
"Z" },
333 { 0x1000,
"A" }, { 0x2000,
"B" }, { 0x2001,
"Z" },
337 { 0x1000,
"A" }, { 0x1001,
"Z" }, { 0x1003,
"Y" }, { 0x100F,
"W" },
346 { 0x1000,
"A" }, { 0x2000,
"B" }, { 0x2001,
"Z" },
354 { 0x1000,
"A" }, { 0x1001,
"Z" },
358 { 0x1000,
"A" }, { 0x1001,
"Z" }, { 0x1003,
"Y" }, { 0x2000,
"B" },
359 { 0x2001,
"X" }, { 0x3000,
"C" }, { 0x3001,
"W" },
371 { 0x1000,
"A" }, { 0x2000,
"B" },
391 .device_str =
"STM32L47/L48xx",
392 .max_flash_size_kb = 1024,
394 .flash_regs_base = 0x40022000,
395 .fsize_addr = 0x1FFF75E0,
396 .otp_base = 0x1FFF7000,
403 .device_str =
"STM32L43/L44xx",
404 .max_flash_size_kb = 256,
406 .flash_regs_base = 0x40022000,
407 .fsize_addr = 0x1FFF75E0,
408 .otp_base = 0x1FFF7000,
415 .device_str =
"STM32C01xx",
416 .max_flash_size_kb = 32,
418 .flash_regs_base = 0x40022000,
419 .fsize_addr = 0x1FFF75A0,
420 .otp_base = 0x1FFF7000,
427 .device_str =
"STM32C03xx",
428 .max_flash_size_kb = 32,
430 .flash_regs_base = 0x40022000,
431 .fsize_addr = 0x1FFF75A0,
432 .otp_base = 0x1FFF7000,
439 .device_str =
"STM32U535/U545",
440 .max_flash_size_kb = 512,
442 .flash_regs_base = 0x40022000,
443 .fsize_addr = 0x0BFA07A0,
444 .otp_base = 0x0BFA0000,
451 .device_str =
"STM32G05/G06xx",
452 .max_flash_size_kb = 64,
454 .flash_regs_base = 0x40022000,
455 .fsize_addr = 0x1FFF75E0,
456 .otp_base = 0x1FFF7000,
463 .device_str =
"STM32G07/G08xx",
464 .max_flash_size_kb = 128,
466 .flash_regs_base = 0x40022000,
467 .fsize_addr = 0x1FFF75E0,
468 .otp_base = 0x1FFF7000,
475 .device_str =
"STM32L49/L4Axx",
476 .max_flash_size_kb = 1024,
478 .flash_regs_base = 0x40022000,
479 .fsize_addr = 0x1FFF75E0,
480 .otp_base = 0x1FFF7000,
487 .device_str =
"STM32L45/L46xx",
488 .max_flash_size_kb = 512,
490 .flash_regs_base = 0x40022000,
491 .fsize_addr = 0x1FFF75E0,
492 .otp_base = 0x1FFF7000,
499 .device_str =
"STM32L41/L42xx",
500 .max_flash_size_kb = 128,
502 .flash_regs_base = 0x40022000,
503 .fsize_addr = 0x1FFF75E0,
504 .otp_base = 0x1FFF7000,
511 .device_str =
"STM32G03x/G04xx",
512 .max_flash_size_kb = 64,
514 .flash_regs_base = 0x40022000,
515 .fsize_addr = 0x1FFF75E0,
516 .otp_base = 0x1FFF7000,
523 .device_str =
"STM32G0B/G0Cx",
524 .max_flash_size_kb = 512,
526 .flash_regs_base = 0x40022000,
527 .fsize_addr = 0x1FFF75E0,
528 .otp_base = 0x1FFF7000,
535 .device_str =
"STM32G43/G44xx",
536 .max_flash_size_kb = 128,
538 .flash_regs_base = 0x40022000,
539 .fsize_addr = 0x1FFF75E0,
540 .otp_base = 0x1FFF7000,
547 .device_str =
"STM32G47/G48xx",
548 .max_flash_size_kb = 512,
550 .flash_regs_base = 0x40022000,
551 .fsize_addr = 0x1FFF75E0,
552 .otp_base = 0x1FFF7000,
559 .device_str =
"STM32L4R/L4Sxx",
560 .max_flash_size_kb = 2048,
562 .flash_regs_base = 0x40022000,
563 .fsize_addr = 0x1FFF75E0,
564 .otp_base = 0x1FFF7000,
571 .device_str =
"STM32L4P/L4Qxx",
572 .max_flash_size_kb = 1024,
574 .flash_regs_base = 0x40022000,
575 .fsize_addr = 0x1FFF75E0,
576 .otp_base = 0x1FFF7000,
583 .device_str =
"STM32L55/L56xx",
584 .max_flash_size_kb = 512,
586 .flash_regs_base = 0x40022000,
587 .fsize_addr = 0x0BFA05E0,
588 .otp_base = 0x0BFA0000,
595 .device_str =
"STM32G49/G4Axx",
596 .max_flash_size_kb = 512,
598 .flash_regs_base = 0x40022000,
599 .fsize_addr = 0x1FFF75E0,
600 .otp_base = 0x1FFF7000,
607 .device_str =
"STM32U59/U5Axx",
608 .max_flash_size_kb = 4096,
610 .flash_regs_base = 0x40022000,
611 .fsize_addr = 0x0BFA07A0,
612 .otp_base = 0x0BFA0000,
619 .device_str =
"STM32U57/U58xx",
620 .max_flash_size_kb = 2048,
622 .flash_regs_base = 0x40022000,
623 .fsize_addr = 0x0BFA07A0,
624 .otp_base = 0x0BFA0000,
631 .device_str =
"STM32WBA5x",
632 .max_flash_size_kb = 1024,
634 .flash_regs_base = 0x40022000,
635 .fsize_addr = 0x0FF907A0,
636 .otp_base = 0x0FF90000,
643 .device_str =
"STM32WB1x",
644 .max_flash_size_kb = 320,
646 .flash_regs_base = 0x58004000,
647 .fsize_addr = 0x1FFF75E0,
648 .otp_base = 0x1FFF7000,
655 .device_str =
"STM32WB5x",
656 .max_flash_size_kb = 1024,
658 .flash_regs_base = 0x58004000,
659 .fsize_addr = 0x1FFF75E0,
660 .otp_base = 0x1FFF7000,
667 .device_str =
"STM32WB3x",
668 .max_flash_size_kb = 512,
670 .flash_regs_base = 0x58004000,
671 .fsize_addr = 0x1FFF75E0,
672 .otp_base = 0x1FFF7000,
679 .device_str =
"STM32WLE/WL5x",
680 .max_flash_size_kb = 256,
682 .flash_regs_base = 0x58004000,
683 .fsize_addr = 0x1FFF75E0,
684 .otp_base = 0x1FFF7000,
704 bank->driver_priv = stm32l4_info;
706 stm32l4_info->
probed =
false;
720 struct range *ranges,
unsigned int *ranges_count)
723 bool last_bit = 0, cur_bit;
724 for (
unsigned int i = 0; i < nbits; i++) {
727 if (cur_bit && !last_bit) {
729 ranges[*ranges_count - 1].
start = i;
730 ranges[*ranges_count - 1].
end = i;
731 }
else if (cur_bit && last_bit) {
733 ranges[*ranges_count - 1].
end = i;
756 char *str = calloc(1, ranges_count * (24 *
sizeof(
char)) + 1);
759 for (
unsigned int i = 0; i < ranges_count; i++) {
762 if (i < ranges_count - 1)
784 char *op_str = enable ?
"enabled" :
"disabled";
786 LOG_INFO(
"OTP memory (bank #%d) is %s%s for write commands",
788 stm32l4_info->
otp_enabled == enable ?
"already " :
"",
883 LOG_ERROR(
"timed out waiting for flash");
925 LOG_DEBUG(
"setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
927 const uint8_t secbb_regs[] = {
933 unsigned int num_secbb_regs =
ARRAY_SIZE(secbb_regs);
941 for (
unsigned int i = 0; i < num_secbb_regs; i++) {
986 LOG_ERROR(
"flash not unlocked STM32_FLASH_CR: %" PRIx32,
ctrl);
1019 LOG_ERROR(
"options not unlocked STM32_FLASH_CR: %" PRIx32,
ctrl);
1028 int retval, retval2;
1051 stm32l4_info->
probed =
false;
1064 uint32_t value, uint32_t
mask)
1067 uint32_t optiondata;
1068 int retval, retval2;
1076 const uint32_t *saved_flash_regs = stm32l4_info->
flash_regs;
1088 optiondata = (optiondata & ~
mask) | (value &
mask);
1146 int wrp2y_sectors_offset = -1;
1162 wrp2y_sectors_offset = 0;
1169 if (wrp2y_sectors_offset >= 0) {
1191 uint32_t wrp_value = (wrp_start & stm32l4_info->
wrpxxr_mask) | ((wrp_end & stm32l4_info->
wrpxxr_mask) << 16);
1200 for (
unsigned int i = 0; i < n_wrp; i++) {
1219 for (
unsigned int i = 0; i <
bank->num_sectors; i++)
1220 bank->sectors[i].is_protected = 0;
1223 for (
unsigned int i = 0; i < n_wrp; i++) {
1224 if (wrpxy[i].
used) {
1225 for (
int s = wrpxy[i].
first; s <= wrpxy[i].
last; s++)
1226 bank->sectors[s].is_protected = 1;
1237 int retval, retval2;
1239 assert((first <= last) && (last < bank->num_sectors));
1276 for (
unsigned int i = first; i <= last; i++) {
1277 uint32_t erase_flags;
1312 unsigned int first,
unsigned int last)
1317 for (i = first; i <= last; i++) {
1318 if (
bank->sectors[i].is_protected != set)
1320 else if (i == last) {
1321 LOG_INFO(
"The specified sectors are already %s", set ?
"protected" :
"unprotected");
1339 for (i = 0; i < n_wrp; i++) {
1340 if (wrpxy[i].
used) {
1341 for (
int p = wrpxy[i].
first; p <= wrpxy[i].
last; p++)
1348 struct range ranges[n_wrp + 1];
1349 unsigned int ranges_count = 0;
1354 if (ranges_count > 0) {
1356 LOG_DEBUG(
"current protected areas: %s", ranges_str);
1359 LOG_DEBUG(
"current protected areas: none");
1362 for (i = first; i <= last; i++)
1365 for (i = first; i <= last; i++)
1373 if (ranges_count > 0) {
1375 LOG_DEBUG(
"requested areas for protection: %s", ranges_str);
1378 LOG_DEBUG(
"requested areas for protection: none");
1380 if (ranges_count > n_wrp) {
1381 LOG_ERROR(
"cannot set the requested protection "
1382 "(only %u write protection areas are available)" , n_wrp);
1387 for (i = 0; i < n_wrp; i++) {
1393 for (i = 0; i < ranges_count; i++) {
1395 wrpxy[i].
last = ranges[i].
end;
1408 LOG_ERROR(
"cannot protect/unprotect OTP memory");
1449 static const uint8_t stm32l4_flash_write_code[] = {
1450 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1455 LOG_WARNING(
"no working area available, can't do block memory writes");
1460 sizeof(stm32l4_flash_write_code),
1461 stm32l4_flash_write_code);
1472 buffer_size &= ~(stm32l4_info->
data_width - 1);
1474 if (buffer_size < 256) {
1475 LOG_WARNING(
"large enough working area not available, can't do block memory writes");
1478 }
else if (buffer_size > 16384) {
1480 buffer_size = 16384;
1484 LOG_ERROR(
"allocating working area failed");
1507 struct stm32l4_loader_params loader_extra_params;
1519 (uint8_t *) &loader_extra_params);
1532 LOG_ERROR(
"error executing stm32l4 flash write algorithm");
1539 LOG_ERROR(
"flash memory write protected");
1542 LOG_ERROR(
"flash write failed = %08" PRIx32, error);
1582 const uint8_t *src =
buffer;
1583 const uint32_t data_width_in_words = stm32l4_info->
data_width / 4;
1613 LOG_ERROR(
"OTP memory is disabled for write commands");
1638 while ((head < tail) && (
offset >= (head + 1)->
offset)) {
1648 LOG_DEBUG(
"data: 0x%08" PRIx32
" - 0x%08" PRIx32
", sectors: 0x%08" PRIx32
" - 0x%08" PRIx32,
1654 while (head < tail) {
1655 if (head->
offset + head->
size != (head + 1)->offset) {
1658 bank->base + (head + 1)->offset - 1);
1687 LOG_WARNING(
"RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
1695 LOG_WARNING(
"falling back to programming without a flash loader (slower)");
1725 for (
unsigned int i = 0; i <
ARRAY_SIZE(dbgmcu_idcode); i++) {
1727 if ((retval ==
ERROR_OK) && ((*
id & 0xfff) != 0) && ((*
id & 0xfff) != 0xfff))
1737 LOG_ERROR(
"Flash requires Cortex-M target");
1772 const uint16_t rev_id = stm32l4_info->
idcode >> 16;
1773 for (
unsigned int i = 0; i < part_info->
num_revs; i++) {
1774 if (rev_id == part_info->
revs[i].
rev)
1775 return part_info->
revs[i].
str;
1794 uint16_t flash_size_kb = 0xffff;
1803 LOG_ERROR(
"Flash requires Cortex-M target");
1807 stm32l4_info->
probed =
false;
1814 const uint32_t device_id = stm32l4_info->
idcode & 0xFFF;
1830 const uint16_t rev_id = stm32l4_info->
idcode >> 16;
1832 LOG_INFO(
"device idcode = 0x%08" PRIx32
" (%s - Rev %s : 0x%04x)",
1864 LOG_ERROR(
"BUG: device supported incomplete");
1870 LOG_INFO(
"TZEN = %d : TrustZone %s by option bytes",
1872 stm32l4_info->
tzen ?
"enabled" :
"disabled");
1884 free(
bank->sectors);
1885 bank->num_sectors = 1;
1888 if (!
bank->sectors) {
1889 LOG_ERROR(
"failed to allocate bank sectors");
1893 stm32l4_info->
probed =
true;
1905 if (retval !=
ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
1907 LOG_WARNING(
"STM32 flash size failed, probe inaccurate - assuming %dk flash",
1915 LOG_WARNING(
"overriding size register by configured bank size - MAY CAUSE TROUBLE");
1919 LOG_INFO(
"flash size = %d KiB", flash_size_kb);
1922 assert((flash_size_kb != 0xffff) && flash_size_kb);
1930 int page_size_kb = 0;
1934 switch (device_id) {
1946 num_pages = flash_size_kb / page_size_kb;
1968 num_pages = flash_size_kb / page_size_kb;
1974 num_pages = flash_size_kb / page_size_kb;
1991 num_pages = flash_size_kb / page_size_kb;
1996 num_pages = flash_size_kb / page_size_kb;
2014 num_pages = flash_size_kb / page_size_kb;
2020 num_pages = flash_size_kb / page_size_kb;
2033 num_pages = flash_size_kb / page_size_kb;
2059 num_pages = flash_size_kb / page_size_kb;
2069 num_pages = flash_size_kb / page_size_kb;
2076 num_pages = flash_size_kb / page_size_kb;
2082 num_pages = flash_size_kb / page_size_kb;
2096 if (num_pages == 0) {
2098 LOG_ERROR(
"The specified flash size is less than page size");
2100 LOG_ERROR(
"Flash pages count cannot be zero");
2106 const int gap_size_kb = stm32l4_info->
hole_sectors * page_size_kb;
2108 if (gap_size_kb != 0) {
2109 LOG_INFO(
"gap detected from 0x%08x to 0x%08x",
2111 * page_size_kb * 1024,
2113 * page_size_kb + gap_size_kb) * 1024 - 1);
2129 assert((stm32l4_info->
wrpxxr_mask & 0xFFFF0000) == 0);
2132 free(
bank->sectors);
2134 bank->size = (flash_size_kb + gap_size_kb) * 1024;
2135 bank->num_sectors = num_pages;
2137 if (!
bank->sectors) {
2138 LOG_ERROR(
"failed to allocate bank sectors");
2142 for (
unsigned int i = 0; i <
bank->num_sectors; i++) {
2143 bank->sectors[i].offset = i * page_size_kb * 1024;
2147 bank->sectors[i].offset += gap_size_kb * 1024;
2148 bank->sectors[i].size = page_size_kb * 1024;
2149 bank->sectors[i].is_erased = -1;
2150 bank->sectors[i].is_protected = 1;
2153 stm32l4_info->
probed =
true;
2160 if (stm32l4_info->
probed) {
2179 if (stm32l4_info->
optr == optr_cur)
2192 const uint16_t rev_id = stm32l4_info->
idcode >> 16;
2195 if (stm32l4_info->
probed)
2206 int retval, retval2;
2299 uint32_t reg_offset, reg_addr;
2309 command_print(
CMD,
"Option Register: <0x%" PRIx32
"> = 0x%" PRIx32
"", reg_addr, value);
2324 uint32_t reg_offset;
2326 uint32_t
mask = 0xFFFFFFFF;
2335 "INFO: a reset or power cycle is required "
2336 "for the new settings to take effect.",
bank->driver->name);
2344 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2354 LOG_ERROR(
"This device does not have a TrustZone");
2366 LOG_INFO(
"Global TrustZone Security is %s", stm32l4_info->
tzen ?
"enabled" :
"disabled");
2373 if (new_tzen == stm32l4_info->
tzen) {
2374 LOG_INFO(
"The requested TZEN is already programmed");
2380 LOG_ERROR(
"TZEN can be set only when RDP level is 0");
2389 LOG_ERROR(
"Deactivation of TZEN is only possible when the RDP is changing to level 0");
2420 command_print(
CMD,
"stm32l4x option load completed. Power-on reset might be required");
2438 LOG_ERROR(
"cannot lock/unlock OTP memory");
2473 LOG_ERROR(
"cannot lock/unlock OTP memory");
2496 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2505 LOG_ERROR(
"OTP memory does not have write protection areas");
2512 if (strcmp(
CMD_ARGV[1],
"bank1") == 0)
2514 else if (strcmp(
CMD_ARGV[1],
"bank2") == 0)
2522 LOG_ERROR(
"this device has no second bank");
2525 LOG_ERROR(
"this device is configured in single bank mode");
2531 unsigned int n_wrp, i;
2542 for (i = 0; i < n_wrp; i++) {
2543 if (wrpxy[i].
used) {
2544 for (
int p = wrpxy[i].
first; p <= wrpxy[i].
last; p++)
2550 struct range ranges[n_wrp];
2551 unsigned int ranges_count = 0;
2555 if (ranges_count > 0) {
2580 if (strcmp(
CMD_ARGV[1],
"enable") == 0)
2582 else if (strcmp(
CMD_ARGV[1],
"disable") == 0)
2584 else if (strcmp(
CMD_ARGV[1],
"show") == 0)
2596 .handler = stm32l4_handle_lock_command,
2599 .help =
"Lock entire flash device.",
2603 .handler = stm32l4_handle_unlock_command,
2606 .help =
"Unlock entire protected flash device.",
2609 .name =
"mass_erase",
2610 .handler = stm32l4_handle_mass_erase_command,
2613 .help =
"Erase entire flash device.",
2616 .name =
"option_read",
2617 .handler = stm32l4_handle_option_read_command,
2619 .usage =
"bank_id reg_offset",
2620 .help =
"Read & Display device option bytes.",
2623 .name =
"option_write",
2624 .handler = stm32l4_handle_option_write_command,
2626 .usage =
"bank_id reg_offset value [mask]",
2627 .help =
"Write device option bit fields with provided value.",
2630 .name =
"trustzone",
2631 .handler = stm32l4_handle_trustzone_command,
2633 .usage =
"<bank_id> [enable|disable]",
2634 .help =
"Configure TrustZone security",
2638 .handler = stm32l4_handle_wrp_info_command,
2640 .usage =
"bank_id [bank1|bank2]",
2641 .help =
"list the protected areas using WRP",
2644 .name =
"option_load",
2645 .handler = stm32l4_handle_option_load_command,
2648 .help =
"Force re-load of device options (will cause device reset).",
2652 .handler = stm32l4_handle_otp_command,
2654 .usage =
"<bank_id> <enable|disable|show>",
2655 .help =
"OTP (One Time Programmable) memory write enable/disable",
2664 .help =
"stm32l4x flash command group",
2674 .flash_bank_command = stm32l4_flash_bank_command,
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
void destroy_reg_param(struct reg_param *param)
This defines formats and data structures used to talk to ADIv5 entities.
static struct armv7m_common * target_to_armv7m_safe(struct target *target)
#define ARMV7M_COMMON_MAGIC
Support functions to access arbitrary bits in a byte array.
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
static int test_bit(unsigned int nr, const volatile unsigned long *addr)
test_bit - Determine whether a bit is set
static void bitmap_zero(unsigned long *dst, unsigned int nbits)
bitmap_zero - Clears all the bits in memory
static void set_bit(unsigned int nr, volatile unsigned long *addr)
set_bit - Set a bit in memory
static void clear_bit(unsigned int nr, volatile unsigned long *addr)
clear_bit - Clear a bit in memory
#define DECLARE_BITMAP(name, bits)
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_PARSE_ENABLE(in, out)
parses an enable/disable command argument
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
#define ERROR_COMMAND_ARGUMENT_INVALID
static enum cortex_m_impl_part cortex_m_get_impl_part(struct target *target)
#define ERROR_FLASH_OPER_UNSUPPORTED
#define ERROR_FLASH_OPERATION_FAILED
#define ERROR_FLASH_DST_OUT_OF_BANK
struct flash_sector * alloc_block_array(uint32_t offset, uint32_t size, unsigned int num_blocks)
Allocate and fill an array of sectors or protection blocks.
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
void alive_sleep(uint64_t ms)
#define ERROR_NOT_IMPLEMENTED
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
struct rtt_control ctrl
Control block.
size_t size
Size of the control block search area.
static const struct stm32l4_rev stm32g05_g06xx_revs[]
static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id, struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
static int stm32l4_protect_check(struct flash_bank *bank)
#define FLASH_ERASE_TIMEOUT
static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, enum stm32l4_flash_reg_index reg_idx, int offset)
static const struct stm32l4_rev stm32l43_l44xx_revs[]
static const struct stm32l4_rev stm32u53_u54xx_revs[]
static const struct stm32l4_rev stm32u59_u5axx_revs[]
static const struct command_registration stm32l4_exec_command_handlers[]
static int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM]
@ STM32_FLASH_CR_WLK_INDEX
@ STM32_FLASH_WRP1AR_INDEX
@ STM32_FLASH_WRP2BR_INDEX
@ STM32_FLASH_OPTKEYR_INDEX
@ STM32_FLASH_WRP1BR_INDEX
@ STM32_FLASH_WRP2AR_INDEX
@ STM32_FLASH_REG_INDEX_NUM
static int stm32l4_perform_obl_launch(struct flash_bank *bank)
static const struct stm32l4_part_info stm32l4_parts[]
static char * range_print_alloc(struct range *ranges, unsigned int ranges_count)
static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
static const struct stm32l4_rev stm32g47_g48xx_revs[]
static int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
static bool stm32l4_otp_is_enabled(struct flash_bank *bank)
#define F_HAS_L5_FLASH_REGS
static const char * get_stm32l4_bank_type_str(struct flash_bank *bank)
static bool stm32l4_is_otp(struct flash_bank *bank)
static int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
static int range_print_one(struct range *range, char *str)
static const struct stm32l4_rev stm32g03_g04xx_revs[]
static const struct stm32l4_rev stm32c01xx_revs[]
static const char * device_families
static const struct stm32l4_rev stm32u57_u58xx_revs[]
static const struct command_registration stm32l4_command_handlers[]
static const struct stm32l4_rev stm32l45_l46xx_revs[]
static int stm32l4_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
static const struct stm32l4_rev stm32l4p_l4qxx_revs[]
static const struct stm32l4_rev stm32l41_l42xx_revs[]
static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
static const struct stm32l4_rev stm32l47_l48xx_revs[]
static const struct stm32l4_rev stm32l4r_l4sxx_revs[]
static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
static const struct stm32l4_rev stm32l55_l56xx_revs[]
static const struct stm32l4_rev stm32wb1xx_revs[]
static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
static const struct stm32l4_rev stm32wba5x_revs[]
static int stm32l4_mass_erase(struct flash_bank *bank)
static const char * get_stm32l4_rev_str(struct flash_bank *bank)
static int get_stm32l4_info(struct flash_bank *bank, struct command_invocation *cmd)
COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
static const struct stm32l4_rev stm32_g07_g08xx_revs[]
static const struct stm32l4_rev stm32g43_g44xx_revs[]
static const struct stm32l4_rev stm32c03xx_revs[]
static uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
static const struct stm32l4_rev stm32wle_wl5xx_revs[]
static int stm32l4_protect_same_bank(struct flash_bank *bank, enum stm32_bank_id bank_id, int set, unsigned int first, unsigned int last)
FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
set all FLASH_SECBB registers to the same value
static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
static const struct stm32l4_rev stm32g49_g4axx_revs[]
const struct flash_driver stm32l4x_flash
static int stm32l4_probe(struct flash_bank *bank)
static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM]
static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
static int stm32l4_read_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index, uint32_t *value)
static int stm32l4_unlock_option_reg(struct flash_bank *bank)
static const uint32_t stm32wl_cpu2_flash_regs[STM32_FLASH_REG_INDEX_NUM]
static int stm32l4_unlock_reg(struct flash_bank *bank)
static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
static const struct stm32l4_rev stm32wb3xx_revs[]
#define FLASH_WRITE_TIMEOUT
static const struct stm32l4_rev stm32wb5xx_revs[]
static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits, struct range *ranges, unsigned int *ranges_count)
static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM]
static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
static int stm32l4_write_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index, uint32_t value)
static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
static uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index)
static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
static const struct stm32l4_rev stm32l49_l4axx_revs[]
static int stm32l4_auto_probe(struct flash_bank *bank)
static const struct stm32l4_rev stm32g0b_g0cxx_revs[]
#define DEVID_STM32G03_G04XX
#define DEVID_STM32L55_L56XX
#define DEVID_STM32G0B_G0CXX
#define FLASH_SECBB_SECURE
#define FLASH_G0_DUAL_BANK
#define STM32_FLASH_S_BANK_BASE
#define DEVID_STM32G49_G4AXX
#define DEVID_STM32U53_U54XX
#define DEVID_STM32L4R_L4SXX
#define FLASH_L4_DUAL_BANK
#define DEVID_STM32G47_G48XX
#define FLASH_U5_DUALBANK
#define STM32_FLASH_BANK_BASE
#define FLASH_G4_DUAL_BANK
#define DEVID_STM32L47_L48XX
#define DEVID_STM32G07_G08XX
#define DEVID_STM32U59_U5AXX
#define DEVID_STM32L49_L4AXX
#define DEVID_STM32L43_L44XX
#define DEVID_STM32L41_L42XX
#define DEVID_STM32WLE_WL5XX
#define DEVID_STM32G05_G06XX
#define DEVID_STM32G43_G44XX
#define UID64_IDS_STM32WL
#define FLASH_SECBB_NON_SECURE
#define STM32L5_REGS_SEC_OFFSET
#define DEVID_STM32U57_U58XX
#define DBGMCU_IDCODE_L4_G4
#define DEVID_STM32L4P_L4QXX
#define DEVID_STM32L45_L46XX
uint64_t ap_num
ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coheren...
unsigned int common_magic
struct adiv5_ap * debug_ap
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Provides details of a flash bank, available either on-chip or through a major interface.
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Describes the geometry and status of a single flash sector within a flash bank.
uint32_t offset
Bus offset from start of the flash chip (in bytes).
uint32_t size
Number of bytes in this flash sector.
unsigned int bank1_sectors
const uint32_t * flash_regs
const struct stm32l4_part_info * part_info
const struct stm32l4_rev * revs
const uint32_t fsize_addr
const uint32_t flash_regs_base
const uint16_t max_flash_size_kb
uint8_t stack[LDR_STACK_SIZE]
enum stm32l4_flash_reg_index reg_idx
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
uint32_t target_get_working_area_avail(struct target *target)
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
int target_alloc_working_area_try(struct target *target, uint32_t size, struct working_area **area)
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
int target_run_flash_async_algorithm(struct target *target, const uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
Streams data to a circular buffer on target intended for consumption by code running asynchronously o...
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
#define ERROR_TARGET_NOT_HALTED
static bool target_was_examined(const struct target *target)
#define ERROR_TARGET_INVALID
#define ERROR_TARGET_NOT_EXAMINED
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
#define ERROR_TARGET_FAILURE
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.