OpenOCD
stm32l4x.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2015 by Uwe Bonnes *
5  * bon@elektron.ikp.physik.tu-darmstadt.de *
6  * *
7  * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
8  * tarek.bouchkati@gmail.com *
9  ***************************************************************************/
10 
11 #ifdef HAVE_CONFIG_H
12 #include "config.h"
13 #endif
14 
15 #include "imp.h"
16 #include <helper/align.h>
17 #include <helper/binarybuffer.h>
18 #include <helper/bits.h>
19 #include <target/algorithm.h>
20 #include <target/arm_adi_v5.h>
21 #include <target/cortex_m.h>
22 #include "stm32l4x.h"
23 
24 /* STM32L4xxx series for reference.
25  *
26  * RM0351 (STM32L4x5/STM32L4x6)
27  * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
28  *
29  * RM0394 (STM32L43x/44x/45x/46x)
30  * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
31  *
32  * RM0432 (STM32L4R/4Sxx)
33  * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
34  *
35  * STM32L476RG Datasheet (for erase timing)
36  * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
37  *
38  * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
39  * an option byte is available to map all sectors to the first bank.
40  * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
41  * handlers do!
42  *
43  * RM0394 devices have a single bank only.
44  *
45  * RM0432 devices have single and dual bank operating modes.
46  * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
47  * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
48  * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
49  *
50  * Bank mode is controlled by two different bits in option bytes register.
51  * - for STM32L4R/Sxx
52  * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
53  * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
54  * - for STM32L4P5/Q5x
55  * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
56  * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
57  */
58 
59 /* STM32WBxxx series for reference.
60  *
61  * RM0493 (STM32WBA52x)
62  * http://www.st.com/resource/en/reference_manual/dm00821869.pdf
63  *
64  * RM0434 (STM32WB55/WB35x)
65  * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
66  *
67  * RM0471 (STM32WB50/WB30x)
68  * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
69  *
70  * RM0473 (STM32WB15x)
71  * http://www.st.com/resource/en/reference_manual/dm00649196.pdf
72  *
73  * RM0478 (STM32WB10x)
74  * http://www.st.com/resource/en/reference_manual/dm00689203.pdf
75  */
76 
77 /* STM32WLxxx series for reference.
78  *
79  * RM0461 (STM32WLEx)
80  * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
81  *
82  * RM0453 (STM32WL5x)
83  * http://www.st.com/resource/en/reference_manual/dm00451556.pdf
84  */
85 
86 /* STM32C0xxx series for reference.
87  *
88  * RM0490 (STM32C0x1)
89  * http://www.st.com/resource/en/reference_manual/dm00781702.pdf
90  */
91 
92 /* STM32G0xxx series for reference.
93  *
94  * RM0444 (STM32G0x1)
95  * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
96  *
97  * RM0454 (STM32G0x0)
98  * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
99  */
100 
101 /* STM32G4xxx series for reference.
102  *
103  * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
104  * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
105  *
106  * Cat. 2 devices have single bank only, page size is 2kByte.
107  *
108  * Cat. 3 devices have single and dual bank operating modes,
109  * Page size is 2kByte (dual mode) or 4kByte (single mode).
110  *
111  * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
112  * Both banks are treated as a single OpenOCD bank.
113  *
114  * Cat. 4 devices have single bank only, page size is 2kByte.
115  */
116 
117 /* STM32L5xxx series for reference.
118  *
119  * RM0428 (STM32L552xx/STM32L562xx)
120  * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
121  */
122 
123 /* STM32U0xxx series for reference.
124  *
125  * RM0503 (STM32U0xx)
126  * https://www.st.com/resource/en/reference_manual/rm0503-stm32u0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
127  */
128 
129 /* STM32U5xxx series for reference.
130  *
131  * RM0456 (STM32U5xx)
132  * http://www.st.com/resource/en/reference_manual/dm00477635.pdf
133  */
134 
135 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
136 
137 #define FLASH_ERASE_TIMEOUT 250
138 #define FLASH_WRITE_TIMEOUT 50
139 
140 
141 /* relevant STM32L4 flags ****************************************************/
142 #define F_NONE 0
143 /* this flag indicates if the device flash is with dual bank architecture */
144 #define F_HAS_DUAL_BANK BIT(0)
145 /* this flags is used for dual bank devices only, it indicates if the
146  * 4 WRPxx are usable if the device is configured in single-bank mode */
147 #define F_USE_ALL_WRPXX BIT(1)
148 /* this flag indicates if the device embeds a TrustZone security feature */
149 #define F_HAS_TZ BIT(2)
150 /* this flag indicates if the device has the same flash registers as STM32L5 */
151 #define F_HAS_L5_FLASH_REGS BIT(3)
152 /* this flag indicates that programming should be done in quad-word
153  * the default programming word size is double-word */
154 #define F_QUAD_WORD_PROG BIT(4)
155 /* end of STM32L4 flags ******************************************************/
156 
157 
164  /* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
165  * so it uses the C2CR for flash operations and CR for checking locks and locking */
166  STM32_FLASH_CR_WLK_INDEX, /* FLASH_CR_WITH_LOCK */
173 };
174 
176  RDP_LEVEL_0 = 0xAA,
177  RDP_LEVEL_0_5 = 0x55, /* for devices with TrustZone enabled */
178  RDP_LEVEL_1 = 0x00,
179  RDP_LEVEL_2 = 0xCC
180 };
181 
183  [STM32_FLASH_ACR_INDEX] = 0x000,
184  [STM32_FLASH_KEYR_INDEX] = 0x008,
185  [STM32_FLASH_OPTKEYR_INDEX] = 0x00C,
186  [STM32_FLASH_SR_INDEX] = 0x010,
187  [STM32_FLASH_CR_INDEX] = 0x014,
188  [STM32_FLASH_OPTR_INDEX] = 0x020,
189  [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
190  [STM32_FLASH_WRP1BR_INDEX] = 0x030,
191  [STM32_FLASH_WRP2AR_INDEX] = 0x04C,
192  [STM32_FLASH_WRP2BR_INDEX] = 0x050,
193 };
194 
196  [STM32_FLASH_ACR_INDEX] = 0x000,
197  [STM32_FLASH_KEYR_INDEX] = 0x008,
198  [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
199  [STM32_FLASH_SR_INDEX] = 0x060,
200  [STM32_FLASH_CR_INDEX] = 0x064,
201  [STM32_FLASH_CR_WLK_INDEX] = 0x014,
202  [STM32_FLASH_OPTR_INDEX] = 0x020,
203  [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
204  [STM32_FLASH_WRP1BR_INDEX] = 0x030,
205 };
206 
208  [STM32_FLASH_ACR_INDEX] = 0x000,
209  [STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */
210  [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
211  [STM32_FLASH_SR_INDEX] = 0x020, /* NSSR */
212  [STM32_FLASH_CR_INDEX] = 0x028, /* NSCR */
213  [STM32_FLASH_OPTR_INDEX] = 0x040,
214  [STM32_FLASH_WRP1AR_INDEX] = 0x058,
215  [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
216  [STM32_FLASH_WRP2AR_INDEX] = 0x068,
217  [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
218 };
219 
221  [STM32_FLASH_ACR_INDEX] = 0x000,
222  [STM32_FLASH_KEYR_INDEX] = 0x00C, /* SECKEYR */
223  [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
224  [STM32_FLASH_SR_INDEX] = 0x024, /* SECSR */
225  [STM32_FLASH_CR_INDEX] = 0x02C, /* SECCR */
226  [STM32_FLASH_OPTR_INDEX] = 0x040,
227  [STM32_FLASH_WRP1AR_INDEX] = 0x058,
228  [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
229  [STM32_FLASH_WRP2AR_INDEX] = 0x068,
230  [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
231 };
232 
233 struct stm32l4_rev {
234  const uint16_t rev;
235  const char *str;
236 };
237 
239  uint16_t id;
240  const char *device_str;
241  const struct stm32l4_rev *revs;
242  const size_t num_revs;
243  const uint16_t max_flash_size_kb;
244  const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
245  const uint32_t flash_regs_base;
246  const uint32_t fsize_addr;
247  const uint32_t otp_base;
248  const uint32_t otp_size;
249 };
250 
252  bool probed;
253  uint32_t idcode;
254  unsigned int bank1_sectors;
257  uint32_t user_bank_size;
258  uint32_t data_width;
259  uint32_t cr_bker_mask;
260  uint32_t sr_bsy_mask;
261  uint32_t wrpxxr_mask;
263  uint32_t flash_regs_base;
264  const uint32_t *flash_regs;
266  enum stm32l4_rdp rdp;
267  bool tzen;
268  uint32_t optr;
269 };
270 
275 };
276 
277 struct stm32l4_wrp {
279  uint32_t value;
280  bool used;
281  int first;
282  int last;
283  int offset;
284 };
285 
286 /* human readable list of families this drivers supports (sorted alphabetically) */
287 static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U0/U5/WB/WL";
288 
289 static const struct stm32l4_rev stm32l47_l48xx_revs[] = {
290  { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
291 };
292 
293 static const struct stm32l4_rev stm32l43_l44xx_revs[] = {
294  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
295 };
296 
297 
298 static const struct stm32l4_rev stm32c01xx_revs[] = {
299  { 0x1000, "A" }, { 0x1001, "Z" },
300 };
301 
302 static const struct stm32l4_rev stm32c03xx_revs[] = {
303  { 0x1000, "A" }, { 0x1001, "Z" },
304 };
305 
306 static const struct stm32l4_rev stm32c05xx_revs[] = {
307  { 0x1000, "A" },
308 };
309 
310 static const struct stm32l4_rev stm32c071xx_revs[] = {
311  { 0x1001, "Z" },
312 };
313 
314 static const struct stm32l4_rev stm32c09xx_revs[] = {
315  { 0x1000, "A" },
316 };
317 
318 static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
319  { 0x1000, "A" },
320 };
321 
322 static const struct stm32l4_rev stm32_g07_g08xx_revs[] = {
323  { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
324 };
325 
326 static const struct stm32l4_rev stm32l49_l4axx_revs[] = {
327  { 0x1000, "A" }, { 0x2000, "B" },
328 };
329 
330 static const struct stm32l4_rev stm32l45_l46xx_revs[] = {
331  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
332 };
333 
334 static const struct stm32l4_rev stm32l41_l42xx_revs[] = {
335  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
336 };
337 
338 static const struct stm32l4_rev stm32g03_g04xx_revs[] = {
339  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
340 };
341 
342 static const struct stm32l4_rev stm32g0b_g0cxx_revs[] = {
343  { 0x1000, "A" },
344 };
345 
346 static const struct stm32l4_rev stm32u0xx_revs[] = {
347  { 0x1000, "A" },
348 };
349 
350 static const struct stm32l4_rev stm32g43_g44xx_revs[] = {
351  { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
352 };
353 
354 static const struct stm32l4_rev stm32g47_g48xx_revs[] = {
355  { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
356 };
357 
358 static const struct stm32l4_rev stm32l4r_l4sxx_revs[] = {
359  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
360  { 0x101F, "V" },
361 };
362 
363 static const struct stm32l4_rev stm32l4p_l4qxx_revs[] = {
364  { 0x1001, "Z" },
365 };
366 
367 static const struct stm32l4_rev stm32l55_l56xx_revs[] = {
368  { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
369 };
370 
371 static const struct stm32l4_rev stm32g49_g4axx_revs[] = {
372  { 0x1000, "A" },
373 };
374 
375 static const struct stm32l4_rev stm32u53_u54xx_revs[] = {
376  { 0x1000, "A" }, { 0x1001, "Z" },
377 };
378 
379 static const struct stm32l4_rev stm32u57_u58xx_revs[] = {
380  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
381  { 0x2001, "X" }, { 0x3000, "C" }, { 0x3001, "W" }, { 0x3007, "U" },
382 };
383 
384 static const struct stm32l4_rev stm32u59_u5axx_revs[] = {
385  { 0x3001, "X" }, { 0x3002, "W" },
386 };
387 
388 static const struct stm32l4_rev stm32u5f_u5gxx_revs[] = {
389  { 0x1000, "A" }, { 0x1001, "Z" },
390 };
391 
392 static const struct stm32l4_rev stm32wba5x_revs[] = {
393  { 0x1000, "A" },
394 };
395 
396 static const struct stm32l4_rev stm32wb1xx_revs[] = {
397  { 0x1000, "A" }, { 0x2000, "B" },
398 };
399 
400 static const struct stm32l4_rev stm32wb5xx_revs[] = {
401  { 0x2001, "2.1" },
402 };
403 
404 static const struct stm32l4_rev stm32wb3xx_revs[] = {
405  { 0x1000, "A" },
406 };
407 
408 static const struct stm32l4_rev stm32wle_wl5xx_revs[] = {
409  { 0x1000, "1.0" },
410 };
411 
412 static const struct stm32l4_part_info stm32l4_parts[] = {
413  {
415  .revs = stm32l47_l48xx_revs,
416  .num_revs = ARRAY_SIZE(stm32l47_l48xx_revs),
417  .device_str = "STM32L47/L48xx",
418  .max_flash_size_kb = 1024,
419  .flags = F_HAS_DUAL_BANK,
420  .flash_regs_base = 0x40022000,
421  .fsize_addr = 0x1FFF75E0,
422  .otp_base = 0x1FFF7000,
423  .otp_size = 1024,
424  },
425  {
426  .id = DEVID_STM32L43_L44XX,
427  .revs = stm32l43_l44xx_revs,
428  .num_revs = ARRAY_SIZE(stm32l43_l44xx_revs),
429  .device_str = "STM32L43/L44xx",
430  .max_flash_size_kb = 256,
431  .flags = F_NONE,
432  .flash_regs_base = 0x40022000,
433  .fsize_addr = 0x1FFF75E0,
434  .otp_base = 0x1FFF7000,
435  .otp_size = 1024,
436  },
437  {
438  .id = DEVID_STM32C01XX,
439  .revs = stm32c01xx_revs,
440  .num_revs = ARRAY_SIZE(stm32c01xx_revs),
441  .device_str = "STM32C01xx",
442  .max_flash_size_kb = 32,
443  .flags = F_NONE,
444  .flash_regs_base = 0x40022000,
445  .fsize_addr = 0x1FFF75A0,
446  .otp_base = 0x1FFF7000,
447  .otp_size = 1024,
448  },
449  {
450  .id = DEVID_STM32C03XX,
451  .revs = stm32c03xx_revs,
452  .num_revs = ARRAY_SIZE(stm32c03xx_revs),
453  .device_str = "STM32C03xx",
454  .max_flash_size_kb = 32,
455  .flags = F_NONE,
456  .flash_regs_base = 0x40022000,
457  .fsize_addr = 0x1FFF75A0,
458  .otp_base = 0x1FFF7000,
459  .otp_size = 1024,
460  },
461  {
462  .id = DEVID_STM32C05XX,
463  .revs = stm32c05xx_revs,
464  .num_revs = ARRAY_SIZE(stm32c05xx_revs),
465  .device_str = "STM32C05xx",
466  .max_flash_size_kb = 64,
467  .flags = F_NONE,
468  .flash_regs_base = 0x40022000,
469  .fsize_addr = 0x1FFF75A0,
470  .otp_base = 0x1FFF7000,
471  .otp_size = 1024,
472  },
473  {
474  .id = DEVID_STM32C071XX,
475  .revs = stm32c071xx_revs,
476  .num_revs = ARRAY_SIZE(stm32c071xx_revs),
477  .device_str = "STM32C071xx",
478  .max_flash_size_kb = 128,
479  .flags = F_NONE,
480  .flash_regs_base = 0x40022000,
481  .fsize_addr = 0x1FFF75A0,
482  .otp_base = 0x1FFF7000,
483  .otp_size = 1024,
484  },
485  {
486  .id = DEVID_STM32C09XX,
487  .revs = stm32c09xx_revs,
488  .num_revs = ARRAY_SIZE(stm32c09xx_revs),
489  .device_str = "STM32C09xx",
490  .max_flash_size_kb = 256,
491  .flags = F_NONE,
492  .flash_regs_base = 0x40022000,
493  .fsize_addr = 0x1FFF75A0,
494  .otp_base = 0x1FFF7000,
495  .otp_size = 1024,
496  },
497  {
498  .id = DEVID_STM32U53_U54XX,
499  .revs = stm32u53_u54xx_revs,
500  .num_revs = ARRAY_SIZE(stm32u53_u54xx_revs),
501  .device_str = "STM32U535/U545",
502  .max_flash_size_kb = 512,
504  .flash_regs_base = 0x40022000,
505  .fsize_addr = 0x0BFA07A0,
506  .otp_base = 0x0BFA0000,
507  .otp_size = 512,
508  },
509  {
510  .id = DEVID_STM32G05_G06XX,
511  .revs = stm32g05_g06xx_revs,
512  .num_revs = ARRAY_SIZE(stm32g05_g06xx_revs),
513  .device_str = "STM32G05/G06xx",
514  .max_flash_size_kb = 64,
515  .flags = F_NONE,
516  .flash_regs_base = 0x40022000,
517  .fsize_addr = 0x1FFF75E0,
518  .otp_base = 0x1FFF7000,
519  .otp_size = 1024,
520  },
521  {
522  .id = DEVID_STM32G07_G08XX,
523  .revs = stm32_g07_g08xx_revs,
524  .num_revs = ARRAY_SIZE(stm32_g07_g08xx_revs),
525  .device_str = "STM32G07/G08xx",
526  .max_flash_size_kb = 128,
527  .flags = F_NONE,
528  .flash_regs_base = 0x40022000,
529  .fsize_addr = 0x1FFF75E0,
530  .otp_base = 0x1FFF7000,
531  .otp_size = 1024,
532  },
533  {
534  .id = DEVID_STM32L49_L4AXX,
535  .revs = stm32l49_l4axx_revs,
536  .num_revs = ARRAY_SIZE(stm32l49_l4axx_revs),
537  .device_str = "STM32L49/L4Axx",
538  .max_flash_size_kb = 1024,
539  .flags = F_HAS_DUAL_BANK,
540  .flash_regs_base = 0x40022000,
541  .fsize_addr = 0x1FFF75E0,
542  .otp_base = 0x1FFF7000,
543  .otp_size = 1024,
544  },
545  {
546  .id = DEVID_STM32L45_L46XX,
547  .revs = stm32l45_l46xx_revs,
548  .num_revs = ARRAY_SIZE(stm32l45_l46xx_revs),
549  .device_str = "STM32L45/L46xx",
550  .max_flash_size_kb = 512,
551  .flags = F_NONE,
552  .flash_regs_base = 0x40022000,
553  .fsize_addr = 0x1FFF75E0,
554  .otp_base = 0x1FFF7000,
555  .otp_size = 1024,
556  },
557  {
558  .id = DEVID_STM32L41_L42XX,
559  .revs = stm32l41_l42xx_revs,
560  .num_revs = ARRAY_SIZE(stm32l41_l42xx_revs),
561  .device_str = "STM32L41/L42xx",
562  .max_flash_size_kb = 128,
563  .flags = F_NONE,
564  .flash_regs_base = 0x40022000,
565  .fsize_addr = 0x1FFF75E0,
566  .otp_base = 0x1FFF7000,
567  .otp_size = 1024,
568  },
569  {
570  .id = DEVID_STM32G03_G04XX,
571  .revs = stm32g03_g04xx_revs,
572  .num_revs = ARRAY_SIZE(stm32g03_g04xx_revs),
573  .device_str = "STM32G03x/G04xx",
574  .max_flash_size_kb = 64,
575  .flags = F_NONE,
576  .flash_regs_base = 0x40022000,
577  .fsize_addr = 0x1FFF75E0,
578  .otp_base = 0x1FFF7000,
579  .otp_size = 1024,
580  },
581  {
582  .id = DEVID_STM32G0B_G0CXX,
583  .revs = stm32g0b_g0cxx_revs,
584  .num_revs = ARRAY_SIZE(stm32g0b_g0cxx_revs),
585  .device_str = "STM32G0B/G0Cx",
586  .max_flash_size_kb = 512,
587  .flags = F_HAS_DUAL_BANK,
588  .flash_regs_base = 0x40022000,
589  .fsize_addr = 0x1FFF75E0,
590  .otp_base = 0x1FFF7000,
591  .otp_size = 1024,
592  },
593  {
594  .id = DEVID_STM32G43_G44XX,
595  .revs = stm32g43_g44xx_revs,
596  .num_revs = ARRAY_SIZE(stm32g43_g44xx_revs),
597  .device_str = "STM32G43/G44xx",
598  .max_flash_size_kb = 128,
599  .flags = F_NONE,
600  .flash_regs_base = 0x40022000,
601  .fsize_addr = 0x1FFF75E0,
602  .otp_base = 0x1FFF7000,
603  .otp_size = 1024,
604  },
605  {
606  .id = DEVID_STM32G47_G48XX,
607  .revs = stm32g47_g48xx_revs,
608  .num_revs = ARRAY_SIZE(stm32g47_g48xx_revs),
609  .device_str = "STM32G47/G48xx",
610  .max_flash_size_kb = 512,
611  .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
612  .flash_regs_base = 0x40022000,
613  .fsize_addr = 0x1FFF75E0,
614  .otp_base = 0x1FFF7000,
615  .otp_size = 1024,
616  },
617  {
618  .id = DEVID_STM32L4R_L4SXX,
619  .revs = stm32l4r_l4sxx_revs,
620  .num_revs = ARRAY_SIZE(stm32l4r_l4sxx_revs),
621  .device_str = "STM32L4R/L4Sxx",
622  .max_flash_size_kb = 2048,
623  .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
624  .flash_regs_base = 0x40022000,
625  .fsize_addr = 0x1FFF75E0,
626  .otp_base = 0x1FFF7000,
627  .otp_size = 1024,
628  },
629  {
630  .id = DEVID_STM32L4P_L4QXX,
631  .revs = stm32l4p_l4qxx_revs,
632  .num_revs = ARRAY_SIZE(stm32l4p_l4qxx_revs),
633  .device_str = "STM32L4P/L4Qxx",
634  .max_flash_size_kb = 1024,
635  .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
636  .flash_regs_base = 0x40022000,
637  .fsize_addr = 0x1FFF75E0,
638  .otp_base = 0x1FFF7000,
639  .otp_size = 1024,
640  },
641  {
642  .id = DEVID_STM32L55_L56XX,
643  .revs = stm32l55_l56xx_revs,
644  .num_revs = ARRAY_SIZE(stm32l55_l56xx_revs),
645  .device_str = "STM32L55/L56xx",
646  .max_flash_size_kb = 512,
648  .flash_regs_base = 0x40022000,
649  .fsize_addr = 0x0BFA05E0,
650  .otp_base = 0x0BFA0000,
651  .otp_size = 512,
652  },
653  {
654  .id = DEVID_STM32G49_G4AXX,
655  .revs = stm32g49_g4axx_revs,
656  .num_revs = ARRAY_SIZE(stm32g49_g4axx_revs),
657  .device_str = "STM32G49/G4Axx",
658  .max_flash_size_kb = 512,
659  .flags = F_NONE,
660  .flash_regs_base = 0x40022000,
661  .fsize_addr = 0x1FFF75E0,
662  .otp_base = 0x1FFF7000,
663  .otp_size = 1024,
664  },
665  {
666  .id = DEVID_STM32U031XX,
667  .revs = stm32u0xx_revs,
668  .num_revs = ARRAY_SIZE(stm32u0xx_revs),
669  .device_str = "STM32U031xx",
670  .max_flash_size_kb = 64,
671  .flags = F_NONE,
672  .flash_regs_base = 0x40022000,
673  .fsize_addr = 0x1FFF3EA0,
674  .otp_base = 0x1FFF6800,
675  .otp_size = 1024,
676  },
677  {
679  .revs = stm32u0xx_revs,
680  .num_revs = ARRAY_SIZE(stm32u0xx_revs),
681  .device_str = "STM32U073/U083xx",
682  .max_flash_size_kb = 256,
683  .flags = F_NONE,
684  .flash_regs_base = 0x40022000,
685  .fsize_addr = 0x1FFF6EA0,
686  .otp_base = 0x1FFF6800,
687  .otp_size = 1024,
688  },
689  {
690  .id = DEVID_STM32U59_U5AXX,
691  .revs = stm32u59_u5axx_revs,
692  .num_revs = ARRAY_SIZE(stm32u59_u5axx_revs),
693  .device_str = "STM32U59/U5Axx",
694  .max_flash_size_kb = 4096,
696  .flash_regs_base = 0x40022000,
697  .fsize_addr = 0x0BFA07A0,
698  .otp_base = 0x0BFA0000,
699  .otp_size = 512,
700  },
701  {
702  .id = DEVID_STM32U57_U58XX,
703  .revs = stm32u57_u58xx_revs,
704  .num_revs = ARRAY_SIZE(stm32u57_u58xx_revs),
705  .device_str = "STM32U57/U58xx",
706  .max_flash_size_kb = 2048,
708  .flash_regs_base = 0x40022000,
709  .fsize_addr = 0x0BFA07A0,
710  .otp_base = 0x0BFA0000,
711  .otp_size = 512,
712  },
713  {
714  .id = DEVID_STM32U5F_U5GXX,
715  .revs = stm32u5f_u5gxx_revs,
716  .num_revs = ARRAY_SIZE(stm32u5f_u5gxx_revs),
717  .device_str = "STM32U5F/U5Gxx",
718  .max_flash_size_kb = 4096,
720  .flash_regs_base = 0x40022000,
721  .fsize_addr = 0x0BFA07A0,
722  .otp_base = 0x0BFA0000,
723  .otp_size = 512,
724  },
725  {
726  .id = DEVID_STM32WBA5X,
727  .revs = stm32wba5x_revs,
728  .num_revs = ARRAY_SIZE(stm32wba5x_revs),
729  .device_str = "STM32WBA5x",
730  .max_flash_size_kb = 1024,
732  .flash_regs_base = 0x40022000,
733  .fsize_addr = 0x0FF907A0,
734  .otp_base = 0x0FF90000,
735  .otp_size = 512,
736  },
737  {
738  .id = DEVID_STM32WB1XX,
739  .revs = stm32wb1xx_revs,
740  .num_revs = ARRAY_SIZE(stm32wb1xx_revs),
741  .device_str = "STM32WB1x",
742  .max_flash_size_kb = 320,
743  .flags = F_NONE,
744  .flash_regs_base = 0x58004000,
745  .fsize_addr = 0x1FFF75E0,
746  .otp_base = 0x1FFF7000,
747  .otp_size = 1024,
748  },
749  {
750  .id = DEVID_STM32WB5XX,
751  .revs = stm32wb5xx_revs,
752  .num_revs = ARRAY_SIZE(stm32wb5xx_revs),
753  .device_str = "STM32WB5x",
754  .max_flash_size_kb = 1024,
755  .flags = F_NONE,
756  .flash_regs_base = 0x58004000,
757  .fsize_addr = 0x1FFF75E0,
758  .otp_base = 0x1FFF7000,
759  .otp_size = 1024,
760  },
761  {
762  .id = DEVID_STM32WB3XX,
763  .revs = stm32wb3xx_revs,
764  .num_revs = ARRAY_SIZE(stm32wb3xx_revs),
765  .device_str = "STM32WB3x",
766  .max_flash_size_kb = 512,
767  .flags = F_NONE,
768  .flash_regs_base = 0x58004000,
769  .fsize_addr = 0x1FFF75E0,
770  .otp_base = 0x1FFF7000,
771  .otp_size = 1024,
772  },
773  {
774  .id = DEVID_STM32WLE_WL5XX,
775  .revs = stm32wle_wl5xx_revs,
776  .num_revs = ARRAY_SIZE(stm32wle_wl5xx_revs),
777  .device_str = "STM32WLE/WL5x",
778  .max_flash_size_kb = 256,
779  .flags = F_NONE,
780  .flash_regs_base = 0x58004000,
781  .fsize_addr = 0x1FFF75E0,
782  .otp_base = 0x1FFF7000,
783  .otp_size = 1024,
784  },
785 };
786 
787 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
788 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
789 {
790  struct stm32l4_flash_bank *stm32l4_info;
791 
792  if (CMD_ARGC < 6)
794 
795  /* fix-up bank base address: 0 is used for normal flash memory */
796  if (bank->base == 0)
797  bank->base = STM32_FLASH_BANK_BASE;
798 
799  stm32l4_info = calloc(1, sizeof(struct stm32l4_flash_bank));
800  if (!stm32l4_info)
801  return ERROR_FAIL; /* Checkme: What better error to use?*/
802  bank->driver_priv = stm32l4_info;
803 
804  stm32l4_info->probed = false;
805  stm32l4_info->otp_enabled = false;
806  stm32l4_info->user_bank_size = bank->size;
807 
808  return ERROR_OK;
809 }
810 
811 /* bitmap helper extension */
812 struct range {
813  unsigned int start;
814  unsigned int end;
815 };
816 
817 static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits,
818  struct range *ranges, unsigned int *ranges_count)
819 {
820  *ranges_count = 0;
821  bool last_bit = 0, cur_bit;
822  for (unsigned int i = 0; i < nbits; i++) {
823  cur_bit = test_bit(i, bitmap);
824 
825  if (cur_bit && !last_bit) {
826  (*ranges_count)++;
827  ranges[*ranges_count - 1].start = i;
828  ranges[*ranges_count - 1].end = i;
829  } else if (cur_bit && last_bit) {
830  /* update (increment) the end this range */
831  ranges[*ranges_count - 1].end = i;
832  }
833 
834  last_bit = cur_bit;
835  }
836 }
837 
838 static inline int range_print_one(struct range *range, char *str)
839 {
840  if (range->start == range->end)
841  return sprintf(str, "[%d]", range->start);
842 
843  return sprintf(str, "[%d,%d]", range->start, range->end);
844 }
845 
846 static char *range_print_alloc(struct range *ranges, unsigned int ranges_count)
847 {
848  /* each range will be printed like the following: [start,end]
849  * start and end, both are unsigned int, an unsigned int takes 10 characters max
850  * plus 3 characters for '[', ',' and ']'
851  * thus means each range can take maximum 23 character
852  * after each range we add a ' ' as separator and finally we need the '\0'
853  * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
854  char *str = calloc(1, ranges_count * (24 * sizeof(char)) + 1);
855  char *ptr = str;
856 
857  for (unsigned int i = 0; i < ranges_count; i++) {
858  ptr += range_print_one(&(ranges[i]), ptr);
859 
860  if (i < ranges_count - 1)
861  *(ptr++) = ' ';
862  }
863 
864  return str;
865 }
866 
867 /* end of bitmap helper extension */
868 
869 static inline bool stm32l4_is_otp(struct flash_bank *bank)
870 {
871  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
872  return bank->base == stm32l4_info->part_info->otp_base;
873 }
874 
875 static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
876 {
877  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
878 
879  if (!stm32l4_is_otp(bank))
880  return ERROR_FAIL;
881 
882  char *op_str = enable ? "enabled" : "disabled";
883 
884  LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
885  bank->bank_number,
886  stm32l4_info->otp_enabled == enable ? "already " : "",
887  op_str);
888 
889  stm32l4_info->otp_enabled = enable;
890 
891  return ERROR_OK;
892 }
893 
894 static inline bool stm32l4_otp_is_enabled(struct flash_bank *bank)
895 {
896  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
897  return stm32l4_info->otp_enabled;
898 }
899 
901 {
902  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
903 
904  bool tzen = false;
905 
906  if (stm32l4_info->part_info->flags & F_HAS_TZ)
907  tzen = (stm32l4_info->optr & FLASH_TZEN) != 0;
908 
909  uint32_t rdp = stm32l4_info->optr & FLASH_RDP_MASK;
910 
911  /* for devices without TrustZone:
912  * RDP level 0 and 2 values are to 0xAA and 0xCC
913  * Any other value corresponds to RDP level 1
914  * for devices with TrusZone:
915  * RDP level 0 and 2 values are 0xAA and 0xCC
916  * RDP level 0.5 value is 0x55 only if TZEN = 1
917  * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
918  */
919 
920  if (rdp != RDP_LEVEL_0 && rdp != RDP_LEVEL_2) {
921  if (!tzen || (tzen && rdp != RDP_LEVEL_0_5))
922  rdp = RDP_LEVEL_1;
923  }
924 
925  stm32l4_info->tzen = tzen;
926  stm32l4_info->rdp = rdp;
927 }
928 
929 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
930 {
931  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
932  return stm32l4_info->flash_regs_base + reg_offset;
933 }
934 
935 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
936  enum stm32l4_flash_reg_index reg_index)
937 {
938  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
939  return stm32l4_get_flash_reg(bank, stm32l4_info->flash_regs[reg_index]);
940 }
941 
942 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
943 {
944  return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
945 }
946 
948  enum stm32l4_flash_reg_index reg_index, uint32_t *value)
949 {
950  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
951  return stm32l4_read_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
952 }
953 
954 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
955 {
956  return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
957 }
958 
960  enum stm32l4_flash_reg_index reg_index, uint32_t value)
961 {
962  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
963  return stm32l4_write_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
964 }
965 
967 {
968  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
969  uint32_t status;
970  int retval = ERROR_OK;
971 
972  /* wait for busy to clear */
973  for (;;) {
975  if (retval != ERROR_OK)
976  return retval;
977  LOG_DEBUG("status: 0x%" PRIx32 "", status);
978  if ((status & stm32l4_info->sr_bsy_mask) == 0)
979  break;
980  if (timeout-- <= 0) {
981  LOG_ERROR("timed out waiting for flash");
982  return ERROR_FAIL;
983  }
984  alive_sleep(1);
985  }
986 
987  if (status & FLASH_WRPERR) {
988  LOG_ERROR("stm32x device protected");
989  retval = ERROR_FAIL;
990  }
991 
992  /* Clear but report errors */
993  if (status & FLASH_ERROR) {
994  if (retval == ERROR_OK)
995  retval = ERROR_FAIL;
996  /* If this operation fails, we ignore it and report the original
997  * retval
998  */
1000  }
1001 
1002  return retval;
1003 }
1004 
1006 static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
1007 {
1008  /* This function should be used only with device with TrustZone, do just a security check */
1009  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1010  assert(stm32l4_info->part_info->flags & F_HAS_TZ);
1011 
1012  /* based on RM0438 Rev6 for STM32L5x devices:
1013  * to modify a page block-based security attribution, it is recommended to
1014  * 1- check that no flash operation is ongoing on the related page
1015  * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
1016  * this step is not need in case of JTAG direct access
1017  */
1019  if (retval != ERROR_OK)
1020  return retval;
1021 
1022  /* write SECBBxRy registers */
1023  LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
1024 
1025  const uint8_t secbb_regs[] = {
1026  FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
1027  FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
1028  };
1029 
1030 
1031  unsigned int num_secbb_regs = ARRAY_SIZE(secbb_regs);
1032 
1033  /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
1034  * then consider only the first half of secbb_regs
1035  */
1036  if (!stm32l4_info->dual_bank_mode)
1037  num_secbb_regs /= 2;
1038 
1039  for (unsigned int i = 0; i < num_secbb_regs; i++) {
1040  retval = stm32l4_write_flash_reg(bank, secbb_regs[i], value);
1041  if (retval != ERROR_OK)
1042  return retval;
1043  }
1044 
1045  return ERROR_OK;
1046 }
1047 
1049 {
1050  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1051  return (stm32l4_info->flash_regs[STM32_FLASH_CR_WLK_INDEX]) ?
1053 }
1054 
1056 {
1057  const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
1058  uint32_t ctrl;
1059 
1060  /* first check if not already unlocked
1061  * otherwise writing on STM32_FLASH_KEYR will fail
1062  */
1063  int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
1064  if (retval != ERROR_OK)
1065  return retval;
1066 
1067  if ((ctrl & FLASH_LOCK) == 0)
1068  return ERROR_OK;
1069 
1070  /* unlock flash registers */
1072  if (retval != ERROR_OK)
1073  return retval;
1074 
1076  if (retval != ERROR_OK)
1077  return retval;
1078 
1079  retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
1080  if (retval != ERROR_OK)
1081  return retval;
1082 
1083  if (ctrl & FLASH_LOCK) {
1084  LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
1085  return ERROR_TARGET_FAILURE;
1086  }
1087 
1088  return ERROR_OK;
1089 }
1090 
1092 {
1093  const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
1094  uint32_t ctrl;
1095 
1096  int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
1097  if (retval != ERROR_OK)
1098  return retval;
1099 
1100  if ((ctrl & FLASH_OPTLOCK) == 0)
1101  return ERROR_OK;
1102 
1103  /* unlock option registers */
1105  if (retval != ERROR_OK)
1106  return retval;
1107 
1109  if (retval != ERROR_OK)
1110  return retval;
1111 
1112  retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
1113  if (retval != ERROR_OK)
1114  return retval;
1115 
1116  if (ctrl & FLASH_OPTLOCK) {
1117  LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
1118  return ERROR_TARGET_FAILURE;
1119  }
1120 
1121  return ERROR_OK;
1122 }
1123 
1125 {
1126  int retval, retval2;
1127 
1128  retval = stm32l4_unlock_reg(bank);
1129  if (retval != ERROR_OK)
1130  goto err_lock;
1131 
1132  retval = stm32l4_unlock_option_reg(bank);
1133  if (retval != ERROR_OK)
1134  goto err_lock;
1135 
1136  /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
1137  * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
1138  * "Note: If the read protection is set while the debugger is still
1139  * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
1140  */
1141 
1142  /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
1143  /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
1144  * then just ignore the returned value */
1146 
1147  /* Need to re-probe after change */
1148  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1149  stm32l4_info->probed = false;
1150 
1151 err_lock:
1154 
1155  if (retval != ERROR_OK)
1156  return retval;
1157 
1158  return retval2;
1159 }
1160 
1161 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
1162  uint32_t value, uint32_t mask)
1163 {
1164  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1165  uint32_t optiondata;
1166  int retval, retval2;
1167 
1168  retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
1169  if (retval != ERROR_OK)
1170  return retval;
1171 
1172  /* for STM32L5 and similar devices, use always non-secure
1173  * registers for option bytes programming */
1174  const uint32_t *saved_flash_regs = stm32l4_info->flash_regs;
1175  if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
1176  stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1177 
1178  retval = stm32l4_unlock_reg(bank);
1179  if (retval != ERROR_OK)
1180  goto err_lock;
1181 
1182  retval = stm32l4_unlock_option_reg(bank);
1183  if (retval != ERROR_OK)
1184  goto err_lock;
1185 
1186  optiondata = (optiondata & ~mask) | (value & mask);
1187 
1188  retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
1189  if (retval != ERROR_OK)
1190  goto err_lock;
1191 
1193  if (retval != ERROR_OK)
1194  goto err_lock;
1195 
1197 
1198 err_lock:
1201  stm32l4_info->flash_regs = saved_flash_regs;
1202 
1203  if (retval != ERROR_OK)
1204  return retval;
1205 
1206  return retval2;
1207 }
1208 
1209 static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy,
1210  enum stm32l4_flash_reg_index reg_idx, int offset)
1211 {
1212  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1213  int ret;
1214 
1215  wrpxy->reg_idx = reg_idx;
1216  wrpxy->offset = offset;
1217 
1218  ret = stm32l4_read_flash_reg_by_index(bank, wrpxy->reg_idx , &wrpxy->value);
1219  if (ret != ERROR_OK)
1220  return ret;
1221 
1222  wrpxy->first = (wrpxy->value & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1223  wrpxy->last = ((wrpxy->value >> 16) & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1224  wrpxy->used = wrpxy->first <= wrpxy->last;
1225 
1226  return ERROR_OK;
1227 }
1228 
1229 static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id,
1230  struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
1231 {
1232  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1233  int ret;
1234 
1235  *n_wrp = 0;
1236 
1237  /* for single bank devices there is 2 WRP regions.
1238  * for dual bank devices there is 2 WRP regions per bank,
1239  * if configured as single bank only 2 WRP are usable
1240  * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
1241  * note: this should be revised, if a device will have the SWAP banks option
1242  */
1243 
1244  int wrp2y_sectors_offset = -1; /* -1 : unused */
1245 
1246  /* if bank_id is BANK1 or ALL_BANKS */
1247  if (dev_bank_id != STM32_BANK2) {
1248  /* get FLASH_WRP1AR */
1249  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1AR_INDEX, 0);
1250  if (ret != ERROR_OK)
1251  return ret;
1252 
1253  /* get WRP1BR */
1254  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1BR_INDEX, 0);
1255  if (ret != ERROR_OK)
1256  return ret;
1257 
1258  /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
1259  if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode)
1260  wrp2y_sectors_offset = 0;
1261  }
1262 
1263  /* if bank_id is BANK2 or ALL_BANKS */
1264  if (dev_bank_id != STM32_BANK1 && stm32l4_info->dual_bank_mode)
1265  wrp2y_sectors_offset = stm32l4_info->bank1_sectors;
1266 
1267  if (wrp2y_sectors_offset >= 0) {
1268  /* get WRP2AR */
1269  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2AR_INDEX, wrp2y_sectors_offset);
1270  if (ret != ERROR_OK)
1271  return ret;
1272 
1273  /* get WRP2BR */
1274  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2BR_INDEX, wrp2y_sectors_offset);
1275  if (ret != ERROR_OK)
1276  return ret;
1277  }
1278 
1279  return ERROR_OK;
1280 }
1281 
1282 static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
1283 {
1284  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1285 
1286  int wrp_start = wrpxy->first - wrpxy->offset;
1287  int wrp_end = wrpxy->last - wrpxy->offset;
1288 
1289  uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16);
1290 
1291  return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff);
1292 }
1293 
1294 static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
1295 {
1296  int ret;
1297 
1298  for (unsigned int i = 0; i < n_wrp; i++) {
1299  ret = stm32l4_write_one_wrpxy(bank, &wrpxy[i]);
1300  if (ret != ERROR_OK)
1301  return ret;
1302  }
1303 
1304  return ERROR_OK;
1305 }
1306 
1308 {
1309  unsigned int n_wrp;
1310  struct stm32l4_wrp wrpxy[4];
1311 
1312  int ret = stm32l4_get_all_wrpxy(bank, STM32_ALL_BANKS, wrpxy, &n_wrp);
1313  if (ret != ERROR_OK)
1314  return ret;
1315 
1316  /* initialize all sectors as unprotected */
1317  for (unsigned int i = 0; i < bank->num_sectors; i++)
1318  bank->sectors[i].is_protected = 0;
1319 
1320  /* now check WRPxy and mark the protected sectors */
1321  for (unsigned int i = 0; i < n_wrp; i++) {
1322  if (wrpxy[i].used) {
1323  for (int s = wrpxy[i].first; s <= wrpxy[i].last; s++)
1324  bank->sectors[s].is_protected = 1;
1325  }
1326  }
1327 
1328  return ERROR_OK;
1329 }
1330 
1331 static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
1332  unsigned int last)
1333 {
1334  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1335  int retval, retval2;
1336 
1337  assert((first <= last) && (last < bank->num_sectors));
1338 
1339  if (stm32l4_is_otp(bank)) {
1340  LOG_ERROR("cannot erase OTP memory");
1342  }
1343 
1344  if (bank->target->state != TARGET_HALTED) {
1345  LOG_ERROR("Target not halted");
1346  return ERROR_TARGET_NOT_HALTED;
1347  }
1348 
1349  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1350  /* set all FLASH pages as secure */
1352  if (retval != ERROR_OK) {
1353  /* restore all FLASH pages as non-secure */
1354  stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1355  return retval;
1356  }
1357  }
1358 
1359  retval = stm32l4_unlock_reg(bank);
1360  if (retval != ERROR_OK)
1361  goto err_lock;
1362 
1363  /*
1364  Sector Erase
1365  To erase a sector, follow the procedure below:
1366  1. Check that no Flash memory operation is ongoing by
1367  checking the BSY bit in the FLASH_SR register
1368  2. Set the PER bit and select the page and bank
1369  you wish to erase in the FLASH_CR register
1370  3. Set the STRT bit in the FLASH_CR register
1371  4. Wait for the BSY bit to be cleared
1372  */
1373 
1374  for (unsigned int i = first; i <= last; i++) {
1375  uint32_t erase_flags;
1376  erase_flags = FLASH_PER | FLASH_STRT;
1377 
1378  if (i >= stm32l4_info->bank1_sectors) {
1379  uint8_t snb;
1380  snb = i - stm32l4_info->bank1_sectors;
1381  erase_flags |= snb << FLASH_PAGE_SHIFT | stm32l4_info->cr_bker_mask;
1382  } else
1383  erase_flags |= i << FLASH_PAGE_SHIFT;
1385  if (retval != ERROR_OK)
1386  break;
1387 
1389  if (retval != ERROR_OK)
1390  break;
1391  }
1392 
1393 err_lock:
1395 
1396  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1397  /* restore all FLASH pages as non-secure */
1399  if (retval3 != ERROR_OK)
1400  return retval3;
1401  }
1402 
1403  if (retval != ERROR_OK)
1404  return retval;
1405 
1406  return retval2;
1407 }
1408 
1409 static int stm32l4_protect_same_bank(struct flash_bank *bank, enum stm32_bank_id bank_id, int set,
1410  unsigned int first, unsigned int last)
1411 {
1412  unsigned int i;
1413 
1414  /* check if the desired protection is already configured */
1415  for (i = first; i <= last; i++) {
1416  if (bank->sectors[i].is_protected != set)
1417  break;
1418  else if (i == last) {
1419  LOG_INFO("The specified sectors are already %s", set ? "protected" : "unprotected");
1420  return ERROR_OK;
1421  }
1422  }
1423 
1424  /* all sectors from first to last (or part of them) could have different
1425  * protection other than the requested */
1426  unsigned int n_wrp;
1427  struct stm32l4_wrp wrpxy[4];
1428 
1429  int ret = stm32l4_get_all_wrpxy(bank, bank_id, wrpxy, &n_wrp);
1430  if (ret != ERROR_OK)
1431  return ret;
1432 
1433  /* use bitmap and range helpers to optimize the WRP usage */
1434  DECLARE_BITMAP(pages, bank->num_sectors);
1435  bitmap_zero(pages, bank->num_sectors);
1436 
1437  for (i = 0; i < n_wrp; i++) {
1438  if (wrpxy[i].used) {
1439  for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
1440  set_bit(p, pages);
1441  }
1442  }
1443 
1444  /* we have at most 'n_wrp' WRP areas
1445  * add one range if the user is trying to protect a fifth range */
1446  struct range ranges[n_wrp + 1];
1447  unsigned int ranges_count = 0;
1448 
1449  bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1450 
1451  /* pretty-print the currently protected ranges */
1452  if (ranges_count > 0) {
1453  char *ranges_str = range_print_alloc(ranges, ranges_count);
1454  LOG_DEBUG("current protected areas: %s", ranges_str);
1455  free(ranges_str);
1456  } else
1457  LOG_DEBUG("current protected areas: none");
1458 
1459  if (set) { /* flash protect */
1460  for (i = first; i <= last; i++)
1461  set_bit(i, pages);
1462  } else { /* flash unprotect */
1463  for (i = first; i <= last; i++)
1464  clear_bit(i, pages);
1465  }
1466 
1467  /* check the ranges_count after the user request */
1468  bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1469 
1470  /* pretty-print the requested areas for protection */
1471  if (ranges_count > 0) {
1472  char *ranges_str = range_print_alloc(ranges, ranges_count);
1473  LOG_DEBUG("requested areas for protection: %s", ranges_str);
1474  free(ranges_str);
1475  } else
1476  LOG_DEBUG("requested areas for protection: none");
1477 
1478  if (ranges_count > n_wrp) {
1479  LOG_ERROR("cannot set the requested protection "
1480  "(only %u write protection areas are available)" , n_wrp);
1481  return ERROR_FAIL;
1482  }
1483 
1484  /* re-init all WRPxy as disabled (first > last)*/
1485  for (i = 0; i < n_wrp; i++) {
1486  wrpxy[i].first = wrpxy[i].offset + 1;
1487  wrpxy[i].last = wrpxy[i].offset;
1488  }
1489 
1490  /* then configure WRPxy areas */
1491  for (i = 0; i < ranges_count; i++) {
1492  wrpxy[i].first = ranges[i].start;
1493  wrpxy[i].last = ranges[i].end;
1494  }
1495 
1496  /* finally write WRPxy registers */
1497  return stm32l4_write_all_wrpxy(bank, wrpxy, n_wrp);
1498 }
1499 
1500 static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
1501 {
1502  struct target *target = bank->target;
1503  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1504 
1505  if (stm32l4_is_otp(bank)) {
1506  LOG_ERROR("cannot protect/unprotect OTP memory");
1508  }
1509 
1510  if (target->state != TARGET_HALTED) {
1511  LOG_ERROR("Target not halted");
1512  return ERROR_TARGET_NOT_HALTED;
1513  }
1514 
1515  /* refresh the sectors' protection */
1516  int ret = stm32l4_protect_check(bank);
1517  if (ret != ERROR_OK)
1518  return ret;
1519 
1520  /* the requested sectors could be located into bank1 and/or bank2 */
1521  if (last < stm32l4_info->bank1_sectors) {
1522  return stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, last);
1523  } else if (first >= stm32l4_info->bank1_sectors) {
1524  return stm32l4_protect_same_bank(bank, STM32_BANK2, set, first, last);
1525  } else {
1526  ret = stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, stm32l4_info->bank1_sectors - 1);
1527  if (ret != ERROR_OK)
1528  return ret;
1529 
1530  return stm32l4_protect_same_bank(bank, STM32_BANK2, set, stm32l4_info->bank1_sectors, last);
1531  }
1532 }
1533 
1534 /* count is the size divided by stm32l4_info->data_width */
1535 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
1536  uint32_t offset, uint32_t count)
1537 {
1538  struct target *target = bank->target;
1539  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1540  struct working_area *write_algorithm;
1541  struct working_area *source;
1542  uint32_t address = bank->base + offset;
1543  struct reg_param reg_params[5];
1544  struct armv7m_algorithm armv7m_info;
1545  int retval = ERROR_OK;
1546 
1547  static const uint8_t stm32l4_flash_write_code[] = {
1548 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1549  };
1550 
1551  if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
1552  &write_algorithm) != ERROR_OK) {
1553  LOG_WARNING("no working area available, can't do block memory writes");
1555  }
1556 
1557  retval = target_write_buffer(target, write_algorithm->address,
1558  sizeof(stm32l4_flash_write_code),
1559  stm32l4_flash_write_code);
1560  if (retval != ERROR_OK) {
1561  target_free_working_area(target, write_algorithm);
1562  return retval;
1563  }
1564 
1565  /* data_width should be multiple of double-word */
1566  assert(stm32l4_info->data_width % 8 == 0);
1567  const size_t extra_size = sizeof(struct stm32l4_work_area);
1568  uint32_t buffer_size = target_get_working_area_avail(target) - extra_size;
1569  /* buffer_size should be multiple of stm32l4_info->data_width */
1570  buffer_size &= ~(stm32l4_info->data_width - 1);
1571 
1572  if (buffer_size < 256) {
1573  LOG_WARNING("large enough working area not available, can't do block memory writes");
1574  target_free_working_area(target, write_algorithm);
1576  } else if (buffer_size > 16384) {
1577  /* probably won't benefit from more than 16k ... */
1578  buffer_size = 16384;
1579  }
1580 
1582  LOG_ERROR("allocating working area failed");
1584  }
1585 
1586  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1587  armv7m_info.core_mode = ARM_MODE_THREAD;
1588 
1589  /* contrib/loaders/flash/stm32/stm32l4x.c:write() arguments */
1590  init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* stm32l4_work_area ptr , status (out) */
1591  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
1592  init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
1593  init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (of stm32l4_info->data_width) */
1594 
1595  buf_set_u32(reg_params[0].value, 0, 32, source->address);
1596  buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
1597  buf_set_u32(reg_params[2].value, 0, 32, address);
1598  buf_set_u32(reg_params[3].value, 0, 32, count);
1599 
1600  /* write algo stack pointer */
1601  init_reg_param(&reg_params[4], "sp", 32, PARAM_OUT);
1602  buf_set_u32(reg_params[4].value, 0, 32, source->address +
1603  offsetof(struct stm32l4_work_area, stack) + LDR_STACK_SIZE);
1604 
1605  struct stm32l4_loader_params loader_extra_params;
1606 
1607  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_addr,
1609  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_cr_addr,
1611  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_word_size,
1612  stm32l4_info->data_width);
1613  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_bsy_mask,
1614  stm32l4_info->sr_bsy_mask);
1615 
1616  retval = target_write_buffer(target, source->address, sizeof(loader_extra_params),
1617  (uint8_t *) &loader_extra_params);
1618  if (retval != ERROR_OK)
1619  return retval;
1620 
1622  0, NULL,
1623  ARRAY_SIZE(reg_params), reg_params,
1624  source->address + offsetof(struct stm32l4_work_area, fifo),
1625  source->size - offsetof(struct stm32l4_work_area, fifo),
1626  write_algorithm->address, 0,
1627  &armv7m_info);
1628 
1629  if (retval == ERROR_FLASH_OPERATION_FAILED) {
1630  LOG_ERROR("error executing stm32l4 flash write algorithm");
1631 
1632  uint32_t error;
1634  error &= FLASH_ERROR;
1635 
1636  if (error & FLASH_WRPERR)
1637  LOG_ERROR("flash memory write protected");
1638 
1639  if (error != 0) {
1640  LOG_ERROR("flash write failed = %08" PRIx32, error);
1641  /* Clear but report errors */
1643  retval = ERROR_FAIL;
1644  }
1645  }
1646 
1648  target_free_working_area(target, write_algorithm);
1649 
1650  destroy_reg_param(&reg_params[0]);
1651  destroy_reg_param(&reg_params[1]);
1652  destroy_reg_param(&reg_params[2]);
1653  destroy_reg_param(&reg_params[3]);
1654  destroy_reg_param(&reg_params[4]);
1655 
1656  return retval;
1657 }
1658 
1659 /* count is the size divided by stm32l4_info->data_width */
1660 static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer,
1661  uint32_t offset, uint32_t count)
1662 {
1663  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1664  struct target *target = bank->target;
1665  uint32_t address = bank->base + offset;
1666  int retval = ERROR_OK;
1667 
1668  /* wait for BSY bit */
1670  if (retval != ERROR_OK)
1671  return retval;
1672 
1673  /* set PG in FLASH_CR */
1675  if (retval != ERROR_OK)
1676  return retval;
1677 
1678 
1679  /* write directly to flash memory */
1680  const uint8_t *src = buffer;
1681  const uint32_t data_width_in_words = stm32l4_info->data_width / 4;
1682  while (count--) {
1683  retval = target_write_memory(target, address, 4, data_width_in_words, src);
1684  if (retval != ERROR_OK)
1685  return retval;
1686 
1687  /* wait for BSY bit */
1689  if (retval != ERROR_OK)
1690  return retval;
1691 
1692  src += stm32l4_info->data_width;
1693  address += stm32l4_info->data_width;
1694  }
1695 
1696  /* reset PG in FLASH_CR */
1698  if (retval != ERROR_OK)
1699  return retval;
1700 
1701  return retval;
1702 }
1703 
1704 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
1705  uint32_t offset, uint32_t count)
1706 {
1707  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1708  int retval = ERROR_OK, retval2;
1709 
1711  LOG_ERROR("OTP memory is disabled for write commands");
1712  return ERROR_FAIL;
1713  }
1714 
1715  if (bank->target->state != TARGET_HALTED) {
1716  LOG_ERROR("Target not halted");
1717  return ERROR_TARGET_NOT_HALTED;
1718  }
1719 
1720  /* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
1721  assert(stm32l4_info->data_width % 8 == 0);
1722 
1723  /* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
1724  * The flash infrastructure ensures it, do just a security check */
1725  assert(offset % stm32l4_info->data_width == 0);
1726  assert(count % stm32l4_info->data_width == 0);
1727 
1728  /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1729  * data to be written does not go into a gap:
1730  * suppose buffer is fully contained in bank from sector 0 to sector
1731  * num->sectors - 1 and sectors are ordered according to offset
1732  */
1733  struct flash_sector *head = &bank->sectors[0];
1734  struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
1735 
1736  while ((head < tail) && (offset >= (head + 1)->offset)) {
1737  /* buffer does not intersect head nor gap behind head */
1738  head++;
1739  }
1740 
1741  while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
1742  /* buffer does not intersect tail nor gap before tail */
1743  --tail;
1744  }
1745 
1746  LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
1747  offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
1748 
1749  /* Now check that there is no gap from head to tail, this should work
1750  * even for multiple or non-symmetric gaps
1751  */
1752  while (head < tail) {
1753  if (head->offset + head->size != (head + 1)->offset) {
1754  LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
1755  bank->base + head->offset + head->size,
1756  bank->base + (head + 1)->offset - 1);
1757  retval = ERROR_FLASH_DST_OUT_OF_BANK;
1758  }
1759  head++;
1760  }
1761 
1762  if (retval != ERROR_OK)
1763  return retval;
1764 
1765  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1766  /* set all FLASH pages as secure */
1768  if (retval != ERROR_OK) {
1769  /* restore all FLASH pages as non-secure */
1770  stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1771  return retval;
1772  }
1773  }
1774 
1775  retval = stm32l4_unlock_reg(bank);
1776  if (retval != ERROR_OK)
1777  goto err_lock;
1778 
1779 
1780  /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
1781  * the debug is possible only in non-secure state.
1782  * Thus means the flashloader will run in non-secure mode,
1783  * and the workarea need to be in non-secure RAM */
1784  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
1785  LOG_WARNING("RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
1786 
1787  /* first try to write using the loader, for better performance */
1789  count / stm32l4_info->data_width);
1790 
1791  /* if resources are not available write without a loader */
1792  if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1793  LOG_WARNING("falling back to programming without a flash loader (slower)");
1795  count / stm32l4_info->data_width);
1796  }
1797 
1798 err_lock:
1800 
1801  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1802  /* restore all FLASH pages as non-secure */
1804  if (retval3 != ERROR_OK)
1805  return retval3;
1806  }
1807 
1808  if (retval != ERROR_OK) {
1809  LOG_ERROR("block write failed");
1810  return retval;
1811  }
1812  return retval2;
1813 }
1814 
1815 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
1816 {
1817  int retval = ERROR_OK;
1818  struct target *target = bank->target;
1819 
1820  /* try reading possible IDCODE registers, in the following order */
1821  uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
1822 
1823  for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) {
1824  retval = target_read_u32(target, dbgmcu_idcode[i], id);
1825  if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
1826  return ERROR_OK;
1827  }
1828 
1829  /* Workaround for STM32WL5x devices:
1830  * DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
1831  * to solve this read the UID64 (IEEE 64-bit unique device ID register) */
1832 
1833  struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1834  if (!armv7m) {
1835  LOG_ERROR("Flash requires Cortex-M target");
1836  return ERROR_TARGET_INVALID;
1837  }
1838 
1839  /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1840  * Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
1842  armv7m->debug_ap && armv7m->debug_ap->ap_num == 1) {
1843  uint32_t uid64_ids;
1844 
1845  /* UID64 is contains
1846  * - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
1847  * - Bits 31:08 : STID (company ID) = 0x0080E1
1848  * - Bits 07:00 : DEVID (device ID) = 0x15
1849  *
1850  * read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
1851  */
1852  retval = target_read_u32(target, UID64_IDS, &uid64_ids);
1853  if (retval == ERROR_OK && uid64_ids == UID64_IDS_STM32WL) {
1854  /* force the DEV_ID to DEVID_STM32WLE_WL5XX and the REV_ID to unknown */
1855  *id = DEVID_STM32WLE_WL5XX;
1856  return ERROR_OK;
1857  }
1858  }
1859 
1860  LOG_ERROR("can't get the device id");
1861  return (retval == ERROR_OK) ? ERROR_FAIL : retval;
1862 }
1863 
1864 static const char *get_stm32l4_rev_str(struct flash_bank *bank)
1865 {
1866  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1867  const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
1868  assert(part_info);
1869 
1870  const uint16_t rev_id = stm32l4_info->idcode >> 16;
1871  for (unsigned int i = 0; i < part_info->num_revs; i++) {
1872  if (rev_id == part_info->revs[i].rev)
1873  return part_info->revs[i].str;
1874  }
1875  return "'unknown'";
1876 }
1877 
1878 static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
1879 {
1880  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1881  assert(stm32l4_info->part_info);
1882  return stm32l4_is_otp(bank) ? "OTP" :
1883  stm32l4_info->dual_bank_mode ? "Flash dual" :
1884  "Flash single";
1885 }
1886 
1887 static int stm32l4_probe(struct flash_bank *bank)
1888 {
1889  struct target *target = bank->target;
1890  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1891  const struct stm32l4_part_info *part_info;
1892  uint16_t flash_size_kb = 0xffff;
1893 
1894  if (!target_was_examined(target)) {
1895  LOG_ERROR("Target not examined yet");
1897  }
1898 
1899  struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1900  if (!armv7m) {
1901  LOG_ERROR("Flash requires Cortex-M target");
1902  return ERROR_TARGET_INVALID;
1903  }
1904 
1905  stm32l4_info->probed = false;
1906 
1907  /* read stm32 device id registers */
1908  int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
1909  if (retval != ERROR_OK)
1910  return retval;
1911 
1912  const uint32_t device_id = stm32l4_info->idcode & 0xFFF;
1913 
1914  for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
1915  if (device_id == stm32l4_parts[n].id) {
1916  stm32l4_info->part_info = &stm32l4_parts[n];
1917  break;
1918  }
1919  }
1920 
1921  if (!stm32l4_info->part_info) {
1922  LOG_WARNING("Cannot identify target as an %s family device.", device_families);
1923  return ERROR_FAIL;
1924  }
1925 
1926  part_info = stm32l4_info->part_info;
1927  const char *rev_str = get_stm32l4_rev_str(bank);
1928  const uint16_t rev_id = stm32l4_info->idcode >> 16;
1929 
1930  LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)",
1931  stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
1932 
1933  stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
1934  stm32l4_info->data_width = (part_info->flags & F_QUAD_WORD_PROG) ? 16 : 8;
1935  stm32l4_info->cr_bker_mask = FLASH_BKER;
1936  stm32l4_info->sr_bsy_mask = FLASH_BSY;
1937 
1938  /* Set flash write alignment boundaries.
1939  * Ask the flash infrastructure to ensure required alignment */
1940  bank->write_start_alignment = stm32l4_info->data_width;
1941  bank->write_end_alignment = stm32l4_info->data_width;
1942 
1943  /* Initialize the flash registers layout */
1944  if (part_info->flags & F_HAS_L5_FLASH_REGS)
1945  stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1946  else
1947  stm32l4_info->flash_regs = stm32l4_flash_regs;
1948 
1949  /* read flash option register */
1951  if (retval != ERROR_OK)
1952  return retval;
1953 
1955 
1956  /* for devices with TrustZone, use flash secure registers when TZEN=1 and RDP is LEVEL_0 */
1957  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1958  if (part_info->flags & F_HAS_L5_FLASH_REGS) {
1959  stm32l4_info->flash_regs_base |= STM32L5_REGS_SEC_OFFSET;
1960  stm32l4_info->flash_regs = stm32l5_s_flash_regs;
1961  } else {
1962  LOG_ERROR("BUG: device supported incomplete");
1963  return ERROR_NOT_IMPLEMENTED;
1964  }
1965  }
1966 
1967  if (part_info->flags & F_HAS_TZ)
1968  LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1969  stm32l4_info->tzen,
1970  stm32l4_info->tzen ? "enabled" : "disabled");
1971 
1972  LOG_INFO("RDP level %s (0x%02X)",
1973  stm32l4_info->rdp == RDP_LEVEL_0 ? "0" : stm32l4_info->rdp == RDP_LEVEL_0_5 ? "0.5" : "1",
1974  stm32l4_info->rdp);
1975 
1976  if (stm32l4_is_otp(bank)) {
1977  bank->size = part_info->otp_size;
1978 
1979  LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT, bank->size, bank->base);
1980 
1981  /* OTP memory is considered as one sector */
1982  free(bank->sectors);
1983  bank->num_sectors = 1;
1984  bank->sectors = alloc_block_array(0, part_info->otp_size, 1);
1985 
1986  if (!bank->sectors) {
1987  LOG_ERROR("failed to allocate bank sectors");
1988  return ERROR_FAIL;
1989  }
1990 
1991  stm32l4_info->probed = true;
1992  return ERROR_OK;
1993  } else if (bank->base != STM32_FLASH_BANK_BASE && bank->base != STM32_FLASH_S_BANK_BASE) {
1994  LOG_ERROR("invalid bank base address");
1995  return ERROR_FAIL;
1996  }
1997 
1998  /* get flash size from target. */
1999  retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
2000 
2001  /* failed reading flash size or flash size invalid (early silicon),
2002  * default to max target family */
2003  if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
2004  || flash_size_kb > part_info->max_flash_size_kb) {
2005  LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
2006  part_info->max_flash_size_kb);
2007  flash_size_kb = part_info->max_flash_size_kb;
2008  }
2009 
2010  /* if the user sets the size manually then ignore the probed value
2011  * this allows us to work around devices that have a invalid flash size register value */
2012  if (stm32l4_info->user_bank_size) {
2013  LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
2014  flash_size_kb = stm32l4_info->user_bank_size / 1024;
2015  }
2016 
2017  LOG_INFO("flash size = %d KiB", flash_size_kb);
2018 
2019  /* did we assign a flash size? */
2020  assert((flash_size_kb != 0xffff) && flash_size_kb);
2021 
2022  const bool is_max_flash_size = flash_size_kb == stm32l4_info->part_info->max_flash_size_kb;
2023 
2024  stm32l4_info->bank1_sectors = 0;
2025  stm32l4_info->hole_sectors = 0;
2026 
2027  int num_pages = 0;
2028  int page_size_kb = 0;
2029 
2030  stm32l4_info->dual_bank_mode = false;
2031 
2032  switch (device_id) {
2033  case DEVID_STM32L47_L48XX:
2034  case DEVID_STM32L49_L4AXX:
2035  /* if flash size is max (1M) the device is always dual bank
2036  * STM32L47/L48xx: has variants with 512K
2037  * STM32L49/L4Axx: has variants with 512 and 256
2038  * for these variants:
2039  * if DUAL_BANK = 0 -> single bank
2040  * else -> dual bank without gap
2041  * note: the page size is invariant
2042  */
2043  page_size_kb = 2;
2044  num_pages = flash_size_kb / page_size_kb;
2045  stm32l4_info->bank1_sectors = num_pages;
2046 
2047  /* check DUAL_BANK option bit if the flash is less than 1M */
2048  if (is_max_flash_size || (stm32l4_info->optr & FLASH_L4_DUAL_BANK)) {
2049  stm32l4_info->dual_bank_mode = true;
2050  stm32l4_info->bank1_sectors = num_pages / 2;
2051  }
2052  break;
2053  case DEVID_STM32L43_L44XX:
2054  case DEVID_STM32C01XX:
2055  case DEVID_STM32C03XX:
2056  case DEVID_STM32C05XX:
2057  case DEVID_STM32C071XX:
2058  case DEVID_STM32C09XX:
2059  case DEVID_STM32G05_G06XX:
2060  case DEVID_STM32G07_G08XX:
2061  case DEVID_STM32U031XX:
2063  case DEVID_STM32L45_L46XX:
2064  case DEVID_STM32L41_L42XX:
2065  case DEVID_STM32G03_G04XX:
2066  case DEVID_STM32G43_G44XX:
2067  case DEVID_STM32G49_G4AXX:
2068  case DEVID_STM32WB1XX:
2069  /* single bank flash */
2070  page_size_kb = 2;
2071  num_pages = flash_size_kb / page_size_kb;
2072  stm32l4_info->bank1_sectors = num_pages;
2073  break;
2074  case DEVID_STM32G0B_G0CXX:
2075  /* single/dual bank depending on DUAL_BANK option bit */
2076  page_size_kb = 2;
2077  num_pages = flash_size_kb / page_size_kb;
2078  stm32l4_info->bank1_sectors = num_pages;
2079  stm32l4_info->cr_bker_mask = FLASH_BKER_G0;
2080 
2081  /* check DUAL_BANK bit */
2082  if (stm32l4_info->optr & FLASH_G0_DUAL_BANK) {
2083  stm32l4_info->sr_bsy_mask = FLASH_BSY | FLASH_BSY2;
2084  stm32l4_info->dual_bank_mode = true;
2085  stm32l4_info->bank1_sectors = num_pages / 2;
2086  }
2087  break;
2088  case DEVID_STM32G47_G48XX:
2089  /* STM32G47/8 can be single/dual bank:
2090  * if DUAL_BANK = 0 -> single bank
2091  * else -> dual bank WITH gap
2092  */
2093  page_size_kb = 4;
2094  num_pages = flash_size_kb / page_size_kb;
2095  stm32l4_info->bank1_sectors = num_pages;
2096  if (stm32l4_info->optr & FLASH_G4_DUAL_BANK) {
2097  stm32l4_info->dual_bank_mode = true;
2098  page_size_kb = 2;
2099  num_pages = flash_size_kb / page_size_kb;
2100  stm32l4_info->bank1_sectors = num_pages / 2;
2101 
2102  /* for devices with trimmed flash, there is a gap between both banks */
2103  stm32l4_info->hole_sectors =
2104  (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
2105  }
2106  break;
2107  case DEVID_STM32L4R_L4SXX:
2108  case DEVID_STM32L4P_L4QXX:
2109  /* STM32L4R/S can be single/dual bank:
2110  * if size = 2M check DBANK bit
2111  * if size = 1M check DB1M bit
2112  * STM32L4P/Q can be single/dual bank
2113  * if size = 1M check DBANK bit
2114  * if size = 512K check DB512K bit (same as DB1M bit)
2115  */
2116  page_size_kb = 8;
2117  num_pages = flash_size_kb / page_size_kb;
2118  stm32l4_info->bank1_sectors = num_pages;
2119  if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L4R_DBANK)) ||
2120  (!is_max_flash_size && (stm32l4_info->optr & FLASH_LRR_DB1M))) {
2121  stm32l4_info->dual_bank_mode = true;
2122  page_size_kb = 4;
2123  num_pages = flash_size_kb / page_size_kb;
2124  stm32l4_info->bank1_sectors = num_pages / 2;
2125  }
2126  break;
2127  case DEVID_STM32L55_L56XX:
2128  /* STM32L55/L56xx can be single/dual bank:
2129  * if size = 512K check DBANK bit
2130  * if size = 256K check DB256K bit
2131  *
2132  * default page size is 4kb, if DBANK = 1, the page size is 2kb.
2133  */
2134 
2135  page_size_kb = (stm32l4_info->optr & FLASH_L5_DBANK) ? 2 : 4;
2136  num_pages = flash_size_kb / page_size_kb;
2137  stm32l4_info->bank1_sectors = num_pages;
2138 
2139  if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DBANK)) ||
2140  (!is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DB256))) {
2141  stm32l4_info->dual_bank_mode = true;
2142  stm32l4_info->bank1_sectors = num_pages / 2;
2143  }
2144  break;
2145  case DEVID_STM32U53_U54XX:
2146  case DEVID_STM32U57_U58XX:
2147  case DEVID_STM32U59_U5AXX:
2148  case DEVID_STM32U5F_U5GXX:
2149  /* according to RM0456 Rev 4, Chapter 7.3.1 and 7.9.13
2150  * U53x/U54x have 512K max flash size:
2151  * 512K variants are always in DUAL BANK mode
2152  * 256K and 128K variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2153  * U57x/U58x have 2M max flash size:
2154  * 2M variants are always in DUAL BANK mode
2155  * 1M variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2156  * U59x/U5Ax/U5Fx/U5Gx have 4M max flash size:
2157  * 4M variants are always in DUAL BANK mode
2158  * 2M variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2159  * Note: flash banks are always contiguous
2160  */
2161 
2162  page_size_kb = 8;
2163  num_pages = flash_size_kb / page_size_kb;
2164  stm32l4_info->bank1_sectors = num_pages;
2165  if (is_max_flash_size || (stm32l4_info->optr & FLASH_U5_DUALBANK)) {
2166  stm32l4_info->dual_bank_mode = true;
2167  stm32l4_info->bank1_sectors = num_pages / 2;
2168  }
2169  break;
2170  case DEVID_STM32WBA5X:
2171  /* single bank flash */
2172  page_size_kb = 8;
2173  num_pages = flash_size_kb / page_size_kb;
2174  stm32l4_info->bank1_sectors = num_pages;
2175  break;
2176  case DEVID_STM32WB5XX:
2177  case DEVID_STM32WB3XX:
2178  /* single bank flash */
2179  page_size_kb = 4;
2180  num_pages = flash_size_kb / page_size_kb;
2181  stm32l4_info->bank1_sectors = num_pages;
2182  break;
2183  case DEVID_STM32WLE_WL5XX:
2184  /* single bank flash */
2185  page_size_kb = 2;
2186  num_pages = flash_size_kb / page_size_kb;
2187  stm32l4_info->bank1_sectors = num_pages;
2188 
2189  /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
2190  * Using HLA adapters armv7m->debug_ap is null, and checking ap_num triggers a segfault */
2191  if (armv7m->debug_ap && armv7m->debug_ap->ap_num == 1)
2192  stm32l4_info->flash_regs = stm32wl_cpu2_flash_regs;
2193  break;
2194  default:
2195  LOG_ERROR("unsupported device");
2196  return ERROR_FAIL;
2197  }
2198 
2199  /* ensure that at least there is 1 flash sector / page */
2200  if (num_pages == 0) {
2201  if (stm32l4_info->user_bank_size)
2202  LOG_ERROR("The specified flash size is less than page size");
2203 
2204  LOG_ERROR("Flash pages count cannot be zero");
2205  return ERROR_FAIL;
2206  }
2207 
2208  LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
2209 
2210  const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
2211 
2212  if (gap_size_kb != 0) {
2213  LOG_INFO("gap detected from 0x%08x to 0x%08x",
2214  STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
2215  * page_size_kb * 1024,
2216  STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
2217  * page_size_kb + gap_size_kb) * 1024 - 1);
2218  }
2219 
2220  /* number of significant bits in WRPxxR differs per device,
2221  * always right adjusted, on some devices non-implemented
2222  * bits read as '0', on others as '1' ...
2223  * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
2224  */
2225 
2226  /* use *max_flash_size* instead of actual size as the trimmed versions
2227  * certainly use the same number of bits
2228  */
2229  uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
2230 
2231  /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
2232  stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
2233  assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
2234  LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
2235 
2236  free(bank->sectors);
2237 
2238  bank->size = (flash_size_kb + gap_size_kb) * 1024;
2239  bank->num_sectors = num_pages;
2240  bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
2241  if (!bank->sectors) {
2242  LOG_ERROR("failed to allocate bank sectors");
2243  return ERROR_FAIL;
2244  }
2245 
2246  for (unsigned int i = 0; i < bank->num_sectors; i++) {
2247  bank->sectors[i].offset = i * page_size_kb * 1024;
2248  /* in dual bank configuration, if there is a gap between banks
2249  * we fix up the sector offset to consider this gap */
2250  if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
2251  bank->sectors[i].offset += gap_size_kb * 1024;
2252  bank->sectors[i].size = page_size_kb * 1024;
2253  bank->sectors[i].is_erased = -1;
2254  bank->sectors[i].is_protected = 1;
2255  }
2256 
2257  stm32l4_info->probed = true;
2258  return ERROR_OK;
2259 }
2260 
2262 {
2263  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2264  if (stm32l4_info->probed) {
2265  uint32_t optr_cur;
2266 
2267  /* save flash_regs_base */
2268  uint32_t saved_flash_regs_base = stm32l4_info->flash_regs_base;
2269 
2270  /* for devices with TrustZone, use NS flash registers to read OPTR */
2271  if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
2272  stm32l4_info->flash_regs_base &= ~STM32L5_REGS_SEC_OFFSET;
2273 
2274  /* read flash option register and re-probe if optr value is changed */
2276 
2277  /* restore saved flash_regs_base */
2278  stm32l4_info->flash_regs_base = saved_flash_regs_base;
2279 
2280  if (retval != ERROR_OK)
2281  return retval;
2282 
2283  if (stm32l4_info->optr == optr_cur)
2284  return ERROR_OK;
2285  }
2286 
2287  return stm32l4_probe(bank);
2288 }
2289 
2291 {
2292  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2293  const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
2294 
2295  if (part_info) {
2296  const uint16_t rev_id = stm32l4_info->idcode >> 16;
2297  command_print_sameline(cmd, "%s - Rev %s : 0x%04x", part_info->device_str,
2298  get_stm32l4_rev_str(bank), rev_id);
2299  if (stm32l4_info->probed)
2301  } else {
2302  command_print_sameline(cmd, "Cannot identify target as an %s device", device_families);
2303  }
2304 
2305  return ERROR_OK;
2306 }
2307 
2309 {
2310  int retval, retval2;
2311  struct target *target = bank->target;
2312  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2313 
2314  if (stm32l4_is_otp(bank)) {
2315  LOG_ERROR("cannot erase OTP memory");
2317  }
2318 
2319  uint32_t action = FLASH_MER1;
2320 
2321  if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)
2322  action |= FLASH_MER2;
2323 
2324  if (target->state != TARGET_HALTED) {
2325  LOG_ERROR("Target not halted");
2326  return ERROR_TARGET_NOT_HALTED;
2327  }
2328 
2329  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2330  /* set all FLASH pages as secure */
2332  if (retval != ERROR_OK) {
2333  /* restore all FLASH pages as non-secure */
2334  stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
2335  return retval;
2336  }
2337  }
2338 
2339  retval = stm32l4_unlock_reg(bank);
2340  if (retval != ERROR_OK)
2341  goto err_lock;
2342 
2343  /* mass erase flash memory */
2345  if (retval != ERROR_OK)
2346  goto err_lock;
2347 
2349  if (retval != ERROR_OK)
2350  goto err_lock;
2351 
2353  if (retval != ERROR_OK)
2354  goto err_lock;
2355 
2357 
2358 err_lock:
2360 
2361  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2362  /* restore all FLASH pages as non-secure */
2364  if (retval3 != ERROR_OK)
2365  return retval3;
2366  }
2367 
2368  if (retval != ERROR_OK)
2369  return retval;
2370 
2371  return retval2;
2372 }
2373 
2374 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
2375 {
2376  if (CMD_ARGC != 1)
2378 
2379  struct flash_bank *bank;
2380  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2381  if (retval != ERROR_OK)
2382  return retval;
2383 
2384  retval = stm32l4_mass_erase(bank);
2385  if (retval == ERROR_OK)
2386  command_print(CMD, "stm32l4x mass erase complete");
2387  else
2388  command_print(CMD, "stm32l4x mass erase failed");
2389 
2390  return retval;
2391 }
2392 
2393 COMMAND_HANDLER(stm32l4_handle_option_read_command)
2394 {
2395  if (CMD_ARGC != 2)
2397 
2398  struct flash_bank *bank;
2399  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2400  if (retval != ERROR_OK)
2401  return retval;
2402 
2403  uint32_t reg_offset, reg_addr;
2404  uint32_t value = 0;
2405 
2406  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2407  reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
2408 
2409  retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
2410  if (retval != ERROR_OK)
2411  return retval;
2412 
2413  command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
2414 
2415  return retval;
2416 }
2417 
2418 COMMAND_HANDLER(stm32l4_handle_option_write_command)
2419 {
2420  if (CMD_ARGC != 3 && CMD_ARGC != 4)
2422 
2423  struct flash_bank *bank;
2424  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2425  if (retval != ERROR_OK)
2426  return retval;
2427 
2428  uint32_t reg_offset;
2429  uint32_t value = 0;
2430  uint32_t mask = 0xFFFFFFFF;
2431 
2432  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2433  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
2434 
2435  if (CMD_ARGC > 3)
2437 
2438  command_print(CMD, "%s Option written.\n"
2439  "INFO: a reset or power cycle is required "
2440  "for the new settings to take effect.", bank->driver->name);
2441 
2442  retval = stm32l4_write_option(bank, reg_offset, value, mask);
2443  return retval;
2444 }
2445 
2446 COMMAND_HANDLER(stm32l4_handle_trustzone_command)
2447 {
2448  if (CMD_ARGC < 1 || CMD_ARGC > 2)
2450 
2451  struct flash_bank *bank;
2452  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2453  if (retval != ERROR_OK)
2454  return retval;
2455 
2456  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2457  if (!(stm32l4_info->part_info->flags & F_HAS_TZ)) {
2458  LOG_ERROR("This device does not have a TrustZone");
2459  return ERROR_FAIL;
2460  }
2461 
2463  if (retval != ERROR_OK)
2464  return retval;
2465 
2467 
2468  if (CMD_ARGC == 1) {
2469  /* only display the TZEN value */
2470  LOG_INFO("Global TrustZone Security is %s", stm32l4_info->tzen ? "enabled" : "disabled");
2471  return ERROR_OK;
2472  }
2473 
2474  bool new_tzen;
2475  COMMAND_PARSE_ENABLE(CMD_ARGV[1], new_tzen);
2476 
2477  if (new_tzen == stm32l4_info->tzen) {
2478  LOG_INFO("The requested TZEN is already programmed");
2479  return ERROR_OK;
2480  }
2481 
2482  if (new_tzen) {
2483  if (stm32l4_info->rdp != RDP_LEVEL_0) {
2484  LOG_ERROR("TZEN can be set only when RDP level is 0");
2485  return ERROR_FAIL;
2486  }
2489  } else {
2490  /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
2491  * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
2492  if (stm32l4_info->rdp != RDP_LEVEL_1 && stm32l4_info->rdp != RDP_LEVEL_0_5) {
2493  LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
2494  return ERROR_FAIL;
2495  }
2496 
2499  }
2500 
2501  if (retval != ERROR_OK)
2502  return retval;
2503 
2505 }
2506 
2507 COMMAND_HANDLER(stm32l4_handle_option_load_command)
2508 {
2509  if (CMD_ARGC != 1)
2511 
2512  struct flash_bank *bank;
2513  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2514  if (retval != ERROR_OK)
2515  return retval;
2516 
2517  retval = stm32l4_perform_obl_launch(bank);
2518  if (retval != ERROR_OK) {
2519  command_print(CMD, "stm32l4x option load failed");
2520  return retval;
2521  }
2522 
2523 
2524  command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
2525 
2526  return ERROR_OK;
2527 }
2528 
2529 COMMAND_HANDLER(stm32l4_handle_lock_command)
2530 {
2531  struct target *target = NULL;
2532 
2533  if (CMD_ARGC != 1)
2535 
2536  struct flash_bank *bank;
2537  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2538  if (retval != ERROR_OK)
2539  return retval;
2540 
2541  if (stm32l4_is_otp(bank)) {
2542  LOG_ERROR("cannot lock/unlock OTP memory");
2544  }
2545 
2546  target = bank->target;
2547 
2548  if (target->state != TARGET_HALTED) {
2549  LOG_ERROR("Target not halted");
2550  return ERROR_TARGET_NOT_HALTED;
2551  }
2552 
2553  /* set readout protection level 1 by erasing the RDP option byte */
2554  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2557  command_print(CMD, "%s failed to lock device", bank->driver->name);
2558  return ERROR_OK;
2559  }
2560 
2561  return ERROR_OK;
2562 }
2563 
2564 COMMAND_HANDLER(stm32l4_handle_unlock_command)
2565 {
2566  struct target *target = NULL;
2567 
2568  if (CMD_ARGC != 1)
2570 
2571  struct flash_bank *bank;
2572  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2573  if (retval != ERROR_OK)
2574  return retval;
2575 
2576  if (stm32l4_is_otp(bank)) {
2577  LOG_ERROR("cannot lock/unlock OTP memory");
2579  }
2580 
2581  target = bank->target;
2582 
2583  if (target->state != TARGET_HALTED) {
2584  LOG_ERROR("Target not halted");
2585  return ERROR_TARGET_NOT_HALTED;
2586  }
2587 
2588  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2591  command_print(CMD, "%s failed to unlock device", bank->driver->name);
2592  return ERROR_OK;
2593  }
2594 
2595  return ERROR_OK;
2596 }
2597 
2598 COMMAND_HANDLER(stm32l4_handle_wrp_info_command)
2599 {
2600  if (CMD_ARGC < 1 || CMD_ARGC > 2)
2602 
2603  struct flash_bank *bank;
2604  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2605  if (retval != ERROR_OK)
2606  return retval;
2607 
2608  if (stm32l4_is_otp(bank)) {
2609  LOG_ERROR("OTP memory does not have write protection areas");
2611  }
2612 
2613  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2614  enum stm32_bank_id dev_bank_id = STM32_ALL_BANKS;
2615  if (CMD_ARGC == 2) {
2616  if (strcmp(CMD_ARGV[1], "bank1") == 0)
2617  dev_bank_id = STM32_BANK1;
2618  else if (strcmp(CMD_ARGV[1], "bank2") == 0)
2619  dev_bank_id = STM32_BANK2;
2620  else
2622  }
2623 
2624  if (dev_bank_id == STM32_BANK2) {
2625  if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) {
2626  LOG_ERROR("this device has no second bank");
2627  return ERROR_FAIL;
2628  } else if (!stm32l4_info->dual_bank_mode) {
2629  LOG_ERROR("this device is configured in single bank mode");
2630  return ERROR_FAIL;
2631  }
2632  }
2633 
2634  int ret;
2635  unsigned int n_wrp, i;
2636  struct stm32l4_wrp wrpxy[4];
2637 
2638  ret = stm32l4_get_all_wrpxy(bank, dev_bank_id, wrpxy, &n_wrp);
2639  if (ret != ERROR_OK)
2640  return ret;
2641 
2642  /* use bitmap and range helpers to better describe protected areas */
2643  DECLARE_BITMAP(pages, bank->num_sectors);
2644  bitmap_zero(pages, bank->num_sectors);
2645 
2646  for (i = 0; i < n_wrp; i++) {
2647  if (wrpxy[i].used) {
2648  for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
2649  set_bit(p, pages);
2650  }
2651  }
2652 
2653  /* we have at most 'n_wrp' WRP areas */
2654  struct range ranges[n_wrp];
2655  unsigned int ranges_count = 0;
2656 
2657  bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
2658 
2659  if (ranges_count > 0) {
2660  /* pretty-print the protected ranges */
2661  char *ranges_str = range_print_alloc(ranges, ranges_count);
2662  command_print(CMD, "protected areas: %s", ranges_str);
2663  free(ranges_str);
2664  } else
2665  command_print(CMD, "no protected areas");
2666 
2667  return ERROR_OK;
2668 }
2669 
2670 COMMAND_HANDLER(stm32l4_handle_otp_command)
2671 {
2672  if (CMD_ARGC != 2)
2674 
2675  struct flash_bank *bank;
2676  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2677  if (retval != ERROR_OK)
2678  return retval;
2679 
2680  if (!stm32l4_is_otp(bank)) {
2681  command_print(CMD, "the specified bank is not an OTP memory");
2682  return ERROR_FAIL;
2683  }
2684  if (strcmp(CMD_ARGV[1], "enable") == 0)
2685  stm32l4_otp_enable(bank, true);
2686  else if (strcmp(CMD_ARGV[1], "disable") == 0)
2687  stm32l4_otp_enable(bank, false);
2688  else if (strcmp(CMD_ARGV[1], "show") == 0)
2689  command_print(CMD, "OTP memory bank #%d is %s for write commands.",
2690  bank->bank_number, stm32l4_otp_is_enabled(bank) ? "enabled" : "disabled");
2691  else
2693 
2694  return ERROR_OK;
2695 }
2696 
2697 static const struct command_registration stm32l4_exec_command_handlers[] = {
2698  {
2699  .name = "lock",
2700  .handler = stm32l4_handle_lock_command,
2701  .mode = COMMAND_EXEC,
2702  .usage = "bank_id",
2703  .help = "Lock entire flash device.",
2704  },
2705  {
2706  .name = "unlock",
2707  .handler = stm32l4_handle_unlock_command,
2708  .mode = COMMAND_EXEC,
2709  .usage = "bank_id",
2710  .help = "Unlock entire protected flash device.",
2711  },
2712  {
2713  .name = "mass_erase",
2714  .handler = stm32l4_handle_mass_erase_command,
2715  .mode = COMMAND_EXEC,
2716  .usage = "bank_id",
2717  .help = "Erase entire flash device.",
2718  },
2719  {
2720  .name = "option_read",
2721  .handler = stm32l4_handle_option_read_command,
2722  .mode = COMMAND_EXEC,
2723  .usage = "bank_id reg_offset",
2724  .help = "Read & Display device option bytes.",
2725  },
2726  {
2727  .name = "option_write",
2728  .handler = stm32l4_handle_option_write_command,
2729  .mode = COMMAND_EXEC,
2730  .usage = "bank_id reg_offset value [mask]",
2731  .help = "Write device option bit fields with provided value.",
2732  },
2733  {
2734  .name = "trustzone",
2735  .handler = stm32l4_handle_trustzone_command,
2736  .mode = COMMAND_EXEC,
2737  .usage = "<bank_id> [enable|disable]",
2738  .help = "Configure TrustZone security",
2739  },
2740  {
2741  .name = "wrp_info",
2742  .handler = stm32l4_handle_wrp_info_command,
2743  .mode = COMMAND_EXEC,
2744  .usage = "bank_id [bank1|bank2]",
2745  .help = "list the protected areas using WRP",
2746  },
2747  {
2748  .name = "option_load",
2749  .handler = stm32l4_handle_option_load_command,
2750  .mode = COMMAND_EXEC,
2751  .usage = "bank_id",
2752  .help = "Force re-load of device options (will cause device reset).",
2753  },
2754  {
2755  .name = "otp",
2756  .handler = stm32l4_handle_otp_command,
2757  .mode = COMMAND_EXEC,
2758  .usage = "<bank_id> <enable|disable|show>",
2759  .help = "OTP (One Time Programmable) memory write enable/disable",
2760  },
2762 };
2763 
2764 static const struct command_registration stm32l4_command_handlers[] = {
2765  {
2766  .name = "stm32l4x",
2767  .mode = COMMAND_ANY,
2768  .help = "stm32l4x flash command group",
2769  .usage = "",
2771  },
2773 };
2774 
2775 const struct flash_driver stm32l4x_flash = {
2776  .name = "stm32l4x",
2777  .commands = stm32l4_command_handlers,
2778  .flash_bank_command = stm32l4_flash_bank_command,
2779  .erase = stm32l4_erase,
2780  .protect = stm32l4_protect,
2781  .write = stm32l4_write,
2782  .read = default_flash_read,
2783  .probe = stm32l4_probe,
2784  .auto_probe = stm32l4_auto_probe,
2785  .erase_check = default_flash_blank_check,
2786  .protect_check = stm32l4_protect_check,
2787  .info = get_stm32l4_info,
2788  .free_driver_priv = default_flash_free_driver_priv,
2789 };
void init_reg_param(struct reg_param *param, const char *reg_name, uint32_t size, enum param_direction direction)
Definition: algorithm.c:29
void destroy_reg_param(struct reg_param *param)
Definition: algorithm.c:38
@ PARAM_OUT
Definition: algorithm.h:16
@ PARAM_IN_OUT
Definition: algorithm.h:17
@ ARM_MODE_THREAD
Definition: arm.h:94
This defines formats and data structures used to talk to ADIv5 entities.
static struct armv7m_common * target_to_armv7m_safe(struct target *target)
Definition: armv7m.h:278
#define ARMV7M_COMMON_MAGIC
Definition: armv7m.h:224
Support functions to access arbitrary bits in a byte array.
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
static int test_bit(unsigned int nr, const volatile unsigned long *addr)
test_bit - Determine whether a bit is set
Definition: bits.h:73
static void bitmap_zero(unsigned long *dst, unsigned int nbits)
bitmap_zero - Clears all the bits in memory
Definition: bits.h:36
static void set_bit(unsigned int nr, volatile unsigned long *addr)
set_bit - Set a bit in memory
Definition: bits.h:60
static void clear_bit(unsigned int nr, volatile unsigned long *addr)
clear_bit - Clear a bit in memory
Definition: bits.h:47
#define DECLARE_BITMAP(name, bits)
Definition: bits.h:29
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:353
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:376
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
Definition: command.h:118
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:402
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
#define COMMAND_PARSE_ENABLE(in, out)
parses an enable/disable command argument
Definition: command.h:533
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:442
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
#define ERROR_COMMAND_ARGUMENT_INVALID
Definition: command.h:404
@ COMMAND_ANY
Definition: command.h:42
@ COMMAND_EXEC
Definition: command.h:40
static enum cortex_m_impl_part cortex_m_get_impl_part(struct target *target)
Definition: cortex_m.h:319
@ CORTEX_M0P_PARTNO
Definition: cortex_m.h:54
uint64_t buffer
Pointer to data buffer to send over SPI.
Definition: dw-spi-helper.h:0
uint32_t size
Size of dw_spi_transaction::buffer.
Definition: dw-spi-helper.h:4
uint32_t buffer_size
Size of dw_spi_program::buffer.
Definition: dw-spi-helper.h:5
uint32_t address
Starting address. Sector aligned.
Definition: dw-spi-helper.h:0
#define FLASH_PG
Definition: em357.c:44
#define KEY2
Definition: em357.c:68
#define FLASH_PER
Definition: em357.c:45
#define FLASH_BSY
Definition: em357.c:55
#define FLASH_LOCK
Definition: em357.c:50
#define FLASH_STRT
Definition: em357.c:49
#define KEY1
Definition: em357.c:67
uint8_t bank
Definition: esirisc.c:135
int mask
Definition: esirisc.c:1740
#define ERROR_FLASH_OPER_UNSUPPORTED
Definition: flash/common.h:36
#define ERROR_FLASH_OPERATION_FAILED
Definition: flash/common.h:30
#define ERROR_FLASH_DST_OUT_OF_BANK
Definition: flash/common.h:31
struct flash_sector * alloc_block_array(uint32_t offset, uint32_t size, unsigned int num_blocks)
Allocate and fill an array of sectors or protection blocks.
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
void alive_sleep(uint64_t ms)
Definition: log.c:467
#define ERROR_NOT_IMPLEMENTED
Definition: log.h:178
#define LOG_WARNING(expr ...)
Definition: log.h:130
#define ERROR_FAIL
Definition: log.h:174
#define LOG_ERROR(expr ...)
Definition: log.h:133
#define LOG_INFO(expr ...)
Definition: log.h:127
#define LOG_DEBUG(expr ...)
Definition: log.h:110
#define ERROR_OK
Definition: log.h:168
#define FLASH_ERROR
Definition: msp432.h:72
struct rtt_control ctrl
Control block.
Definition: rtt/rtt.c:25
struct rtt_source source
Definition: rtt/rtt.c:23
#define FLASH_OBL_LAUNCH
Definition: stm32f1x.c:72
#define FLASH_WRPERR
Definition: stm32f2x.c:157
#define OPTKEY2
Definition: stm32f2x.c:178
#define FLASH_MER1
Definition: stm32f2x.c:142
#define OPTKEY1
Definition: stm32f2x.c:177
stm32l4_rdp
Definition: stm32l4x.c:175
@ RDP_LEVEL_1
Definition: stm32l4x.c:178
@ RDP_LEVEL_2
Definition: stm32l4x.c:179
@ RDP_LEVEL_0_5
Definition: stm32l4x.c:177
@ RDP_LEVEL_0
Definition: stm32l4x.c:176
static const struct stm32l4_rev stm32g05_g06xx_revs[]
Definition: stm32l4x.c:318
static const struct stm32l4_rev stm32c071xx_revs[]
Definition: stm32l4x.c:310
static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id, struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
Definition: stm32l4x.c:1229
static int stm32l4_protect_check(struct flash_bank *bank)
Definition: stm32l4x.c:1307
#define FLASH_ERASE_TIMEOUT
Definition: stm32l4x.c:137
static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, enum stm32l4_flash_reg_index reg_idx, int offset)
Definition: stm32l4x.c:1209
static const struct stm32l4_rev stm32l43_l44xx_revs[]
Definition: stm32l4x.c:293
static const struct stm32l4_rev stm32u53_u54xx_revs[]
Definition: stm32l4x.c:375
static const struct stm32l4_rev stm32u59_u5axx_revs[]
Definition: stm32l4x.c:384
#define F_QUAD_WORD_PROG
Definition: stm32l4x.c:154
static const struct command_registration stm32l4_exec_command_handlers[]
Definition: stm32l4x.c:2697
#define F_NONE
Definition: stm32l4x.c:142
static int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
Definition: stm32l4x.c:954
static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:182
#define F_USE_ALL_WRPXX
Definition: stm32l4x.c:147
stm32l4_flash_reg_index
Definition: stm32l4x.c:158
@ STM32_FLASH_SR_INDEX
Definition: stm32l4x.c:162
@ STM32_FLASH_CR_WLK_INDEX
Definition: stm32l4x.c:166
@ STM32_FLASH_ACR_INDEX
Definition: stm32l4x.c:159
@ STM32_FLASH_OPTR_INDEX
Definition: stm32l4x.c:167
@ STM32_FLASH_WRP1AR_INDEX
Definition: stm32l4x.c:168
@ STM32_FLASH_CR_INDEX
Definition: stm32l4x.c:163
@ STM32_FLASH_WRP2BR_INDEX
Definition: stm32l4x.c:171
@ STM32_FLASH_OPTKEYR_INDEX
Definition: stm32l4x.c:161
@ STM32_FLASH_WRP1BR_INDEX
Definition: stm32l4x.c:169
@ STM32_FLASH_KEYR_INDEX
Definition: stm32l4x.c:160
@ STM32_FLASH_WRP2AR_INDEX
Definition: stm32l4x.c:170
@ STM32_FLASH_REG_INDEX_NUM
Definition: stm32l4x.c:172
static const struct stm32l4_rev stm32c09xx_revs[]
Definition: stm32l4x.c:314
#define F_HAS_TZ
Definition: stm32l4x.c:149
static int stm32l4_perform_obl_launch(struct flash_bank *bank)
Definition: stm32l4x.c:1124
static const struct stm32l4_part_info stm32l4_parts[]
Definition: stm32l4x.c:412
static char * range_print_alloc(struct range *ranges, unsigned int ranges_count)
Definition: stm32l4x.c:846
static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
Definition: stm32l4x.c:1815
static const struct stm32l4_rev stm32g47_g48xx_revs[]
Definition: stm32l4x.c:354
static int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
Definition: stm32l4x.c:942
static bool stm32l4_otp_is_enabled(struct flash_bank *bank)
Definition: stm32l4x.c:894
#define F_HAS_L5_FLASH_REGS
Definition: stm32l4x.c:151
static const char * get_stm32l4_bank_type_str(struct flash_bank *bank)
Definition: stm32l4x.c:1878
static bool stm32l4_is_otp(struct flash_bank *bank)
Definition: stm32l4x.c:869
static int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
Definition: stm32l4x.c:1048
static int range_print_one(struct range *range, char *str)
Definition: stm32l4x.c:838
static const struct stm32l4_rev stm32g03_g04xx_revs[]
Definition: stm32l4x.c:338
static const struct stm32l4_rev stm32c01xx_revs[]
Definition: stm32l4x.c:298
#define F_HAS_DUAL_BANK
Definition: stm32l4x.c:144
static const char * device_families
Definition: stm32l4x.c:287
stm32_bank_id
Definition: stm32l4x.c:271
@ STM32_BANK1
Definition: stm32l4x.c:272
@ STM32_BANK2
Definition: stm32l4x.c:273
@ STM32_ALL_BANKS
Definition: stm32l4x.c:274
static const struct stm32l4_rev stm32u57_u58xx_revs[]
Definition: stm32l4x.c:379
static const struct command_registration stm32l4_command_handlers[]
Definition: stm32l4x.c:2764
static const struct stm32l4_rev stm32l45_l46xx_revs[]
Definition: stm32l4x.c:330
static int stm32l4_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: stm32l4x.c:1331
static const struct stm32l4_rev stm32l4p_l4qxx_revs[]
Definition: stm32l4x.c:363
static const struct stm32l4_rev stm32l41_l42xx_revs[]
Definition: stm32l4x.c:334
static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
Definition: stm32l4x.c:875
static const struct stm32l4_rev stm32l47_l48xx_revs[]
Definition: stm32l4x.c:289
static const struct stm32l4_rev stm32l4r_l4sxx_revs[]
Definition: stm32l4x.c:358
static const struct stm32l4_rev stm32c05xx_revs[]
Definition: stm32l4x.c:306
static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
Definition: stm32l4x.c:1161
static const struct stm32l4_rev stm32l55_l56xx_revs[]
Definition: stm32l4x.c:367
static const struct stm32l4_rev stm32wb1xx_revs[]
Definition: stm32l4x.c:396
static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
Definition: stm32l4x.c:966
static const struct stm32l4_rev stm32wba5x_revs[]
Definition: stm32l4x.c:392
static int stm32l4_mass_erase(struct flash_bank *bank)
Definition: stm32l4x.c:2308
static const char * get_stm32l4_rev_str(struct flash_bank *bank)
Definition: stm32l4x.c:1864
static int get_stm32l4_info(struct flash_bank *bank, struct command_invocation *cmd)
Definition: stm32l4x.c:2290
COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
Definition: stm32l4x.c:2374
static const struct stm32l4_rev stm32_g07_g08xx_revs[]
Definition: stm32l4x.c:322
static const struct stm32l4_rev stm32g43_g44xx_revs[]
Definition: stm32l4x.c:350
static const struct stm32l4_rev stm32c03xx_revs[]
Definition: stm32l4x.c:302
static uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
Definition: stm32l4x.c:929
static const struct stm32l4_rev stm32wle_wl5xx_revs[]
Definition: stm32l4x.c:408
static int stm32l4_protect_same_bank(struct flash_bank *bank, enum stm32_bank_id bank_id, int set, unsigned int first, unsigned int last)
Definition: stm32l4x.c:1409
FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
Definition: stm32l4x.c:788
static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
set all FLASH_SECBB registers to the same value
Definition: stm32l4x.c:1006
static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32l4x.c:1704
static const struct stm32l4_rev stm32g49_g4axx_revs[]
Definition: stm32l4x.c:371
const struct flash_driver stm32l4x_flash
Definition: stm32l4x.c:2775
static int stm32l4_probe(struct flash_bank *bank)
Definition: stm32l4x.c:1887
static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:220
static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32l4x.c:1660
static int stm32l4_read_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index, uint32_t *value)
Definition: stm32l4x.c:947
static const struct stm32l4_rev stm32u0xx_revs[]
Definition: stm32l4x.c:346
static int stm32l4_unlock_option_reg(struct flash_bank *bank)
Definition: stm32l4x.c:1091
static const uint32_t stm32wl_cpu2_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:195
static int stm32l4_unlock_reg(struct flash_bank *bank)
Definition: stm32l4x.c:1055
static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
Definition: stm32l4x.c:1294
static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
Definition: stm32l4x.c:900
static const struct stm32l4_rev stm32wb3xx_revs[]
Definition: stm32l4x.c:404
#define FLASH_WRITE_TIMEOUT
Definition: stm32l4x.c:138
static const struct stm32l4_rev stm32wb5xx_revs[]
Definition: stm32l4x.c:400
static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits, struct range *ranges, unsigned int *ranges_count)
Definition: stm32l4x.c:817
static const struct stm32l4_rev stm32u5f_u5gxx_revs[]
Definition: stm32l4x.c:388
static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:207
static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32l4x.c:1535
static int stm32l4_write_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index, uint32_t value)
Definition: stm32l4x.c:959
static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
Definition: stm32l4x.c:1500
static uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index)
Definition: stm32l4x.c:935
static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
Definition: stm32l4x.c:1282
static const struct stm32l4_rev stm32l49_l4axx_revs[]
Definition: stm32l4x.c:326
static int stm32l4_auto_probe(struct flash_bank *bank)
Definition: stm32l4x.c:2261
static const struct stm32l4_rev stm32g0b_g0cxx_revs[]
Definition: stm32l4x.c:342
#define DEVID_STM32G03_G04XX
Definition: stm32l4x.h:101
#define DEVID_STM32L55_L56XX
Definition: stm32l4x.h:107
#define DBGMCU_IDCODE_G0
Definition: stm32l4x.h:80
#define DEVID_STM32G0B_G0CXX
Definition: stm32l4x.h:102
#define FLASH_L5_DB256
Definition: stm32l4x.h:68
#define FLASH_SECBB_SECURE
Definition: stm32l4x.h:76
#define DBGMCU_IDCODE_L5
Definition: stm32l4x.h:82
#define FLASH_G0_DUAL_BANK
Definition: stm32l4x.h:62
#define STM32_FLASH_S_BANK_BASE
Definition: stm32l4x.h:122
#define DEVID_STM32G49_G4AXX
Definition: stm32l4x.h:109
#define DEVID_STM32WBA5X
Definition: stm32l4x.h:113
#define DEVID_STM32WB1XX
Definition: stm32l4x.h:115
#define DEVID_STM32C03XX
Definition: stm32l4x.h:93
#define FLASH_OPTSTRT
Definition: stm32l4x.h:30
#define FLASH_SECBB2(X)
Definition: stm32l4x.h:74
#define DEVID_STM32U53_U54XX
Definition: stm32l4x.h:94
#define DEVID_STM32L4R_L4SXX
Definition: stm32l4x.h:105
#define UID64_IDS
Definition: stm32l4x.h:84
#define FLASH_L5_DBANK
Definition: stm32l4x.h:67
#define FLASH_L4_DUAL_BANK
Definition: stm32l4x.h:64
#define FLASH_PAGE_SHIFT
Definition: stm32l4x.h:25
#define DEVID_STM32G47_G48XX
Definition: stm32l4x.h:104
#define FLASH_U5_DUALBANK
Definition: stm32l4x.h:69
#define DEVID_STM32U5F_U5GXX
Definition: stm32l4x.h:108
#define STM32_FLASH_BANK_BASE
Definition: stm32l4x.h:121
#define FLASH_G4_DUAL_BANK
Definition: stm32l4x.h:63
#define DEVID_STM32L47_L48XX
Definition: stm32l4x.h:88
#define DEVID_STM32G07_G08XX
Definition: stm32l4x.h:97
#define DEVID_STM32C071XX
Definition: stm32l4x.h:114
#define DEVID_STM32WB5XX
Definition: stm32l4x.h:116
#define DEVID_STM32U59_U5AXX
Definition: stm32l4x.h:110
#define DEVID_STM32L49_L4AXX
Definition: stm32l4x.h:98
#define DEVID_STM32L43_L44XX
Definition: stm32l4x.h:89
#define FLASH_RDP_MASK
Definition: stm32l4x.h:61
#define DEVID_STM32L41_L42XX
Definition: stm32l4x.h:100
#define DEVID_STM32U073_U083XX
Definition: stm32l4x.h:112
#define DEVID_STM32WLE_WL5XX
Definition: stm32l4x.h:118
#define FLASH_L4R_DBANK
Definition: stm32l4x.h:65
#define DEVID_STM32G05_G06XX
Definition: stm32l4x.h:95
#define LDR_STACK_SIZE
Definition: stm32l4x.h:128
#define DEVID_STM32U031XX
Definition: stm32l4x.h:96
#define FLASH_OPTLOCK
Definition: stm32l4x.h:34
#define DEVID_STM32WB3XX
Definition: stm32l4x.h:117
#define DEVID_STM32C09XX
Definition: stm32l4x.h:92
#define FLASH_TZEN
Definition: stm32l4x.h:70
#define DEVID_STM32G43_G44XX
Definition: stm32l4x.h:103
#define UID64_IDS_STM32WL
Definition: stm32l4x.h:85
#define FLASH_BSY2
Definition: stm32l4x.h:39
#define FLASH_SECBB_NON_SECURE
Definition: stm32l4x.h:77
#define STM32L5_REGS_SEC_OFFSET
Definition: stm32l4x.h:125
#define FLASH_SECBB1(X)
Definition: stm32l4x.h:73
#define FLASH_BKER_G0
Definition: stm32l4x.h:27
#define DEVID_STM32U57_U58XX
Definition: stm32l4x.h:111
#define DBGMCU_IDCODE_L4_G4
Definition: stm32l4x.h:81
#define DEVID_STM32L4P_L4QXX
Definition: stm32l4x.h:106
#define FLASH_LRR_DB1M
Definition: stm32l4x.h:66
#define DEVID_STM32C05XX
Definition: stm32l4x.h:91
#define FLASH_BKER
Definition: stm32l4x.h:26
#define DEVID_STM32C01XX
Definition: stm32l4x.h:90
#define DEVID_STM32L45_L46XX
Definition: stm32l4x.h:99
#define FLASH_MER2
Definition: stm32l4x.h:28
uint64_t ap_num
ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coheren...
Definition: arm_adi_v5.h:261
unsigned int common_magic
Definition: armv7m.h:299
enum arm_mode core_mode
Definition: armv7m.h:301
struct adiv5_ap * debug_ap
Definition: armv7m.h:234
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
const char * name
Definition: command.h:235
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
Describes the geometry and status of a single flash sector within a flash bank.
Definition: nor/core.h:28
uint32_t offset
Bus offset from start of the flash chip (in bytes).
Definition: nor/core.h:30
uint32_t size
Number of bytes in this flash sector.
Definition: nor/core.h:32
unsigned int start
Definition: stm32l4x.c:813
unsigned int end
Definition: stm32l4x.c:814
unsigned int bank1_sectors
Definition: stm32l4x.c:254
uint32_t wrpxxr_mask
Definition: stm32l4x.c:261
uint32_t user_bank_size
Definition: stm32l4x.c:257
const uint32_t * flash_regs
Definition: stm32l4x.c:264
uint32_t flash_regs_base
Definition: stm32l4x.c:263
enum stm32l4_rdp rdp
Definition: stm32l4x.c:266
uint32_t idcode
Definition: stm32l4x.c:253
uint32_t cr_bker_mask
Definition: stm32l4x.c:259
uint32_t data_width
Definition: stm32l4x.c:258
const struct stm32l4_part_info * part_info
Definition: stm32l4x.c:262
uint32_t sr_bsy_mask
Definition: stm32l4x.c:260
const uint32_t otp_size
Definition: stm32l4x.c:248
const struct stm32l4_rev * revs
Definition: stm32l4x.c:241
const char * device_str
Definition: stm32l4x.c:240
const uint32_t fsize_addr
Definition: stm32l4x.c:246
const uint32_t flash_regs_base
Definition: stm32l4x.c:245
const uint32_t flags
Definition: stm32l4x.c:244
const uint32_t otp_base
Definition: stm32l4x.c:247
const size_t num_revs
Definition: stm32l4x.c:242
const uint16_t max_flash_size_kb
Definition: stm32l4x.c:243
const char * str
Definition: stm32l4x.c:235
const uint16_t rev
Definition: stm32l4x.c:234
uint8_t stack[LDR_STACK_SIZE]
Definition: stm32l4x.h:137
bool used
Definition: stm32l4x.c:280
enum stm32l4_flash_reg_index reg_idx
Definition: stm32l4x.c:278
int offset
Definition: stm32l4x.c:283
uint32_t value
Definition: stm32l4x.c:279
Definition: target.h:116
enum target_state state
Definition: target.h:157
Definition: psoc6.c:83
target_addr_t address
Definition: target.h:86
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
Definition: target.c:360
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2350
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1274
uint32_t target_get_working_area_avail(struct target *target)
Definition: target.c:2173
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2069
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2649
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2127
int target_alloc_working_area_try(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:1975
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
Definition: target.c:2582
int target_run_flash_async_algorithm(struct target *target, const uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
Streams data to a circular buffer on target intended for consumption by code running asynchronously o...
Definition: target.c:939
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2558
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:783
static bool target_was_examined(const struct target *target)
Definition: target.h:429
#define ERROR_TARGET_INVALID
Definition: target.h:780
@ TARGET_HALTED
Definition: target.h:56
#define ERROR_TARGET_NOT_EXAMINED
Definition: target.h:790
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:787
#define ERROR_TARGET_FAILURE
Definition: target.h:784
#define TARGET_ADDR_FMT
Definition: types.h:342
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57
#define NULL
Definition: usb.h:16
uint8_t status[4]
Definition: vdebug.c:17
uint8_t cmd
Definition: vdebug.c:1
uint8_t offset[4]
Definition: vdebug.c:9
uint8_t count[4]
Definition: vdebug.c:22