OpenOCD
stm32l4x.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2015 by Uwe Bonnes *
5  * bon@elektron.ikp.physik.tu-darmstadt.de *
6  * *
7  * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
8  * tarek.bouchkati@gmail.com *
9  ***************************************************************************/
10 
11 #ifdef HAVE_CONFIG_H
12 #include "config.h"
13 #endif
14 
15 #include "imp.h"
16 #include <helper/align.h>
17 #include <helper/binarybuffer.h>
18 #include <helper/bits.h>
19 #include <target/algorithm.h>
20 #include <target/arm_adi_v5.h>
21 #include <target/cortex_m.h>
22 #include "stm32l4x.h"
23 
24 /* STM32L4xxx series for reference.
25  *
26  * RM0351 (STM32L4x5/STM32L4x6)
27  * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
28  *
29  * RM0394 (STM32L43x/44x/45x/46x)
30  * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
31  *
32  * RM0432 (STM32L4R/4Sxx)
33  * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
34  *
35  * STM32L476RG Datasheet (for erase timing)
36  * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
37  *
38  * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
39  * an option byte is available to map all sectors to the first bank.
40  * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
41  * handlers do!
42  *
43  * RM0394 devices have a single bank only.
44  *
45  * RM0432 devices have single and dual bank operating modes.
46  * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
47  * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
48  * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
49  *
50  * Bank mode is controlled by two different bits in option bytes register.
51  * - for STM32L4R/Sxx
52  * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
53  * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
54  * - for STM32L4P5/Q5x
55  * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
56  * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
57  */
58 
59 /* STM32WBxxx series for reference.
60  *
61  * RM0493 (STM32WBA52x)
62  * http://www.st.com/resource/en/reference_manual/dm00821869.pdf
63  *
64  * RM0434 (STM32WB55/WB35x)
65  * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
66  *
67  * RM0471 (STM32WB50/WB30x)
68  * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
69  *
70  * RM0473 (STM32WB15x)
71  * http://www.st.com/resource/en/reference_manual/dm00649196.pdf
72  *
73  * RM0478 (STM32WB10x)
74  * http://www.st.com/resource/en/reference_manual/dm00689203.pdf
75  */
76 
77 /* STM32WLxxx series for reference.
78  *
79  * RM0461 (STM32WLEx)
80  * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
81  *
82  * RM0453 (STM32WL5x)
83  * http://www.st.com/resource/en/reference_manual/dm00451556.pdf
84  */
85 
86 /* STM32C0xxx series for reference.
87  *
88  * RM0490 (STM32C0x1)
89  * http://www.st.com/resource/en/reference_manual/dm00781702.pdf
90  */
91 
92 /* STM32G0xxx series for reference.
93  *
94  * RM0444 (STM32G0x1)
95  * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
96  *
97  * RM0454 (STM32G0x0)
98  * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
99  */
100 
101 /* STM32G4xxx series for reference.
102  *
103  * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
104  * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
105  *
106  * Cat. 2 devices have single bank only, page size is 2kByte.
107  *
108  * Cat. 3 devices have single and dual bank operating modes,
109  * Page size is 2kByte (dual mode) or 4kByte (single mode).
110  *
111  * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
112  * Both banks are treated as a single OpenOCD bank.
113  *
114  * Cat. 4 devices have single bank only, page size is 2kByte.
115  */
116 
117 /* STM32L5xxx series for reference.
118  *
119  * RM0428 (STM32L552xx/STM32L562xx)
120  * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
121  */
122 
123 /* STM32U5xxx series for reference.
124  *
125  * RM0456 (STM32U5xx)
126  * http://www.st.com/resource/en/reference_manual/dm00477635.pdf
127  */
128 
129 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
130 
131 #define FLASH_ERASE_TIMEOUT 250
132 #define FLASH_WRITE_TIMEOUT 50
133 
134 
135 /* relevant STM32L4 flags ****************************************************/
136 #define F_NONE 0
137 /* this flag indicates if the device flash is with dual bank architecture */
138 #define F_HAS_DUAL_BANK BIT(0)
139 /* this flags is used for dual bank devices only, it indicates if the
140  * 4 WRPxx are usable if the device is configured in single-bank mode */
141 #define F_USE_ALL_WRPXX BIT(1)
142 /* this flag indicates if the device embeds a TrustZone security feature */
143 #define F_HAS_TZ BIT(2)
144 /* this flag indicates if the device has the same flash registers as STM32L5 */
145 #define F_HAS_L5_FLASH_REGS BIT(3)
146 /* this flag indicates that programming should be done in quad-word
147  * the default programming word size is double-word */
148 #define F_QUAD_WORD_PROG BIT(4)
149 /* end of STM32L4 flags ******************************************************/
150 
151 
158  /* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
159  * so it uses the C2CR for flash operations and CR for checking locks and locking */
160  STM32_FLASH_CR_WLK_INDEX, /* FLASH_CR_WITH_LOCK */
167 };
168 
170  RDP_LEVEL_0 = 0xAA,
171  RDP_LEVEL_0_5 = 0x55, /* for devices with TrustZone enabled */
172  RDP_LEVEL_1 = 0x00,
173  RDP_LEVEL_2 = 0xCC
174 };
175 
177  [STM32_FLASH_ACR_INDEX] = 0x000,
178  [STM32_FLASH_KEYR_INDEX] = 0x008,
179  [STM32_FLASH_OPTKEYR_INDEX] = 0x00C,
180  [STM32_FLASH_SR_INDEX] = 0x010,
181  [STM32_FLASH_CR_INDEX] = 0x014,
182  [STM32_FLASH_OPTR_INDEX] = 0x020,
183  [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
184  [STM32_FLASH_WRP1BR_INDEX] = 0x030,
185  [STM32_FLASH_WRP2AR_INDEX] = 0x04C,
186  [STM32_FLASH_WRP2BR_INDEX] = 0x050,
187 };
188 
190  [STM32_FLASH_ACR_INDEX] = 0x000,
191  [STM32_FLASH_KEYR_INDEX] = 0x008,
192  [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
193  [STM32_FLASH_SR_INDEX] = 0x060,
194  [STM32_FLASH_CR_INDEX] = 0x064,
195  [STM32_FLASH_CR_WLK_INDEX] = 0x014,
196  [STM32_FLASH_OPTR_INDEX] = 0x020,
197  [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
198  [STM32_FLASH_WRP1BR_INDEX] = 0x030,
199 };
200 
202  [STM32_FLASH_ACR_INDEX] = 0x000,
203  [STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */
204  [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
205  [STM32_FLASH_SR_INDEX] = 0x020, /* NSSR */
206  [STM32_FLASH_CR_INDEX] = 0x028, /* NSCR */
207  [STM32_FLASH_OPTR_INDEX] = 0x040,
208  [STM32_FLASH_WRP1AR_INDEX] = 0x058,
209  [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
210  [STM32_FLASH_WRP2AR_INDEX] = 0x068,
211  [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
212 };
213 
215  [STM32_FLASH_ACR_INDEX] = 0x000,
216  [STM32_FLASH_KEYR_INDEX] = 0x00C, /* SECKEYR */
217  [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
218  [STM32_FLASH_SR_INDEX] = 0x024, /* SECSR */
219  [STM32_FLASH_CR_INDEX] = 0x02C, /* SECCR */
220  [STM32_FLASH_OPTR_INDEX] = 0x040,
221  [STM32_FLASH_WRP1AR_INDEX] = 0x058,
222  [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
223  [STM32_FLASH_WRP2AR_INDEX] = 0x068,
224  [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
225 };
226 
227 struct stm32l4_rev {
228  const uint16_t rev;
229  const char *str;
230 };
231 
233  uint16_t id;
234  const char *device_str;
235  const struct stm32l4_rev *revs;
236  const size_t num_revs;
237  const uint16_t max_flash_size_kb;
238  const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
239  const uint32_t flash_regs_base;
240  const uint32_t fsize_addr;
241  const uint32_t otp_base;
242  const uint32_t otp_size;
243 };
244 
246  bool probed;
247  uint32_t idcode;
248  unsigned int bank1_sectors;
251  uint32_t user_bank_size;
252  uint32_t data_width;
253  uint32_t cr_bker_mask;
254  uint32_t sr_bsy_mask;
255  uint32_t wrpxxr_mask;
257  uint32_t flash_regs_base;
258  const uint32_t *flash_regs;
260  enum stm32l4_rdp rdp;
261  bool tzen;
262  uint32_t optr;
263 };
264 
269 };
270 
271 struct stm32l4_wrp {
273  uint32_t value;
274  bool used;
275  int first;
276  int last;
277  int offset;
278 };
279 
280 /* human readable list of families this drivers supports (sorted alphabetically) */
281 static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U5/WB/WL";
282 
283 static const struct stm32l4_rev stm32l47_l48xx_revs[] = {
284  { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
285 };
286 
287 static const struct stm32l4_rev stm32l43_l44xx_revs[] = {
288  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
289 };
290 
291 
292 static const struct stm32l4_rev stm32c01xx_revs[] = {
293  { 0x1000, "A" }, { 0x1001, "Z" },
294 };
295 
296 static const struct stm32l4_rev stm32c03xx_revs[] = {
297  { 0x1000, "A" }, { 0x1001, "Z" },
298 };
299 
300 static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
301  { 0x1000, "A" },
302 };
303 
304 static const struct stm32l4_rev stm32_g07_g08xx_revs[] = {
305  { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
306 };
307 
308 static const struct stm32l4_rev stm32l49_l4axx_revs[] = {
309  { 0x1000, "A" }, { 0x2000, "B" },
310 };
311 
312 static const struct stm32l4_rev stm32l45_l46xx_revs[] = {
313  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
314 };
315 
316 static const struct stm32l4_rev stm32l41_l42xx_revs[] = {
317  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
318 };
319 
320 static const struct stm32l4_rev stm32g03_g04xx_revs[] = {
321  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
322 };
323 
324 static const struct stm32l4_rev stm32g0b_g0cxx_revs[] = {
325  { 0x1000, "A" },
326 };
327 
328 static const struct stm32l4_rev stm32g43_g44xx_revs[] = {
329  { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
330 };
331 
332 static const struct stm32l4_rev stm32g47_g48xx_revs[] = {
333  { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
334 };
335 
336 static const struct stm32l4_rev stm32l4r_l4sxx_revs[] = {
337  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
338  { 0x101F, "V" },
339 };
340 
341 static const struct stm32l4_rev stm32l4p_l4qxx_revs[] = {
342  { 0x1001, "Z" },
343 };
344 
345 static const struct stm32l4_rev stm32l55_l56xx_revs[] = {
346  { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
347 };
348 
349 static const struct stm32l4_rev stm32g49_g4axx_revs[] = {
350  { 0x1000, "A" },
351 };
352 
353 static const struct stm32l4_rev stm32u53_u54xx_revs[] = {
354  { 0x1000, "A" }, { 0x1001, "Z" },
355 };
356 
357 static const struct stm32l4_rev stm32u57_u58xx_revs[] = {
358  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
359  { 0x2001, "X" }, { 0x3000, "C" }, { 0x3001, "W" },
360 };
361 
362 static const struct stm32l4_rev stm32u59_u5axx_revs[] = {
363  { 0x3001, "X" },
364 };
365 
366 static const struct stm32l4_rev stm32wba5x_revs[] = {
367  { 0x1000, "A" },
368 };
369 
370 static const struct stm32l4_rev stm32wb1xx_revs[] = {
371  { 0x1000, "A" }, { 0x2000, "B" },
372 };
373 
374 static const struct stm32l4_rev stm32wb5xx_revs[] = {
375  { 0x2001, "2.1" },
376 };
377 
378 static const struct stm32l4_rev stm32wb3xx_revs[] = {
379  { 0x1000, "A" },
380 };
381 
382 static const struct stm32l4_rev stm32wle_wl5xx_revs[] = {
383  { 0x1000, "1.0" },
384 };
385 
386 static const struct stm32l4_part_info stm32l4_parts[] = {
387  {
389  .revs = stm32l47_l48xx_revs,
390  .num_revs = ARRAY_SIZE(stm32l47_l48xx_revs),
391  .device_str = "STM32L47/L48xx",
392  .max_flash_size_kb = 1024,
393  .flags = F_HAS_DUAL_BANK,
394  .flash_regs_base = 0x40022000,
395  .fsize_addr = 0x1FFF75E0,
396  .otp_base = 0x1FFF7000,
397  .otp_size = 1024,
398  },
399  {
400  .id = DEVID_STM32L43_L44XX,
401  .revs = stm32l43_l44xx_revs,
402  .num_revs = ARRAY_SIZE(stm32l43_l44xx_revs),
403  .device_str = "STM32L43/L44xx",
404  .max_flash_size_kb = 256,
405  .flags = F_NONE,
406  .flash_regs_base = 0x40022000,
407  .fsize_addr = 0x1FFF75E0,
408  .otp_base = 0x1FFF7000,
409  .otp_size = 1024,
410  },
411  {
412  .id = DEVID_STM32C01XX,
413  .revs = stm32c01xx_revs,
414  .num_revs = ARRAY_SIZE(stm32c01xx_revs),
415  .device_str = "STM32C01xx",
416  .max_flash_size_kb = 32,
417  .flags = F_NONE,
418  .flash_regs_base = 0x40022000,
419  .fsize_addr = 0x1FFF75A0,
420  .otp_base = 0x1FFF7000,
421  .otp_size = 1024,
422  },
423  {
424  .id = DEVID_STM32C03XX,
425  .revs = stm32c03xx_revs,
426  .num_revs = ARRAY_SIZE(stm32c03xx_revs),
427  .device_str = "STM32C03xx",
428  .max_flash_size_kb = 32,
429  .flags = F_NONE,
430  .flash_regs_base = 0x40022000,
431  .fsize_addr = 0x1FFF75A0,
432  .otp_base = 0x1FFF7000,
433  .otp_size = 1024,
434  },
435  {
436  .id = DEVID_STM32U53_U54XX,
437  .revs = stm32u53_u54xx_revs,
438  .num_revs = ARRAY_SIZE(stm32u53_u54xx_revs),
439  .device_str = "STM32U535/U545",
440  .max_flash_size_kb = 512,
442  .flash_regs_base = 0x40022000,
443  .fsize_addr = 0x0BFA07A0,
444  .otp_base = 0x0BFA0000,
445  .otp_size = 512,
446  },
447  {
448  .id = DEVID_STM32G05_G06XX,
449  .revs = stm32g05_g06xx_revs,
450  .num_revs = ARRAY_SIZE(stm32g05_g06xx_revs),
451  .device_str = "STM32G05/G06xx",
452  .max_flash_size_kb = 64,
453  .flags = F_NONE,
454  .flash_regs_base = 0x40022000,
455  .fsize_addr = 0x1FFF75E0,
456  .otp_base = 0x1FFF7000,
457  .otp_size = 1024,
458  },
459  {
460  .id = DEVID_STM32G07_G08XX,
461  .revs = stm32_g07_g08xx_revs,
462  .num_revs = ARRAY_SIZE(stm32_g07_g08xx_revs),
463  .device_str = "STM32G07/G08xx",
464  .max_flash_size_kb = 128,
465  .flags = F_NONE,
466  .flash_regs_base = 0x40022000,
467  .fsize_addr = 0x1FFF75E0,
468  .otp_base = 0x1FFF7000,
469  .otp_size = 1024,
470  },
471  {
472  .id = DEVID_STM32L49_L4AXX,
473  .revs = stm32l49_l4axx_revs,
474  .num_revs = ARRAY_SIZE(stm32l49_l4axx_revs),
475  .device_str = "STM32L49/L4Axx",
476  .max_flash_size_kb = 1024,
477  .flags = F_HAS_DUAL_BANK,
478  .flash_regs_base = 0x40022000,
479  .fsize_addr = 0x1FFF75E0,
480  .otp_base = 0x1FFF7000,
481  .otp_size = 1024,
482  },
483  {
484  .id = DEVID_STM32L45_L46XX,
485  .revs = stm32l45_l46xx_revs,
486  .num_revs = ARRAY_SIZE(stm32l45_l46xx_revs),
487  .device_str = "STM32L45/L46xx",
488  .max_flash_size_kb = 512,
489  .flags = F_NONE,
490  .flash_regs_base = 0x40022000,
491  .fsize_addr = 0x1FFF75E0,
492  .otp_base = 0x1FFF7000,
493  .otp_size = 1024,
494  },
495  {
496  .id = DEVID_STM32L41_L42XX,
497  .revs = stm32l41_l42xx_revs,
498  .num_revs = ARRAY_SIZE(stm32l41_l42xx_revs),
499  .device_str = "STM32L41/L42xx",
500  .max_flash_size_kb = 128,
501  .flags = F_NONE,
502  .flash_regs_base = 0x40022000,
503  .fsize_addr = 0x1FFF75E0,
504  .otp_base = 0x1FFF7000,
505  .otp_size = 1024,
506  },
507  {
508  .id = DEVID_STM32G03_G04XX,
509  .revs = stm32g03_g04xx_revs,
510  .num_revs = ARRAY_SIZE(stm32g03_g04xx_revs),
511  .device_str = "STM32G03x/G04xx",
512  .max_flash_size_kb = 64,
513  .flags = F_NONE,
514  .flash_regs_base = 0x40022000,
515  .fsize_addr = 0x1FFF75E0,
516  .otp_base = 0x1FFF7000,
517  .otp_size = 1024,
518  },
519  {
520  .id = DEVID_STM32G0B_G0CXX,
521  .revs = stm32g0b_g0cxx_revs,
522  .num_revs = ARRAY_SIZE(stm32g0b_g0cxx_revs),
523  .device_str = "STM32G0B/G0Cx",
524  .max_flash_size_kb = 512,
525  .flags = F_HAS_DUAL_BANK,
526  .flash_regs_base = 0x40022000,
527  .fsize_addr = 0x1FFF75E0,
528  .otp_base = 0x1FFF7000,
529  .otp_size = 1024,
530  },
531  {
532  .id = DEVID_STM32G43_G44XX,
533  .revs = stm32g43_g44xx_revs,
534  .num_revs = ARRAY_SIZE(stm32g43_g44xx_revs),
535  .device_str = "STM32G43/G44xx",
536  .max_flash_size_kb = 128,
537  .flags = F_NONE,
538  .flash_regs_base = 0x40022000,
539  .fsize_addr = 0x1FFF75E0,
540  .otp_base = 0x1FFF7000,
541  .otp_size = 1024,
542  },
543  {
544  .id = DEVID_STM32G47_G48XX,
545  .revs = stm32g47_g48xx_revs,
546  .num_revs = ARRAY_SIZE(stm32g47_g48xx_revs),
547  .device_str = "STM32G47/G48xx",
548  .max_flash_size_kb = 512,
549  .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
550  .flash_regs_base = 0x40022000,
551  .fsize_addr = 0x1FFF75E0,
552  .otp_base = 0x1FFF7000,
553  .otp_size = 1024,
554  },
555  {
556  .id = DEVID_STM32L4R_L4SXX,
557  .revs = stm32l4r_l4sxx_revs,
558  .num_revs = ARRAY_SIZE(stm32l4r_l4sxx_revs),
559  .device_str = "STM32L4R/L4Sxx",
560  .max_flash_size_kb = 2048,
561  .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
562  .flash_regs_base = 0x40022000,
563  .fsize_addr = 0x1FFF75E0,
564  .otp_base = 0x1FFF7000,
565  .otp_size = 1024,
566  },
567  {
568  .id = DEVID_STM32L4P_L4QXX,
569  .revs = stm32l4p_l4qxx_revs,
570  .num_revs = ARRAY_SIZE(stm32l4p_l4qxx_revs),
571  .device_str = "STM32L4P/L4Qxx",
572  .max_flash_size_kb = 1024,
573  .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
574  .flash_regs_base = 0x40022000,
575  .fsize_addr = 0x1FFF75E0,
576  .otp_base = 0x1FFF7000,
577  .otp_size = 1024,
578  },
579  {
580  .id = DEVID_STM32L55_L56XX,
581  .revs = stm32l55_l56xx_revs,
582  .num_revs = ARRAY_SIZE(stm32l55_l56xx_revs),
583  .device_str = "STM32L55/L56xx",
584  .max_flash_size_kb = 512,
586  .flash_regs_base = 0x40022000,
587  .fsize_addr = 0x0BFA05E0,
588  .otp_base = 0x0BFA0000,
589  .otp_size = 512,
590  },
591  {
592  .id = DEVID_STM32G49_G4AXX,
593  .revs = stm32g49_g4axx_revs,
594  .num_revs = ARRAY_SIZE(stm32g49_g4axx_revs),
595  .device_str = "STM32G49/G4Axx",
596  .max_flash_size_kb = 512,
597  .flags = F_NONE,
598  .flash_regs_base = 0x40022000,
599  .fsize_addr = 0x1FFF75E0,
600  .otp_base = 0x1FFF7000,
601  .otp_size = 1024,
602  },
603  {
604  .id = DEVID_STM32U59_U5AXX,
605  .revs = stm32u59_u5axx_revs,
606  .num_revs = ARRAY_SIZE(stm32u59_u5axx_revs),
607  .device_str = "STM32U59/U5Axx",
608  .max_flash_size_kb = 4096,
610  .flash_regs_base = 0x40022000,
611  .fsize_addr = 0x0BFA07A0,
612  .otp_base = 0x0BFA0000,
613  .otp_size = 512,
614  },
615  {
616  .id = DEVID_STM32U57_U58XX,
617  .revs = stm32u57_u58xx_revs,
618  .num_revs = ARRAY_SIZE(stm32u57_u58xx_revs),
619  .device_str = "STM32U57/U58xx",
620  .max_flash_size_kb = 2048,
622  .flash_regs_base = 0x40022000,
623  .fsize_addr = 0x0BFA07A0,
624  .otp_base = 0x0BFA0000,
625  .otp_size = 512,
626  },
627  {
628  .id = DEVID_STM32WBA5X,
629  .revs = stm32wba5x_revs,
630  .num_revs = ARRAY_SIZE(stm32wba5x_revs),
631  .device_str = "STM32WBA5x",
632  .max_flash_size_kb = 1024,
634  .flash_regs_base = 0x40022000,
635  .fsize_addr = 0x0FF907A0,
636  .otp_base = 0x0FF90000,
637  .otp_size = 512,
638  },
639  {
640  .id = DEVID_STM32WB1XX,
641  .revs = stm32wb1xx_revs,
642  .num_revs = ARRAY_SIZE(stm32wb1xx_revs),
643  .device_str = "STM32WB1x",
644  .max_flash_size_kb = 320,
645  .flags = F_NONE,
646  .flash_regs_base = 0x58004000,
647  .fsize_addr = 0x1FFF75E0,
648  .otp_base = 0x1FFF7000,
649  .otp_size = 1024,
650  },
651  {
652  .id = DEVID_STM32WB5XX,
653  .revs = stm32wb5xx_revs,
654  .num_revs = ARRAY_SIZE(stm32wb5xx_revs),
655  .device_str = "STM32WB5x",
656  .max_flash_size_kb = 1024,
657  .flags = F_NONE,
658  .flash_regs_base = 0x58004000,
659  .fsize_addr = 0x1FFF75E0,
660  .otp_base = 0x1FFF7000,
661  .otp_size = 1024,
662  },
663  {
664  .id = DEVID_STM32WB3XX,
665  .revs = stm32wb3xx_revs,
666  .num_revs = ARRAY_SIZE(stm32wb3xx_revs),
667  .device_str = "STM32WB3x",
668  .max_flash_size_kb = 512,
669  .flags = F_NONE,
670  .flash_regs_base = 0x58004000,
671  .fsize_addr = 0x1FFF75E0,
672  .otp_base = 0x1FFF7000,
673  .otp_size = 1024,
674  },
675  {
676  .id = DEVID_STM32WLE_WL5XX,
677  .revs = stm32wle_wl5xx_revs,
678  .num_revs = ARRAY_SIZE(stm32wle_wl5xx_revs),
679  .device_str = "STM32WLE/WL5x",
680  .max_flash_size_kb = 256,
681  .flags = F_NONE,
682  .flash_regs_base = 0x58004000,
683  .fsize_addr = 0x1FFF75E0,
684  .otp_base = 0x1FFF7000,
685  .otp_size = 1024,
686  },
687 };
688 
689 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
690 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
691 {
692  struct stm32l4_flash_bank *stm32l4_info;
693 
694  if (CMD_ARGC < 6)
696 
697  /* fix-up bank base address: 0 is used for normal flash memory */
698  if (bank->base == 0)
699  bank->base = STM32_FLASH_BANK_BASE;
700 
701  stm32l4_info = calloc(1, sizeof(struct stm32l4_flash_bank));
702  if (!stm32l4_info)
703  return ERROR_FAIL; /* Checkme: What better error to use?*/
704  bank->driver_priv = stm32l4_info;
705 
706  stm32l4_info->probed = false;
707  stm32l4_info->otp_enabled = false;
708  stm32l4_info->user_bank_size = bank->size;
709 
710  return ERROR_OK;
711 }
712 
713 /* bitmap helper extension */
714 struct range {
715  unsigned int start;
716  unsigned int end;
717 };
718 
719 static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits,
720  struct range *ranges, unsigned int *ranges_count)
721 {
722  *ranges_count = 0;
723  bool last_bit = 0, cur_bit;
724  for (unsigned int i = 0; i < nbits; i++) {
725  cur_bit = test_bit(i, bitmap);
726 
727  if (cur_bit && !last_bit) {
728  (*ranges_count)++;
729  ranges[*ranges_count - 1].start = i;
730  ranges[*ranges_count - 1].end = i;
731  } else if (cur_bit && last_bit) {
732  /* update (increment) the end this range */
733  ranges[*ranges_count - 1].end = i;
734  }
735 
736  last_bit = cur_bit;
737  }
738 }
739 
740 static inline int range_print_one(struct range *range, char *str)
741 {
742  if (range->start == range->end)
743  return sprintf(str, "[%d]", range->start);
744 
745  return sprintf(str, "[%d,%d]", range->start, range->end);
746 }
747 
748 static char *range_print_alloc(struct range *ranges, unsigned int ranges_count)
749 {
750  /* each range will be printed like the following: [start,end]
751  * start and end, both are unsigned int, an unsigned int takes 10 characters max
752  * plus 3 characters for '[', ',' and ']'
753  * thus means each range can take maximum 23 character
754  * after each range we add a ' ' as separator and finally we need the '\0'
755  * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
756  char *str = calloc(1, ranges_count * (24 * sizeof(char)) + 1);
757  char *ptr = str;
758 
759  for (unsigned int i = 0; i < ranges_count; i++) {
760  ptr += range_print_one(&(ranges[i]), ptr);
761 
762  if (i < ranges_count - 1)
763  *(ptr++) = ' ';
764  }
765 
766  return str;
767 }
768 
769 /* end of bitmap helper extension */
770 
771 static inline bool stm32l4_is_otp(struct flash_bank *bank)
772 {
773  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
774  return bank->base == stm32l4_info->part_info->otp_base;
775 }
776 
777 static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
778 {
779  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
780 
781  if (!stm32l4_is_otp(bank))
782  return ERROR_FAIL;
783 
784  char *op_str = enable ? "enabled" : "disabled";
785 
786  LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
787  bank->bank_number,
788  stm32l4_info->otp_enabled == enable ? "already " : "",
789  op_str);
790 
791  stm32l4_info->otp_enabled = enable;
792 
793  return ERROR_OK;
794 }
795 
796 static inline bool stm32l4_otp_is_enabled(struct flash_bank *bank)
797 {
798  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
799  return stm32l4_info->otp_enabled;
800 }
801 
803 {
804  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
805 
806  bool tzen = false;
807 
808  if (stm32l4_info->part_info->flags & F_HAS_TZ)
809  tzen = (stm32l4_info->optr & FLASH_TZEN) != 0;
810 
811  uint32_t rdp = stm32l4_info->optr & FLASH_RDP_MASK;
812 
813  /* for devices without TrustZone:
814  * RDP level 0 and 2 values are to 0xAA and 0xCC
815  * Any other value corresponds to RDP level 1
816  * for devices with TrusZone:
817  * RDP level 0 and 2 values are 0xAA and 0xCC
818  * RDP level 0.5 value is 0x55 only if TZEN = 1
819  * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
820  */
821 
822  if (rdp != RDP_LEVEL_0 && rdp != RDP_LEVEL_2) {
823  if (!tzen || (tzen && rdp != RDP_LEVEL_0_5))
824  rdp = RDP_LEVEL_1;
825  }
826 
827  stm32l4_info->tzen = tzen;
828  stm32l4_info->rdp = rdp;
829 }
830 
831 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
832 {
833  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
834  return stm32l4_info->flash_regs_base + reg_offset;
835 }
836 
837 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
838  enum stm32l4_flash_reg_index reg_index)
839 {
840  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
841  return stm32l4_get_flash_reg(bank, stm32l4_info->flash_regs[reg_index]);
842 }
843 
844 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
845 {
846  return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
847 }
848 
850  enum stm32l4_flash_reg_index reg_index, uint32_t *value)
851 {
852  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
853  return stm32l4_read_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
854 }
855 
856 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
857 {
858  return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
859 }
860 
862  enum stm32l4_flash_reg_index reg_index, uint32_t value)
863 {
864  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
865  return stm32l4_write_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
866 }
867 
869 {
870  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
871  uint32_t status;
872  int retval = ERROR_OK;
873 
874  /* wait for busy to clear */
875  for (;;) {
877  if (retval != ERROR_OK)
878  return retval;
879  LOG_DEBUG("status: 0x%" PRIx32 "", status);
880  if ((status & stm32l4_info->sr_bsy_mask) == 0)
881  break;
882  if (timeout-- <= 0) {
883  LOG_ERROR("timed out waiting for flash");
884  return ERROR_FAIL;
885  }
886  alive_sleep(1);
887  }
888 
889  if (status & FLASH_WRPERR) {
890  LOG_ERROR("stm32x device protected");
891  retval = ERROR_FAIL;
892  }
893 
894  /* Clear but report errors */
895  if (status & FLASH_ERROR) {
896  if (retval == ERROR_OK)
897  retval = ERROR_FAIL;
898  /* If this operation fails, we ignore it and report the original
899  * retval
900  */
902  }
903 
904  return retval;
905 }
906 
908 static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
909 {
910  /* This function should be used only with device with TrustZone, do just a security check */
911  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
912  assert(stm32l4_info->part_info->flags & F_HAS_TZ);
913 
914  /* based on RM0438 Rev6 for STM32L5x devices:
915  * to modify a page block-based security attribution, it is recommended to
916  * 1- check that no flash operation is ongoing on the related page
917  * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
918  * this step is not need in case of JTAG direct access
919  */
921  if (retval != ERROR_OK)
922  return retval;
923 
924  /* write SECBBxRy registers */
925  LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
926 
927  const uint8_t secbb_regs[] = {
928  FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
929  FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
930  };
931 
932 
933  unsigned int num_secbb_regs = ARRAY_SIZE(secbb_regs);
934 
935  /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
936  * then consider only the first half of secbb_regs
937  */
938  if (!stm32l4_info->dual_bank_mode)
939  num_secbb_regs /= 2;
940 
941  for (unsigned int i = 0; i < num_secbb_regs; i++) {
942  retval = stm32l4_write_flash_reg(bank, secbb_regs[i], value);
943  if (retval != ERROR_OK)
944  return retval;
945  }
946 
947  return ERROR_OK;
948 }
949 
951 {
952  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
953  return (stm32l4_info->flash_regs[STM32_FLASH_CR_WLK_INDEX]) ?
955 }
956 
957 static int stm32l4_unlock_reg(struct flash_bank *bank)
958 {
959  const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
960  uint32_t ctrl;
961 
962  /* first check if not already unlocked
963  * otherwise writing on STM32_FLASH_KEYR will fail
964  */
965  int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
966  if (retval != ERROR_OK)
967  return retval;
968 
969  if ((ctrl & FLASH_LOCK) == 0)
970  return ERROR_OK;
971 
972  /* unlock flash registers */
974  if (retval != ERROR_OK)
975  return retval;
976 
978  if (retval != ERROR_OK)
979  return retval;
980 
981  retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
982  if (retval != ERROR_OK)
983  return retval;
984 
985  if (ctrl & FLASH_LOCK) {
986  LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
987  return ERROR_TARGET_FAILURE;
988  }
989 
990  return ERROR_OK;
991 }
992 
994 {
995  const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
996  uint32_t ctrl;
997 
998  int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
999  if (retval != ERROR_OK)
1000  return retval;
1001 
1002  if ((ctrl & FLASH_OPTLOCK) == 0)
1003  return ERROR_OK;
1004 
1005  /* unlock option registers */
1007  if (retval != ERROR_OK)
1008  return retval;
1009 
1011  if (retval != ERROR_OK)
1012  return retval;
1013 
1014  retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
1015  if (retval != ERROR_OK)
1016  return retval;
1017 
1018  if (ctrl & FLASH_OPTLOCK) {
1019  LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
1020  return ERROR_TARGET_FAILURE;
1021  }
1022 
1023  return ERROR_OK;
1024 }
1025 
1027 {
1028  int retval, retval2;
1029 
1030  retval = stm32l4_unlock_reg(bank);
1031  if (retval != ERROR_OK)
1032  goto err_lock;
1033 
1034  retval = stm32l4_unlock_option_reg(bank);
1035  if (retval != ERROR_OK)
1036  goto err_lock;
1037 
1038  /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
1039  * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
1040  * "Note: If the read protection is set while the debugger is still
1041  * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
1042  */
1043 
1044  /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
1045  /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
1046  * then just ignore the returned value */
1048 
1049  /* Need to re-probe after change */
1050  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1051  stm32l4_info->probed = false;
1052 
1053 err_lock:
1056 
1057  if (retval != ERROR_OK)
1058  return retval;
1059 
1060  return retval2;
1061 }
1062 
1063 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
1064  uint32_t value, uint32_t mask)
1065 {
1066  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1067  uint32_t optiondata;
1068  int retval, retval2;
1069 
1070  retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
1071  if (retval != ERROR_OK)
1072  return retval;
1073 
1074  /* for STM32L5 and similar devices, use always non-secure
1075  * registers for option bytes programming */
1076  const uint32_t *saved_flash_regs = stm32l4_info->flash_regs;
1077  if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
1078  stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1079 
1080  retval = stm32l4_unlock_reg(bank);
1081  if (retval != ERROR_OK)
1082  goto err_lock;
1083 
1084  retval = stm32l4_unlock_option_reg(bank);
1085  if (retval != ERROR_OK)
1086  goto err_lock;
1087 
1088  optiondata = (optiondata & ~mask) | (value & mask);
1089 
1090  retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
1091  if (retval != ERROR_OK)
1092  goto err_lock;
1093 
1095  if (retval != ERROR_OK)
1096  goto err_lock;
1097 
1099 
1100 err_lock:
1103  stm32l4_info->flash_regs = saved_flash_regs;
1104 
1105  if (retval != ERROR_OK)
1106  return retval;
1107 
1108  return retval2;
1109 }
1110 
1111 static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy,
1112  enum stm32l4_flash_reg_index reg_idx, int offset)
1113 {
1114  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1115  int ret;
1116 
1117  wrpxy->reg_idx = reg_idx;
1118  wrpxy->offset = offset;
1119 
1120  ret = stm32l4_read_flash_reg_by_index(bank, wrpxy->reg_idx , &wrpxy->value);
1121  if (ret != ERROR_OK)
1122  return ret;
1123 
1124  wrpxy->first = (wrpxy->value & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1125  wrpxy->last = ((wrpxy->value >> 16) & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1126  wrpxy->used = wrpxy->first <= wrpxy->last;
1127 
1128  return ERROR_OK;
1129 }
1130 
1131 static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id,
1132  struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
1133 {
1134  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1135  int ret;
1136 
1137  *n_wrp = 0;
1138 
1139  /* for single bank devices there is 2 WRP regions.
1140  * for dual bank devices there is 2 WRP regions per bank,
1141  * if configured as single bank only 2 WRP are usable
1142  * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
1143  * note: this should be revised, if a device will have the SWAP banks option
1144  */
1145 
1146  int wrp2y_sectors_offset = -1; /* -1 : unused */
1147 
1148  /* if bank_id is BANK1 or ALL_BANKS */
1149  if (dev_bank_id != STM32_BANK2) {
1150  /* get FLASH_WRP1AR */
1151  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1AR_INDEX, 0);
1152  if (ret != ERROR_OK)
1153  return ret;
1154 
1155  /* get WRP1BR */
1156  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1BR_INDEX, 0);
1157  if (ret != ERROR_OK)
1158  return ret;
1159 
1160  /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
1161  if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode)
1162  wrp2y_sectors_offset = 0;
1163  }
1164 
1165  /* if bank_id is BANK2 or ALL_BANKS */
1166  if (dev_bank_id != STM32_BANK1 && stm32l4_info->dual_bank_mode)
1167  wrp2y_sectors_offset = stm32l4_info->bank1_sectors;
1168 
1169  if (wrp2y_sectors_offset >= 0) {
1170  /* get WRP2AR */
1171  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2AR_INDEX, wrp2y_sectors_offset);
1172  if (ret != ERROR_OK)
1173  return ret;
1174 
1175  /* get WRP2BR */
1176  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2BR_INDEX, wrp2y_sectors_offset);
1177  if (ret != ERROR_OK)
1178  return ret;
1179  }
1180 
1181  return ERROR_OK;
1182 }
1183 
1184 static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
1185 {
1186  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1187 
1188  int wrp_start = wrpxy->first - wrpxy->offset;
1189  int wrp_end = wrpxy->last - wrpxy->offset;
1190 
1191  uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16);
1192 
1193  return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff);
1194 }
1195 
1196 static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
1197 {
1198  int ret;
1199 
1200  for (unsigned int i = 0; i < n_wrp; i++) {
1201  ret = stm32l4_write_one_wrpxy(bank, &wrpxy[i]);
1202  if (ret != ERROR_OK)
1203  return ret;
1204  }
1205 
1206  return ERROR_OK;
1207 }
1208 
1210 {
1211  unsigned int n_wrp;
1212  struct stm32l4_wrp wrpxy[4];
1213 
1214  int ret = stm32l4_get_all_wrpxy(bank, STM32_ALL_BANKS, wrpxy, &n_wrp);
1215  if (ret != ERROR_OK)
1216  return ret;
1217 
1218  /* initialize all sectors as unprotected */
1219  for (unsigned int i = 0; i < bank->num_sectors; i++)
1220  bank->sectors[i].is_protected = 0;
1221 
1222  /* now check WRPxy and mark the protected sectors */
1223  for (unsigned int i = 0; i < n_wrp; i++) {
1224  if (wrpxy[i].used) {
1225  for (int s = wrpxy[i].first; s <= wrpxy[i].last; s++)
1226  bank->sectors[s].is_protected = 1;
1227  }
1228  }
1229 
1230  return ERROR_OK;
1231 }
1232 
1233 static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
1234  unsigned int last)
1235 {
1236  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1237  int retval, retval2;
1238 
1239  assert((first <= last) && (last < bank->num_sectors));
1240 
1241  if (stm32l4_is_otp(bank)) {
1242  LOG_ERROR("cannot erase OTP memory");
1244  }
1245 
1246  if (bank->target->state != TARGET_HALTED) {
1247  LOG_ERROR("Target not halted");
1248  return ERROR_TARGET_NOT_HALTED;
1249  }
1250 
1251  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1252  /* set all FLASH pages as secure */
1254  if (retval != ERROR_OK) {
1255  /* restore all FLASH pages as non-secure */
1256  stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1257  return retval;
1258  }
1259  }
1260 
1261  retval = stm32l4_unlock_reg(bank);
1262  if (retval != ERROR_OK)
1263  goto err_lock;
1264 
1265  /*
1266  Sector Erase
1267  To erase a sector, follow the procedure below:
1268  1. Check that no Flash memory operation is ongoing by
1269  checking the BSY bit in the FLASH_SR register
1270  2. Set the PER bit and select the page and bank
1271  you wish to erase in the FLASH_CR register
1272  3. Set the STRT bit in the FLASH_CR register
1273  4. Wait for the BSY bit to be cleared
1274  */
1275 
1276  for (unsigned int i = first; i <= last; i++) {
1277  uint32_t erase_flags;
1278  erase_flags = FLASH_PER | FLASH_STRT;
1279 
1280  if (i >= stm32l4_info->bank1_sectors) {
1281  uint8_t snb;
1282  snb = i - stm32l4_info->bank1_sectors;
1283  erase_flags |= snb << FLASH_PAGE_SHIFT | stm32l4_info->cr_bker_mask;
1284  } else
1285  erase_flags |= i << FLASH_PAGE_SHIFT;
1287  if (retval != ERROR_OK)
1288  break;
1289 
1291  if (retval != ERROR_OK)
1292  break;
1293  }
1294 
1295 err_lock:
1297 
1298  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1299  /* restore all FLASH pages as non-secure */
1301  if (retval3 != ERROR_OK)
1302  return retval3;
1303  }
1304 
1305  if (retval != ERROR_OK)
1306  return retval;
1307 
1308  return retval2;
1309 }
1310 
1311 static int stm32l4_protect_same_bank(struct flash_bank *bank, enum stm32_bank_id bank_id, int set,
1312  unsigned int first, unsigned int last)
1313 {
1314  unsigned int i;
1315 
1316  /* check if the desired protection is already configured */
1317  for (i = first; i <= last; i++) {
1318  if (bank->sectors[i].is_protected != set)
1319  break;
1320  else if (i == last) {
1321  LOG_INFO("The specified sectors are already %s", set ? "protected" : "unprotected");
1322  return ERROR_OK;
1323  }
1324  }
1325 
1326  /* all sectors from first to last (or part of them) could have different
1327  * protection other than the requested */
1328  unsigned int n_wrp;
1329  struct stm32l4_wrp wrpxy[4];
1330 
1331  int ret = stm32l4_get_all_wrpxy(bank, bank_id, wrpxy, &n_wrp);
1332  if (ret != ERROR_OK)
1333  return ret;
1334 
1335  /* use bitmap and range helpers to optimize the WRP usage */
1336  DECLARE_BITMAP(pages, bank->num_sectors);
1337  bitmap_zero(pages, bank->num_sectors);
1338 
1339  for (i = 0; i < n_wrp; i++) {
1340  if (wrpxy[i].used) {
1341  for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
1342  set_bit(p, pages);
1343  }
1344  }
1345 
1346  /* we have at most 'n_wrp' WRP areas
1347  * add one range if the user is trying to protect a fifth range */
1348  struct range ranges[n_wrp + 1];
1349  unsigned int ranges_count = 0;
1350 
1351  bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1352 
1353  /* pretty-print the currently protected ranges */
1354  if (ranges_count > 0) {
1355  char *ranges_str = range_print_alloc(ranges, ranges_count);
1356  LOG_DEBUG("current protected areas: %s", ranges_str);
1357  free(ranges_str);
1358  } else
1359  LOG_DEBUG("current protected areas: none");
1360 
1361  if (set) { /* flash protect */
1362  for (i = first; i <= last; i++)
1363  set_bit(i, pages);
1364  } else { /* flash unprotect */
1365  for (i = first; i <= last; i++)
1366  clear_bit(i, pages);
1367  }
1368 
1369  /* check the ranges_count after the user request */
1370  bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1371 
1372  /* pretty-print the requested areas for protection */
1373  if (ranges_count > 0) {
1374  char *ranges_str = range_print_alloc(ranges, ranges_count);
1375  LOG_DEBUG("requested areas for protection: %s", ranges_str);
1376  free(ranges_str);
1377  } else
1378  LOG_DEBUG("requested areas for protection: none");
1379 
1380  if (ranges_count > n_wrp) {
1381  LOG_ERROR("cannot set the requested protection "
1382  "(only %u write protection areas are available)" , n_wrp);
1383  return ERROR_FAIL;
1384  }
1385 
1386  /* re-init all WRPxy as disabled (first > last)*/
1387  for (i = 0; i < n_wrp; i++) {
1388  wrpxy[i].first = wrpxy[i].offset + 1;
1389  wrpxy[i].last = wrpxy[i].offset;
1390  }
1391 
1392  /* then configure WRPxy areas */
1393  for (i = 0; i < ranges_count; i++) {
1394  wrpxy[i].first = ranges[i].start;
1395  wrpxy[i].last = ranges[i].end;
1396  }
1397 
1398  /* finally write WRPxy registers */
1399  return stm32l4_write_all_wrpxy(bank, wrpxy, n_wrp);
1400 }
1401 
1402 static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
1403 {
1404  struct target *target = bank->target;
1405  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1406 
1407  if (stm32l4_is_otp(bank)) {
1408  LOG_ERROR("cannot protect/unprotect OTP memory");
1410  }
1411 
1412  if (target->state != TARGET_HALTED) {
1413  LOG_ERROR("Target not halted");
1414  return ERROR_TARGET_NOT_HALTED;
1415  }
1416 
1417  /* refresh the sectors' protection */
1418  int ret = stm32l4_protect_check(bank);
1419  if (ret != ERROR_OK)
1420  return ret;
1421 
1422  /* the requested sectors could be located into bank1 and/or bank2 */
1423  if (last < stm32l4_info->bank1_sectors) {
1424  return stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, last);
1425  } else if (first >= stm32l4_info->bank1_sectors) {
1426  return stm32l4_protect_same_bank(bank, STM32_BANK2, set, first, last);
1427  } else {
1428  ret = stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, stm32l4_info->bank1_sectors - 1);
1429  if (ret != ERROR_OK)
1430  return ret;
1431 
1432  return stm32l4_protect_same_bank(bank, STM32_BANK2, set, stm32l4_info->bank1_sectors, last);
1433  }
1434 }
1435 
1436 /* count is the size divided by stm32l4_info->data_width */
1437 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
1438  uint32_t offset, uint32_t count)
1439 {
1440  struct target *target = bank->target;
1441  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1442  struct working_area *write_algorithm;
1443  struct working_area *source;
1444  uint32_t address = bank->base + offset;
1445  struct reg_param reg_params[5];
1446  struct armv7m_algorithm armv7m_info;
1447  int retval = ERROR_OK;
1448 
1449  static const uint8_t stm32l4_flash_write_code[] = {
1450 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1451  };
1452 
1453  if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
1454  &write_algorithm) != ERROR_OK) {
1455  LOG_WARNING("no working area available, can't do block memory writes");
1457  }
1458 
1459  retval = target_write_buffer(target, write_algorithm->address,
1460  sizeof(stm32l4_flash_write_code),
1461  stm32l4_flash_write_code);
1462  if (retval != ERROR_OK) {
1463  target_free_working_area(target, write_algorithm);
1464  return retval;
1465  }
1466 
1467  /* data_width should be multiple of double-word */
1468  assert(stm32l4_info->data_width % 8 == 0);
1469  const size_t extra_size = sizeof(struct stm32l4_work_area);
1470  uint32_t buffer_size = target_get_working_area_avail(target) - extra_size;
1471  /* buffer_size should be multiple of stm32l4_info->data_width */
1472  buffer_size &= ~(stm32l4_info->data_width - 1);
1473 
1474  if (buffer_size < 256) {
1475  LOG_WARNING("large enough working area not available, can't do block memory writes");
1476  target_free_working_area(target, write_algorithm);
1478  } else if (buffer_size > 16384) {
1479  /* probably won't benefit from more than 16k ... */
1480  buffer_size = 16384;
1481  }
1482 
1483  if (target_alloc_working_area_try(target, buffer_size + extra_size, &source) != ERROR_OK) {
1484  LOG_ERROR("allocating working area failed");
1486  }
1487 
1488  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1489  armv7m_info.core_mode = ARM_MODE_THREAD;
1490 
1491  /* contrib/loaders/flash/stm32/stm32l4x.c:write() arguments */
1492  init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* stm32l4_work_area ptr , status (out) */
1493  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
1494  init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
1495  init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (of stm32l4_info->data_width) */
1496 
1497  buf_set_u32(reg_params[0].value, 0, 32, source->address);
1498  buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
1499  buf_set_u32(reg_params[2].value, 0, 32, address);
1500  buf_set_u32(reg_params[3].value, 0, 32, count);
1501 
1502  /* write algo stack pointer */
1503  init_reg_param(&reg_params[4], "sp", 32, PARAM_OUT);
1504  buf_set_u32(reg_params[4].value, 0, 32, source->address +
1505  offsetof(struct stm32l4_work_area, stack) + LDR_STACK_SIZE);
1506 
1507  struct stm32l4_loader_params loader_extra_params;
1508 
1509  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_addr,
1511  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_cr_addr,
1513  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_word_size,
1514  stm32l4_info->data_width);
1515  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_bsy_mask,
1516  stm32l4_info->sr_bsy_mask);
1517 
1518  retval = target_write_buffer(target, source->address, sizeof(loader_extra_params),
1519  (uint8_t *) &loader_extra_params);
1520  if (retval != ERROR_OK)
1521  return retval;
1522 
1524  0, NULL,
1525  ARRAY_SIZE(reg_params), reg_params,
1526  source->address + offsetof(struct stm32l4_work_area, fifo),
1527  source->size - offsetof(struct stm32l4_work_area, fifo),
1528  write_algorithm->address, 0,
1529  &armv7m_info);
1530 
1531  if (retval == ERROR_FLASH_OPERATION_FAILED) {
1532  LOG_ERROR("error executing stm32l4 flash write algorithm");
1533 
1534  uint32_t error;
1536  error &= FLASH_ERROR;
1537 
1538  if (error & FLASH_WRPERR)
1539  LOG_ERROR("flash memory write protected");
1540 
1541  if (error != 0) {
1542  LOG_ERROR("flash write failed = %08" PRIx32, error);
1543  /* Clear but report errors */
1545  retval = ERROR_FAIL;
1546  }
1547  }
1548 
1550  target_free_working_area(target, write_algorithm);
1551 
1552  destroy_reg_param(&reg_params[0]);
1553  destroy_reg_param(&reg_params[1]);
1554  destroy_reg_param(&reg_params[2]);
1555  destroy_reg_param(&reg_params[3]);
1556  destroy_reg_param(&reg_params[4]);
1557 
1558  return retval;
1559 }
1560 
1561 /* count is the size divided by stm32l4_info->data_width */
1562 static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer,
1563  uint32_t offset, uint32_t count)
1564 {
1565  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1566  struct target *target = bank->target;
1567  uint32_t address = bank->base + offset;
1568  int retval = ERROR_OK;
1569 
1570  /* wait for BSY bit */
1572  if (retval != ERROR_OK)
1573  return retval;
1574 
1575  /* set PG in FLASH_CR */
1577  if (retval != ERROR_OK)
1578  return retval;
1579 
1580 
1581  /* write directly to flash memory */
1582  const uint8_t *src = buffer;
1583  const uint32_t data_width_in_words = stm32l4_info->data_width / 4;
1584  while (count--) {
1585  retval = target_write_memory(target, address, 4, data_width_in_words, src);
1586  if (retval != ERROR_OK)
1587  return retval;
1588 
1589  /* wait for BSY bit */
1591  if (retval != ERROR_OK)
1592  return retval;
1593 
1594  src += stm32l4_info->data_width;
1595  address += stm32l4_info->data_width;
1596  }
1597 
1598  /* reset PG in FLASH_CR */
1600  if (retval != ERROR_OK)
1601  return retval;
1602 
1603  return retval;
1604 }
1605 
1606 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
1607  uint32_t offset, uint32_t count)
1608 {
1609  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1610  int retval = ERROR_OK, retval2;
1611 
1613  LOG_ERROR("OTP memory is disabled for write commands");
1614  return ERROR_FAIL;
1615  }
1616 
1617  if (bank->target->state != TARGET_HALTED) {
1618  LOG_ERROR("Target not halted");
1619  return ERROR_TARGET_NOT_HALTED;
1620  }
1621 
1622  /* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
1623  assert(stm32l4_info->data_width % 8 == 0);
1624 
1625  /* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
1626  * The flash infrastructure ensures it, do just a security check */
1627  assert(offset % stm32l4_info->data_width == 0);
1628  assert(count % stm32l4_info->data_width == 0);
1629 
1630  /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1631  * data to be written does not go into a gap:
1632  * suppose buffer is fully contained in bank from sector 0 to sector
1633  * num->sectors - 1 and sectors are ordered according to offset
1634  */
1635  struct flash_sector *head = &bank->sectors[0];
1636  struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
1637 
1638  while ((head < tail) && (offset >= (head + 1)->offset)) {
1639  /* buffer does not intersect head nor gap behind head */
1640  head++;
1641  }
1642 
1643  while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
1644  /* buffer does not intersect tail nor gap before tail */
1645  --tail;
1646  }
1647 
1648  LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
1649  offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
1650 
1651  /* Now check that there is no gap from head to tail, this should work
1652  * even for multiple or non-symmetric gaps
1653  */
1654  while (head < tail) {
1655  if (head->offset + head->size != (head + 1)->offset) {
1656  LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
1657  bank->base + head->offset + head->size,
1658  bank->base + (head + 1)->offset - 1);
1659  retval = ERROR_FLASH_DST_OUT_OF_BANK;
1660  }
1661  head++;
1662  }
1663 
1664  if (retval != ERROR_OK)
1665  return retval;
1666 
1667  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1668  /* set all FLASH pages as secure */
1670  if (retval != ERROR_OK) {
1671  /* restore all FLASH pages as non-secure */
1672  stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1673  return retval;
1674  }
1675  }
1676 
1677  retval = stm32l4_unlock_reg(bank);
1678  if (retval != ERROR_OK)
1679  goto err_lock;
1680 
1681 
1682  /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
1683  * the debug is possible only in non-secure state.
1684  * Thus means the flashloader will run in non-secure mode,
1685  * and the workarea need to be in non-secure RAM */
1686  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
1687  LOG_WARNING("RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
1688 
1689  /* first try to write using the loader, for better performance */
1691  count / stm32l4_info->data_width);
1692 
1693  /* if resources are not available write without a loader */
1694  if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1695  LOG_WARNING("falling back to programming without a flash loader (slower)");
1697  count / stm32l4_info->data_width);
1698  }
1699 
1700 err_lock:
1702 
1703  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1704  /* restore all FLASH pages as non-secure */
1706  if (retval3 != ERROR_OK)
1707  return retval3;
1708  }
1709 
1710  if (retval != ERROR_OK) {
1711  LOG_ERROR("block write failed");
1712  return retval;
1713  }
1714  return retval2;
1715 }
1716 
1717 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
1718 {
1719  int retval = ERROR_OK;
1720  struct target *target = bank->target;
1721 
1722  /* try reading possible IDCODE registers, in the following order */
1723  uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
1724 
1725  for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) {
1726  retval = target_read_u32(target, dbgmcu_idcode[i], id);
1727  if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
1728  return ERROR_OK;
1729  }
1730 
1731  /* Workaround for STM32WL5x devices:
1732  * DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
1733  * to solve this read the UID64 (IEEE 64-bit unique device ID register) */
1734 
1735  struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1736  if (!armv7m) {
1737  LOG_ERROR("Flash requires Cortex-M target");
1738  return ERROR_TARGET_INVALID;
1739  }
1740 
1741  /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1742  * Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
1744  armv7m->debug_ap && armv7m->debug_ap->ap_num == 1) {
1745  uint32_t uid64_ids;
1746 
1747  /* UID64 is contains
1748  * - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
1749  * - Bits 31:08 : STID (company ID) = 0x0080E1
1750  * - Bits 07:00 : DEVID (device ID) = 0x15
1751  *
1752  * read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
1753  */
1754  retval = target_read_u32(target, UID64_IDS, &uid64_ids);
1755  if (retval == ERROR_OK && uid64_ids == UID64_IDS_STM32WL) {
1756  /* force the DEV_ID to DEVID_STM32WLE_WL5XX and the REV_ID to unknown */
1757  *id = DEVID_STM32WLE_WL5XX;
1758  return ERROR_OK;
1759  }
1760  }
1761 
1762  LOG_ERROR("can't get the device id");
1763  return (retval == ERROR_OK) ? ERROR_FAIL : retval;
1764 }
1765 
1766 static const char *get_stm32l4_rev_str(struct flash_bank *bank)
1767 {
1768  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1769  const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
1770  assert(part_info);
1771 
1772  const uint16_t rev_id = stm32l4_info->idcode >> 16;
1773  for (unsigned int i = 0; i < part_info->num_revs; i++) {
1774  if (rev_id == part_info->revs[i].rev)
1775  return part_info->revs[i].str;
1776  }
1777  return "'unknown'";
1778 }
1779 
1780 static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
1781 {
1782  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1783  assert(stm32l4_info->part_info);
1784  return stm32l4_is_otp(bank) ? "OTP" :
1785  stm32l4_info->dual_bank_mode ? "Flash dual" :
1786  "Flash single";
1787 }
1788 
1789 static int stm32l4_probe(struct flash_bank *bank)
1790 {
1791  struct target *target = bank->target;
1792  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1793  const struct stm32l4_part_info *part_info;
1794  uint16_t flash_size_kb = 0xffff;
1795 
1796  if (!target_was_examined(target)) {
1797  LOG_ERROR("Target not examined yet");
1799  }
1800 
1801  struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1802  if (!armv7m) {
1803  LOG_ERROR("Flash requires Cortex-M target");
1804  return ERROR_TARGET_INVALID;
1805  }
1806 
1807  stm32l4_info->probed = false;
1808 
1809  /* read stm32 device id registers */
1810  int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
1811  if (retval != ERROR_OK)
1812  return retval;
1813 
1814  const uint32_t device_id = stm32l4_info->idcode & 0xFFF;
1815 
1816  for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
1817  if (device_id == stm32l4_parts[n].id) {
1818  stm32l4_info->part_info = &stm32l4_parts[n];
1819  break;
1820  }
1821  }
1822 
1823  if (!stm32l4_info->part_info) {
1824  LOG_WARNING("Cannot identify target as an %s family device.", device_families);
1825  return ERROR_FAIL;
1826  }
1827 
1828  part_info = stm32l4_info->part_info;
1829  const char *rev_str = get_stm32l4_rev_str(bank);
1830  const uint16_t rev_id = stm32l4_info->idcode >> 16;
1831 
1832  LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)",
1833  stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
1834 
1835  stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
1836  stm32l4_info->data_width = (part_info->flags & F_QUAD_WORD_PROG) ? 16 : 8;
1837  stm32l4_info->cr_bker_mask = FLASH_BKER;
1838  stm32l4_info->sr_bsy_mask = FLASH_BSY;
1839 
1840  /* Set flash write alignment boundaries.
1841  * Ask the flash infrastructure to ensure required alignment */
1842  bank->write_start_alignment = stm32l4_info->data_width;
1843  bank->write_end_alignment = stm32l4_info->data_width;
1844 
1845  /* Initialize the flash registers layout */
1846  if (part_info->flags & F_HAS_L5_FLASH_REGS)
1847  stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1848  else
1849  stm32l4_info->flash_regs = stm32l4_flash_regs;
1850 
1851  /* read flash option register */
1853  if (retval != ERROR_OK)
1854  return retval;
1855 
1857 
1858  /* for devices with TrustZone, use flash secure registers when TZEN=1 and RDP is LEVEL_0 */
1859  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1860  if (part_info->flags & F_HAS_L5_FLASH_REGS) {
1861  stm32l4_info->flash_regs_base |= STM32L5_REGS_SEC_OFFSET;
1862  stm32l4_info->flash_regs = stm32l5_s_flash_regs;
1863  } else {
1864  LOG_ERROR("BUG: device supported incomplete");
1865  return ERROR_NOT_IMPLEMENTED;
1866  }
1867  }
1868 
1869  if (part_info->flags & F_HAS_TZ)
1870  LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1871  stm32l4_info->tzen,
1872  stm32l4_info->tzen ? "enabled" : "disabled");
1873 
1874  LOG_INFO("RDP level %s (0x%02X)",
1875  stm32l4_info->rdp == RDP_LEVEL_0 ? "0" : stm32l4_info->rdp == RDP_LEVEL_0_5 ? "0.5" : "1",
1876  stm32l4_info->rdp);
1877 
1878  if (stm32l4_is_otp(bank)) {
1879  bank->size = part_info->otp_size;
1880 
1881  LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT, bank->size, bank->base);
1882 
1883  /* OTP memory is considered as one sector */
1884  free(bank->sectors);
1885  bank->num_sectors = 1;
1886  bank->sectors = alloc_block_array(0, part_info->otp_size, 1);
1887 
1888  if (!bank->sectors) {
1889  LOG_ERROR("failed to allocate bank sectors");
1890  return ERROR_FAIL;
1891  }
1892 
1893  stm32l4_info->probed = true;
1894  return ERROR_OK;
1895  } else if (bank->base != STM32_FLASH_BANK_BASE && bank->base != STM32_FLASH_S_BANK_BASE) {
1896  LOG_ERROR("invalid bank base address");
1897  return ERROR_FAIL;
1898  }
1899 
1900  /* get flash size from target. */
1901  retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
1902 
1903  /* failed reading flash size or flash size invalid (early silicon),
1904  * default to max target family */
1905  if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
1906  || flash_size_kb > part_info->max_flash_size_kb) {
1907  LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1908  part_info->max_flash_size_kb);
1909  flash_size_kb = part_info->max_flash_size_kb;
1910  }
1911 
1912  /* if the user sets the size manually then ignore the probed value
1913  * this allows us to work around devices that have a invalid flash size register value */
1914  if (stm32l4_info->user_bank_size) {
1915  LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
1916  flash_size_kb = stm32l4_info->user_bank_size / 1024;
1917  }
1918 
1919  LOG_INFO("flash size = %d KiB", flash_size_kb);
1920 
1921  /* did we assign a flash size? */
1922  assert((flash_size_kb != 0xffff) && flash_size_kb);
1923 
1924  const bool is_max_flash_size = flash_size_kb == stm32l4_info->part_info->max_flash_size_kb;
1925 
1926  stm32l4_info->bank1_sectors = 0;
1927  stm32l4_info->hole_sectors = 0;
1928 
1929  int num_pages = 0;
1930  int page_size_kb = 0;
1931 
1932  stm32l4_info->dual_bank_mode = false;
1933 
1934  switch (device_id) {
1935  case DEVID_STM32L47_L48XX:
1936  case DEVID_STM32L49_L4AXX:
1937  /* if flash size is max (1M) the device is always dual bank
1938  * STM32L47/L48xx: has variants with 512K
1939  * STM32L49/L4Axx: has variants with 512 and 256
1940  * for these variants:
1941  * if DUAL_BANK = 0 -> single bank
1942  * else -> dual bank without gap
1943  * note: the page size is invariant
1944  */
1945  page_size_kb = 2;
1946  num_pages = flash_size_kb / page_size_kb;
1947  stm32l4_info->bank1_sectors = num_pages;
1948 
1949  /* check DUAL_BANK option bit if the flash is less than 1M */
1950  if (is_max_flash_size || (stm32l4_info->optr & FLASH_L4_DUAL_BANK)) {
1951  stm32l4_info->dual_bank_mode = true;
1952  stm32l4_info->bank1_sectors = num_pages / 2;
1953  }
1954  break;
1955  case DEVID_STM32L43_L44XX:
1956  case DEVID_STM32C01XX:
1957  case DEVID_STM32C03XX:
1958  case DEVID_STM32G05_G06XX:
1959  case DEVID_STM32G07_G08XX:
1960  case DEVID_STM32L45_L46XX:
1961  case DEVID_STM32L41_L42XX:
1962  case DEVID_STM32G03_G04XX:
1963  case DEVID_STM32G43_G44XX:
1964  case DEVID_STM32G49_G4AXX:
1965  case DEVID_STM32WB1XX:
1966  /* single bank flash */
1967  page_size_kb = 2;
1968  num_pages = flash_size_kb / page_size_kb;
1969  stm32l4_info->bank1_sectors = num_pages;
1970  break;
1971  case DEVID_STM32G0B_G0CXX:
1972  /* single/dual bank depending on DUAL_BANK option bit */
1973  page_size_kb = 2;
1974  num_pages = flash_size_kb / page_size_kb;
1975  stm32l4_info->bank1_sectors = num_pages;
1976  stm32l4_info->cr_bker_mask = FLASH_BKER_G0;
1977 
1978  /* check DUAL_BANK bit */
1979  if (stm32l4_info->optr & FLASH_G0_DUAL_BANK) {
1980  stm32l4_info->sr_bsy_mask = FLASH_BSY | FLASH_BSY2;
1981  stm32l4_info->dual_bank_mode = true;
1982  stm32l4_info->bank1_sectors = num_pages / 2;
1983  }
1984  break;
1985  case DEVID_STM32G47_G48XX:
1986  /* STM32G47/8 can be single/dual bank:
1987  * if DUAL_BANK = 0 -> single bank
1988  * else -> dual bank WITH gap
1989  */
1990  page_size_kb = 4;
1991  num_pages = flash_size_kb / page_size_kb;
1992  stm32l4_info->bank1_sectors = num_pages;
1993  if (stm32l4_info->optr & FLASH_G4_DUAL_BANK) {
1994  stm32l4_info->dual_bank_mode = true;
1995  page_size_kb = 2;
1996  num_pages = flash_size_kb / page_size_kb;
1997  stm32l4_info->bank1_sectors = num_pages / 2;
1998 
1999  /* for devices with trimmed flash, there is a gap between both banks */
2000  stm32l4_info->hole_sectors =
2001  (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
2002  }
2003  break;
2004  case DEVID_STM32L4R_L4SXX:
2005  case DEVID_STM32L4P_L4QXX:
2006  /* STM32L4R/S can be single/dual bank:
2007  * if size = 2M check DBANK bit
2008  * if size = 1M check DB1M bit
2009  * STM32L4P/Q can be single/dual bank
2010  * if size = 1M check DBANK bit
2011  * if size = 512K check DB512K bit (same as DB1M bit)
2012  */
2013  page_size_kb = 8;
2014  num_pages = flash_size_kb / page_size_kb;
2015  stm32l4_info->bank1_sectors = num_pages;
2016  if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L4R_DBANK)) ||
2017  (!is_max_flash_size && (stm32l4_info->optr & FLASH_LRR_DB1M))) {
2018  stm32l4_info->dual_bank_mode = true;
2019  page_size_kb = 4;
2020  num_pages = flash_size_kb / page_size_kb;
2021  stm32l4_info->bank1_sectors = num_pages / 2;
2022  }
2023  break;
2024  case DEVID_STM32L55_L56XX:
2025  /* STM32L55/L56xx can be single/dual bank:
2026  * if size = 512K check DBANK bit
2027  * if size = 256K check DB256K bit
2028  *
2029  * default page size is 4kb, if DBANK = 1, the page size is 2kb.
2030  */
2031 
2032  page_size_kb = (stm32l4_info->optr & FLASH_L5_DBANK) ? 2 : 4;
2033  num_pages = flash_size_kb / page_size_kb;
2034  stm32l4_info->bank1_sectors = num_pages;
2035 
2036  if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DBANK)) ||
2037  (!is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DB256))) {
2038  stm32l4_info->dual_bank_mode = true;
2039  stm32l4_info->bank1_sectors = num_pages / 2;
2040  }
2041  break;
2042  case DEVID_STM32U53_U54XX:
2043  case DEVID_STM32U57_U58XX:
2044  case DEVID_STM32U59_U5AXX:
2045  /* according to RM0456 Rev 4, Chapter 7.3.1 and 7.9.13
2046  * U53x/U54x have 512K max flash size:
2047  * 512K variants are always in DUAL BANK mode
2048  * 256K and 128K variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2049  * U57x/U58x have 2M max flash size:
2050  * 2M variants are always in DUAL BANK mode
2051  * 1M variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2052  * U59x/U5Ax have 4M max flash size:
2053  * 4M variants are always in DUAL BANK mode
2054  * 2M variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2055  * Note: flash banks are always contiguous
2056  */
2057 
2058  page_size_kb = 8;
2059  num_pages = flash_size_kb / page_size_kb;
2060  stm32l4_info->bank1_sectors = num_pages;
2061  if (is_max_flash_size || (stm32l4_info->optr & FLASH_U5_DUALBANK)) {
2062  stm32l4_info->dual_bank_mode = true;
2063  stm32l4_info->bank1_sectors = num_pages / 2;
2064  }
2065  break;
2066  case DEVID_STM32WBA5X:
2067  /* single bank flash */
2068  page_size_kb = 8;
2069  num_pages = flash_size_kb / page_size_kb;
2070  stm32l4_info->bank1_sectors = num_pages;
2071  break;
2072  case DEVID_STM32WB5XX:
2073  case DEVID_STM32WB3XX:
2074  /* single bank flash */
2075  page_size_kb = 4;
2076  num_pages = flash_size_kb / page_size_kb;
2077  stm32l4_info->bank1_sectors = num_pages;
2078  break;
2079  case DEVID_STM32WLE_WL5XX:
2080  /* single bank flash */
2081  page_size_kb = 2;
2082  num_pages = flash_size_kb / page_size_kb;
2083  stm32l4_info->bank1_sectors = num_pages;
2084 
2085  /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
2086  * Using HLA adapters armv7m->debug_ap is null, and checking ap_num triggers a segfault */
2087  if (armv7m->debug_ap && armv7m->debug_ap->ap_num == 1)
2088  stm32l4_info->flash_regs = stm32wl_cpu2_flash_regs;
2089  break;
2090  default:
2091  LOG_ERROR("unsupported device");
2092  return ERROR_FAIL;
2093  }
2094 
2095  /* ensure that at least there is 1 flash sector / page */
2096  if (num_pages == 0) {
2097  if (stm32l4_info->user_bank_size)
2098  LOG_ERROR("The specified flash size is less than page size");
2099 
2100  LOG_ERROR("Flash pages count cannot be zero");
2101  return ERROR_FAIL;
2102  }
2103 
2104  LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
2105 
2106  const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
2107 
2108  if (gap_size_kb != 0) {
2109  LOG_INFO("gap detected from 0x%08x to 0x%08x",
2110  STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
2111  * page_size_kb * 1024,
2112  STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
2113  * page_size_kb + gap_size_kb) * 1024 - 1);
2114  }
2115 
2116  /* number of significant bits in WRPxxR differs per device,
2117  * always right adjusted, on some devices non-implemented
2118  * bits read as '0', on others as '1' ...
2119  * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
2120  */
2121 
2122  /* use *max_flash_size* instead of actual size as the trimmed versions
2123  * certainly use the same number of bits
2124  */
2125  uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
2126 
2127  /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
2128  stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
2129  assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
2130  LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
2131 
2132  free(bank->sectors);
2133 
2134  bank->size = (flash_size_kb + gap_size_kb) * 1024;
2135  bank->num_sectors = num_pages;
2136  bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
2137  if (!bank->sectors) {
2138  LOG_ERROR("failed to allocate bank sectors");
2139  return ERROR_FAIL;
2140  }
2141 
2142  for (unsigned int i = 0; i < bank->num_sectors; i++) {
2143  bank->sectors[i].offset = i * page_size_kb * 1024;
2144  /* in dual bank configuration, if there is a gap between banks
2145  * we fix up the sector offset to consider this gap */
2146  if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
2147  bank->sectors[i].offset += gap_size_kb * 1024;
2148  bank->sectors[i].size = page_size_kb * 1024;
2149  bank->sectors[i].is_erased = -1;
2150  bank->sectors[i].is_protected = 1;
2151  }
2152 
2153  stm32l4_info->probed = true;
2154  return ERROR_OK;
2155 }
2156 
2158 {
2159  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2160  if (stm32l4_info->probed) {
2161  uint32_t optr_cur;
2162 
2163  /* save flash_regs_base */
2164  uint32_t saved_flash_regs_base = stm32l4_info->flash_regs_base;
2165 
2166  /* for devices with TrustZone, use NS flash registers to read OPTR */
2167  if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
2168  stm32l4_info->flash_regs_base &= ~STM32L5_REGS_SEC_OFFSET;
2169 
2170  /* read flash option register and re-probe if optr value is changed */
2172 
2173  /* restore saved flash_regs_base */
2174  stm32l4_info->flash_regs_base = saved_flash_regs_base;
2175 
2176  if (retval != ERROR_OK)
2177  return retval;
2178 
2179  if (stm32l4_info->optr == optr_cur)
2180  return ERROR_OK;
2181  }
2182 
2183  return stm32l4_probe(bank);
2184 }
2185 
2187 {
2188  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2189  const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
2190 
2191  if (part_info) {
2192  const uint16_t rev_id = stm32l4_info->idcode >> 16;
2193  command_print_sameline(cmd, "%s - Rev %s : 0x%04x", part_info->device_str,
2194  get_stm32l4_rev_str(bank), rev_id);
2195  if (stm32l4_info->probed)
2197  } else {
2198  command_print_sameline(cmd, "Cannot identify target as an %s device", device_families);
2199  }
2200 
2201  return ERROR_OK;
2202 }
2203 
2205 {
2206  int retval, retval2;
2207  struct target *target = bank->target;
2208  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2209 
2210  if (stm32l4_is_otp(bank)) {
2211  LOG_ERROR("cannot erase OTP memory");
2213  }
2214 
2215  uint32_t action = FLASH_MER1;
2216 
2217  if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)
2218  action |= FLASH_MER2;
2219 
2220  if (target->state != TARGET_HALTED) {
2221  LOG_ERROR("Target not halted");
2222  return ERROR_TARGET_NOT_HALTED;
2223  }
2224 
2225  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2226  /* set all FLASH pages as secure */
2228  if (retval != ERROR_OK) {
2229  /* restore all FLASH pages as non-secure */
2230  stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
2231  return retval;
2232  }
2233  }
2234 
2235  retval = stm32l4_unlock_reg(bank);
2236  if (retval != ERROR_OK)
2237  goto err_lock;
2238 
2239  /* mass erase flash memory */
2241  if (retval != ERROR_OK)
2242  goto err_lock;
2243 
2245  if (retval != ERROR_OK)
2246  goto err_lock;
2247 
2249  if (retval != ERROR_OK)
2250  goto err_lock;
2251 
2253 
2254 err_lock:
2256 
2257  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2258  /* restore all FLASH pages as non-secure */
2260  if (retval3 != ERROR_OK)
2261  return retval3;
2262  }
2263 
2264  if (retval != ERROR_OK)
2265  return retval;
2266 
2267  return retval2;
2268 }
2269 
2270 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
2271 {
2272  if (CMD_ARGC != 1)
2274 
2275  struct flash_bank *bank;
2276  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2277  if (retval != ERROR_OK)
2278  return retval;
2279 
2280  retval = stm32l4_mass_erase(bank);
2281  if (retval == ERROR_OK)
2282  command_print(CMD, "stm32l4x mass erase complete");
2283  else
2284  command_print(CMD, "stm32l4x mass erase failed");
2285 
2286  return retval;
2287 }
2288 
2289 COMMAND_HANDLER(stm32l4_handle_option_read_command)
2290 {
2291  if (CMD_ARGC != 2)
2293 
2294  struct flash_bank *bank;
2295  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2296  if (retval != ERROR_OK)
2297  return retval;
2298 
2299  uint32_t reg_offset, reg_addr;
2300  uint32_t value = 0;
2301 
2302  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2303  reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
2304 
2305  retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
2306  if (retval != ERROR_OK)
2307  return retval;
2308 
2309  command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
2310 
2311  return retval;
2312 }
2313 
2314 COMMAND_HANDLER(stm32l4_handle_option_write_command)
2315 {
2316  if (CMD_ARGC != 3 && CMD_ARGC != 4)
2318 
2319  struct flash_bank *bank;
2320  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2321  if (retval != ERROR_OK)
2322  return retval;
2323 
2324  uint32_t reg_offset;
2325  uint32_t value = 0;
2326  uint32_t mask = 0xFFFFFFFF;
2327 
2328  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2329  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
2330 
2331  if (CMD_ARGC > 3)
2333 
2334  command_print(CMD, "%s Option written.\n"
2335  "INFO: a reset or power cycle is required "
2336  "for the new settings to take effect.", bank->driver->name);
2337 
2338  retval = stm32l4_write_option(bank, reg_offset, value, mask);
2339  return retval;
2340 }
2341 
2342 COMMAND_HANDLER(stm32l4_handle_trustzone_command)
2343 {
2344  if (CMD_ARGC < 1 || CMD_ARGC > 2)
2346 
2347  struct flash_bank *bank;
2348  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2349  if (retval != ERROR_OK)
2350  return retval;
2351 
2352  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2353  if (!(stm32l4_info->part_info->flags & F_HAS_TZ)) {
2354  LOG_ERROR("This device does not have a TrustZone");
2355  return ERROR_FAIL;
2356  }
2357 
2359  if (retval != ERROR_OK)
2360  return retval;
2361 
2363 
2364  if (CMD_ARGC == 1) {
2365  /* only display the TZEN value */
2366  LOG_INFO("Global TrustZone Security is %s", stm32l4_info->tzen ? "enabled" : "disabled");
2367  return ERROR_OK;
2368  }
2369 
2370  bool new_tzen;
2371  COMMAND_PARSE_ENABLE(CMD_ARGV[1], new_tzen);
2372 
2373  if (new_tzen == stm32l4_info->tzen) {
2374  LOG_INFO("The requested TZEN is already programmed");
2375  return ERROR_OK;
2376  }
2377 
2378  if (new_tzen) {
2379  if (stm32l4_info->rdp != RDP_LEVEL_0) {
2380  LOG_ERROR("TZEN can be set only when RDP level is 0");
2381  return ERROR_FAIL;
2382  }
2385  } else {
2386  /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
2387  * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
2388  if (stm32l4_info->rdp != RDP_LEVEL_1 && stm32l4_info->rdp != RDP_LEVEL_0_5) {
2389  LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
2390  return ERROR_FAIL;
2391  }
2392 
2395  }
2396 
2397  if (retval != ERROR_OK)
2398  return retval;
2399 
2401 }
2402 
2403 COMMAND_HANDLER(stm32l4_handle_option_load_command)
2404 {
2405  if (CMD_ARGC != 1)
2407 
2408  struct flash_bank *bank;
2409  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2410  if (retval != ERROR_OK)
2411  return retval;
2412 
2413  retval = stm32l4_perform_obl_launch(bank);
2414  if (retval != ERROR_OK) {
2415  command_print(CMD, "stm32l4x option load failed");
2416  return retval;
2417  }
2418 
2419 
2420  command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
2421 
2422  return ERROR_OK;
2423 }
2424 
2425 COMMAND_HANDLER(stm32l4_handle_lock_command)
2426 {
2427  struct target *target = NULL;
2428 
2429  if (CMD_ARGC != 1)
2431 
2432  struct flash_bank *bank;
2433  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2434  if (retval != ERROR_OK)
2435  return retval;
2436 
2437  if (stm32l4_is_otp(bank)) {
2438  LOG_ERROR("cannot lock/unlock OTP memory");
2440  }
2441 
2442  target = bank->target;
2443 
2444  if (target->state != TARGET_HALTED) {
2445  LOG_ERROR("Target not halted");
2446  return ERROR_TARGET_NOT_HALTED;
2447  }
2448 
2449  /* set readout protection level 1 by erasing the RDP option byte */
2450  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2453  command_print(CMD, "%s failed to lock device", bank->driver->name);
2454  return ERROR_OK;
2455  }
2456 
2457  return ERROR_OK;
2458 }
2459 
2460 COMMAND_HANDLER(stm32l4_handle_unlock_command)
2461 {
2462  struct target *target = NULL;
2463 
2464  if (CMD_ARGC != 1)
2466 
2467  struct flash_bank *bank;
2468  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2469  if (retval != ERROR_OK)
2470  return retval;
2471 
2472  if (stm32l4_is_otp(bank)) {
2473  LOG_ERROR("cannot lock/unlock OTP memory");
2475  }
2476 
2477  target = bank->target;
2478 
2479  if (target->state != TARGET_HALTED) {
2480  LOG_ERROR("Target not halted");
2481  return ERROR_TARGET_NOT_HALTED;
2482  }
2483 
2484  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2487  command_print(CMD, "%s failed to unlock device", bank->driver->name);
2488  return ERROR_OK;
2489  }
2490 
2491  return ERROR_OK;
2492 }
2493 
2494 COMMAND_HANDLER(stm32l4_handle_wrp_info_command)
2495 {
2496  if (CMD_ARGC < 1 || CMD_ARGC > 2)
2498 
2499  struct flash_bank *bank;
2500  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2501  if (retval != ERROR_OK)
2502  return retval;
2503 
2504  if (stm32l4_is_otp(bank)) {
2505  LOG_ERROR("OTP memory does not have write protection areas");
2507  }
2508 
2509  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2510  enum stm32_bank_id dev_bank_id = STM32_ALL_BANKS;
2511  if (CMD_ARGC == 2) {
2512  if (strcmp(CMD_ARGV[1], "bank1") == 0)
2513  dev_bank_id = STM32_BANK1;
2514  else if (strcmp(CMD_ARGV[1], "bank2") == 0)
2515  dev_bank_id = STM32_BANK2;
2516  else
2518  }
2519 
2520  if (dev_bank_id == STM32_BANK2) {
2521  if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) {
2522  LOG_ERROR("this device has no second bank");
2523  return ERROR_FAIL;
2524  } else if (!stm32l4_info->dual_bank_mode) {
2525  LOG_ERROR("this device is configured in single bank mode");
2526  return ERROR_FAIL;
2527  }
2528  }
2529 
2530  int ret;
2531  unsigned int n_wrp, i;
2532  struct stm32l4_wrp wrpxy[4];
2533 
2534  ret = stm32l4_get_all_wrpxy(bank, dev_bank_id, wrpxy, &n_wrp);
2535  if (ret != ERROR_OK)
2536  return ret;
2537 
2538  /* use bitmap and range helpers to better describe protected areas */
2539  DECLARE_BITMAP(pages, bank->num_sectors);
2540  bitmap_zero(pages, bank->num_sectors);
2541 
2542  for (i = 0; i < n_wrp; i++) {
2543  if (wrpxy[i].used) {
2544  for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
2545  set_bit(p, pages);
2546  }
2547  }
2548 
2549  /* we have at most 'n_wrp' WRP areas */
2550  struct range ranges[n_wrp];
2551  unsigned int ranges_count = 0;
2552 
2553  bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
2554 
2555  if (ranges_count > 0) {
2556  /* pretty-print the protected ranges */
2557  char *ranges_str = range_print_alloc(ranges, ranges_count);
2558  command_print(CMD, "protected areas: %s", ranges_str);
2559  free(ranges_str);
2560  } else
2561  command_print(CMD, "no protected areas");
2562 
2563  return ERROR_OK;
2564 }
2565 
2566 COMMAND_HANDLER(stm32l4_handle_otp_command)
2567 {
2568  if (CMD_ARGC != 2)
2570 
2571  struct flash_bank *bank;
2572  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2573  if (retval != ERROR_OK)
2574  return retval;
2575 
2576  if (!stm32l4_is_otp(bank)) {
2577  command_print(CMD, "the specified bank is not an OTP memory");
2578  return ERROR_FAIL;
2579  }
2580  if (strcmp(CMD_ARGV[1], "enable") == 0)
2581  stm32l4_otp_enable(bank, true);
2582  else if (strcmp(CMD_ARGV[1], "disable") == 0)
2583  stm32l4_otp_enable(bank, false);
2584  else if (strcmp(CMD_ARGV[1], "show") == 0)
2585  command_print(CMD, "OTP memory bank #%d is %s for write commands.",
2586  bank->bank_number, stm32l4_otp_is_enabled(bank) ? "enabled" : "disabled");
2587  else
2589 
2590  return ERROR_OK;
2591 }
2592 
2593 static const struct command_registration stm32l4_exec_command_handlers[] = {
2594  {
2595  .name = "lock",
2596  .handler = stm32l4_handle_lock_command,
2597  .mode = COMMAND_EXEC,
2598  .usage = "bank_id",
2599  .help = "Lock entire flash device.",
2600  },
2601  {
2602  .name = "unlock",
2603  .handler = stm32l4_handle_unlock_command,
2604  .mode = COMMAND_EXEC,
2605  .usage = "bank_id",
2606  .help = "Unlock entire protected flash device.",
2607  },
2608  {
2609  .name = "mass_erase",
2610  .handler = stm32l4_handle_mass_erase_command,
2611  .mode = COMMAND_EXEC,
2612  .usage = "bank_id",
2613  .help = "Erase entire flash device.",
2614  },
2615  {
2616  .name = "option_read",
2617  .handler = stm32l4_handle_option_read_command,
2618  .mode = COMMAND_EXEC,
2619  .usage = "bank_id reg_offset",
2620  .help = "Read & Display device option bytes.",
2621  },
2622  {
2623  .name = "option_write",
2624  .handler = stm32l4_handle_option_write_command,
2625  .mode = COMMAND_EXEC,
2626  .usage = "bank_id reg_offset value [mask]",
2627  .help = "Write device option bit fields with provided value.",
2628  },
2629  {
2630  .name = "trustzone",
2631  .handler = stm32l4_handle_trustzone_command,
2632  .mode = COMMAND_EXEC,
2633  .usage = "<bank_id> [enable|disable]",
2634  .help = "Configure TrustZone security",
2635  },
2636  {
2637  .name = "wrp_info",
2638  .handler = stm32l4_handle_wrp_info_command,
2639  .mode = COMMAND_EXEC,
2640  .usage = "bank_id [bank1|bank2]",
2641  .help = "list the protected areas using WRP",
2642  },
2643  {
2644  .name = "option_load",
2645  .handler = stm32l4_handle_option_load_command,
2646  .mode = COMMAND_EXEC,
2647  .usage = "bank_id",
2648  .help = "Force re-load of device options (will cause device reset).",
2649  },
2650  {
2651  .name = "otp",
2652  .handler = stm32l4_handle_otp_command,
2653  .mode = COMMAND_EXEC,
2654  .usage = "<bank_id> <enable|disable|show>",
2655  .help = "OTP (One Time Programmable) memory write enable/disable",
2656  },
2658 };
2659 
2660 static const struct command_registration stm32l4_command_handlers[] = {
2661  {
2662  .name = "stm32l4x",
2663  .mode = COMMAND_ANY,
2664  .help = "stm32l4x flash command group",
2665  .usage = "",
2667  },
2669 };
2670 
2671 const struct flash_driver stm32l4x_flash = {
2672  .name = "stm32l4x",
2673  .commands = stm32l4_command_handlers,
2674  .flash_bank_command = stm32l4_flash_bank_command,
2675  .erase = stm32l4_erase,
2676  .protect = stm32l4_protect,
2677  .write = stm32l4_write,
2678  .read = default_flash_read,
2679  .probe = stm32l4_probe,
2680  .auto_probe = stm32l4_auto_probe,
2681  .erase_check = default_flash_blank_check,
2682  .protect_check = stm32l4_protect_check,
2683  .info = get_stm32l4_info,
2684  .free_driver_priv = default_flash_free_driver_priv,
2685 };
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
Definition: algorithm.c:29
void destroy_reg_param(struct reg_param *param)
Definition: algorithm.c:37
@ PARAM_OUT
Definition: algorithm.h:16
@ PARAM_IN_OUT
Definition: algorithm.h:17
@ ARM_MODE_THREAD
Definition: arm.h:94
This defines formats and data structures used to talk to ADIv5 entities.
static struct armv7m_common * target_to_armv7m_safe(struct target *target)
Definition: armv7m.h:274
#define ARMV7M_COMMON_MAGIC
Definition: armv7m.h:220
Support functions to access arbitrary bits in a byte array.
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
static int test_bit(unsigned int nr, const volatile unsigned long *addr)
test_bit - Determine whether a bit is set
Definition: bits.h:73
static void bitmap_zero(unsigned long *dst, unsigned int nbits)
bitmap_zero - Clears all the bits in memory
Definition: bits.h:36
static void set_bit(unsigned int nr, volatile unsigned long *addr)
set_bit - Set a bit in memory
Definition: bits.h:60
static void clear_bit(unsigned int nr, volatile unsigned long *addr)
clear_bit - Clear a bit in memory
Definition: bits.h:47
#define DECLARE_BITMAP(name, bits)
Definition: bits.h:29
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:420
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:443
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
Definition: command.h:118
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:402
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
#define COMMAND_PARSE_ENABLE(in, out)
parses an enable/disable command argument
Definition: command.h:533
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:442
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
#define ERROR_COMMAND_ARGUMENT_INVALID
Definition: command.h:404
@ COMMAND_ANY
Definition: command.h:42
@ COMMAND_EXEC
Definition: command.h:40
static enum cortex_m_impl_part cortex_m_get_impl_part(struct target *target)
Definition: cortex_m.h:319
@ CORTEX_M0P_PARTNO
Definition: cortex_m.h:54
#define FLASH_PG
Definition: em357.c:44
#define KEY2
Definition: em357.c:68
#define FLASH_PER
Definition: em357.c:45
#define FLASH_BSY
Definition: em357.c:55
#define FLASH_LOCK
Definition: em357.c:50
#define FLASH_STRT
Definition: em357.c:49
#define KEY1
Definition: em357.c:67
uint8_t bank
Definition: esirisc.c:135
int mask
Definition: esirisc.c:1741
#define ERROR_FLASH_OPER_UNSUPPORTED
Definition: flash/common.h:36
#define ERROR_FLASH_OPERATION_FAILED
Definition: flash/common.h:30
#define ERROR_FLASH_DST_OUT_OF_BANK
Definition: flash/common.h:31
struct flash_sector * alloc_block_array(uint32_t offset, uint32_t size, unsigned int num_blocks)
Allocate and fill an array of sectors or protection blocks.
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
void alive_sleep(uint64_t ms)
Definition: log.c:456
#define ERROR_NOT_IMPLEMENTED
Definition: log.h:174
#define LOG_WARNING(expr ...)
Definition: log.h:129
#define ERROR_FAIL
Definition: log.h:170
#define LOG_ERROR(expr ...)
Definition: log.h:132
#define LOG_INFO(expr ...)
Definition: log.h:126
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:164
#define FLASH_ERROR
Definition: msp432.h:72
struct rtt_control ctrl
Control block.
Definition: rtt/rtt.c:25
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
struct rtt_source source
Definition: rtt/rtt.c:23
#define FLASH_OBL_LAUNCH
Definition: stm32f1x.c:72
#define FLASH_WRPERR
Definition: stm32f2x.c:157
#define OPTKEY2
Definition: stm32f2x.c:178
#define FLASH_MER1
Definition: stm32f2x.c:142
#define OPTKEY1
Definition: stm32f2x.c:177
stm32l4_rdp
Definition: stm32l4x.c:169
@ RDP_LEVEL_1
Definition: stm32l4x.c:172
@ RDP_LEVEL_2
Definition: stm32l4x.c:173
@ RDP_LEVEL_0_5
Definition: stm32l4x.c:171
@ RDP_LEVEL_0
Definition: stm32l4x.c:170
static const struct stm32l4_rev stm32g05_g06xx_revs[]
Definition: stm32l4x.c:300
static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id, struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
Definition: stm32l4x.c:1131
static int stm32l4_protect_check(struct flash_bank *bank)
Definition: stm32l4x.c:1209
#define FLASH_ERASE_TIMEOUT
Definition: stm32l4x.c:131
static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, enum stm32l4_flash_reg_index reg_idx, int offset)
Definition: stm32l4x.c:1111
static const struct stm32l4_rev stm32l43_l44xx_revs[]
Definition: stm32l4x.c:287
static const struct stm32l4_rev stm32u53_u54xx_revs[]
Definition: stm32l4x.c:353
static const struct stm32l4_rev stm32u59_u5axx_revs[]
Definition: stm32l4x.c:362
#define F_QUAD_WORD_PROG
Definition: stm32l4x.c:148
static const struct command_registration stm32l4_exec_command_handlers[]
Definition: stm32l4x.c:2593
#define F_NONE
Definition: stm32l4x.c:136
static int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
Definition: stm32l4x.c:856
static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:176
#define F_USE_ALL_WRPXX
Definition: stm32l4x.c:141
stm32l4_flash_reg_index
Definition: stm32l4x.c:152
@ STM32_FLASH_SR_INDEX
Definition: stm32l4x.c:156
@ STM32_FLASH_CR_WLK_INDEX
Definition: stm32l4x.c:160
@ STM32_FLASH_ACR_INDEX
Definition: stm32l4x.c:153
@ STM32_FLASH_OPTR_INDEX
Definition: stm32l4x.c:161
@ STM32_FLASH_WRP1AR_INDEX
Definition: stm32l4x.c:162
@ STM32_FLASH_CR_INDEX
Definition: stm32l4x.c:157
@ STM32_FLASH_WRP2BR_INDEX
Definition: stm32l4x.c:165
@ STM32_FLASH_OPTKEYR_INDEX
Definition: stm32l4x.c:155
@ STM32_FLASH_WRP1BR_INDEX
Definition: stm32l4x.c:163
@ STM32_FLASH_KEYR_INDEX
Definition: stm32l4x.c:154
@ STM32_FLASH_WRP2AR_INDEX
Definition: stm32l4x.c:164
@ STM32_FLASH_REG_INDEX_NUM
Definition: stm32l4x.c:166
#define F_HAS_TZ
Definition: stm32l4x.c:143
static int stm32l4_perform_obl_launch(struct flash_bank *bank)
Definition: stm32l4x.c:1026
static const struct stm32l4_part_info stm32l4_parts[]
Definition: stm32l4x.c:386
static char * range_print_alloc(struct range *ranges, unsigned int ranges_count)
Definition: stm32l4x.c:748
static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
Definition: stm32l4x.c:1717
static const struct stm32l4_rev stm32g47_g48xx_revs[]
Definition: stm32l4x.c:332
static int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
Definition: stm32l4x.c:844
static bool stm32l4_otp_is_enabled(struct flash_bank *bank)
Definition: stm32l4x.c:796
#define F_HAS_L5_FLASH_REGS
Definition: stm32l4x.c:145
static const char * get_stm32l4_bank_type_str(struct flash_bank *bank)
Definition: stm32l4x.c:1780
static bool stm32l4_is_otp(struct flash_bank *bank)
Definition: stm32l4x.c:771
static int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
Definition: stm32l4x.c:950
static int range_print_one(struct range *range, char *str)
Definition: stm32l4x.c:740
static const struct stm32l4_rev stm32g03_g04xx_revs[]
Definition: stm32l4x.c:320
static const struct stm32l4_rev stm32c01xx_revs[]
Definition: stm32l4x.c:292
#define F_HAS_DUAL_BANK
Definition: stm32l4x.c:138
static const char * device_families
Definition: stm32l4x.c:281
stm32_bank_id
Definition: stm32l4x.c:265
@ STM32_BANK1
Definition: stm32l4x.c:266
@ STM32_BANK2
Definition: stm32l4x.c:267
@ STM32_ALL_BANKS
Definition: stm32l4x.c:268
static const struct stm32l4_rev stm32u57_u58xx_revs[]
Definition: stm32l4x.c:357
static const struct command_registration stm32l4_command_handlers[]
Definition: stm32l4x.c:2660
static const struct stm32l4_rev stm32l45_l46xx_revs[]
Definition: stm32l4x.c:312
static int stm32l4_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: stm32l4x.c:1233
static const struct stm32l4_rev stm32l4p_l4qxx_revs[]
Definition: stm32l4x.c:341
static const struct stm32l4_rev stm32l41_l42xx_revs[]
Definition: stm32l4x.c:316
static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
Definition: stm32l4x.c:777
static const struct stm32l4_rev stm32l47_l48xx_revs[]
Definition: stm32l4x.c:283
static const struct stm32l4_rev stm32l4r_l4sxx_revs[]
Definition: stm32l4x.c:336
static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
Definition: stm32l4x.c:1063
static const struct stm32l4_rev stm32l55_l56xx_revs[]
Definition: stm32l4x.c:345
static const struct stm32l4_rev stm32wb1xx_revs[]
Definition: stm32l4x.c:370
static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
Definition: stm32l4x.c:868
static const struct stm32l4_rev stm32wba5x_revs[]
Definition: stm32l4x.c:366
static int stm32l4_mass_erase(struct flash_bank *bank)
Definition: stm32l4x.c:2204
static const char * get_stm32l4_rev_str(struct flash_bank *bank)
Definition: stm32l4x.c:1766
static int get_stm32l4_info(struct flash_bank *bank, struct command_invocation *cmd)
Definition: stm32l4x.c:2186
COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
Definition: stm32l4x.c:2270
static const struct stm32l4_rev stm32_g07_g08xx_revs[]
Definition: stm32l4x.c:304
static const struct stm32l4_rev stm32g43_g44xx_revs[]
Definition: stm32l4x.c:328
static const struct stm32l4_rev stm32c03xx_revs[]
Definition: stm32l4x.c:296
static uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
Definition: stm32l4x.c:831
static const struct stm32l4_rev stm32wle_wl5xx_revs[]
Definition: stm32l4x.c:382
static int stm32l4_protect_same_bank(struct flash_bank *bank, enum stm32_bank_id bank_id, int set, unsigned int first, unsigned int last)
Definition: stm32l4x.c:1311
FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
Definition: stm32l4x.c:690
static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
set all FLASH_SECBB registers to the same value
Definition: stm32l4x.c:908
static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32l4x.c:1606
static const struct stm32l4_rev stm32g49_g4axx_revs[]
Definition: stm32l4x.c:349
const struct flash_driver stm32l4x_flash
Definition: stm32l4x.c:2671
static int stm32l4_probe(struct flash_bank *bank)
Definition: stm32l4x.c:1789
static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:214
static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32l4x.c:1562
static int stm32l4_read_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index, uint32_t *value)
Definition: stm32l4x.c:849
static int stm32l4_unlock_option_reg(struct flash_bank *bank)
Definition: stm32l4x.c:993
static const uint32_t stm32wl_cpu2_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:189
static int stm32l4_unlock_reg(struct flash_bank *bank)
Definition: stm32l4x.c:957
static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
Definition: stm32l4x.c:1196
static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
Definition: stm32l4x.c:802
static const struct stm32l4_rev stm32wb3xx_revs[]
Definition: stm32l4x.c:378
#define FLASH_WRITE_TIMEOUT
Definition: stm32l4x.c:132
static const struct stm32l4_rev stm32wb5xx_revs[]
Definition: stm32l4x.c:374
static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits, struct range *ranges, unsigned int *ranges_count)
Definition: stm32l4x.c:719
static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:201
static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32l4x.c:1437
static int stm32l4_write_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index, uint32_t value)
Definition: stm32l4x.c:861
static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
Definition: stm32l4x.c:1402
static uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index)
Definition: stm32l4x.c:837
static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
Definition: stm32l4x.c:1184
static const struct stm32l4_rev stm32l49_l4axx_revs[]
Definition: stm32l4x.c:308
static int stm32l4_auto_probe(struct flash_bank *bank)
Definition: stm32l4x.c:2157
static const struct stm32l4_rev stm32g0b_g0cxx_revs[]
Definition: stm32l4x.c:324
#define DEVID_STM32G03_G04XX
Definition: stm32l4x.h:98
#define DEVID_STM32L55_L56XX
Definition: stm32l4x.h:104
#define DBGMCU_IDCODE_G0
Definition: stm32l4x.h:80
#define DEVID_STM32G0B_G0CXX
Definition: stm32l4x.h:99
#define FLASH_L5_DB256
Definition: stm32l4x.h:68
#define FLASH_SECBB_SECURE
Definition: stm32l4x.h:76
#define DBGMCU_IDCODE_L5
Definition: stm32l4x.h:82
#define FLASH_G0_DUAL_BANK
Definition: stm32l4x.h:62
#define STM32_FLASH_S_BANK_BASE
Definition: stm32l4x.h:116
#define DEVID_STM32G49_G4AXX
Definition: stm32l4x.h:105
#define DEVID_STM32WBA5X
Definition: stm32l4x.h:108
#define DEVID_STM32WB1XX
Definition: stm32l4x.h:109
#define DEVID_STM32C03XX
Definition: stm32l4x.h:91
#define FLASH_OPTSTRT
Definition: stm32l4x.h:30
#define FLASH_SECBB2(X)
Definition: stm32l4x.h:74
#define DEVID_STM32U53_U54XX
Definition: stm32l4x.h:92
#define DEVID_STM32L4R_L4SXX
Definition: stm32l4x.h:102
#define UID64_IDS
Definition: stm32l4x.h:84
#define FLASH_L5_DBANK
Definition: stm32l4x.h:67
#define FLASH_L4_DUAL_BANK
Definition: stm32l4x.h:64
#define FLASH_PAGE_SHIFT
Definition: stm32l4x.h:25
#define DEVID_STM32G47_G48XX
Definition: stm32l4x.h:101
#define FLASH_U5_DUALBANK
Definition: stm32l4x.h:69
#define STM32_FLASH_BANK_BASE
Definition: stm32l4x.h:115
#define FLASH_G4_DUAL_BANK
Definition: stm32l4x.h:63
#define DEVID_STM32L47_L48XX
Definition: stm32l4x.h:88
#define DEVID_STM32G07_G08XX
Definition: stm32l4x.h:94
#define DEVID_STM32WB5XX
Definition: stm32l4x.h:110
#define DEVID_STM32U59_U5AXX
Definition: stm32l4x.h:106
#define DEVID_STM32L49_L4AXX
Definition: stm32l4x.h:95
#define DEVID_STM32L43_L44XX
Definition: stm32l4x.h:89
#define FLASH_RDP_MASK
Definition: stm32l4x.h:61
#define DEVID_STM32L41_L42XX
Definition: stm32l4x.h:97
#define DEVID_STM32WLE_WL5XX
Definition: stm32l4x.h:112
#define FLASH_L4R_DBANK
Definition: stm32l4x.h:65
#define DEVID_STM32G05_G06XX
Definition: stm32l4x.h:93
#define LDR_STACK_SIZE
Definition: stm32l4x.h:122
#define FLASH_OPTLOCK
Definition: stm32l4x.h:34
#define DEVID_STM32WB3XX
Definition: stm32l4x.h:111
#define FLASH_TZEN
Definition: stm32l4x.h:70
#define DEVID_STM32G43_G44XX
Definition: stm32l4x.h:100
#define UID64_IDS_STM32WL
Definition: stm32l4x.h:85
#define FLASH_BSY2
Definition: stm32l4x.h:39
#define FLASH_SECBB_NON_SECURE
Definition: stm32l4x.h:77
#define STM32L5_REGS_SEC_OFFSET
Definition: stm32l4x.h:119
#define FLASH_SECBB1(X)
Definition: stm32l4x.h:73
#define FLASH_BKER_G0
Definition: stm32l4x.h:27
#define DEVID_STM32U57_U58XX
Definition: stm32l4x.h:107
#define DBGMCU_IDCODE_L4_G4
Definition: stm32l4x.h:81
#define DEVID_STM32L4P_L4QXX
Definition: stm32l4x.h:103
#define FLASH_LRR_DB1M
Definition: stm32l4x.h:66
#define FLASH_BKER
Definition: stm32l4x.h:26
#define DEVID_STM32C01XX
Definition: stm32l4x.h:90
#define DEVID_STM32L45_L46XX
Definition: stm32l4x.h:96
#define FLASH_MER2
Definition: stm32l4x.h:28
uint64_t ap_num
ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coheren...
Definition: arm_adi_v5.h:261
unsigned int common_magic
Definition: armv7m.h:295
enum arm_mode core_mode
Definition: armv7m.h:297
struct adiv5_ap * debug_ap
Definition: armv7m.h:230
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
const char * name
Definition: command.h:235
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
Describes the geometry and status of a single flash sector within a flash bank.
Definition: nor/core.h:28
uint32_t offset
Bus offset from start of the flash chip (in bytes).
Definition: nor/core.h:30
uint32_t size
Number of bytes in this flash sector.
Definition: nor/core.h:32
unsigned int start
Definition: stm32l4x.c:715
unsigned int end
Definition: stm32l4x.c:716
unsigned int bank1_sectors
Definition: stm32l4x.c:248
uint32_t wrpxxr_mask
Definition: stm32l4x.c:255
uint32_t user_bank_size
Definition: stm32l4x.c:251
const uint32_t * flash_regs
Definition: stm32l4x.c:258
uint32_t flash_regs_base
Definition: stm32l4x.c:257
enum stm32l4_rdp rdp
Definition: stm32l4x.c:260
uint32_t idcode
Definition: stm32l4x.c:247
uint32_t cr_bker_mask
Definition: stm32l4x.c:253
uint32_t data_width
Definition: stm32l4x.c:252
const struct stm32l4_part_info * part_info
Definition: stm32l4x.c:256
uint32_t sr_bsy_mask
Definition: stm32l4x.c:254
const uint32_t otp_size
Definition: stm32l4x.c:242
const struct stm32l4_rev * revs
Definition: stm32l4x.c:235
const char * device_str
Definition: stm32l4x.c:234
const uint32_t fsize_addr
Definition: stm32l4x.c:240
const uint32_t flash_regs_base
Definition: stm32l4x.c:239
const uint32_t flags
Definition: stm32l4x.c:238
const uint32_t otp_base
Definition: stm32l4x.c:241
const size_t num_revs
Definition: stm32l4x.c:236
const uint16_t max_flash_size_kb
Definition: stm32l4x.c:237
const char * str
Definition: stm32l4x.c:229
const uint16_t rev
Definition: stm32l4x.c:228
uint8_t stack[LDR_STACK_SIZE]
Definition: stm32l4x.h:131
bool used
Definition: stm32l4x.c:274
enum stm32l4_flash_reg_index reg_idx
Definition: stm32l4x.c:272
int offset
Definition: stm32l4x.c:277
uint32_t value
Definition: stm32l4x.c:273
Definition: target.h:116
enum target_state state
Definition: target.h:157
Definition: psoc6.c:83
target_addr_t address
Definition: target.h:86
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
Definition: target.c:352
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2342
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1265
uint32_t target_get_working_area_avail(struct target *target)
Definition: target.c:2164
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2060
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2641
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2118
int target_alloc_working_area_try(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:1966
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
Definition: target.c:2574
int target_run_flash_async_algorithm(struct target *target, const uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
Streams data to a circular buffer on target intended for consumption by code running asynchronously o...
Definition: target.c:930
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2550
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:790
static bool target_was_examined(const struct target *target)
Definition: target.h:436
#define ERROR_TARGET_INVALID
Definition: target.h:787
@ TARGET_HALTED
Definition: target.h:56
#define ERROR_TARGET_NOT_EXAMINED
Definition: target.h:797
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:794
#define ERROR_TARGET_FAILURE
Definition: target.h:791
#define TARGET_ADDR_FMT
Definition: types.h:342
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57
#define NULL
Definition: usb.h:16
uint8_t status[4]
Definition: vdebug.c:17
uint8_t cmd
Definition: vdebug.c:1
uint8_t offset[4]
Definition: vdebug.c:9
uint8_t count[4]
Definition: vdebug.c:22