OpenOCD
stm32l4x.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2015 by Uwe Bonnes *
5  * bon@elektron.ikp.physik.tu-darmstadt.de *
6  * *
7  * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
8  * tarek.bouchkati@gmail.com *
9  ***************************************************************************/
10 
11 #ifdef HAVE_CONFIG_H
12 #include "config.h"
13 #endif
14 
15 #include "imp.h"
16 #include <helper/align.h>
17 #include <helper/binarybuffer.h>
18 #include <helper/bits.h>
19 #include <target/algorithm.h>
20 #include <target/arm_adi_v5.h>
21 #include <target/cortex_m.h>
22 #include "stm32l4x.h"
23 
24 /* STM32L4xxx series for reference.
25  *
26  * RM0351 (STM32L4x5/STM32L4x6)
27  * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
28  *
29  * RM0394 (STM32L43x/44x/45x/46x)
30  * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
31  *
32  * RM0432 (STM32L4R/4Sxx)
33  * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
34  *
35  * STM32L476RG Datasheet (for erase timing)
36  * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
37  *
38  * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
39  * an option byte is available to map all sectors to the first bank.
40  * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
41  * handlers do!
42  *
43  * RM0394 devices have a single bank only.
44  *
45  * RM0432 devices have single and dual bank operating modes.
46  * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
47  * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
48  * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
49  *
50  * Bank mode is controlled by two different bits in option bytes register.
51  * - for STM32L4R/Sxx
52  * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
53  * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
54  * - for STM32L4P5/Q5x
55  * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
56  * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
57  */
58 
59 /* STM32WBxxx series for reference.
60  *
61  * RM0493 (STM32WBA52x)
62  * http://www.st.com/resource/en/reference_manual/dm00821869.pdf
63  *
64  * RM0434 (STM32WB55/WB35x)
65  * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
66  *
67  * RM0471 (STM32WB50/WB30x)
68  * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
69  *
70  * RM0473 (STM32WB15x)
71  * http://www.st.com/resource/en/reference_manual/dm00649196.pdf
72  *
73  * RM0478 (STM32WB10x)
74  * http://www.st.com/resource/en/reference_manual/dm00689203.pdf
75  */
76 
77 /* STM32WLxxx series for reference.
78  *
79  * RM0461 (STM32WLEx)
80  * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
81  *
82  * RM0453 (STM32WL5x)
83  * http://www.st.com/resource/en/reference_manual/dm00451556.pdf
84  */
85 
86 /* STM32C0xxx series for reference.
87  *
88  * RM0490 (STM32C0x1)
89  * http://www.st.com/resource/en/reference_manual/dm00781702.pdf
90  */
91 
92 /* STM32G0xxx series for reference.
93  *
94  * RM0444 (STM32G0x1)
95  * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
96  *
97  * RM0454 (STM32G0x0)
98  * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
99  */
100 
101 /* STM32G4xxx series for reference.
102  *
103  * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
104  * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
105  *
106  * Cat. 2 devices have single bank only, page size is 2kByte.
107  *
108  * Cat. 3 devices have single and dual bank operating modes,
109  * Page size is 2kByte (dual mode) or 4kByte (single mode).
110  *
111  * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
112  * Both banks are treated as a single OpenOCD bank.
113  *
114  * Cat. 4 devices have single bank only, page size is 2kByte.
115  */
116 
117 /* STM32L5xxx series for reference.
118  *
119  * RM0428 (STM32L552xx/STM32L562xx)
120  * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
121  */
122 
123 /* STM32U0xxx series for reference.
124  *
125  * RM0503 (STM32U0xx)
126  * https://www.st.com/resource/en/reference_manual/rm0503-stm32u0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
127  */
128 
129 /* STM32U5xxx series for reference.
130  *
131  * RM0456 (STM32U5xx)
132  * http://www.st.com/resource/en/reference_manual/dm00477635.pdf
133  */
134 
135 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
136 
137 #define FLASH_ERASE_TIMEOUT 250
138 #define FLASH_WRITE_TIMEOUT 50
139 
140 
141 /* relevant STM32L4 flags ****************************************************/
142 #define F_NONE 0
143 /* this flag indicates if the device flash is with dual bank architecture */
144 #define F_HAS_DUAL_BANK BIT(0)
145 /* this flags is used for dual bank devices only, it indicates if the
146  * 4 WRPxx are usable if the device is configured in single-bank mode */
147 #define F_USE_ALL_WRPXX BIT(1)
148 /* this flag indicates if the device embeds a TrustZone security feature */
149 #define F_HAS_TZ BIT(2)
150 /* this flag indicates if the device has the same flash registers as STM32L5 */
151 #define F_HAS_L5_FLASH_REGS BIT(3)
152 /* this flag indicates that programming should be done in quad-word
153  * the default programming word size is double-word */
154 #define F_QUAD_WORD_PROG BIT(4)
155 /* end of STM32L4 flags ******************************************************/
156 
157 
164  /* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
165  * so it uses the C2CR for flash operations and CR for checking locks and locking */
166  STM32_FLASH_CR_WLK_INDEX, /* FLASH_CR_WITH_LOCK */
173 };
174 
176  RDP_LEVEL_0 = 0xAA,
177  RDP_LEVEL_0_5 = 0x55, /* for devices with TrustZone enabled */
178  RDP_LEVEL_1 = 0x00,
179  RDP_LEVEL_2 = 0xCC
180 };
181 
183  [STM32_FLASH_ACR_INDEX] = 0x000,
184  [STM32_FLASH_KEYR_INDEX] = 0x008,
185  [STM32_FLASH_OPTKEYR_INDEX] = 0x00C,
186  [STM32_FLASH_SR_INDEX] = 0x010,
187  [STM32_FLASH_CR_INDEX] = 0x014,
188  [STM32_FLASH_OPTR_INDEX] = 0x020,
189  [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
190  [STM32_FLASH_WRP1BR_INDEX] = 0x030,
191  [STM32_FLASH_WRP2AR_INDEX] = 0x04C,
192  [STM32_FLASH_WRP2BR_INDEX] = 0x050,
193 };
194 
196  [STM32_FLASH_ACR_INDEX] = 0x000,
197  [STM32_FLASH_KEYR_INDEX] = 0x008,
198  [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
199  [STM32_FLASH_SR_INDEX] = 0x060,
200  [STM32_FLASH_CR_INDEX] = 0x064,
201  [STM32_FLASH_CR_WLK_INDEX] = 0x014,
202  [STM32_FLASH_OPTR_INDEX] = 0x020,
203  [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
204  [STM32_FLASH_WRP1BR_INDEX] = 0x030,
205 };
206 
208  [STM32_FLASH_ACR_INDEX] = 0x000,
209  [STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */
210  [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
211  [STM32_FLASH_SR_INDEX] = 0x020, /* NSSR */
212  [STM32_FLASH_CR_INDEX] = 0x028, /* NSCR */
213  [STM32_FLASH_OPTR_INDEX] = 0x040,
214  [STM32_FLASH_WRP1AR_INDEX] = 0x058,
215  [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
216  [STM32_FLASH_WRP2AR_INDEX] = 0x068,
217  [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
218 };
219 
221  [STM32_FLASH_ACR_INDEX] = 0x000,
222  [STM32_FLASH_KEYR_INDEX] = 0x00C, /* SECKEYR */
223  [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
224  [STM32_FLASH_SR_INDEX] = 0x024, /* SECSR */
225  [STM32_FLASH_CR_INDEX] = 0x02C, /* SECCR */
226  [STM32_FLASH_OPTR_INDEX] = 0x040,
227  [STM32_FLASH_WRP1AR_INDEX] = 0x058,
228  [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
229  [STM32_FLASH_WRP2AR_INDEX] = 0x068,
230  [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
231 };
232 
233 struct stm32l4_rev {
234  const uint16_t rev;
235  const char *str;
236 };
237 
239  uint16_t id;
240  const char *device_str;
241  const struct stm32l4_rev *revs;
242  const size_t num_revs;
243  const uint16_t max_flash_size_kb;
244  const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
245  const uint32_t flash_regs_base;
246  const uint32_t fsize_addr;
247  const uint32_t otp_base;
248  const uint32_t otp_size;
249 };
250 
252  bool probed;
253  uint32_t idcode;
254  unsigned int bank1_sectors;
257  uint32_t user_bank_size;
258  uint32_t data_width;
259  uint32_t cr_bker_mask;
260  uint32_t sr_bsy_mask;
261  uint32_t wrpxxr_mask;
263  uint32_t flash_regs_base;
264  const uint32_t *flash_regs;
266  enum stm32l4_rdp rdp;
267  bool tzen;
268  uint32_t optr;
269 };
270 
275 };
276 
277 struct stm32l4_wrp {
279  uint32_t value;
280  bool used;
281  int first;
282  int last;
283  int offset;
284 };
285 
286 /* human readable list of families this drivers supports (sorted alphabetically) */
287 static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U0/U5/WB/WL";
288 
289 static const struct stm32l4_rev stm32l47_l48xx_revs[] = {
290  { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
291 };
292 
293 static const struct stm32l4_rev stm32l43_l44xx_revs[] = {
294  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
295 };
296 
297 
298 static const struct stm32l4_rev stm32c01xx_revs[] = {
299  { 0x1000, "A" }, { 0x1001, "Z" },
300 };
301 
302 static const struct stm32l4_rev stm32c03xx_revs[] = {
303  { 0x1000, "A" }, { 0x1001, "Z" },
304 };
305 
306 static const struct stm32l4_rev stm32c071xx_revs[] = {
307  { 0x1001, "Z" },
308 };
309 
310 static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
311  { 0x1000, "A" },
312 };
313 
314 static const struct stm32l4_rev stm32_g07_g08xx_revs[] = {
315  { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
316 };
317 
318 static const struct stm32l4_rev stm32l49_l4axx_revs[] = {
319  { 0x1000, "A" }, { 0x2000, "B" },
320 };
321 
322 static const struct stm32l4_rev stm32l45_l46xx_revs[] = {
323  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
324 };
325 
326 static const struct stm32l4_rev stm32l41_l42xx_revs[] = {
327  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
328 };
329 
330 static const struct stm32l4_rev stm32g03_g04xx_revs[] = {
331  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
332 };
333 
334 static const struct stm32l4_rev stm32g0b_g0cxx_revs[] = {
335  { 0x1000, "A" },
336 };
337 
338 static const struct stm32l4_rev stm32u0xx_revs[] = {
339  { 0x1000, "A" },
340 };
341 
342 static const struct stm32l4_rev stm32g43_g44xx_revs[] = {
343  { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
344 };
345 
346 static const struct stm32l4_rev stm32g47_g48xx_revs[] = {
347  { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
348 };
349 
350 static const struct stm32l4_rev stm32l4r_l4sxx_revs[] = {
351  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
352  { 0x101F, "V" },
353 };
354 
355 static const struct stm32l4_rev stm32l4p_l4qxx_revs[] = {
356  { 0x1001, "Z" },
357 };
358 
359 static const struct stm32l4_rev stm32l55_l56xx_revs[] = {
360  { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
361 };
362 
363 static const struct stm32l4_rev stm32g49_g4axx_revs[] = {
364  { 0x1000, "A" },
365 };
366 
367 static const struct stm32l4_rev stm32u53_u54xx_revs[] = {
368  { 0x1000, "A" }, { 0x1001, "Z" },
369 };
370 
371 static const struct stm32l4_rev stm32u57_u58xx_revs[] = {
372  { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
373  { 0x2001, "X" }, { 0x3000, "C" }, { 0x3001, "W" }, { 0x3007, "U" },
374 };
375 
376 static const struct stm32l4_rev stm32u59_u5axx_revs[] = {
377  { 0x3001, "X" }, { 0x3002, "W" },
378 };
379 
380 static const struct stm32l4_rev stm32u5f_u5gxx_revs[] = {
381  { 0x1000, "A" }, { 0x1001, "Z" },
382 };
383 
384 static const struct stm32l4_rev stm32wba5x_revs[] = {
385  { 0x1000, "A" },
386 };
387 
388 static const struct stm32l4_rev stm32wb1xx_revs[] = {
389  { 0x1000, "A" }, { 0x2000, "B" },
390 };
391 
392 static const struct stm32l4_rev stm32wb5xx_revs[] = {
393  { 0x2001, "2.1" },
394 };
395 
396 static const struct stm32l4_rev stm32wb3xx_revs[] = {
397  { 0x1000, "A" },
398 };
399 
400 static const struct stm32l4_rev stm32wle_wl5xx_revs[] = {
401  { 0x1000, "1.0" },
402 };
403 
404 static const struct stm32l4_part_info stm32l4_parts[] = {
405  {
407  .revs = stm32l47_l48xx_revs,
408  .num_revs = ARRAY_SIZE(stm32l47_l48xx_revs),
409  .device_str = "STM32L47/L48xx",
410  .max_flash_size_kb = 1024,
411  .flags = F_HAS_DUAL_BANK,
412  .flash_regs_base = 0x40022000,
413  .fsize_addr = 0x1FFF75E0,
414  .otp_base = 0x1FFF7000,
415  .otp_size = 1024,
416  },
417  {
418  .id = DEVID_STM32L43_L44XX,
419  .revs = stm32l43_l44xx_revs,
420  .num_revs = ARRAY_SIZE(stm32l43_l44xx_revs),
421  .device_str = "STM32L43/L44xx",
422  .max_flash_size_kb = 256,
423  .flags = F_NONE,
424  .flash_regs_base = 0x40022000,
425  .fsize_addr = 0x1FFF75E0,
426  .otp_base = 0x1FFF7000,
427  .otp_size = 1024,
428  },
429  {
430  .id = DEVID_STM32C01XX,
431  .revs = stm32c01xx_revs,
432  .num_revs = ARRAY_SIZE(stm32c01xx_revs),
433  .device_str = "STM32C01xx",
434  .max_flash_size_kb = 32,
435  .flags = F_NONE,
436  .flash_regs_base = 0x40022000,
437  .fsize_addr = 0x1FFF75A0,
438  .otp_base = 0x1FFF7000,
439  .otp_size = 1024,
440  },
441  {
442  .id = DEVID_STM32C03XX,
443  .revs = stm32c03xx_revs,
444  .num_revs = ARRAY_SIZE(stm32c03xx_revs),
445  .device_str = "STM32C03xx",
446  .max_flash_size_kb = 32,
447  .flags = F_NONE,
448  .flash_regs_base = 0x40022000,
449  .fsize_addr = 0x1FFF75A0,
450  .otp_base = 0x1FFF7000,
451  .otp_size = 1024,
452  },
453  {
454  .id = DEVID_STM32C071XX,
455  .revs = stm32c071xx_revs,
456  .num_revs = ARRAY_SIZE(stm32c071xx_revs),
457  .device_str = "STM32C071xx",
458  .max_flash_size_kb = 128,
459  .flags = F_NONE,
460  .flash_regs_base = 0x40022000,
461  .fsize_addr = 0x1FFF75A0,
462  .otp_base = 0x1FFF7000,
463  .otp_size = 1024,
464  },
465  {
466  .id = DEVID_STM32U53_U54XX,
467  .revs = stm32u53_u54xx_revs,
468  .num_revs = ARRAY_SIZE(stm32u53_u54xx_revs),
469  .device_str = "STM32U535/U545",
470  .max_flash_size_kb = 512,
472  .flash_regs_base = 0x40022000,
473  .fsize_addr = 0x0BFA07A0,
474  .otp_base = 0x0BFA0000,
475  .otp_size = 512,
476  },
477  {
478  .id = DEVID_STM32G05_G06XX,
479  .revs = stm32g05_g06xx_revs,
480  .num_revs = ARRAY_SIZE(stm32g05_g06xx_revs),
481  .device_str = "STM32G05/G06xx",
482  .max_flash_size_kb = 64,
483  .flags = F_NONE,
484  .flash_regs_base = 0x40022000,
485  .fsize_addr = 0x1FFF75E0,
486  .otp_base = 0x1FFF7000,
487  .otp_size = 1024,
488  },
489  {
490  .id = DEVID_STM32G07_G08XX,
491  .revs = stm32_g07_g08xx_revs,
492  .num_revs = ARRAY_SIZE(stm32_g07_g08xx_revs),
493  .device_str = "STM32G07/G08xx",
494  .max_flash_size_kb = 128,
495  .flags = F_NONE,
496  .flash_regs_base = 0x40022000,
497  .fsize_addr = 0x1FFF75E0,
498  .otp_base = 0x1FFF7000,
499  .otp_size = 1024,
500  },
501  {
502  .id = DEVID_STM32L49_L4AXX,
503  .revs = stm32l49_l4axx_revs,
504  .num_revs = ARRAY_SIZE(stm32l49_l4axx_revs),
505  .device_str = "STM32L49/L4Axx",
506  .max_flash_size_kb = 1024,
507  .flags = F_HAS_DUAL_BANK,
508  .flash_regs_base = 0x40022000,
509  .fsize_addr = 0x1FFF75E0,
510  .otp_base = 0x1FFF7000,
511  .otp_size = 1024,
512  },
513  {
514  .id = DEVID_STM32L45_L46XX,
515  .revs = stm32l45_l46xx_revs,
516  .num_revs = ARRAY_SIZE(stm32l45_l46xx_revs),
517  .device_str = "STM32L45/L46xx",
518  .max_flash_size_kb = 512,
519  .flags = F_NONE,
520  .flash_regs_base = 0x40022000,
521  .fsize_addr = 0x1FFF75E0,
522  .otp_base = 0x1FFF7000,
523  .otp_size = 1024,
524  },
525  {
526  .id = DEVID_STM32L41_L42XX,
527  .revs = stm32l41_l42xx_revs,
528  .num_revs = ARRAY_SIZE(stm32l41_l42xx_revs),
529  .device_str = "STM32L41/L42xx",
530  .max_flash_size_kb = 128,
531  .flags = F_NONE,
532  .flash_regs_base = 0x40022000,
533  .fsize_addr = 0x1FFF75E0,
534  .otp_base = 0x1FFF7000,
535  .otp_size = 1024,
536  },
537  {
538  .id = DEVID_STM32G03_G04XX,
539  .revs = stm32g03_g04xx_revs,
540  .num_revs = ARRAY_SIZE(stm32g03_g04xx_revs),
541  .device_str = "STM32G03x/G04xx",
542  .max_flash_size_kb = 64,
543  .flags = F_NONE,
544  .flash_regs_base = 0x40022000,
545  .fsize_addr = 0x1FFF75E0,
546  .otp_base = 0x1FFF7000,
547  .otp_size = 1024,
548  },
549  {
550  .id = DEVID_STM32G0B_G0CXX,
551  .revs = stm32g0b_g0cxx_revs,
552  .num_revs = ARRAY_SIZE(stm32g0b_g0cxx_revs),
553  .device_str = "STM32G0B/G0Cx",
554  .max_flash_size_kb = 512,
555  .flags = F_HAS_DUAL_BANK,
556  .flash_regs_base = 0x40022000,
557  .fsize_addr = 0x1FFF75E0,
558  .otp_base = 0x1FFF7000,
559  .otp_size = 1024,
560  },
561  {
562  .id = DEVID_STM32G43_G44XX,
563  .revs = stm32g43_g44xx_revs,
564  .num_revs = ARRAY_SIZE(stm32g43_g44xx_revs),
565  .device_str = "STM32G43/G44xx",
566  .max_flash_size_kb = 128,
567  .flags = F_NONE,
568  .flash_regs_base = 0x40022000,
569  .fsize_addr = 0x1FFF75E0,
570  .otp_base = 0x1FFF7000,
571  .otp_size = 1024,
572  },
573  {
574  .id = DEVID_STM32G47_G48XX,
575  .revs = stm32g47_g48xx_revs,
576  .num_revs = ARRAY_SIZE(stm32g47_g48xx_revs),
577  .device_str = "STM32G47/G48xx",
578  .max_flash_size_kb = 512,
579  .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
580  .flash_regs_base = 0x40022000,
581  .fsize_addr = 0x1FFF75E0,
582  .otp_base = 0x1FFF7000,
583  .otp_size = 1024,
584  },
585  {
586  .id = DEVID_STM32L4R_L4SXX,
587  .revs = stm32l4r_l4sxx_revs,
588  .num_revs = ARRAY_SIZE(stm32l4r_l4sxx_revs),
589  .device_str = "STM32L4R/L4Sxx",
590  .max_flash_size_kb = 2048,
591  .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
592  .flash_regs_base = 0x40022000,
593  .fsize_addr = 0x1FFF75E0,
594  .otp_base = 0x1FFF7000,
595  .otp_size = 1024,
596  },
597  {
598  .id = DEVID_STM32L4P_L4QXX,
599  .revs = stm32l4p_l4qxx_revs,
600  .num_revs = ARRAY_SIZE(stm32l4p_l4qxx_revs),
601  .device_str = "STM32L4P/L4Qxx",
602  .max_flash_size_kb = 1024,
603  .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
604  .flash_regs_base = 0x40022000,
605  .fsize_addr = 0x1FFF75E0,
606  .otp_base = 0x1FFF7000,
607  .otp_size = 1024,
608  },
609  {
610  .id = DEVID_STM32L55_L56XX,
611  .revs = stm32l55_l56xx_revs,
612  .num_revs = ARRAY_SIZE(stm32l55_l56xx_revs),
613  .device_str = "STM32L55/L56xx",
614  .max_flash_size_kb = 512,
616  .flash_regs_base = 0x40022000,
617  .fsize_addr = 0x0BFA05E0,
618  .otp_base = 0x0BFA0000,
619  .otp_size = 512,
620  },
621  {
622  .id = DEVID_STM32G49_G4AXX,
623  .revs = stm32g49_g4axx_revs,
624  .num_revs = ARRAY_SIZE(stm32g49_g4axx_revs),
625  .device_str = "STM32G49/G4Axx",
626  .max_flash_size_kb = 512,
627  .flags = F_NONE,
628  .flash_regs_base = 0x40022000,
629  .fsize_addr = 0x1FFF75E0,
630  .otp_base = 0x1FFF7000,
631  .otp_size = 1024,
632  },
633  {
634  .id = DEVID_STM32U031XX,
635  .revs = stm32u0xx_revs,
636  .num_revs = ARRAY_SIZE(stm32u0xx_revs),
637  .device_str = "STM32U031xx",
638  .max_flash_size_kb = 64,
639  .flags = F_NONE,
640  .flash_regs_base = 0x40022000,
641  .fsize_addr = 0x1FFF3EA0,
642  .otp_base = 0x1FFF6800,
643  .otp_size = 1024,
644  },
645  {
647  .revs = stm32u0xx_revs,
648  .num_revs = ARRAY_SIZE(stm32u0xx_revs),
649  .device_str = "STM32U073/U083xx",
650  .max_flash_size_kb = 256,
651  .flags = F_NONE,
652  .flash_regs_base = 0x40022000,
653  .fsize_addr = 0x1FFF6EA0,
654  .otp_base = 0x1FFF6800,
655  .otp_size = 1024,
656  },
657  {
658  .id = DEVID_STM32U59_U5AXX,
659  .revs = stm32u59_u5axx_revs,
660  .num_revs = ARRAY_SIZE(stm32u59_u5axx_revs),
661  .device_str = "STM32U59/U5Axx",
662  .max_flash_size_kb = 4096,
664  .flash_regs_base = 0x40022000,
665  .fsize_addr = 0x0BFA07A0,
666  .otp_base = 0x0BFA0000,
667  .otp_size = 512,
668  },
669  {
670  .id = DEVID_STM32U57_U58XX,
671  .revs = stm32u57_u58xx_revs,
672  .num_revs = ARRAY_SIZE(stm32u57_u58xx_revs),
673  .device_str = "STM32U57/U58xx",
674  .max_flash_size_kb = 2048,
676  .flash_regs_base = 0x40022000,
677  .fsize_addr = 0x0BFA07A0,
678  .otp_base = 0x0BFA0000,
679  .otp_size = 512,
680  },
681  {
682  .id = DEVID_STM32U5F_U5GXX,
683  .revs = stm32u5f_u5gxx_revs,
684  .num_revs = ARRAY_SIZE(stm32u5f_u5gxx_revs),
685  .device_str = "STM32U5F/U5Gxx",
686  .max_flash_size_kb = 4096,
688  .flash_regs_base = 0x40022000,
689  .fsize_addr = 0x0BFA07A0,
690  .otp_base = 0x0BFA0000,
691  .otp_size = 512,
692  },
693  {
694  .id = DEVID_STM32WBA5X,
695  .revs = stm32wba5x_revs,
696  .num_revs = ARRAY_SIZE(stm32wba5x_revs),
697  .device_str = "STM32WBA5x",
698  .max_flash_size_kb = 1024,
700  .flash_regs_base = 0x40022000,
701  .fsize_addr = 0x0FF907A0,
702  .otp_base = 0x0FF90000,
703  .otp_size = 512,
704  },
705  {
706  .id = DEVID_STM32WB1XX,
707  .revs = stm32wb1xx_revs,
708  .num_revs = ARRAY_SIZE(stm32wb1xx_revs),
709  .device_str = "STM32WB1x",
710  .max_flash_size_kb = 320,
711  .flags = F_NONE,
712  .flash_regs_base = 0x58004000,
713  .fsize_addr = 0x1FFF75E0,
714  .otp_base = 0x1FFF7000,
715  .otp_size = 1024,
716  },
717  {
718  .id = DEVID_STM32WB5XX,
719  .revs = stm32wb5xx_revs,
720  .num_revs = ARRAY_SIZE(stm32wb5xx_revs),
721  .device_str = "STM32WB5x",
722  .max_flash_size_kb = 1024,
723  .flags = F_NONE,
724  .flash_regs_base = 0x58004000,
725  .fsize_addr = 0x1FFF75E0,
726  .otp_base = 0x1FFF7000,
727  .otp_size = 1024,
728  },
729  {
730  .id = DEVID_STM32WB3XX,
731  .revs = stm32wb3xx_revs,
732  .num_revs = ARRAY_SIZE(stm32wb3xx_revs),
733  .device_str = "STM32WB3x",
734  .max_flash_size_kb = 512,
735  .flags = F_NONE,
736  .flash_regs_base = 0x58004000,
737  .fsize_addr = 0x1FFF75E0,
738  .otp_base = 0x1FFF7000,
739  .otp_size = 1024,
740  },
741  {
742  .id = DEVID_STM32WLE_WL5XX,
743  .revs = stm32wle_wl5xx_revs,
744  .num_revs = ARRAY_SIZE(stm32wle_wl5xx_revs),
745  .device_str = "STM32WLE/WL5x",
746  .max_flash_size_kb = 256,
747  .flags = F_NONE,
748  .flash_regs_base = 0x58004000,
749  .fsize_addr = 0x1FFF75E0,
750  .otp_base = 0x1FFF7000,
751  .otp_size = 1024,
752  },
753 };
754 
755 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
756 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
757 {
758  struct stm32l4_flash_bank *stm32l4_info;
759 
760  if (CMD_ARGC < 6)
762 
763  /* fix-up bank base address: 0 is used for normal flash memory */
764  if (bank->base == 0)
765  bank->base = STM32_FLASH_BANK_BASE;
766 
767  stm32l4_info = calloc(1, sizeof(struct stm32l4_flash_bank));
768  if (!stm32l4_info)
769  return ERROR_FAIL; /* Checkme: What better error to use?*/
770  bank->driver_priv = stm32l4_info;
771 
772  stm32l4_info->probed = false;
773  stm32l4_info->otp_enabled = false;
774  stm32l4_info->user_bank_size = bank->size;
775 
776  return ERROR_OK;
777 }
778 
779 /* bitmap helper extension */
780 struct range {
781  unsigned int start;
782  unsigned int end;
783 };
784 
785 static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits,
786  struct range *ranges, unsigned int *ranges_count)
787 {
788  *ranges_count = 0;
789  bool last_bit = 0, cur_bit;
790  for (unsigned int i = 0; i < nbits; i++) {
791  cur_bit = test_bit(i, bitmap);
792 
793  if (cur_bit && !last_bit) {
794  (*ranges_count)++;
795  ranges[*ranges_count - 1].start = i;
796  ranges[*ranges_count - 1].end = i;
797  } else if (cur_bit && last_bit) {
798  /* update (increment) the end this range */
799  ranges[*ranges_count - 1].end = i;
800  }
801 
802  last_bit = cur_bit;
803  }
804 }
805 
806 static inline int range_print_one(struct range *range, char *str)
807 {
808  if (range->start == range->end)
809  return sprintf(str, "[%d]", range->start);
810 
811  return sprintf(str, "[%d,%d]", range->start, range->end);
812 }
813 
814 static char *range_print_alloc(struct range *ranges, unsigned int ranges_count)
815 {
816  /* each range will be printed like the following: [start,end]
817  * start and end, both are unsigned int, an unsigned int takes 10 characters max
818  * plus 3 characters for '[', ',' and ']'
819  * thus means each range can take maximum 23 character
820  * after each range we add a ' ' as separator and finally we need the '\0'
821  * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
822  char *str = calloc(1, ranges_count * (24 * sizeof(char)) + 1);
823  char *ptr = str;
824 
825  for (unsigned int i = 0; i < ranges_count; i++) {
826  ptr += range_print_one(&(ranges[i]), ptr);
827 
828  if (i < ranges_count - 1)
829  *(ptr++) = ' ';
830  }
831 
832  return str;
833 }
834 
835 /* end of bitmap helper extension */
836 
837 static inline bool stm32l4_is_otp(struct flash_bank *bank)
838 {
839  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
840  return bank->base == stm32l4_info->part_info->otp_base;
841 }
842 
843 static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
844 {
845  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
846 
847  if (!stm32l4_is_otp(bank))
848  return ERROR_FAIL;
849 
850  char *op_str = enable ? "enabled" : "disabled";
851 
852  LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
853  bank->bank_number,
854  stm32l4_info->otp_enabled == enable ? "already " : "",
855  op_str);
856 
857  stm32l4_info->otp_enabled = enable;
858 
859  return ERROR_OK;
860 }
861 
862 static inline bool stm32l4_otp_is_enabled(struct flash_bank *bank)
863 {
864  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
865  return stm32l4_info->otp_enabled;
866 }
867 
869 {
870  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
871 
872  bool tzen = false;
873 
874  if (stm32l4_info->part_info->flags & F_HAS_TZ)
875  tzen = (stm32l4_info->optr & FLASH_TZEN) != 0;
876 
877  uint32_t rdp = stm32l4_info->optr & FLASH_RDP_MASK;
878 
879  /* for devices without TrustZone:
880  * RDP level 0 and 2 values are to 0xAA and 0xCC
881  * Any other value corresponds to RDP level 1
882  * for devices with TrusZone:
883  * RDP level 0 and 2 values are 0xAA and 0xCC
884  * RDP level 0.5 value is 0x55 only if TZEN = 1
885  * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
886  */
887 
888  if (rdp != RDP_LEVEL_0 && rdp != RDP_LEVEL_2) {
889  if (!tzen || (tzen && rdp != RDP_LEVEL_0_5))
890  rdp = RDP_LEVEL_1;
891  }
892 
893  stm32l4_info->tzen = tzen;
894  stm32l4_info->rdp = rdp;
895 }
896 
897 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
898 {
899  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
900  return stm32l4_info->flash_regs_base + reg_offset;
901 }
902 
903 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
904  enum stm32l4_flash_reg_index reg_index)
905 {
906  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
907  return stm32l4_get_flash_reg(bank, stm32l4_info->flash_regs[reg_index]);
908 }
909 
910 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
911 {
912  return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
913 }
914 
916  enum stm32l4_flash_reg_index reg_index, uint32_t *value)
917 {
918  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
919  return stm32l4_read_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
920 }
921 
922 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
923 {
924  return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
925 }
926 
928  enum stm32l4_flash_reg_index reg_index, uint32_t value)
929 {
930  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
931  return stm32l4_write_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
932 }
933 
935 {
936  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
937  uint32_t status;
938  int retval = ERROR_OK;
939 
940  /* wait for busy to clear */
941  for (;;) {
943  if (retval != ERROR_OK)
944  return retval;
945  LOG_DEBUG("status: 0x%" PRIx32 "", status);
946  if ((status & stm32l4_info->sr_bsy_mask) == 0)
947  break;
948  if (timeout-- <= 0) {
949  LOG_ERROR("timed out waiting for flash");
950  return ERROR_FAIL;
951  }
952  alive_sleep(1);
953  }
954 
955  if (status & FLASH_WRPERR) {
956  LOG_ERROR("stm32x device protected");
957  retval = ERROR_FAIL;
958  }
959 
960  /* Clear but report errors */
961  if (status & FLASH_ERROR) {
962  if (retval == ERROR_OK)
963  retval = ERROR_FAIL;
964  /* If this operation fails, we ignore it and report the original
965  * retval
966  */
968  }
969 
970  return retval;
971 }
972 
974 static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
975 {
976  /* This function should be used only with device with TrustZone, do just a security check */
977  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
978  assert(stm32l4_info->part_info->flags & F_HAS_TZ);
979 
980  /* based on RM0438 Rev6 for STM32L5x devices:
981  * to modify a page block-based security attribution, it is recommended to
982  * 1- check that no flash operation is ongoing on the related page
983  * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
984  * this step is not need in case of JTAG direct access
985  */
987  if (retval != ERROR_OK)
988  return retval;
989 
990  /* write SECBBxRy registers */
991  LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
992 
993  const uint8_t secbb_regs[] = {
994  FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
995  FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
996  };
997 
998 
999  unsigned int num_secbb_regs = ARRAY_SIZE(secbb_regs);
1000 
1001  /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
1002  * then consider only the first half of secbb_regs
1003  */
1004  if (!stm32l4_info->dual_bank_mode)
1005  num_secbb_regs /= 2;
1006 
1007  for (unsigned int i = 0; i < num_secbb_regs; i++) {
1008  retval = stm32l4_write_flash_reg(bank, secbb_regs[i], value);
1009  if (retval != ERROR_OK)
1010  return retval;
1011  }
1012 
1013  return ERROR_OK;
1014 }
1015 
1017 {
1018  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1019  return (stm32l4_info->flash_regs[STM32_FLASH_CR_WLK_INDEX]) ?
1021 }
1022 
1024 {
1025  const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
1026  uint32_t ctrl;
1027 
1028  /* first check if not already unlocked
1029  * otherwise writing on STM32_FLASH_KEYR will fail
1030  */
1031  int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
1032  if (retval != ERROR_OK)
1033  return retval;
1034 
1035  if ((ctrl & FLASH_LOCK) == 0)
1036  return ERROR_OK;
1037 
1038  /* unlock flash registers */
1040  if (retval != ERROR_OK)
1041  return retval;
1042 
1044  if (retval != ERROR_OK)
1045  return retval;
1046 
1047  retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
1048  if (retval != ERROR_OK)
1049  return retval;
1050 
1051  if (ctrl & FLASH_LOCK) {
1052  LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
1053  return ERROR_TARGET_FAILURE;
1054  }
1055 
1056  return ERROR_OK;
1057 }
1058 
1060 {
1061  const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
1062  uint32_t ctrl;
1063 
1064  int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
1065  if (retval != ERROR_OK)
1066  return retval;
1067 
1068  if ((ctrl & FLASH_OPTLOCK) == 0)
1069  return ERROR_OK;
1070 
1071  /* unlock option registers */
1073  if (retval != ERROR_OK)
1074  return retval;
1075 
1077  if (retval != ERROR_OK)
1078  return retval;
1079 
1080  retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
1081  if (retval != ERROR_OK)
1082  return retval;
1083 
1084  if (ctrl & FLASH_OPTLOCK) {
1085  LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
1086  return ERROR_TARGET_FAILURE;
1087  }
1088 
1089  return ERROR_OK;
1090 }
1091 
1093 {
1094  int retval, retval2;
1095 
1096  retval = stm32l4_unlock_reg(bank);
1097  if (retval != ERROR_OK)
1098  goto err_lock;
1099 
1100  retval = stm32l4_unlock_option_reg(bank);
1101  if (retval != ERROR_OK)
1102  goto err_lock;
1103 
1104  /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
1105  * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
1106  * "Note: If the read protection is set while the debugger is still
1107  * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
1108  */
1109 
1110  /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
1111  /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
1112  * then just ignore the returned value */
1114 
1115  /* Need to re-probe after change */
1116  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1117  stm32l4_info->probed = false;
1118 
1119 err_lock:
1122 
1123  if (retval != ERROR_OK)
1124  return retval;
1125 
1126  return retval2;
1127 }
1128 
1129 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
1130  uint32_t value, uint32_t mask)
1131 {
1132  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1133  uint32_t optiondata;
1134  int retval, retval2;
1135 
1136  retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
1137  if (retval != ERROR_OK)
1138  return retval;
1139 
1140  /* for STM32L5 and similar devices, use always non-secure
1141  * registers for option bytes programming */
1142  const uint32_t *saved_flash_regs = stm32l4_info->flash_regs;
1143  if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
1144  stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1145 
1146  retval = stm32l4_unlock_reg(bank);
1147  if (retval != ERROR_OK)
1148  goto err_lock;
1149 
1150  retval = stm32l4_unlock_option_reg(bank);
1151  if (retval != ERROR_OK)
1152  goto err_lock;
1153 
1154  optiondata = (optiondata & ~mask) | (value & mask);
1155 
1156  retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
1157  if (retval != ERROR_OK)
1158  goto err_lock;
1159 
1161  if (retval != ERROR_OK)
1162  goto err_lock;
1163 
1165 
1166 err_lock:
1169  stm32l4_info->flash_regs = saved_flash_regs;
1170 
1171  if (retval != ERROR_OK)
1172  return retval;
1173 
1174  return retval2;
1175 }
1176 
1177 static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy,
1178  enum stm32l4_flash_reg_index reg_idx, int offset)
1179 {
1180  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1181  int ret;
1182 
1183  wrpxy->reg_idx = reg_idx;
1184  wrpxy->offset = offset;
1185 
1186  ret = stm32l4_read_flash_reg_by_index(bank, wrpxy->reg_idx , &wrpxy->value);
1187  if (ret != ERROR_OK)
1188  return ret;
1189 
1190  wrpxy->first = (wrpxy->value & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1191  wrpxy->last = ((wrpxy->value >> 16) & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1192  wrpxy->used = wrpxy->first <= wrpxy->last;
1193 
1194  return ERROR_OK;
1195 }
1196 
1197 static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id,
1198  struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
1199 {
1200  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1201  int ret;
1202 
1203  *n_wrp = 0;
1204 
1205  /* for single bank devices there is 2 WRP regions.
1206  * for dual bank devices there is 2 WRP regions per bank,
1207  * if configured as single bank only 2 WRP are usable
1208  * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
1209  * note: this should be revised, if a device will have the SWAP banks option
1210  */
1211 
1212  int wrp2y_sectors_offset = -1; /* -1 : unused */
1213 
1214  /* if bank_id is BANK1 or ALL_BANKS */
1215  if (dev_bank_id != STM32_BANK2) {
1216  /* get FLASH_WRP1AR */
1217  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1AR_INDEX, 0);
1218  if (ret != ERROR_OK)
1219  return ret;
1220 
1221  /* get WRP1BR */
1222  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1BR_INDEX, 0);
1223  if (ret != ERROR_OK)
1224  return ret;
1225 
1226  /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
1227  if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode)
1228  wrp2y_sectors_offset = 0;
1229  }
1230 
1231  /* if bank_id is BANK2 or ALL_BANKS */
1232  if (dev_bank_id != STM32_BANK1 && stm32l4_info->dual_bank_mode)
1233  wrp2y_sectors_offset = stm32l4_info->bank1_sectors;
1234 
1235  if (wrp2y_sectors_offset >= 0) {
1236  /* get WRP2AR */
1237  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2AR_INDEX, wrp2y_sectors_offset);
1238  if (ret != ERROR_OK)
1239  return ret;
1240 
1241  /* get WRP2BR */
1242  ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2BR_INDEX, wrp2y_sectors_offset);
1243  if (ret != ERROR_OK)
1244  return ret;
1245  }
1246 
1247  return ERROR_OK;
1248 }
1249 
1250 static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
1251 {
1252  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1253 
1254  int wrp_start = wrpxy->first - wrpxy->offset;
1255  int wrp_end = wrpxy->last - wrpxy->offset;
1256 
1257  uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16);
1258 
1259  return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff);
1260 }
1261 
1262 static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
1263 {
1264  int ret;
1265 
1266  for (unsigned int i = 0; i < n_wrp; i++) {
1267  ret = stm32l4_write_one_wrpxy(bank, &wrpxy[i]);
1268  if (ret != ERROR_OK)
1269  return ret;
1270  }
1271 
1272  return ERROR_OK;
1273 }
1274 
1276 {
1277  unsigned int n_wrp;
1278  struct stm32l4_wrp wrpxy[4];
1279 
1280  int ret = stm32l4_get_all_wrpxy(bank, STM32_ALL_BANKS, wrpxy, &n_wrp);
1281  if (ret != ERROR_OK)
1282  return ret;
1283 
1284  /* initialize all sectors as unprotected */
1285  for (unsigned int i = 0; i < bank->num_sectors; i++)
1286  bank->sectors[i].is_protected = 0;
1287 
1288  /* now check WRPxy and mark the protected sectors */
1289  for (unsigned int i = 0; i < n_wrp; i++) {
1290  if (wrpxy[i].used) {
1291  for (int s = wrpxy[i].first; s <= wrpxy[i].last; s++)
1292  bank->sectors[s].is_protected = 1;
1293  }
1294  }
1295 
1296  return ERROR_OK;
1297 }
1298 
1299 static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
1300  unsigned int last)
1301 {
1302  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1303  int retval, retval2;
1304 
1305  assert((first <= last) && (last < bank->num_sectors));
1306 
1307  if (stm32l4_is_otp(bank)) {
1308  LOG_ERROR("cannot erase OTP memory");
1310  }
1311 
1312  if (bank->target->state != TARGET_HALTED) {
1313  LOG_ERROR("Target not halted");
1314  return ERROR_TARGET_NOT_HALTED;
1315  }
1316 
1317  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1318  /* set all FLASH pages as secure */
1320  if (retval != ERROR_OK) {
1321  /* restore all FLASH pages as non-secure */
1322  stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1323  return retval;
1324  }
1325  }
1326 
1327  retval = stm32l4_unlock_reg(bank);
1328  if (retval != ERROR_OK)
1329  goto err_lock;
1330 
1331  /*
1332  Sector Erase
1333  To erase a sector, follow the procedure below:
1334  1. Check that no Flash memory operation is ongoing by
1335  checking the BSY bit in the FLASH_SR register
1336  2. Set the PER bit and select the page and bank
1337  you wish to erase in the FLASH_CR register
1338  3. Set the STRT bit in the FLASH_CR register
1339  4. Wait for the BSY bit to be cleared
1340  */
1341 
1342  for (unsigned int i = first; i <= last; i++) {
1343  uint32_t erase_flags;
1344  erase_flags = FLASH_PER | FLASH_STRT;
1345 
1346  if (i >= stm32l4_info->bank1_sectors) {
1347  uint8_t snb;
1348  snb = i - stm32l4_info->bank1_sectors;
1349  erase_flags |= snb << FLASH_PAGE_SHIFT | stm32l4_info->cr_bker_mask;
1350  } else
1351  erase_flags |= i << FLASH_PAGE_SHIFT;
1353  if (retval != ERROR_OK)
1354  break;
1355 
1357  if (retval != ERROR_OK)
1358  break;
1359  }
1360 
1361 err_lock:
1363 
1364  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1365  /* restore all FLASH pages as non-secure */
1367  if (retval3 != ERROR_OK)
1368  return retval3;
1369  }
1370 
1371  if (retval != ERROR_OK)
1372  return retval;
1373 
1374  return retval2;
1375 }
1376 
1377 static int stm32l4_protect_same_bank(struct flash_bank *bank, enum stm32_bank_id bank_id, int set,
1378  unsigned int first, unsigned int last)
1379 {
1380  unsigned int i;
1381 
1382  /* check if the desired protection is already configured */
1383  for (i = first; i <= last; i++) {
1384  if (bank->sectors[i].is_protected != set)
1385  break;
1386  else if (i == last) {
1387  LOG_INFO("The specified sectors are already %s", set ? "protected" : "unprotected");
1388  return ERROR_OK;
1389  }
1390  }
1391 
1392  /* all sectors from first to last (or part of them) could have different
1393  * protection other than the requested */
1394  unsigned int n_wrp;
1395  struct stm32l4_wrp wrpxy[4];
1396 
1397  int ret = stm32l4_get_all_wrpxy(bank, bank_id, wrpxy, &n_wrp);
1398  if (ret != ERROR_OK)
1399  return ret;
1400 
1401  /* use bitmap and range helpers to optimize the WRP usage */
1402  DECLARE_BITMAP(pages, bank->num_sectors);
1403  bitmap_zero(pages, bank->num_sectors);
1404 
1405  for (i = 0; i < n_wrp; i++) {
1406  if (wrpxy[i].used) {
1407  for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
1408  set_bit(p, pages);
1409  }
1410  }
1411 
1412  /* we have at most 'n_wrp' WRP areas
1413  * add one range if the user is trying to protect a fifth range */
1414  struct range ranges[n_wrp + 1];
1415  unsigned int ranges_count = 0;
1416 
1417  bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1418 
1419  /* pretty-print the currently protected ranges */
1420  if (ranges_count > 0) {
1421  char *ranges_str = range_print_alloc(ranges, ranges_count);
1422  LOG_DEBUG("current protected areas: %s", ranges_str);
1423  free(ranges_str);
1424  } else
1425  LOG_DEBUG("current protected areas: none");
1426 
1427  if (set) { /* flash protect */
1428  for (i = first; i <= last; i++)
1429  set_bit(i, pages);
1430  } else { /* flash unprotect */
1431  for (i = first; i <= last; i++)
1432  clear_bit(i, pages);
1433  }
1434 
1435  /* check the ranges_count after the user request */
1436  bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1437 
1438  /* pretty-print the requested areas for protection */
1439  if (ranges_count > 0) {
1440  char *ranges_str = range_print_alloc(ranges, ranges_count);
1441  LOG_DEBUG("requested areas for protection: %s", ranges_str);
1442  free(ranges_str);
1443  } else
1444  LOG_DEBUG("requested areas for protection: none");
1445 
1446  if (ranges_count > n_wrp) {
1447  LOG_ERROR("cannot set the requested protection "
1448  "(only %u write protection areas are available)" , n_wrp);
1449  return ERROR_FAIL;
1450  }
1451 
1452  /* re-init all WRPxy as disabled (first > last)*/
1453  for (i = 0; i < n_wrp; i++) {
1454  wrpxy[i].first = wrpxy[i].offset + 1;
1455  wrpxy[i].last = wrpxy[i].offset;
1456  }
1457 
1458  /* then configure WRPxy areas */
1459  for (i = 0; i < ranges_count; i++) {
1460  wrpxy[i].first = ranges[i].start;
1461  wrpxy[i].last = ranges[i].end;
1462  }
1463 
1464  /* finally write WRPxy registers */
1465  return stm32l4_write_all_wrpxy(bank, wrpxy, n_wrp);
1466 }
1467 
1468 static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
1469 {
1470  struct target *target = bank->target;
1471  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1472 
1473  if (stm32l4_is_otp(bank)) {
1474  LOG_ERROR("cannot protect/unprotect OTP memory");
1476  }
1477 
1478  if (target->state != TARGET_HALTED) {
1479  LOG_ERROR("Target not halted");
1480  return ERROR_TARGET_NOT_HALTED;
1481  }
1482 
1483  /* refresh the sectors' protection */
1484  int ret = stm32l4_protect_check(bank);
1485  if (ret != ERROR_OK)
1486  return ret;
1487 
1488  /* the requested sectors could be located into bank1 and/or bank2 */
1489  if (last < stm32l4_info->bank1_sectors) {
1490  return stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, last);
1491  } else if (first >= stm32l4_info->bank1_sectors) {
1492  return stm32l4_protect_same_bank(bank, STM32_BANK2, set, first, last);
1493  } else {
1494  ret = stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, stm32l4_info->bank1_sectors - 1);
1495  if (ret != ERROR_OK)
1496  return ret;
1497 
1498  return stm32l4_protect_same_bank(bank, STM32_BANK2, set, stm32l4_info->bank1_sectors, last);
1499  }
1500 }
1501 
1502 /* count is the size divided by stm32l4_info->data_width */
1503 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
1504  uint32_t offset, uint32_t count)
1505 {
1506  struct target *target = bank->target;
1507  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1508  struct working_area *write_algorithm;
1509  struct working_area *source;
1510  uint32_t address = bank->base + offset;
1511  struct reg_param reg_params[5];
1512  struct armv7m_algorithm armv7m_info;
1513  int retval = ERROR_OK;
1514 
1515  static const uint8_t stm32l4_flash_write_code[] = {
1516 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1517  };
1518 
1519  if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
1520  &write_algorithm) != ERROR_OK) {
1521  LOG_WARNING("no working area available, can't do block memory writes");
1523  }
1524 
1525  retval = target_write_buffer(target, write_algorithm->address,
1526  sizeof(stm32l4_flash_write_code),
1527  stm32l4_flash_write_code);
1528  if (retval != ERROR_OK) {
1529  target_free_working_area(target, write_algorithm);
1530  return retval;
1531  }
1532 
1533  /* data_width should be multiple of double-word */
1534  assert(stm32l4_info->data_width % 8 == 0);
1535  const size_t extra_size = sizeof(struct stm32l4_work_area);
1536  uint32_t buffer_size = target_get_working_area_avail(target) - extra_size;
1537  /* buffer_size should be multiple of stm32l4_info->data_width */
1538  buffer_size &= ~(stm32l4_info->data_width - 1);
1539 
1540  if (buffer_size < 256) {
1541  LOG_WARNING("large enough working area not available, can't do block memory writes");
1542  target_free_working_area(target, write_algorithm);
1544  } else if (buffer_size > 16384) {
1545  /* probably won't benefit from more than 16k ... */
1546  buffer_size = 16384;
1547  }
1548 
1550  LOG_ERROR("allocating working area failed");
1552  }
1553 
1554  armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1555  armv7m_info.core_mode = ARM_MODE_THREAD;
1556 
1557  /* contrib/loaders/flash/stm32/stm32l4x.c:write() arguments */
1558  init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* stm32l4_work_area ptr , status (out) */
1559  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
1560  init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
1561  init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (of stm32l4_info->data_width) */
1562 
1563  buf_set_u32(reg_params[0].value, 0, 32, source->address);
1564  buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
1565  buf_set_u32(reg_params[2].value, 0, 32, address);
1566  buf_set_u32(reg_params[3].value, 0, 32, count);
1567 
1568  /* write algo stack pointer */
1569  init_reg_param(&reg_params[4], "sp", 32, PARAM_OUT);
1570  buf_set_u32(reg_params[4].value, 0, 32, source->address +
1571  offsetof(struct stm32l4_work_area, stack) + LDR_STACK_SIZE);
1572 
1573  struct stm32l4_loader_params loader_extra_params;
1574 
1575  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_addr,
1577  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_cr_addr,
1579  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_word_size,
1580  stm32l4_info->data_width);
1581  target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_bsy_mask,
1582  stm32l4_info->sr_bsy_mask);
1583 
1584  retval = target_write_buffer(target, source->address, sizeof(loader_extra_params),
1585  (uint8_t *) &loader_extra_params);
1586  if (retval != ERROR_OK)
1587  return retval;
1588 
1590  0, NULL,
1591  ARRAY_SIZE(reg_params), reg_params,
1592  source->address + offsetof(struct stm32l4_work_area, fifo),
1593  source->size - offsetof(struct stm32l4_work_area, fifo),
1594  write_algorithm->address, 0,
1595  &armv7m_info);
1596 
1597  if (retval == ERROR_FLASH_OPERATION_FAILED) {
1598  LOG_ERROR("error executing stm32l4 flash write algorithm");
1599 
1600  uint32_t error;
1602  error &= FLASH_ERROR;
1603 
1604  if (error & FLASH_WRPERR)
1605  LOG_ERROR("flash memory write protected");
1606 
1607  if (error != 0) {
1608  LOG_ERROR("flash write failed = %08" PRIx32, error);
1609  /* Clear but report errors */
1611  retval = ERROR_FAIL;
1612  }
1613  }
1614 
1616  target_free_working_area(target, write_algorithm);
1617 
1618  destroy_reg_param(&reg_params[0]);
1619  destroy_reg_param(&reg_params[1]);
1620  destroy_reg_param(&reg_params[2]);
1621  destroy_reg_param(&reg_params[3]);
1622  destroy_reg_param(&reg_params[4]);
1623 
1624  return retval;
1625 }
1626 
1627 /* count is the size divided by stm32l4_info->data_width */
1628 static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer,
1629  uint32_t offset, uint32_t count)
1630 {
1631  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1632  struct target *target = bank->target;
1633  uint32_t address = bank->base + offset;
1634  int retval = ERROR_OK;
1635 
1636  /* wait for BSY bit */
1638  if (retval != ERROR_OK)
1639  return retval;
1640 
1641  /* set PG in FLASH_CR */
1643  if (retval != ERROR_OK)
1644  return retval;
1645 
1646 
1647  /* write directly to flash memory */
1648  const uint8_t *src = buffer;
1649  const uint32_t data_width_in_words = stm32l4_info->data_width / 4;
1650  while (count--) {
1651  retval = target_write_memory(target, address, 4, data_width_in_words, src);
1652  if (retval != ERROR_OK)
1653  return retval;
1654 
1655  /* wait for BSY bit */
1657  if (retval != ERROR_OK)
1658  return retval;
1659 
1660  src += stm32l4_info->data_width;
1661  address += stm32l4_info->data_width;
1662  }
1663 
1664  /* reset PG in FLASH_CR */
1666  if (retval != ERROR_OK)
1667  return retval;
1668 
1669  return retval;
1670 }
1671 
1672 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
1673  uint32_t offset, uint32_t count)
1674 {
1675  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1676  int retval = ERROR_OK, retval2;
1677 
1679  LOG_ERROR("OTP memory is disabled for write commands");
1680  return ERROR_FAIL;
1681  }
1682 
1683  if (bank->target->state != TARGET_HALTED) {
1684  LOG_ERROR("Target not halted");
1685  return ERROR_TARGET_NOT_HALTED;
1686  }
1687 
1688  /* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
1689  assert(stm32l4_info->data_width % 8 == 0);
1690 
1691  /* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
1692  * The flash infrastructure ensures it, do just a security check */
1693  assert(offset % stm32l4_info->data_width == 0);
1694  assert(count % stm32l4_info->data_width == 0);
1695 
1696  /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1697  * data to be written does not go into a gap:
1698  * suppose buffer is fully contained in bank from sector 0 to sector
1699  * num->sectors - 1 and sectors are ordered according to offset
1700  */
1701  struct flash_sector *head = &bank->sectors[0];
1702  struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
1703 
1704  while ((head < tail) && (offset >= (head + 1)->offset)) {
1705  /* buffer does not intersect head nor gap behind head */
1706  head++;
1707  }
1708 
1709  while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
1710  /* buffer does not intersect tail nor gap before tail */
1711  --tail;
1712  }
1713 
1714  LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
1715  offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
1716 
1717  /* Now check that there is no gap from head to tail, this should work
1718  * even for multiple or non-symmetric gaps
1719  */
1720  while (head < tail) {
1721  if (head->offset + head->size != (head + 1)->offset) {
1722  LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
1723  bank->base + head->offset + head->size,
1724  bank->base + (head + 1)->offset - 1);
1725  retval = ERROR_FLASH_DST_OUT_OF_BANK;
1726  }
1727  head++;
1728  }
1729 
1730  if (retval != ERROR_OK)
1731  return retval;
1732 
1733  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1734  /* set all FLASH pages as secure */
1736  if (retval != ERROR_OK) {
1737  /* restore all FLASH pages as non-secure */
1738  stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1739  return retval;
1740  }
1741  }
1742 
1743  retval = stm32l4_unlock_reg(bank);
1744  if (retval != ERROR_OK)
1745  goto err_lock;
1746 
1747 
1748  /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
1749  * the debug is possible only in non-secure state.
1750  * Thus means the flashloader will run in non-secure mode,
1751  * and the workarea need to be in non-secure RAM */
1752  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
1753  LOG_WARNING("RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
1754 
1755  /* first try to write using the loader, for better performance */
1757  count / stm32l4_info->data_width);
1758 
1759  /* if resources are not available write without a loader */
1760  if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1761  LOG_WARNING("falling back to programming without a flash loader (slower)");
1763  count / stm32l4_info->data_width);
1764  }
1765 
1766 err_lock:
1768 
1769  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1770  /* restore all FLASH pages as non-secure */
1772  if (retval3 != ERROR_OK)
1773  return retval3;
1774  }
1775 
1776  if (retval != ERROR_OK) {
1777  LOG_ERROR("block write failed");
1778  return retval;
1779  }
1780  return retval2;
1781 }
1782 
1783 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
1784 {
1785  int retval = ERROR_OK;
1786  struct target *target = bank->target;
1787 
1788  /* try reading possible IDCODE registers, in the following order */
1789  uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
1790 
1791  for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) {
1792  retval = target_read_u32(target, dbgmcu_idcode[i], id);
1793  if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
1794  return ERROR_OK;
1795  }
1796 
1797  /* Workaround for STM32WL5x devices:
1798  * DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
1799  * to solve this read the UID64 (IEEE 64-bit unique device ID register) */
1800 
1801  struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1802  if (!armv7m) {
1803  LOG_ERROR("Flash requires Cortex-M target");
1804  return ERROR_TARGET_INVALID;
1805  }
1806 
1807  /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1808  * Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
1810  armv7m->debug_ap && armv7m->debug_ap->ap_num == 1) {
1811  uint32_t uid64_ids;
1812 
1813  /* UID64 is contains
1814  * - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
1815  * - Bits 31:08 : STID (company ID) = 0x0080E1
1816  * - Bits 07:00 : DEVID (device ID) = 0x15
1817  *
1818  * read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
1819  */
1820  retval = target_read_u32(target, UID64_IDS, &uid64_ids);
1821  if (retval == ERROR_OK && uid64_ids == UID64_IDS_STM32WL) {
1822  /* force the DEV_ID to DEVID_STM32WLE_WL5XX and the REV_ID to unknown */
1823  *id = DEVID_STM32WLE_WL5XX;
1824  return ERROR_OK;
1825  }
1826  }
1827 
1828  LOG_ERROR("can't get the device id");
1829  return (retval == ERROR_OK) ? ERROR_FAIL : retval;
1830 }
1831 
1832 static const char *get_stm32l4_rev_str(struct flash_bank *bank)
1833 {
1834  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1835  const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
1836  assert(part_info);
1837 
1838  const uint16_t rev_id = stm32l4_info->idcode >> 16;
1839  for (unsigned int i = 0; i < part_info->num_revs; i++) {
1840  if (rev_id == part_info->revs[i].rev)
1841  return part_info->revs[i].str;
1842  }
1843  return "'unknown'";
1844 }
1845 
1846 static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
1847 {
1848  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1849  assert(stm32l4_info->part_info);
1850  return stm32l4_is_otp(bank) ? "OTP" :
1851  stm32l4_info->dual_bank_mode ? "Flash dual" :
1852  "Flash single";
1853 }
1854 
1855 static int stm32l4_probe(struct flash_bank *bank)
1856 {
1857  struct target *target = bank->target;
1858  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1859  const struct stm32l4_part_info *part_info;
1860  uint16_t flash_size_kb = 0xffff;
1861 
1862  if (!target_was_examined(target)) {
1863  LOG_ERROR("Target not examined yet");
1865  }
1866 
1867  struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1868  if (!armv7m) {
1869  LOG_ERROR("Flash requires Cortex-M target");
1870  return ERROR_TARGET_INVALID;
1871  }
1872 
1873  stm32l4_info->probed = false;
1874 
1875  /* read stm32 device id registers */
1876  int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
1877  if (retval != ERROR_OK)
1878  return retval;
1879 
1880  const uint32_t device_id = stm32l4_info->idcode & 0xFFF;
1881 
1882  for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
1883  if (device_id == stm32l4_parts[n].id) {
1884  stm32l4_info->part_info = &stm32l4_parts[n];
1885  break;
1886  }
1887  }
1888 
1889  if (!stm32l4_info->part_info) {
1890  LOG_WARNING("Cannot identify target as an %s family device.", device_families);
1891  return ERROR_FAIL;
1892  }
1893 
1894  part_info = stm32l4_info->part_info;
1895  const char *rev_str = get_stm32l4_rev_str(bank);
1896  const uint16_t rev_id = stm32l4_info->idcode >> 16;
1897 
1898  LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)",
1899  stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
1900 
1901  stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
1902  stm32l4_info->data_width = (part_info->flags & F_QUAD_WORD_PROG) ? 16 : 8;
1903  stm32l4_info->cr_bker_mask = FLASH_BKER;
1904  stm32l4_info->sr_bsy_mask = FLASH_BSY;
1905 
1906  /* Set flash write alignment boundaries.
1907  * Ask the flash infrastructure to ensure required alignment */
1908  bank->write_start_alignment = stm32l4_info->data_width;
1909  bank->write_end_alignment = stm32l4_info->data_width;
1910 
1911  /* Initialize the flash registers layout */
1912  if (part_info->flags & F_HAS_L5_FLASH_REGS)
1913  stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1914  else
1915  stm32l4_info->flash_regs = stm32l4_flash_regs;
1916 
1917  /* read flash option register */
1919  if (retval != ERROR_OK)
1920  return retval;
1921 
1923 
1924  /* for devices with TrustZone, use flash secure registers when TZEN=1 and RDP is LEVEL_0 */
1925  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1926  if (part_info->flags & F_HAS_L5_FLASH_REGS) {
1927  stm32l4_info->flash_regs_base |= STM32L5_REGS_SEC_OFFSET;
1928  stm32l4_info->flash_regs = stm32l5_s_flash_regs;
1929  } else {
1930  LOG_ERROR("BUG: device supported incomplete");
1931  return ERROR_NOT_IMPLEMENTED;
1932  }
1933  }
1934 
1935  if (part_info->flags & F_HAS_TZ)
1936  LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1937  stm32l4_info->tzen,
1938  stm32l4_info->tzen ? "enabled" : "disabled");
1939 
1940  LOG_INFO("RDP level %s (0x%02X)",
1941  stm32l4_info->rdp == RDP_LEVEL_0 ? "0" : stm32l4_info->rdp == RDP_LEVEL_0_5 ? "0.5" : "1",
1942  stm32l4_info->rdp);
1943 
1944  if (stm32l4_is_otp(bank)) {
1945  bank->size = part_info->otp_size;
1946 
1947  LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT, bank->size, bank->base);
1948 
1949  /* OTP memory is considered as one sector */
1950  free(bank->sectors);
1951  bank->num_sectors = 1;
1952  bank->sectors = alloc_block_array(0, part_info->otp_size, 1);
1953 
1954  if (!bank->sectors) {
1955  LOG_ERROR("failed to allocate bank sectors");
1956  return ERROR_FAIL;
1957  }
1958 
1959  stm32l4_info->probed = true;
1960  return ERROR_OK;
1961  } else if (bank->base != STM32_FLASH_BANK_BASE && bank->base != STM32_FLASH_S_BANK_BASE) {
1962  LOG_ERROR("invalid bank base address");
1963  return ERROR_FAIL;
1964  }
1965 
1966  /* get flash size from target. */
1967  retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
1968 
1969  /* failed reading flash size or flash size invalid (early silicon),
1970  * default to max target family */
1971  if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
1972  || flash_size_kb > part_info->max_flash_size_kb) {
1973  LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1974  part_info->max_flash_size_kb);
1975  flash_size_kb = part_info->max_flash_size_kb;
1976  }
1977 
1978  /* if the user sets the size manually then ignore the probed value
1979  * this allows us to work around devices that have a invalid flash size register value */
1980  if (stm32l4_info->user_bank_size) {
1981  LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
1982  flash_size_kb = stm32l4_info->user_bank_size / 1024;
1983  }
1984 
1985  LOG_INFO("flash size = %d KiB", flash_size_kb);
1986 
1987  /* did we assign a flash size? */
1988  assert((flash_size_kb != 0xffff) && flash_size_kb);
1989 
1990  const bool is_max_flash_size = flash_size_kb == stm32l4_info->part_info->max_flash_size_kb;
1991 
1992  stm32l4_info->bank1_sectors = 0;
1993  stm32l4_info->hole_sectors = 0;
1994 
1995  int num_pages = 0;
1996  int page_size_kb = 0;
1997 
1998  stm32l4_info->dual_bank_mode = false;
1999 
2000  switch (device_id) {
2001  case DEVID_STM32L47_L48XX:
2002  case DEVID_STM32L49_L4AXX:
2003  /* if flash size is max (1M) the device is always dual bank
2004  * STM32L47/L48xx: has variants with 512K
2005  * STM32L49/L4Axx: has variants with 512 and 256
2006  * for these variants:
2007  * if DUAL_BANK = 0 -> single bank
2008  * else -> dual bank without gap
2009  * note: the page size is invariant
2010  */
2011  page_size_kb = 2;
2012  num_pages = flash_size_kb / page_size_kb;
2013  stm32l4_info->bank1_sectors = num_pages;
2014 
2015  /* check DUAL_BANK option bit if the flash is less than 1M */
2016  if (is_max_flash_size || (stm32l4_info->optr & FLASH_L4_DUAL_BANK)) {
2017  stm32l4_info->dual_bank_mode = true;
2018  stm32l4_info->bank1_sectors = num_pages / 2;
2019  }
2020  break;
2021  case DEVID_STM32L43_L44XX:
2022  case DEVID_STM32C01XX:
2023  case DEVID_STM32C03XX:
2024  case DEVID_STM32C071XX:
2025  case DEVID_STM32G05_G06XX:
2026  case DEVID_STM32G07_G08XX:
2027  case DEVID_STM32U031XX:
2029  case DEVID_STM32L45_L46XX:
2030  case DEVID_STM32L41_L42XX:
2031  case DEVID_STM32G03_G04XX:
2032  case DEVID_STM32G43_G44XX:
2033  case DEVID_STM32G49_G4AXX:
2034  case DEVID_STM32WB1XX:
2035  /* single bank flash */
2036  page_size_kb = 2;
2037  num_pages = flash_size_kb / page_size_kb;
2038  stm32l4_info->bank1_sectors = num_pages;
2039  break;
2040  case DEVID_STM32G0B_G0CXX:
2041  /* single/dual bank depending on DUAL_BANK option bit */
2042  page_size_kb = 2;
2043  num_pages = flash_size_kb / page_size_kb;
2044  stm32l4_info->bank1_sectors = num_pages;
2045  stm32l4_info->cr_bker_mask = FLASH_BKER_G0;
2046 
2047  /* check DUAL_BANK bit */
2048  if (stm32l4_info->optr & FLASH_G0_DUAL_BANK) {
2049  stm32l4_info->sr_bsy_mask = FLASH_BSY | FLASH_BSY2;
2050  stm32l4_info->dual_bank_mode = true;
2051  stm32l4_info->bank1_sectors = num_pages / 2;
2052  }
2053  break;
2054  case DEVID_STM32G47_G48XX:
2055  /* STM32G47/8 can be single/dual bank:
2056  * if DUAL_BANK = 0 -> single bank
2057  * else -> dual bank WITH gap
2058  */
2059  page_size_kb = 4;
2060  num_pages = flash_size_kb / page_size_kb;
2061  stm32l4_info->bank1_sectors = num_pages;
2062  if (stm32l4_info->optr & FLASH_G4_DUAL_BANK) {
2063  stm32l4_info->dual_bank_mode = true;
2064  page_size_kb = 2;
2065  num_pages = flash_size_kb / page_size_kb;
2066  stm32l4_info->bank1_sectors = num_pages / 2;
2067 
2068  /* for devices with trimmed flash, there is a gap between both banks */
2069  stm32l4_info->hole_sectors =
2070  (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
2071  }
2072  break;
2073  case DEVID_STM32L4R_L4SXX:
2074  case DEVID_STM32L4P_L4QXX:
2075  /* STM32L4R/S can be single/dual bank:
2076  * if size = 2M check DBANK bit
2077  * if size = 1M check DB1M bit
2078  * STM32L4P/Q can be single/dual bank
2079  * if size = 1M check DBANK bit
2080  * if size = 512K check DB512K bit (same as DB1M bit)
2081  */
2082  page_size_kb = 8;
2083  num_pages = flash_size_kb / page_size_kb;
2084  stm32l4_info->bank1_sectors = num_pages;
2085  if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L4R_DBANK)) ||
2086  (!is_max_flash_size && (stm32l4_info->optr & FLASH_LRR_DB1M))) {
2087  stm32l4_info->dual_bank_mode = true;
2088  page_size_kb = 4;
2089  num_pages = flash_size_kb / page_size_kb;
2090  stm32l4_info->bank1_sectors = num_pages / 2;
2091  }
2092  break;
2093  case DEVID_STM32L55_L56XX:
2094  /* STM32L55/L56xx can be single/dual bank:
2095  * if size = 512K check DBANK bit
2096  * if size = 256K check DB256K bit
2097  *
2098  * default page size is 4kb, if DBANK = 1, the page size is 2kb.
2099  */
2100 
2101  page_size_kb = (stm32l4_info->optr & FLASH_L5_DBANK) ? 2 : 4;
2102  num_pages = flash_size_kb / page_size_kb;
2103  stm32l4_info->bank1_sectors = num_pages;
2104 
2105  if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DBANK)) ||
2106  (!is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DB256))) {
2107  stm32l4_info->dual_bank_mode = true;
2108  stm32l4_info->bank1_sectors = num_pages / 2;
2109  }
2110  break;
2111  case DEVID_STM32U53_U54XX:
2112  case DEVID_STM32U57_U58XX:
2113  case DEVID_STM32U59_U5AXX:
2114  case DEVID_STM32U5F_U5GXX:
2115  /* according to RM0456 Rev 4, Chapter 7.3.1 and 7.9.13
2116  * U53x/U54x have 512K max flash size:
2117  * 512K variants are always in DUAL BANK mode
2118  * 256K and 128K variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2119  * U57x/U58x have 2M max flash size:
2120  * 2M variants are always in DUAL BANK mode
2121  * 1M variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2122  * U59x/U5Ax/U5Fx/U5Gx have 4M max flash size:
2123  * 4M variants are always in DUAL BANK mode
2124  * 2M variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2125  * Note: flash banks are always contiguous
2126  */
2127 
2128  page_size_kb = 8;
2129  num_pages = flash_size_kb / page_size_kb;
2130  stm32l4_info->bank1_sectors = num_pages;
2131  if (is_max_flash_size || (stm32l4_info->optr & FLASH_U5_DUALBANK)) {
2132  stm32l4_info->dual_bank_mode = true;
2133  stm32l4_info->bank1_sectors = num_pages / 2;
2134  }
2135  break;
2136  case DEVID_STM32WBA5X:
2137  /* single bank flash */
2138  page_size_kb = 8;
2139  num_pages = flash_size_kb / page_size_kb;
2140  stm32l4_info->bank1_sectors = num_pages;
2141  break;
2142  case DEVID_STM32WB5XX:
2143  case DEVID_STM32WB3XX:
2144  /* single bank flash */
2145  page_size_kb = 4;
2146  num_pages = flash_size_kb / page_size_kb;
2147  stm32l4_info->bank1_sectors = num_pages;
2148  break;
2149  case DEVID_STM32WLE_WL5XX:
2150  /* single bank flash */
2151  page_size_kb = 2;
2152  num_pages = flash_size_kb / page_size_kb;
2153  stm32l4_info->bank1_sectors = num_pages;
2154 
2155  /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
2156  * Using HLA adapters armv7m->debug_ap is null, and checking ap_num triggers a segfault */
2157  if (armv7m->debug_ap && armv7m->debug_ap->ap_num == 1)
2158  stm32l4_info->flash_regs = stm32wl_cpu2_flash_regs;
2159  break;
2160  default:
2161  LOG_ERROR("unsupported device");
2162  return ERROR_FAIL;
2163  }
2164 
2165  /* ensure that at least there is 1 flash sector / page */
2166  if (num_pages == 0) {
2167  if (stm32l4_info->user_bank_size)
2168  LOG_ERROR("The specified flash size is less than page size");
2169 
2170  LOG_ERROR("Flash pages count cannot be zero");
2171  return ERROR_FAIL;
2172  }
2173 
2174  LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
2175 
2176  const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
2177 
2178  if (gap_size_kb != 0) {
2179  LOG_INFO("gap detected from 0x%08x to 0x%08x",
2180  STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
2181  * page_size_kb * 1024,
2182  STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
2183  * page_size_kb + gap_size_kb) * 1024 - 1);
2184  }
2185 
2186  /* number of significant bits in WRPxxR differs per device,
2187  * always right adjusted, on some devices non-implemented
2188  * bits read as '0', on others as '1' ...
2189  * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
2190  */
2191 
2192  /* use *max_flash_size* instead of actual size as the trimmed versions
2193  * certainly use the same number of bits
2194  */
2195  uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
2196 
2197  /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
2198  stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
2199  assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
2200  LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
2201 
2202  free(bank->sectors);
2203 
2204  bank->size = (flash_size_kb + gap_size_kb) * 1024;
2205  bank->num_sectors = num_pages;
2206  bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
2207  if (!bank->sectors) {
2208  LOG_ERROR("failed to allocate bank sectors");
2209  return ERROR_FAIL;
2210  }
2211 
2212  for (unsigned int i = 0; i < bank->num_sectors; i++) {
2213  bank->sectors[i].offset = i * page_size_kb * 1024;
2214  /* in dual bank configuration, if there is a gap between banks
2215  * we fix up the sector offset to consider this gap */
2216  if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
2217  bank->sectors[i].offset += gap_size_kb * 1024;
2218  bank->sectors[i].size = page_size_kb * 1024;
2219  bank->sectors[i].is_erased = -1;
2220  bank->sectors[i].is_protected = 1;
2221  }
2222 
2223  stm32l4_info->probed = true;
2224  return ERROR_OK;
2225 }
2226 
2228 {
2229  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2230  if (stm32l4_info->probed) {
2231  uint32_t optr_cur;
2232 
2233  /* save flash_regs_base */
2234  uint32_t saved_flash_regs_base = stm32l4_info->flash_regs_base;
2235 
2236  /* for devices with TrustZone, use NS flash registers to read OPTR */
2237  if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
2238  stm32l4_info->flash_regs_base &= ~STM32L5_REGS_SEC_OFFSET;
2239 
2240  /* read flash option register and re-probe if optr value is changed */
2242 
2243  /* restore saved flash_regs_base */
2244  stm32l4_info->flash_regs_base = saved_flash_regs_base;
2245 
2246  if (retval != ERROR_OK)
2247  return retval;
2248 
2249  if (stm32l4_info->optr == optr_cur)
2250  return ERROR_OK;
2251  }
2252 
2253  return stm32l4_probe(bank);
2254 }
2255 
2257 {
2258  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2259  const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
2260 
2261  if (part_info) {
2262  const uint16_t rev_id = stm32l4_info->idcode >> 16;
2263  command_print_sameline(cmd, "%s - Rev %s : 0x%04x", part_info->device_str,
2264  get_stm32l4_rev_str(bank), rev_id);
2265  if (stm32l4_info->probed)
2267  } else {
2268  command_print_sameline(cmd, "Cannot identify target as an %s device", device_families);
2269  }
2270 
2271  return ERROR_OK;
2272 }
2273 
2275 {
2276  int retval, retval2;
2277  struct target *target = bank->target;
2278  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2279 
2280  if (stm32l4_is_otp(bank)) {
2281  LOG_ERROR("cannot erase OTP memory");
2283  }
2284 
2285  uint32_t action = FLASH_MER1;
2286 
2287  if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)
2288  action |= FLASH_MER2;
2289 
2290  if (target->state != TARGET_HALTED) {
2291  LOG_ERROR("Target not halted");
2292  return ERROR_TARGET_NOT_HALTED;
2293  }
2294 
2295  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2296  /* set all FLASH pages as secure */
2298  if (retval != ERROR_OK) {
2299  /* restore all FLASH pages as non-secure */
2300  stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
2301  return retval;
2302  }
2303  }
2304 
2305  retval = stm32l4_unlock_reg(bank);
2306  if (retval != ERROR_OK)
2307  goto err_lock;
2308 
2309  /* mass erase flash memory */
2311  if (retval != ERROR_OK)
2312  goto err_lock;
2313 
2315  if (retval != ERROR_OK)
2316  goto err_lock;
2317 
2319  if (retval != ERROR_OK)
2320  goto err_lock;
2321 
2323 
2324 err_lock:
2326 
2327  if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2328  /* restore all FLASH pages as non-secure */
2330  if (retval3 != ERROR_OK)
2331  return retval3;
2332  }
2333 
2334  if (retval != ERROR_OK)
2335  return retval;
2336 
2337  return retval2;
2338 }
2339 
2340 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
2341 {
2342  if (CMD_ARGC != 1)
2344 
2345  struct flash_bank *bank;
2346  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2347  if (retval != ERROR_OK)
2348  return retval;
2349 
2350  retval = stm32l4_mass_erase(bank);
2351  if (retval == ERROR_OK)
2352  command_print(CMD, "stm32l4x mass erase complete");
2353  else
2354  command_print(CMD, "stm32l4x mass erase failed");
2355 
2356  return retval;
2357 }
2358 
2359 COMMAND_HANDLER(stm32l4_handle_option_read_command)
2360 {
2361  if (CMD_ARGC != 2)
2363 
2364  struct flash_bank *bank;
2365  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2366  if (retval != ERROR_OK)
2367  return retval;
2368 
2369  uint32_t reg_offset, reg_addr;
2370  uint32_t value = 0;
2371 
2372  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2373  reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
2374 
2375  retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
2376  if (retval != ERROR_OK)
2377  return retval;
2378 
2379  command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
2380 
2381  return retval;
2382 }
2383 
2384 COMMAND_HANDLER(stm32l4_handle_option_write_command)
2385 {
2386  if (CMD_ARGC != 3 && CMD_ARGC != 4)
2388 
2389  struct flash_bank *bank;
2390  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2391  if (retval != ERROR_OK)
2392  return retval;
2393 
2394  uint32_t reg_offset;
2395  uint32_t value = 0;
2396  uint32_t mask = 0xFFFFFFFF;
2397 
2398  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2399  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
2400 
2401  if (CMD_ARGC > 3)
2403 
2404  command_print(CMD, "%s Option written.\n"
2405  "INFO: a reset or power cycle is required "
2406  "for the new settings to take effect.", bank->driver->name);
2407 
2408  retval = stm32l4_write_option(bank, reg_offset, value, mask);
2409  return retval;
2410 }
2411 
2412 COMMAND_HANDLER(stm32l4_handle_trustzone_command)
2413 {
2414  if (CMD_ARGC < 1 || CMD_ARGC > 2)
2416 
2417  struct flash_bank *bank;
2418  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2419  if (retval != ERROR_OK)
2420  return retval;
2421 
2422  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2423  if (!(stm32l4_info->part_info->flags & F_HAS_TZ)) {
2424  LOG_ERROR("This device does not have a TrustZone");
2425  return ERROR_FAIL;
2426  }
2427 
2429  if (retval != ERROR_OK)
2430  return retval;
2431 
2433 
2434  if (CMD_ARGC == 1) {
2435  /* only display the TZEN value */
2436  LOG_INFO("Global TrustZone Security is %s", stm32l4_info->tzen ? "enabled" : "disabled");
2437  return ERROR_OK;
2438  }
2439 
2440  bool new_tzen;
2441  COMMAND_PARSE_ENABLE(CMD_ARGV[1], new_tzen);
2442 
2443  if (new_tzen == stm32l4_info->tzen) {
2444  LOG_INFO("The requested TZEN is already programmed");
2445  return ERROR_OK;
2446  }
2447 
2448  if (new_tzen) {
2449  if (stm32l4_info->rdp != RDP_LEVEL_0) {
2450  LOG_ERROR("TZEN can be set only when RDP level is 0");
2451  return ERROR_FAIL;
2452  }
2455  } else {
2456  /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
2457  * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
2458  if (stm32l4_info->rdp != RDP_LEVEL_1 && stm32l4_info->rdp != RDP_LEVEL_0_5) {
2459  LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
2460  return ERROR_FAIL;
2461  }
2462 
2465  }
2466 
2467  if (retval != ERROR_OK)
2468  return retval;
2469 
2471 }
2472 
2473 COMMAND_HANDLER(stm32l4_handle_option_load_command)
2474 {
2475  if (CMD_ARGC != 1)
2477 
2478  struct flash_bank *bank;
2479  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2480  if (retval != ERROR_OK)
2481  return retval;
2482 
2483  retval = stm32l4_perform_obl_launch(bank);
2484  if (retval != ERROR_OK) {
2485  command_print(CMD, "stm32l4x option load failed");
2486  return retval;
2487  }
2488 
2489 
2490  command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
2491 
2492  return ERROR_OK;
2493 }
2494 
2495 COMMAND_HANDLER(stm32l4_handle_lock_command)
2496 {
2497  struct target *target = NULL;
2498 
2499  if (CMD_ARGC != 1)
2501 
2502  struct flash_bank *bank;
2503  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2504  if (retval != ERROR_OK)
2505  return retval;
2506 
2507  if (stm32l4_is_otp(bank)) {
2508  LOG_ERROR("cannot lock/unlock OTP memory");
2510  }
2511 
2512  target = bank->target;
2513 
2514  if (target->state != TARGET_HALTED) {
2515  LOG_ERROR("Target not halted");
2516  return ERROR_TARGET_NOT_HALTED;
2517  }
2518 
2519  /* set readout protection level 1 by erasing the RDP option byte */
2520  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2523  command_print(CMD, "%s failed to lock device", bank->driver->name);
2524  return ERROR_OK;
2525  }
2526 
2527  return ERROR_OK;
2528 }
2529 
2530 COMMAND_HANDLER(stm32l4_handle_unlock_command)
2531 {
2532  struct target *target = NULL;
2533 
2534  if (CMD_ARGC != 1)
2536 
2537  struct flash_bank *bank;
2538  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2539  if (retval != ERROR_OK)
2540  return retval;
2541 
2542  if (stm32l4_is_otp(bank)) {
2543  LOG_ERROR("cannot lock/unlock OTP memory");
2545  }
2546 
2547  target = bank->target;
2548 
2549  if (target->state != TARGET_HALTED) {
2550  LOG_ERROR("Target not halted");
2551  return ERROR_TARGET_NOT_HALTED;
2552  }
2553 
2554  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2557  command_print(CMD, "%s failed to unlock device", bank->driver->name);
2558  return ERROR_OK;
2559  }
2560 
2561  return ERROR_OK;
2562 }
2563 
2564 COMMAND_HANDLER(stm32l4_handle_wrp_info_command)
2565 {
2566  if (CMD_ARGC < 1 || CMD_ARGC > 2)
2568 
2569  struct flash_bank *bank;
2570  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2571  if (retval != ERROR_OK)
2572  return retval;
2573 
2574  if (stm32l4_is_otp(bank)) {
2575  LOG_ERROR("OTP memory does not have write protection areas");
2577  }
2578 
2579  struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2580  enum stm32_bank_id dev_bank_id = STM32_ALL_BANKS;
2581  if (CMD_ARGC == 2) {
2582  if (strcmp(CMD_ARGV[1], "bank1") == 0)
2583  dev_bank_id = STM32_BANK1;
2584  else if (strcmp(CMD_ARGV[1], "bank2") == 0)
2585  dev_bank_id = STM32_BANK2;
2586  else
2588  }
2589 
2590  if (dev_bank_id == STM32_BANK2) {
2591  if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) {
2592  LOG_ERROR("this device has no second bank");
2593  return ERROR_FAIL;
2594  } else if (!stm32l4_info->dual_bank_mode) {
2595  LOG_ERROR("this device is configured in single bank mode");
2596  return ERROR_FAIL;
2597  }
2598  }
2599 
2600  int ret;
2601  unsigned int n_wrp, i;
2602  struct stm32l4_wrp wrpxy[4];
2603 
2604  ret = stm32l4_get_all_wrpxy(bank, dev_bank_id, wrpxy, &n_wrp);
2605  if (ret != ERROR_OK)
2606  return ret;
2607 
2608  /* use bitmap and range helpers to better describe protected areas */
2609  DECLARE_BITMAP(pages, bank->num_sectors);
2610  bitmap_zero(pages, bank->num_sectors);
2611 
2612  for (i = 0; i < n_wrp; i++) {
2613  if (wrpxy[i].used) {
2614  for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
2615  set_bit(p, pages);
2616  }
2617  }
2618 
2619  /* we have at most 'n_wrp' WRP areas */
2620  struct range ranges[n_wrp];
2621  unsigned int ranges_count = 0;
2622 
2623  bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
2624 
2625  if (ranges_count > 0) {
2626  /* pretty-print the protected ranges */
2627  char *ranges_str = range_print_alloc(ranges, ranges_count);
2628  command_print(CMD, "protected areas: %s", ranges_str);
2629  free(ranges_str);
2630  } else
2631  command_print(CMD, "no protected areas");
2632 
2633  return ERROR_OK;
2634 }
2635 
2636 COMMAND_HANDLER(stm32l4_handle_otp_command)
2637 {
2638  if (CMD_ARGC != 2)
2640 
2641  struct flash_bank *bank;
2642  int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2643  if (retval != ERROR_OK)
2644  return retval;
2645 
2646  if (!stm32l4_is_otp(bank)) {
2647  command_print(CMD, "the specified bank is not an OTP memory");
2648  return ERROR_FAIL;
2649  }
2650  if (strcmp(CMD_ARGV[1], "enable") == 0)
2651  stm32l4_otp_enable(bank, true);
2652  else if (strcmp(CMD_ARGV[1], "disable") == 0)
2653  stm32l4_otp_enable(bank, false);
2654  else if (strcmp(CMD_ARGV[1], "show") == 0)
2655  command_print(CMD, "OTP memory bank #%d is %s for write commands.",
2656  bank->bank_number, stm32l4_otp_is_enabled(bank) ? "enabled" : "disabled");
2657  else
2659 
2660  return ERROR_OK;
2661 }
2662 
2663 static const struct command_registration stm32l4_exec_command_handlers[] = {
2664  {
2665  .name = "lock",
2666  .handler = stm32l4_handle_lock_command,
2667  .mode = COMMAND_EXEC,
2668  .usage = "bank_id",
2669  .help = "Lock entire flash device.",
2670  },
2671  {
2672  .name = "unlock",
2673  .handler = stm32l4_handle_unlock_command,
2674  .mode = COMMAND_EXEC,
2675  .usage = "bank_id",
2676  .help = "Unlock entire protected flash device.",
2677  },
2678  {
2679  .name = "mass_erase",
2680  .handler = stm32l4_handle_mass_erase_command,
2681  .mode = COMMAND_EXEC,
2682  .usage = "bank_id",
2683  .help = "Erase entire flash device.",
2684  },
2685  {
2686  .name = "option_read",
2687  .handler = stm32l4_handle_option_read_command,
2688  .mode = COMMAND_EXEC,
2689  .usage = "bank_id reg_offset",
2690  .help = "Read & Display device option bytes.",
2691  },
2692  {
2693  .name = "option_write",
2694  .handler = stm32l4_handle_option_write_command,
2695  .mode = COMMAND_EXEC,
2696  .usage = "bank_id reg_offset value [mask]",
2697  .help = "Write device option bit fields with provided value.",
2698  },
2699  {
2700  .name = "trustzone",
2701  .handler = stm32l4_handle_trustzone_command,
2702  .mode = COMMAND_EXEC,
2703  .usage = "<bank_id> [enable|disable]",
2704  .help = "Configure TrustZone security",
2705  },
2706  {
2707  .name = "wrp_info",
2708  .handler = stm32l4_handle_wrp_info_command,
2709  .mode = COMMAND_EXEC,
2710  .usage = "bank_id [bank1|bank2]",
2711  .help = "list the protected areas using WRP",
2712  },
2713  {
2714  .name = "option_load",
2715  .handler = stm32l4_handle_option_load_command,
2716  .mode = COMMAND_EXEC,
2717  .usage = "bank_id",
2718  .help = "Force re-load of device options (will cause device reset).",
2719  },
2720  {
2721  .name = "otp",
2722  .handler = stm32l4_handle_otp_command,
2723  .mode = COMMAND_EXEC,
2724  .usage = "<bank_id> <enable|disable|show>",
2725  .help = "OTP (One Time Programmable) memory write enable/disable",
2726  },
2728 };
2729 
2730 static const struct command_registration stm32l4_command_handlers[] = {
2731  {
2732  .name = "stm32l4x",
2733  .mode = COMMAND_ANY,
2734  .help = "stm32l4x flash command group",
2735  .usage = "",
2737  },
2739 };
2740 
2741 const struct flash_driver stm32l4x_flash = {
2742  .name = "stm32l4x",
2743  .commands = stm32l4_command_handlers,
2744  .flash_bank_command = stm32l4_flash_bank_command,
2745  .erase = stm32l4_erase,
2746  .protect = stm32l4_protect,
2747  .write = stm32l4_write,
2748  .read = default_flash_read,
2749  .probe = stm32l4_probe,
2750  .auto_probe = stm32l4_auto_probe,
2751  .erase_check = default_flash_blank_check,
2752  .protect_check = stm32l4_protect_check,
2753  .info = get_stm32l4_info,
2754  .free_driver_priv = default_flash_free_driver_priv,
2755 };
void init_reg_param(struct reg_param *param, const char *reg_name, uint32_t size, enum param_direction direction)
Definition: algorithm.c:29
void destroy_reg_param(struct reg_param *param)
Definition: algorithm.c:38
@ PARAM_OUT
Definition: algorithm.h:16
@ PARAM_IN_OUT
Definition: algorithm.h:17
@ ARM_MODE_THREAD
Definition: arm.h:94
This defines formats and data structures used to talk to ADIv5 entities.
static struct armv7m_common * target_to_armv7m_safe(struct target *target)
Definition: armv7m.h:278
#define ARMV7M_COMMON_MAGIC
Definition: armv7m.h:224
Support functions to access arbitrary bits in a byte array.
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
static int test_bit(unsigned int nr, const volatile unsigned long *addr)
test_bit - Determine whether a bit is set
Definition: bits.h:73
static void bitmap_zero(unsigned long *dst, unsigned int nbits)
bitmap_zero - Clears all the bits in memory
Definition: bits.h:36
static void set_bit(unsigned int nr, volatile unsigned long *addr)
set_bit - Set a bit in memory
Definition: bits.h:60
static void clear_bit(unsigned int nr, volatile unsigned long *addr)
clear_bit - Clear a bit in memory
Definition: bits.h:47
#define DECLARE_BITMAP(name, bits)
Definition: bits.h:29
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:421
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:444
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
Definition: command.h:118
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:402
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
#define COMMAND_PARSE_ENABLE(in, out)
parses an enable/disable command argument
Definition: command.h:533
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:442
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
#define ERROR_COMMAND_ARGUMENT_INVALID
Definition: command.h:404
@ COMMAND_ANY
Definition: command.h:42
@ COMMAND_EXEC
Definition: command.h:40
static enum cortex_m_impl_part cortex_m_get_impl_part(struct target *target)
Definition: cortex_m.h:319
@ CORTEX_M0P_PARTNO
Definition: cortex_m.h:54
uint64_t buffer
Pointer to data buffer to send over SPI.
Definition: dw-spi-helper.h:0
uint32_t size
Size of dw_spi_transaction::buffer.
Definition: dw-spi-helper.h:4
uint32_t buffer_size
Size of dw_spi_program::buffer.
Definition: dw-spi-helper.h:5
uint32_t address
Starting address. Sector aligned.
Definition: dw-spi-helper.h:0
#define FLASH_PG
Definition: em357.c:44
#define KEY2
Definition: em357.c:68
#define FLASH_PER
Definition: em357.c:45
#define FLASH_BSY
Definition: em357.c:55
#define FLASH_LOCK
Definition: em357.c:50
#define FLASH_STRT
Definition: em357.c:49
#define KEY1
Definition: em357.c:67
uint8_t bank
Definition: esirisc.c:135
int mask
Definition: esirisc.c:1740
#define ERROR_FLASH_OPER_UNSUPPORTED
Definition: flash/common.h:36
#define ERROR_FLASH_OPERATION_FAILED
Definition: flash/common.h:30
#define ERROR_FLASH_DST_OUT_OF_BANK
Definition: flash/common.h:31
struct flash_sector * alloc_block_array(uint32_t offset, uint32_t size, unsigned int num_blocks)
Allocate and fill an array of sectors or protection blocks.
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
void alive_sleep(uint64_t ms)
Definition: log.c:467
#define ERROR_NOT_IMPLEMENTED
Definition: log.h:178
#define LOG_WARNING(expr ...)
Definition: log.h:130
#define ERROR_FAIL
Definition: log.h:174
#define LOG_ERROR(expr ...)
Definition: log.h:133
#define LOG_INFO(expr ...)
Definition: log.h:127
#define LOG_DEBUG(expr ...)
Definition: log.h:110
#define ERROR_OK
Definition: log.h:168
#define FLASH_ERROR
Definition: msp432.h:72
struct rtt_control ctrl
Control block.
Definition: rtt/rtt.c:25
struct rtt_source source
Definition: rtt/rtt.c:23
#define FLASH_OBL_LAUNCH
Definition: stm32f1x.c:72
#define FLASH_WRPERR
Definition: stm32f2x.c:157
#define OPTKEY2
Definition: stm32f2x.c:178
#define FLASH_MER1
Definition: stm32f2x.c:142
#define OPTKEY1
Definition: stm32f2x.c:177
stm32l4_rdp
Definition: stm32l4x.c:175
@ RDP_LEVEL_1
Definition: stm32l4x.c:178
@ RDP_LEVEL_2
Definition: stm32l4x.c:179
@ RDP_LEVEL_0_5
Definition: stm32l4x.c:177
@ RDP_LEVEL_0
Definition: stm32l4x.c:176
static const struct stm32l4_rev stm32g05_g06xx_revs[]
Definition: stm32l4x.c:310
static const struct stm32l4_rev stm32c071xx_revs[]
Definition: stm32l4x.c:306
static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id, struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
Definition: stm32l4x.c:1197
static int stm32l4_protect_check(struct flash_bank *bank)
Definition: stm32l4x.c:1275
#define FLASH_ERASE_TIMEOUT
Definition: stm32l4x.c:137
static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, enum stm32l4_flash_reg_index reg_idx, int offset)
Definition: stm32l4x.c:1177
static const struct stm32l4_rev stm32l43_l44xx_revs[]
Definition: stm32l4x.c:293
static const struct stm32l4_rev stm32u53_u54xx_revs[]
Definition: stm32l4x.c:367
static const struct stm32l4_rev stm32u59_u5axx_revs[]
Definition: stm32l4x.c:376
#define F_QUAD_WORD_PROG
Definition: stm32l4x.c:154
static const struct command_registration stm32l4_exec_command_handlers[]
Definition: stm32l4x.c:2663
#define F_NONE
Definition: stm32l4x.c:142
static int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
Definition: stm32l4x.c:922
static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:182
#define F_USE_ALL_WRPXX
Definition: stm32l4x.c:147
stm32l4_flash_reg_index
Definition: stm32l4x.c:158
@ STM32_FLASH_SR_INDEX
Definition: stm32l4x.c:162
@ STM32_FLASH_CR_WLK_INDEX
Definition: stm32l4x.c:166
@ STM32_FLASH_ACR_INDEX
Definition: stm32l4x.c:159
@ STM32_FLASH_OPTR_INDEX
Definition: stm32l4x.c:167
@ STM32_FLASH_WRP1AR_INDEX
Definition: stm32l4x.c:168
@ STM32_FLASH_CR_INDEX
Definition: stm32l4x.c:163
@ STM32_FLASH_WRP2BR_INDEX
Definition: stm32l4x.c:171
@ STM32_FLASH_OPTKEYR_INDEX
Definition: stm32l4x.c:161
@ STM32_FLASH_WRP1BR_INDEX
Definition: stm32l4x.c:169
@ STM32_FLASH_KEYR_INDEX
Definition: stm32l4x.c:160
@ STM32_FLASH_WRP2AR_INDEX
Definition: stm32l4x.c:170
@ STM32_FLASH_REG_INDEX_NUM
Definition: stm32l4x.c:172
#define F_HAS_TZ
Definition: stm32l4x.c:149
static int stm32l4_perform_obl_launch(struct flash_bank *bank)
Definition: stm32l4x.c:1092
static const struct stm32l4_part_info stm32l4_parts[]
Definition: stm32l4x.c:404
static char * range_print_alloc(struct range *ranges, unsigned int ranges_count)
Definition: stm32l4x.c:814
static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
Definition: stm32l4x.c:1783
static const struct stm32l4_rev stm32g47_g48xx_revs[]
Definition: stm32l4x.c:346
static int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
Definition: stm32l4x.c:910
static bool stm32l4_otp_is_enabled(struct flash_bank *bank)
Definition: stm32l4x.c:862
#define F_HAS_L5_FLASH_REGS
Definition: stm32l4x.c:151
static const char * get_stm32l4_bank_type_str(struct flash_bank *bank)
Definition: stm32l4x.c:1846
static bool stm32l4_is_otp(struct flash_bank *bank)
Definition: stm32l4x.c:837
static int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
Definition: stm32l4x.c:1016
static int range_print_one(struct range *range, char *str)
Definition: stm32l4x.c:806
static const struct stm32l4_rev stm32g03_g04xx_revs[]
Definition: stm32l4x.c:330
static const struct stm32l4_rev stm32c01xx_revs[]
Definition: stm32l4x.c:298
#define F_HAS_DUAL_BANK
Definition: stm32l4x.c:144
static const char * device_families
Definition: stm32l4x.c:287
stm32_bank_id
Definition: stm32l4x.c:271
@ STM32_BANK1
Definition: stm32l4x.c:272
@ STM32_BANK2
Definition: stm32l4x.c:273
@ STM32_ALL_BANKS
Definition: stm32l4x.c:274
static const struct stm32l4_rev stm32u57_u58xx_revs[]
Definition: stm32l4x.c:371
static const struct command_registration stm32l4_command_handlers[]
Definition: stm32l4x.c:2730
static const struct stm32l4_rev stm32l45_l46xx_revs[]
Definition: stm32l4x.c:322
static int stm32l4_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: stm32l4x.c:1299
static const struct stm32l4_rev stm32l4p_l4qxx_revs[]
Definition: stm32l4x.c:355
static const struct stm32l4_rev stm32l41_l42xx_revs[]
Definition: stm32l4x.c:326
static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
Definition: stm32l4x.c:843
static const struct stm32l4_rev stm32l47_l48xx_revs[]
Definition: stm32l4x.c:289
static const struct stm32l4_rev stm32l4r_l4sxx_revs[]
Definition: stm32l4x.c:350
static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
Definition: stm32l4x.c:1129
static const struct stm32l4_rev stm32l55_l56xx_revs[]
Definition: stm32l4x.c:359
static const struct stm32l4_rev stm32wb1xx_revs[]
Definition: stm32l4x.c:388
static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
Definition: stm32l4x.c:934
static const struct stm32l4_rev stm32wba5x_revs[]
Definition: stm32l4x.c:384
static int stm32l4_mass_erase(struct flash_bank *bank)
Definition: stm32l4x.c:2274
static const char * get_stm32l4_rev_str(struct flash_bank *bank)
Definition: stm32l4x.c:1832
static int get_stm32l4_info(struct flash_bank *bank, struct command_invocation *cmd)
Definition: stm32l4x.c:2256
COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
Definition: stm32l4x.c:2340
static const struct stm32l4_rev stm32_g07_g08xx_revs[]
Definition: stm32l4x.c:314
static const struct stm32l4_rev stm32g43_g44xx_revs[]
Definition: stm32l4x.c:342
static const struct stm32l4_rev stm32c03xx_revs[]
Definition: stm32l4x.c:302
static uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
Definition: stm32l4x.c:897
static const struct stm32l4_rev stm32wle_wl5xx_revs[]
Definition: stm32l4x.c:400
static int stm32l4_protect_same_bank(struct flash_bank *bank, enum stm32_bank_id bank_id, int set, unsigned int first, unsigned int last)
Definition: stm32l4x.c:1377
FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
Definition: stm32l4x.c:756
static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
set all FLASH_SECBB registers to the same value
Definition: stm32l4x.c:974
static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32l4x.c:1672
static const struct stm32l4_rev stm32g49_g4axx_revs[]
Definition: stm32l4x.c:363
const struct flash_driver stm32l4x_flash
Definition: stm32l4x.c:2741
static int stm32l4_probe(struct flash_bank *bank)
Definition: stm32l4x.c:1855
static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:220
static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32l4x.c:1628
static int stm32l4_read_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index, uint32_t *value)
Definition: stm32l4x.c:915
static const struct stm32l4_rev stm32u0xx_revs[]
Definition: stm32l4x.c:338
static int stm32l4_unlock_option_reg(struct flash_bank *bank)
Definition: stm32l4x.c:1059
static const uint32_t stm32wl_cpu2_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:195
static int stm32l4_unlock_reg(struct flash_bank *bank)
Definition: stm32l4x.c:1023
static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
Definition: stm32l4x.c:1262
static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
Definition: stm32l4x.c:868
static const struct stm32l4_rev stm32wb3xx_revs[]
Definition: stm32l4x.c:396
#define FLASH_WRITE_TIMEOUT
Definition: stm32l4x.c:138
static const struct stm32l4_rev stm32wb5xx_revs[]
Definition: stm32l4x.c:392
static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits, struct range *ranges, unsigned int *ranges_count)
Definition: stm32l4x.c:785
static const struct stm32l4_rev stm32u5f_u5gxx_revs[]
Definition: stm32l4x.c:380
static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM]
Definition: stm32l4x.c:207
static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: stm32l4x.c:1503
static int stm32l4_write_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index, uint32_t value)
Definition: stm32l4x.c:927
static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
Definition: stm32l4x.c:1468
static uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index)
Definition: stm32l4x.c:903
static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
Definition: stm32l4x.c:1250
static const struct stm32l4_rev stm32l49_l4axx_revs[]
Definition: stm32l4x.c:318
static int stm32l4_auto_probe(struct flash_bank *bank)
Definition: stm32l4x.c:2227
static const struct stm32l4_rev stm32g0b_g0cxx_revs[]
Definition: stm32l4x.c:334
#define DEVID_STM32G03_G04XX
Definition: stm32l4x.h:99
#define DEVID_STM32L55_L56XX
Definition: stm32l4x.h:105
#define DBGMCU_IDCODE_G0
Definition: stm32l4x.h:80
#define DEVID_STM32G0B_G0CXX
Definition: stm32l4x.h:100
#define FLASH_L5_DB256
Definition: stm32l4x.h:68
#define FLASH_SECBB_SECURE
Definition: stm32l4x.h:76
#define DBGMCU_IDCODE_L5
Definition: stm32l4x.h:82
#define FLASH_G0_DUAL_BANK
Definition: stm32l4x.h:62
#define STM32_FLASH_S_BANK_BASE
Definition: stm32l4x.h:120
#define DEVID_STM32G49_G4AXX
Definition: stm32l4x.h:107
#define DEVID_STM32WBA5X
Definition: stm32l4x.h:111
#define DEVID_STM32WB1XX
Definition: stm32l4x.h:113
#define DEVID_STM32C03XX
Definition: stm32l4x.h:91
#define FLASH_OPTSTRT
Definition: stm32l4x.h:30
#define FLASH_SECBB2(X)
Definition: stm32l4x.h:74
#define DEVID_STM32U53_U54XX
Definition: stm32l4x.h:92
#define DEVID_STM32L4R_L4SXX
Definition: stm32l4x.h:103
#define UID64_IDS
Definition: stm32l4x.h:84
#define FLASH_L5_DBANK
Definition: stm32l4x.h:67
#define FLASH_L4_DUAL_BANK
Definition: stm32l4x.h:64
#define FLASH_PAGE_SHIFT
Definition: stm32l4x.h:25
#define DEVID_STM32G47_G48XX
Definition: stm32l4x.h:102
#define FLASH_U5_DUALBANK
Definition: stm32l4x.h:69
#define DEVID_STM32U5F_U5GXX
Definition: stm32l4x.h:106
#define STM32_FLASH_BANK_BASE
Definition: stm32l4x.h:119
#define FLASH_G4_DUAL_BANK
Definition: stm32l4x.h:63
#define DEVID_STM32L47_L48XX
Definition: stm32l4x.h:88
#define DEVID_STM32G07_G08XX
Definition: stm32l4x.h:95
#define DEVID_STM32C071XX
Definition: stm32l4x.h:112
#define DEVID_STM32WB5XX
Definition: stm32l4x.h:114
#define DEVID_STM32U59_U5AXX
Definition: stm32l4x.h:108
#define DEVID_STM32L49_L4AXX
Definition: stm32l4x.h:96
#define DEVID_STM32L43_L44XX
Definition: stm32l4x.h:89
#define FLASH_RDP_MASK
Definition: stm32l4x.h:61
#define DEVID_STM32L41_L42XX
Definition: stm32l4x.h:98
#define DEVID_STM32U073_U083XX
Definition: stm32l4x.h:110
#define DEVID_STM32WLE_WL5XX
Definition: stm32l4x.h:116
#define FLASH_L4R_DBANK
Definition: stm32l4x.h:65
#define DEVID_STM32G05_G06XX
Definition: stm32l4x.h:93
#define LDR_STACK_SIZE
Definition: stm32l4x.h:126
#define DEVID_STM32U031XX
Definition: stm32l4x.h:94
#define FLASH_OPTLOCK
Definition: stm32l4x.h:34
#define DEVID_STM32WB3XX
Definition: stm32l4x.h:115
#define FLASH_TZEN
Definition: stm32l4x.h:70
#define DEVID_STM32G43_G44XX
Definition: stm32l4x.h:101
#define UID64_IDS_STM32WL
Definition: stm32l4x.h:85
#define FLASH_BSY2
Definition: stm32l4x.h:39
#define FLASH_SECBB_NON_SECURE
Definition: stm32l4x.h:77
#define STM32L5_REGS_SEC_OFFSET
Definition: stm32l4x.h:123
#define FLASH_SECBB1(X)
Definition: stm32l4x.h:73
#define FLASH_BKER_G0
Definition: stm32l4x.h:27
#define DEVID_STM32U57_U58XX
Definition: stm32l4x.h:109
#define DBGMCU_IDCODE_L4_G4
Definition: stm32l4x.h:81
#define DEVID_STM32L4P_L4QXX
Definition: stm32l4x.h:104
#define FLASH_LRR_DB1M
Definition: stm32l4x.h:66
#define FLASH_BKER
Definition: stm32l4x.h:26
#define DEVID_STM32C01XX
Definition: stm32l4x.h:90
#define DEVID_STM32L45_L46XX
Definition: stm32l4x.h:97
#define FLASH_MER2
Definition: stm32l4x.h:28
uint64_t ap_num
ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coheren...
Definition: arm_adi_v5.h:261
unsigned int common_magic
Definition: armv7m.h:299
enum arm_mode core_mode
Definition: armv7m.h:301
struct adiv5_ap * debug_ap
Definition: armv7m.h:234
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
const char * name
Definition: command.h:235
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
Describes the geometry and status of a single flash sector within a flash bank.
Definition: nor/core.h:28
uint32_t offset
Bus offset from start of the flash chip (in bytes).
Definition: nor/core.h:30
uint32_t size
Number of bytes in this flash sector.
Definition: nor/core.h:32
unsigned int start
Definition: stm32l4x.c:781
unsigned int end
Definition: stm32l4x.c:782
unsigned int bank1_sectors
Definition: stm32l4x.c:254
uint32_t wrpxxr_mask
Definition: stm32l4x.c:261
uint32_t user_bank_size
Definition: stm32l4x.c:257
const uint32_t * flash_regs
Definition: stm32l4x.c:264
uint32_t flash_regs_base
Definition: stm32l4x.c:263
enum stm32l4_rdp rdp
Definition: stm32l4x.c:266
uint32_t idcode
Definition: stm32l4x.c:253
uint32_t cr_bker_mask
Definition: stm32l4x.c:259
uint32_t data_width
Definition: stm32l4x.c:258
const struct stm32l4_part_info * part_info
Definition: stm32l4x.c:262
uint32_t sr_bsy_mask
Definition: stm32l4x.c:260
const uint32_t otp_size
Definition: stm32l4x.c:248
const struct stm32l4_rev * revs
Definition: stm32l4x.c:241
const char * device_str
Definition: stm32l4x.c:240
const uint32_t fsize_addr
Definition: stm32l4x.c:246
const uint32_t flash_regs_base
Definition: stm32l4x.c:245
const uint32_t flags
Definition: stm32l4x.c:244
const uint32_t otp_base
Definition: stm32l4x.c:247
const size_t num_revs
Definition: stm32l4x.c:242
const uint16_t max_flash_size_kb
Definition: stm32l4x.c:243
const char * str
Definition: stm32l4x.c:235
const uint16_t rev
Definition: stm32l4x.c:234
uint8_t stack[LDR_STACK_SIZE]
Definition: stm32l4x.h:135
bool used
Definition: stm32l4x.c:280
enum stm32l4_flash_reg_index reg_idx
Definition: stm32l4x.c:278
int offset
Definition: stm32l4x.c:283
uint32_t value
Definition: stm32l4x.c:279
Definition: target.h:116
enum target_state state
Definition: target.h:157
Definition: psoc6.c:83
target_addr_t address
Definition: target.h:86
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
Definition: target.c:352
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2343
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1266
uint32_t target_get_working_area_avail(struct target *target)
Definition: target.c:2165
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2061
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2642
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2119
int target_alloc_working_area_try(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:1967
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
Definition: target.c:2575
int target_run_flash_async_algorithm(struct target *target, const uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
Streams data to a circular buffer on target intended for consumption by code running asynchronously o...
Definition: target.c:931
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2551
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:790
static bool target_was_examined(const struct target *target)
Definition: target.h:436
#define ERROR_TARGET_INVALID
Definition: target.h:787
@ TARGET_HALTED
Definition: target.h:56
#define ERROR_TARGET_NOT_EXAMINED
Definition: target.h:797
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:794
#define ERROR_TARGET_FAILURE
Definition: target.h:791
#define TARGET_ADDR_FMT
Definition: types.h:342
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57
#define NULL
Definition: usb.h:16
uint8_t status[4]
Definition: vdebug.c:17
uint8_t cmd
Definition: vdebug.c:1
uint8_t offset[4]
Definition: vdebug.c:9
uint8_t count[4]
Definition: vdebug.c:22