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cortex_a.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2005 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  * *
7  * Copyright (C) 2006 by Magnus Lundin *
8  * lundin@mlu.mine.nu *
9  * *
10  * Copyright (C) 2008 by Spencer Oliver *
11  * spen@spen-soft.co.uk *
12  * *
13  * Copyright (C) 2009 by Dirk Behme *
14  * dirk.behme@gmail.com - copy from cortex_m3 *
15  * *
16  * Copyright (C) 2010 Øyvind Harboe *
17  * oyvind.harboe@zylin.com *
18  * *
19  * Copyright (C) ST-Ericsson SA 2011 *
20  * michel.jaouen@stericsson.com : smp minimum support *
21  * *
22  * Copyright (C) Broadcom 2012 *
23  * ehunter@broadcom.com : Cortex-R4 support *
24  * *
25  * Copyright (C) 2013 Kamal Dasu *
26  * kdasu.kdev@gmail.com *
27  * *
28  * Copyright (C) 2016 Chengyu Zheng *
29  * chengyu.zheng@polimi.it : watchpoint support *
30  * *
31  * Cortex-A8(tm) TRM, ARM DDI 0344H *
32  * Cortex-A9(tm) TRM, ARM DDI 0407F *
33  * Cortex-A4(tm) TRM, ARM DDI 0363E *
34  * Cortex-A15(tm)TRM, ARM DDI 0438C *
35  * *
36  ***************************************************************************/
37 
38 #ifdef HAVE_CONFIG_H
39 #include "config.h"
40 #endif
41 
42 #include "breakpoints.h"
43 #include "cortex_a.h"
44 #include "register.h"
45 #include "armv7a_mmu.h"
46 #include "target_request.h"
47 #include "target_type.h"
48 #include "arm_coresight.h"
49 #include "arm_opcodes.h"
50 #include "arm_semihosting.h"
51 #include "jtag/interface.h"
52 #include "transport/transport.h"
53 #include "smp.h"
54 #include <helper/bits.h>
55 #include <helper/nvp.h>
56 #include <helper/time_support.h>
57 
58 static int cortex_a_poll(struct target *target);
59 static int cortex_a_debug_entry(struct target *target);
60 static int cortex_a_restore_context(struct target *target, bool bpwp);
61 static int cortex_a_set_breakpoint(struct target *target,
62  struct breakpoint *breakpoint, uint8_t matchmode);
64  struct breakpoint *breakpoint, uint8_t matchmode);
66  struct breakpoint *breakpoint);
67 static int cortex_a_unset_breakpoint(struct target *target,
68  struct breakpoint *breakpoint);
69 static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
70  uint32_t value, uint32_t *dscr);
71 static int cortex_a_mmu(struct target *target, int *enabled);
72 static int cortex_a_mmu_modify(struct target *target, int enable);
73 static int cortex_a_virt2phys(struct target *target,
74  target_addr_t virt, target_addr_t *phys);
75 static int cortex_a_read_cpu_memory(struct target *target,
76  uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
77 
78 static unsigned int ilog2(unsigned int x)
79 {
80  unsigned int y = 0;
81  x /= 2;
82  while (x) {
83  ++y;
84  x /= 2;
85  }
86  return y;
87 }
88 
89 /* restore cp15_control_reg at resume */
91 {
92  int retval = ERROR_OK;
93  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
94  struct armv7a_common *armv7a = target_to_armv7a(target);
95 
96  if (cortex_a->cp15_control_reg != cortex_a->cp15_control_reg_curr) {
97  cortex_a->cp15_control_reg_curr = cortex_a->cp15_control_reg;
98  /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
99  retval = armv7a->arm.mcr(target, 15,
100  0, 0, /* op1, op2 */
101  1, 0, /* CRn, CRm */
102  cortex_a->cp15_control_reg);
103  }
104  return retval;
105 }
106 
107 /*
108  * Set up ARM core for memory access.
109  * If !phys_access, switch to SVC mode and make sure MMU is on
110  * If phys_access, switch off mmu
111  */
112 static int cortex_a_prep_memaccess(struct target *target, int phys_access)
113 {
114  struct armv7a_common *armv7a = target_to_armv7a(target);
115  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
116  int mmu_enabled = 0;
117 
118  if (phys_access == 0) {
120  cortex_a_mmu(target, &mmu_enabled);
121  if (mmu_enabled)
123  if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
124  /* overwrite DACR to all-manager */
125  armv7a->arm.mcr(target, 15,
126  0, 0, 3, 0,
127  0xFFFFFFFF);
128  }
129  } else {
130  cortex_a_mmu(target, &mmu_enabled);
131  if (mmu_enabled)
133  }
134  return ERROR_OK;
135 }
136 
137 /*
138  * Restore ARM core after memory access.
139  * If !phys_access, switch to previous mode
140  * If phys_access, restore MMU setting
141  */
142 static int cortex_a_post_memaccess(struct target *target, int phys_access)
143 {
144  struct armv7a_common *armv7a = target_to_armv7a(target);
145  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
146 
147  if (phys_access == 0) {
148  if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
149  /* restore */
150  armv7a->arm.mcr(target, 15,
151  0, 0, 3, 0,
152  cortex_a->cp15_dacr_reg);
153  }
155  } else {
156  int mmu_enabled = 0;
157  cortex_a_mmu(target, &mmu_enabled);
158  if (mmu_enabled)
160  }
161  return ERROR_OK;
162 }
163 
164 
165 /* modify cp15_control_reg in order to enable or disable mmu for :
166  * - virt2phys address conversion
167  * - read or write memory in phys or virt address */
168 static int cortex_a_mmu_modify(struct target *target, int enable)
169 {
170  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
171  struct armv7a_common *armv7a = target_to_armv7a(target);
172  int retval = ERROR_OK;
173  int need_write = 0;
174 
175  if (enable) {
176  /* if mmu enabled at target stop and mmu not enable */
177  if (!(cortex_a->cp15_control_reg & 0x1U)) {
178  LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
179  return ERROR_FAIL;
180  }
181  if ((cortex_a->cp15_control_reg_curr & 0x1U) == 0) {
182  cortex_a->cp15_control_reg_curr |= 0x1U;
183  need_write = 1;
184  }
185  } else {
186  if ((cortex_a->cp15_control_reg_curr & 0x1U) == 0x1U) {
187  cortex_a->cp15_control_reg_curr &= ~0x1U;
188  need_write = 1;
189  }
190  }
191 
192  if (need_write) {
193  LOG_DEBUG("%s, writing cp15 ctrl: %" PRIx32,
194  enable ? "enable mmu" : "disable mmu",
195  cortex_a->cp15_control_reg_curr);
196 
197  retval = armv7a->arm.mcr(target, 15,
198  0, 0, /* op1, op2 */
199  1, 0, /* CRn, CRm */
200  cortex_a->cp15_control_reg_curr);
201  }
202  return retval;
203 }
204 
205 /*
206  * Cortex-A Basic debug access, very low level assumes state is saved
207  */
209 {
210  struct armv7a_common *armv7a = target_to_armv7a(target);
211  uint32_t dscr;
212  int retval;
213 
214  /* lock memory-mapped access to debug registers to prevent
215  * software interference */
216  retval = mem_ap_write_u32(armv7a->debug_ap,
217  armv7a->debug_base + CPUDBG_LOCKACCESS, 0);
218  if (retval != ERROR_OK)
219  return retval;
220 
221  /* Disable cacheline fills and force cache write-through in debug state */
222  retval = mem_ap_write_u32(armv7a->debug_ap,
223  armv7a->debug_base + CPUDBG_DSCCR, 0);
224  if (retval != ERROR_OK)
225  return retval;
226 
227  /* Disable TLB lookup and refill/eviction in debug state */
228  retval = mem_ap_write_u32(armv7a->debug_ap,
229  armv7a->debug_base + CPUDBG_DSMCR, 0);
230  if (retval != ERROR_OK)
231  return retval;
232 
233  retval = dap_run(armv7a->debug_ap->dap);
234  if (retval != ERROR_OK)
235  return retval;
236 
237  /* Enabling of instruction execution in debug mode is done in debug_entry code */
238 
239  /* Resync breakpoint registers */
240 
241  /* Enable halt for breakpoint, watchpoint and vector catch */
242  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
243  armv7a->debug_base + CPUDBG_DSCR, &dscr);
244  if (retval != ERROR_OK)
245  return retval;
246  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
247  armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
248  if (retval != ERROR_OK)
249  return retval;
250 
251  /* Since this is likely called from init or reset, update target state information*/
252  return cortex_a_poll(target);
253 }
254 
255 static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool force)
256 {
257  /* Waits until InstrCmpl_l becomes 1, indicating instruction is done.
258  * Writes final value of DSCR into *dscr. Pass force to force always
259  * reading DSCR at least once. */
260  struct armv7a_common *armv7a = target_to_armv7a(target);
261  int retval;
262 
263  if (force) {
264  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
265  armv7a->debug_base + CPUDBG_DSCR, dscr);
266  if (retval != ERROR_OK) {
267  LOG_ERROR("Could not read DSCR register");
268  return retval;
269  }
270  }
271 
273  if (retval != ERROR_OK)
274  LOG_ERROR("Error waiting for InstrCompl=1");
275  return retval;
276 }
277 
278 /* To reduce needless round-trips, pass in a pointer to the current
279  * DSCR value. Initialize it to zero if you just need to know the
280  * value on return from this function; or DSCR_INSTR_COMP if you
281  * happen to know that no instruction is pending.
282  */
283 static int cortex_a_exec_opcode(struct target *target,
284  uint32_t opcode, uint32_t *dscr_p)
285 {
286  uint32_t dscr;
287  int retval;
288  struct armv7a_common *armv7a = target_to_armv7a(target);
289 
290  dscr = dscr_p ? *dscr_p : 0;
291 
292  LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
293 
294  /* Wait for InstrCompl bit to be set */
295  retval = cortex_a_wait_instrcmpl(target, dscr_p, false);
296  if (retval != ERROR_OK)
297  return retval;
298 
299  retval = mem_ap_write_u32(armv7a->debug_ap,
300  armv7a->debug_base + CPUDBG_ITR, opcode);
301  if (retval != ERROR_OK)
302  return retval;
303 
304  /* Wait for InstrCompl bit to be set */
305  retval = cortex_a_wait_instrcmpl(target, &dscr, true);
306  if (retval != ERROR_OK) {
307  LOG_ERROR("Error waiting for cortex_a_exec_opcode");
308  return retval;
309  }
310 
311  if (dscr_p)
312  *dscr_p = dscr;
313 
314  return retval;
315 }
316 
317 /*
318  * Cortex-A implementation of Debug Programmer's Model
319  *
320  * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
321  * so there's no need to poll for it before executing an instruction.
322  *
323  * NOTE that in several of these cases the "stall" mode might be useful.
324  * It'd let us queue a few operations together... prepare/finish might
325  * be the places to enable/disable that mode.
326  */
327 
328 static inline struct cortex_a_common *dpm_to_a(struct arm_dpm *dpm)
329 {
330  return container_of(dpm, struct cortex_a_common, armv7a_common.dpm);
331 }
332 
333 static int cortex_a_write_dcc(struct cortex_a_common *a, uint32_t data)
334 {
335  LOG_DEBUG("write DCC 0x%08" PRIx32, data);
338 }
339 
340 static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
341  uint32_t *dscr_p)
342 {
343  uint32_t dscr = DSCR_INSTR_COMP;
344  int retval;
345 
346  if (dscr_p)
347  dscr = *dscr_p;
348 
349  /* Wait for DTRRXfull */
352  if (retval != ERROR_OK) {
353  LOG_ERROR("Error waiting for read dcc");
354  return retval;
355  }
356 
359  if (retval != ERROR_OK)
360  return retval;
361  /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
362 
363  if (dscr_p)
364  *dscr_p = dscr;
365 
366  return retval;
367 }
368 
369 static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
370 {
371  struct cortex_a_common *a = dpm_to_a(dpm);
372  uint32_t dscr;
373  int retval;
374 
375  /* set up invariant: INSTR_COMP is set after ever DPM operation */
376  retval = cortex_a_wait_instrcmpl(dpm->arm->target, &dscr, true);
377  if (retval != ERROR_OK) {
378  LOG_ERROR("Error waiting for dpm prepare");
379  return retval;
380  }
381 
382  /* this "should never happen" ... */
383  if (dscr & DSCR_DTR_RX_FULL) {
384  LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
385  /* Clear DCCRX */
386  retval = cortex_a_exec_opcode(
388  ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
389  &dscr);
390  if (retval != ERROR_OK)
391  return retval;
392  }
393 
394  return retval;
395 }
396 
397 static int cortex_a_dpm_finish(struct arm_dpm *dpm)
398 {
399  /* REVISIT what could be done here? */
400  return ERROR_OK;
401 }
402 
403 static int cortex_a_instr_write_data_dcc(struct arm_dpm *dpm,
404  uint32_t opcode, uint32_t data)
405 {
406  struct cortex_a_common *a = dpm_to_a(dpm);
407  int retval;
408  uint32_t dscr = DSCR_INSTR_COMP;
409 
410  retval = cortex_a_write_dcc(a, data);
411  if (retval != ERROR_OK)
412  return retval;
413 
414  return cortex_a_exec_opcode(
416  opcode,
417  &dscr);
418 }
419 
421  uint8_t rt, uint32_t data)
422 {
423  struct cortex_a_common *a = dpm_to_a(dpm);
424  uint32_t dscr = DSCR_INSTR_COMP;
425  int retval;
426 
427  if (rt > 15)
428  return ERROR_TARGET_INVALID;
429 
430  retval = cortex_a_write_dcc(a, data);
431  if (retval != ERROR_OK)
432  return retval;
433 
434  /* DCCRX to Rt, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
435  return cortex_a_exec_opcode(
437  ARMV4_5_MRC(14, 0, rt, 0, 5, 0),
438  &dscr);
439 }
440 
441 static int cortex_a_instr_write_data_r0(struct arm_dpm *dpm,
442  uint32_t opcode, uint32_t data)
443 {
444  struct cortex_a_common *a = dpm_to_a(dpm);
445  uint32_t dscr = DSCR_INSTR_COMP;
446  int retval;
447 
448  retval = cortex_a_instr_write_data_rt_dcc(dpm, 0, data);
449  if (retval != ERROR_OK)
450  return retval;
451 
452  /* then the opcode, taking data from R0 */
453  retval = cortex_a_exec_opcode(
455  opcode,
456  &dscr);
457 
458  return retval;
459 }
460 
462  uint32_t opcode, uint64_t data)
463 {
464  struct cortex_a_common *a = dpm_to_a(dpm);
465  uint32_t dscr = DSCR_INSTR_COMP;
466  int retval;
467 
468  retval = cortex_a_instr_write_data_rt_dcc(dpm, 0, data & 0xffffffffULL);
469  if (retval != ERROR_OK)
470  return retval;
471 
472  retval = cortex_a_instr_write_data_rt_dcc(dpm, 1, data >> 32);
473  if (retval != ERROR_OK)
474  return retval;
475 
476  /* then the opcode, taking data from R0, R1 */
478  opcode,
479  &dscr);
480  return retval;
481 }
482 
483 static int cortex_a_instr_cpsr_sync(struct arm_dpm *dpm)
484 {
485  struct target *target = dpm->arm->target;
486  uint32_t dscr = DSCR_INSTR_COMP;
487 
488  /* "Prefetch flush" after modifying execution status in CPSR */
490  ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
491  &dscr);
492 }
493 
494 static int cortex_a_instr_read_data_dcc(struct arm_dpm *dpm,
495  uint32_t opcode, uint32_t *data)
496 {
497  struct cortex_a_common *a = dpm_to_a(dpm);
498  int retval;
499  uint32_t dscr = DSCR_INSTR_COMP;
500 
501  /* the opcode, writing data to DCC */
502  retval = cortex_a_exec_opcode(
504  opcode,
505  &dscr);
506  if (retval != ERROR_OK)
507  return retval;
508 
509  return cortex_a_read_dcc(a, data, &dscr);
510 }
511 
513  uint8_t rt, uint32_t *data)
514 {
515  struct cortex_a_common *a = dpm_to_a(dpm);
516  uint32_t dscr = DSCR_INSTR_COMP;
517  int retval;
518 
519  if (rt > 15)
520  return ERROR_TARGET_INVALID;
521 
522  retval = cortex_a_exec_opcode(
524  ARMV4_5_MCR(14, 0, rt, 0, 5, 0),
525  &dscr);
526  if (retval != ERROR_OK)
527  return retval;
528 
529  return cortex_a_read_dcc(a, data, &dscr);
530 }
531 
532 static int cortex_a_instr_read_data_r0(struct arm_dpm *dpm,
533  uint32_t opcode, uint32_t *data)
534 {
535  struct cortex_a_common *a = dpm_to_a(dpm);
536  uint32_t dscr = DSCR_INSTR_COMP;
537  int retval;
538 
539  /* the opcode, writing data to R0 */
540  retval = cortex_a_exec_opcode(
542  opcode,
543  &dscr);
544  if (retval != ERROR_OK)
545  return retval;
546 
547  /* write R0 to DCC */
548  return cortex_a_instr_read_data_rt_dcc(dpm, 0, data);
549 }
550 
552  uint32_t opcode, uint64_t *data)
553 {
554  uint32_t lo, hi;
555  int retval;
556 
557  /* the opcode, writing data to RO, R1 */
558  retval = cortex_a_instr_read_data_r0(dpm, opcode, &lo);
559  if (retval != ERROR_OK)
560  return retval;
561 
562  *data = lo;
563 
564  /* write R1 to DCC */
565  retval = cortex_a_instr_read_data_rt_dcc(dpm, 1, &hi);
566  if (retval != ERROR_OK)
567  return retval;
568 
569  *data |= (uint64_t)hi << 32;
570 
571  return retval;
572 }
573 
574 static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t,
575  uint32_t addr, uint32_t control)
576 {
577  struct cortex_a_common *a = dpm_to_a(dpm);
578  uint32_t vr = a->armv7a_common.debug_base;
579  uint32_t cr = a->armv7a_common.debug_base;
580  int retval;
581 
582  switch (index_t) {
583  case 0 ... 15: /* breakpoints */
584  vr += CPUDBG_BVR_BASE;
585  cr += CPUDBG_BCR_BASE;
586  break;
587  case 16 ... 31: /* watchpoints */
588  vr += CPUDBG_WVR_BASE;
589  cr += CPUDBG_WCR_BASE;
590  index_t -= 16;
591  break;
592  default:
593  return ERROR_FAIL;
594  }
595  vr += 4 * index_t;
596  cr += 4 * index_t;
597 
598  LOG_DEBUG("A: bpwp enable, vr %08" PRIx32 " cr %08" PRIx32, vr, cr);
599 
601  vr, addr);
602  if (retval != ERROR_OK)
603  return retval;
605  cr, control);
606  return retval;
607 }
608 
609 static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t)
610 {
611  struct cortex_a_common *a = dpm_to_a(dpm);
612  uint32_t cr;
613 
614  switch (index_t) {
615  case 0 ... 15:
617  break;
618  case 16 ... 31:
620  index_t -= 16;
621  break;
622  default:
623  return ERROR_FAIL;
624  }
625  cr += 4 * index_t;
626 
627  LOG_DEBUG("A: bpwp disable, cr %08" PRIx32, cr);
628 
629  /* clear control register */
631 }
632 
633 static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr)
634 {
635  struct arm_dpm *dpm = &a->armv7a_common.dpm;
636  int retval;
637 
638  dpm->arm = &a->armv7a_common.arm;
639  dpm->didr = didr;
640 
643 
648 
652 
655 
656  retval = arm_dpm_setup(dpm);
657  if (retval == ERROR_OK)
658  retval = arm_dpm_initialize(dpm);
659 
660  return retval;
661 }
662 static struct target *get_cortex_a(struct target *target, int32_t coreid)
663 {
664  struct target_list *head;
665 
667  struct target *curr = head->target;
668  if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
669  return curr;
670  }
671  return target;
672 }
673 static int cortex_a_halt(struct target *target);
674 
675 static int cortex_a_halt_smp(struct target *target)
676 {
677  int retval = 0;
678  struct target_list *head;
679 
681  struct target *curr = head->target;
682  if ((curr != target) && (curr->state != TARGET_HALTED)
683  && target_was_examined(curr))
684  retval += cortex_a_halt(curr);
685  }
686  return retval;
687 }
688 
689 static int update_halt_gdb(struct target *target)
690 {
691  struct target *gdb_target = NULL;
692  struct target_list *head;
693  struct target *curr;
694  int retval = 0;
695 
696  if (target->gdb_service && target->gdb_service->core[0] == -1) {
699  retval += cortex_a_halt_smp(target);
700  }
701 
702  if (target->gdb_service)
703  gdb_target = target->gdb_service->target;
704 
706  curr = head->target;
707  /* skip calling context */
708  if (curr == target)
709  continue;
710  if (!target_was_examined(curr))
711  continue;
712  /* skip targets that were already halted */
713  if (curr->state == TARGET_HALTED)
714  continue;
715  /* Skip gdb_target; it alerts GDB so has to be polled as last one */
716  if (curr == gdb_target)
717  continue;
718 
719  /* avoid recursion in cortex_a_poll() */
720  curr->smp = 0;
721  cortex_a_poll(curr);
722  curr->smp = 1;
723  }
724 
725  /* after all targets were updated, poll the gdb serving target */
726  if (gdb_target && gdb_target != target)
727  cortex_a_poll(gdb_target);
728  return retval;
729 }
730 
731 /*
732  * Cortex-A Run control
733  */
734 
735 static int cortex_a_poll(struct target *target)
736 {
737  int retval = ERROR_OK;
738  uint32_t dscr;
739  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
740  struct armv7a_common *armv7a = &cortex_a->armv7a_common;
741  enum target_state prev_target_state = target->state;
742  /* toggle to another core is done by gdb as follow */
743  /* maint packet J core_id */
744  /* continue */
745  /* the next polling trigger an halt event sent to gdb */
746  if ((target->state == TARGET_HALTED) && (target->smp) &&
747  (target->gdb_service) &&
748  (!target->gdb_service->target)) {
752  return retval;
753  }
754  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
755  armv7a->debug_base + CPUDBG_DSCR, &dscr);
756  if (retval != ERROR_OK)
757  return retval;
758  cortex_a->cpudbg_dscr = dscr;
759 
761  if (prev_target_state != TARGET_HALTED) {
762  /* We have a halting debug event */
763  LOG_DEBUG("Target halted");
765 
766  retval = cortex_a_debug_entry(target);
767  if (retval != ERROR_OK)
768  return retval;
769 
770  if (target->smp) {
771  retval = update_halt_gdb(target);
772  if (retval != ERROR_OK)
773  return retval;
774  }
775 
776  if (prev_target_state == TARGET_DEBUG_RUNNING) {
778  } else { /* prev_target_state is RUNNING, UNKNOWN or RESET */
779  if (arm_semihosting(target, &retval) != 0)
780  return retval;
781 
784  }
785  }
786  } else
788 
789  return retval;
790 }
791 
792 static int cortex_a_halt(struct target *target)
793 {
794  int retval;
795  uint32_t dscr;
796  struct armv7a_common *armv7a = target_to_armv7a(target);
797 
798  /*
799  * Tell the core to be halted by writing DRCR with 0x1
800  * and then wait for the core to be halted.
801  */
802  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
803  armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
804  if (retval != ERROR_OK)
805  return retval;
806 
807  dscr = 0; /* force read of dscr */
809  DSCR_CORE_HALTED, &dscr);
810  if (retval != ERROR_OK) {
811  LOG_ERROR("Error waiting for halt");
812  return retval;
813  }
814 
816 
817  return ERROR_OK;
818 }
819 
820 static int cortex_a_internal_restore(struct target *target, int current,
821  target_addr_t *address, int handle_breakpoints, int debug_execution)
822 {
823  struct armv7a_common *armv7a = target_to_armv7a(target);
824  struct arm *arm = &armv7a->arm;
825  int retval;
826  uint32_t resume_pc;
827 
828  if (!debug_execution)
830 
831 #if 0
832  if (debug_execution) {
833  /* Disable interrupts */
834  /* We disable interrupts in the PRIMASK register instead of
835  * masking with C_MASKINTS,
836  * This is probably the same issue as Cortex-M3 Errata 377493:
837  * C_MASKINTS in parallel with disabled interrupts can cause
838  * local faults to not be taken. */
839  buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
840  armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = true;
841  armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = true;
842 
843  /* Make sure we are in Thumb mode */
844  buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_XPSR].value, 0, 32,
845  buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_XPSR].value, 0,
846  32) | (1 << 24));
847  armv7m->core_cache->reg_list[ARMV7M_XPSR].dirty = true;
848  armv7m->core_cache->reg_list[ARMV7M_XPSR].valid = true;
849  }
850 #endif
851 
852  /* current = 1: continue on current pc, otherwise continue at <address> */
853  resume_pc = buf_get_u32(arm->pc->value, 0, 32);
854  if (!current)
855  resume_pc = *address;
856  else
857  *address = resume_pc;
858 
859  /* Make sure that the Armv7 gdb thumb fixups does not
860  * kill the return address
861  */
862  switch (arm->core_state) {
863  case ARM_STATE_ARM:
864  resume_pc &= 0xFFFFFFFC;
865  break;
866  case ARM_STATE_THUMB:
867  case ARM_STATE_THUMB_EE:
868  /* When the return address is loaded into PC
869  * bit 0 must be 1 to stay in Thumb state
870  */
871  resume_pc |= 0x1;
872  break;
873  case ARM_STATE_JAZELLE:
874  LOG_ERROR("How do I resume into Jazelle state??");
875  return ERROR_FAIL;
876  case ARM_STATE_AARCH64:
877  LOG_ERROR("Shouldn't be in AARCH64 state");
878  return ERROR_FAIL;
879  }
880  LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
881  buf_set_u32(arm->pc->value, 0, 32, resume_pc);
882  arm->pc->dirty = true;
883  arm->pc->valid = true;
884 
885  /* restore dpm_mode at system halt */
887  /* called it now before restoring context because it uses cpu
888  * register r0 for restoring cp15 control register */
890  if (retval != ERROR_OK)
891  return retval;
892  retval = cortex_a_restore_context(target, handle_breakpoints);
893  if (retval != ERROR_OK)
894  return retval;
897 
898  /* registers are now invalid */
900 
901 #if 0
902  /* the front-end may request us not to handle breakpoints */
903  if (handle_breakpoints) {
904  /* Single step past breakpoint at current address */
905  breakpoint = breakpoint_find(target, resume_pc);
906  if (breakpoint) {
907  LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
908  cortex_m3_unset_breakpoint(target, breakpoint);
909  cortex_m3_single_step_core(target);
910  cortex_m3_set_breakpoint(target, breakpoint);
911  }
912  }
913 
914 #endif
915  return retval;
916 }
917 
919 {
920  struct armv7a_common *armv7a = target_to_armv7a(target);
921  struct arm *arm = &armv7a->arm;
922  int retval;
923  uint32_t dscr;
924  /*
925  * * Restart core and wait for it to be started. Clear ITRen and sticky
926  * * exception flags: see ARMv7 ARM, C5.9.
927  *
928  * REVISIT: for single stepping, we probably want to
929  * disable IRQs by default, with optional override...
930  */
931 
932  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
933  armv7a->debug_base + CPUDBG_DSCR, &dscr);
934  if (retval != ERROR_OK)
935  return retval;
936 
937  if ((dscr & DSCR_INSTR_COMP) == 0)
938  LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
939 
940  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
941  armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
942  if (retval != ERROR_OK)
943  return retval;
944 
945  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
946  armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART |
948  if (retval != ERROR_OK)
949  return retval;
950 
951  dscr = 0; /* force read of dscr */
953  DSCR_CORE_RESTARTED, &dscr);
954  if (retval != ERROR_OK) {
955  LOG_ERROR("Error waiting for resume");
956  return retval;
957  }
958 
961 
962  /* registers are now invalid */
964 
965  return ERROR_OK;
966 }
967 
968 static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
969 {
970  int retval = 0;
971  struct target_list *head;
972  target_addr_t address;
973 
975  struct target *curr = head->target;
976  if ((curr != target) && (curr->state != TARGET_RUNNING)
977  && target_was_examined(curr)) {
978  /* resume current address , not in step mode */
979  retval += cortex_a_internal_restore(curr, 1, &address,
980  handle_breakpoints, 0);
981  retval += cortex_a_internal_restart(curr);
982  }
983  }
984  return retval;
985 }
986 
987 static int cortex_a_resume(struct target *target, int current,
988  target_addr_t address, int handle_breakpoints, int debug_execution)
989 {
990  int retval = 0;
991  /* dummy resume for smp toggle in order to reduce gdb impact */
992  if ((target->smp) && (target->gdb_service->core[1] != -1)) {
993  /* simulate a start and halt of target */
996  /* fake resume at next poll we play the target core[1], see poll*/
998  return 0;
999  }
1000  cortex_a_internal_restore(target, current, &address, handle_breakpoints, debug_execution);
1001  if (target->smp) {
1002  target->gdb_service->core[0] = -1;
1003  retval = cortex_a_restore_smp(target, handle_breakpoints);
1004  if (retval != ERROR_OK)
1005  return retval;
1006  }
1008 
1009  if (!debug_execution) {
1012  LOG_DEBUG("target resumed at " TARGET_ADDR_FMT, address);
1013  } else {
1016  LOG_DEBUG("target debug resumed at " TARGET_ADDR_FMT, address);
1017  }
1018 
1019  return ERROR_OK;
1020 }
1021 
1023 {
1024  uint32_t dscr;
1025  int retval = ERROR_OK;
1026  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1027  struct armv7a_common *armv7a = target_to_armv7a(target);
1028  struct arm *arm = &armv7a->arm;
1029 
1030  LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a->cpudbg_dscr);
1031 
1032  /* REVISIT surely we should not re-read DSCR !! */
1033  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
1034  armv7a->debug_base + CPUDBG_DSCR, &dscr);
1035  if (retval != ERROR_OK)
1036  return retval;
1037 
1038  /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
1039  * imprecise data aborts get discarded by issuing a Data
1040  * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
1041  */
1042 
1043  /* Enable the ITR execution once we are in debug mode */
1044  dscr |= DSCR_ITR_EN;
1045  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1046  armv7a->debug_base + CPUDBG_DSCR, dscr);
1047  if (retval != ERROR_OK)
1048  return retval;
1049 
1050  /* Examine debug reason */
1051  arm_dpm_report_dscr(&armv7a->dpm, cortex_a->cpudbg_dscr);
1052 
1053  /* save address of instruction that triggered the watchpoint? */
1055  uint32_t wfar;
1056 
1057  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
1058  armv7a->debug_base + CPUDBG_WFAR,
1059  &wfar);
1060  if (retval != ERROR_OK)
1061  return retval;
1062  arm_dpm_report_wfar(&armv7a->dpm, wfar);
1063  }
1064 
1065  /* First load register accessible through core debug port */
1066  retval = arm_dpm_read_current_registers(&armv7a->dpm);
1067  if (retval != ERROR_OK)
1068  return retval;
1069 
1070  if (arm->spsr) {
1071  /* read SPSR */
1072  retval = arm_dpm_read_reg(&armv7a->dpm, arm->spsr, 17);
1073  if (retval != ERROR_OK)
1074  return retval;
1075  }
1076 
1077 #if 0
1078 /* TODO, Move this */
1079  uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
1080  cortex_a_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
1081  LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register);
1082 
1083  cortex_a_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
1084  LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
1085 
1086  cortex_a_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
1087  LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
1088 #endif
1089 
1090  /* Are we in an exception handler */
1091 /* armv4_5->exception_number = 0; */
1092  if (armv7a->post_debug_entry) {
1093  retval = armv7a->post_debug_entry(target);
1094  if (retval != ERROR_OK)
1095  return retval;
1096  }
1097 
1098  return retval;
1099 }
1100 
1102 {
1103  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1104  struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1105  int retval;
1106 
1107  /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1108  retval = armv7a->arm.mrc(target, 15,
1109  0, 0, /* op1, op2 */
1110  1, 0, /* CRn, CRm */
1111  &cortex_a->cp15_control_reg);
1112  if (retval != ERROR_OK)
1113  return retval;
1114  LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg);
1115  cortex_a->cp15_control_reg_curr = cortex_a->cp15_control_reg;
1116 
1117  if (!armv7a->is_armv7r)
1119 
1120  if (armv7a->armv7a_mmu.armv7a_cache.info == -1)
1122 
1123  if (armv7a->is_armv7r) {
1124  armv7a->armv7a_mmu.mmu_enabled = 0;
1125  } else {
1126  armv7a->armv7a_mmu.mmu_enabled =
1127  (cortex_a->cp15_control_reg & 0x1U) ? 1 : 0;
1128  }
1130  (cortex_a->cp15_control_reg & 0x4U) ? 1 : 0;
1132  (cortex_a->cp15_control_reg & 0x1000U) ? 1 : 0;
1133  cortex_a->curr_mode = armv7a->arm.core_mode;
1134 
1135  /* switch to SVC mode to read DACR */
1136  arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
1137  armv7a->arm.mrc(target, 15,
1138  0, 0, 3, 0,
1139  &cortex_a->cp15_dacr_reg);
1140 
1141  LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32,
1142  cortex_a->cp15_dacr_reg);
1143 
1144  arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
1145  return ERROR_OK;
1146 }
1147 
1149  unsigned long bit_mask, unsigned long value)
1150 {
1151  struct armv7a_common *armv7a = target_to_armv7a(target);
1152  uint32_t dscr;
1153 
1154  /* Read DSCR */
1155  int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
1156  armv7a->debug_base + CPUDBG_DSCR, &dscr);
1157  if (retval != ERROR_OK)
1158  return retval;
1159 
1160  /* clear bitfield */
1161  dscr &= ~bit_mask;
1162  /* put new value */
1163  dscr |= value & bit_mask;
1164 
1165  /* write new DSCR */
1166  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1167  armv7a->debug_base + CPUDBG_DSCR, dscr);
1168  return retval;
1169 }
1170 
1171 static int cortex_a_step(struct target *target, int current, target_addr_t address,
1172  int handle_breakpoints)
1173 {
1174  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1175  struct armv7a_common *armv7a = target_to_armv7a(target);
1176  struct arm *arm = &armv7a->arm;
1177  struct breakpoint *breakpoint = NULL;
1178  struct breakpoint stepbreakpoint;
1179  struct reg *r;
1180  int retval;
1181 
1182  if (target->state != TARGET_HALTED) {
1183  LOG_TARGET_ERROR(target, "not halted");
1184  return ERROR_TARGET_NOT_HALTED;
1185  }
1186 
1187  /* current = 1: continue on current pc, otherwise continue at <address> */
1188  r = arm->pc;
1189  if (!current)
1190  buf_set_u32(r->value, 0, 32, address);
1191  else
1192  address = buf_get_u32(r->value, 0, 32);
1193 
1194  /* The front-end may request us not to handle breakpoints.
1195  * But since Cortex-A uses breakpoint for single step,
1196  * we MUST handle breakpoints.
1197  */
1198  handle_breakpoints = 1;
1199  if (handle_breakpoints) {
1200  breakpoint = breakpoint_find(target, address);
1201  if (breakpoint)
1203  }
1204 
1205  /* Setup single step breakpoint */
1206  stepbreakpoint.address = address;
1207  stepbreakpoint.asid = 0;
1208  stepbreakpoint.length = (arm->core_state == ARM_STATE_THUMB)
1209  ? 2 : 4;
1210  stepbreakpoint.type = BKPT_HARD;
1211  stepbreakpoint.is_set = false;
1212 
1213  /* Disable interrupts during single step if requested */
1214  if (cortex_a->isrmasking_mode == CORTEX_A_ISRMASK_ON) {
1216  if (retval != ERROR_OK)
1217  return retval;
1218  }
1219 
1220  /* Break on IVA mismatch */
1221  cortex_a_set_breakpoint(target, &stepbreakpoint, 0x04);
1222 
1224 
1225  retval = cortex_a_resume(target, 1, address, 0, 0);
1226  if (retval != ERROR_OK)
1227  return retval;
1228 
1229  int64_t then = timeval_ms();
1230  while (target->state != TARGET_HALTED) {
1231  retval = cortex_a_poll(target);
1232  if (retval != ERROR_OK)
1233  return retval;
1234  if (target->state == TARGET_HALTED)
1235  break;
1236  if (timeval_ms() > then + 1000) {
1237  LOG_ERROR("timeout waiting for target halt");
1238  return ERROR_FAIL;
1239  }
1240  }
1241 
1242  cortex_a_unset_breakpoint(target, &stepbreakpoint);
1243 
1244  /* Re-enable interrupts if they were disabled */
1245  if (cortex_a->isrmasking_mode == CORTEX_A_ISRMASK_ON) {
1247  if (retval != ERROR_OK)
1248  return retval;
1249  }
1250 
1251 
1253 
1254  if (breakpoint)
1256 
1257  if (target->state != TARGET_HALTED)
1258  LOG_DEBUG("target stepped");
1259 
1260  return ERROR_OK;
1261 }
1262 
1263 static int cortex_a_restore_context(struct target *target, bool bpwp)
1264 {
1265  struct armv7a_common *armv7a = target_to_armv7a(target);
1266 
1267  LOG_DEBUG(" ");
1268 
1269  if (armv7a->pre_restore_context)
1270  armv7a->pre_restore_context(target);
1271 
1272  return arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
1273 }
1274 
1275 /*
1276  * Cortex-A Breakpoint and watchpoint functions
1277  */
1278 
1279 /* Setup hardware Breakpoint Register Pair */
1281  struct breakpoint *breakpoint, uint8_t matchmode)
1282 {
1283  int retval;
1284  int brp_i = 0;
1285  uint32_t control;
1286  uint8_t byte_addr_select = 0x0F;
1287  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1288  struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1289  struct cortex_a_brp *brp_list = cortex_a->brp_list;
1290 
1291  if (breakpoint->is_set) {
1292  LOG_WARNING("breakpoint already set");
1293  return ERROR_OK;
1294  }
1295 
1296  if (breakpoint->type == BKPT_HARD) {
1297  while (brp_list[brp_i].used && (brp_i < cortex_a->brp_num))
1298  brp_i++;
1299  if (brp_i >= cortex_a->brp_num) {
1300  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1302  }
1303  breakpoint_hw_set(breakpoint, brp_i);
1304  if (breakpoint->length == 2)
1305  byte_addr_select = (3 << (breakpoint->address & 0x02));
1306  control = ((matchmode & 0x7) << 20)
1307  | (byte_addr_select << 5)
1308  | (3 << 1) | 1;
1309  brp_list[brp_i].used = true;
1310  brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
1311  brp_list[brp_i].control = control;
1312  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1313  armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
1314  brp_list[brp_i].value);
1315  if (retval != ERROR_OK)
1316  return retval;
1317  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1318  armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
1319  brp_list[brp_i].control);
1320  if (retval != ERROR_OK)
1321  return retval;
1322  LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1323  brp_list[brp_i].control,
1324  brp_list[brp_i].value);
1325  } else if (breakpoint->type == BKPT_SOFT) {
1326  uint8_t code[4];
1327  /* length == 2: Thumb breakpoint */
1328  if (breakpoint->length == 2)
1329  buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1330  else
1331  /* length == 3: Thumb-2 breakpoint, actual encoding is
1332  * a regular Thumb BKPT instruction but we replace a
1333  * 32bit Thumb-2 instruction, so fix-up the breakpoint
1334  * length
1335  */
1336  if (breakpoint->length == 3) {
1337  buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1338  breakpoint->length = 4;
1339  } else
1340  /* length == 4, normal ARM breakpoint */
1341  buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
1342 
1343  retval = target_read_memory(target,
1344  breakpoint->address & 0xFFFFFFFE,
1345  breakpoint->length, 1,
1347  if (retval != ERROR_OK)
1348  return retval;
1349 
1350  /* make sure data cache is cleaned & invalidated down to PoC */
1352  breakpoint->length);
1353 
1354  retval = target_write_memory(target,
1355  breakpoint->address & 0xFFFFFFFE,
1356  breakpoint->length, 1, code);
1357  if (retval != ERROR_OK)
1358  return retval;
1359 
1360  /* update i-cache at breakpoint location */
1362  breakpoint->length);
1364  breakpoint->length);
1365 
1366  breakpoint->is_set = true;
1367  }
1368 
1369  return ERROR_OK;
1370 }
1371 
1373  struct breakpoint *breakpoint, uint8_t matchmode)
1374 {
1375  int retval = ERROR_FAIL;
1376  int brp_i = 0;
1377  uint32_t control;
1378  uint8_t byte_addr_select = 0x0F;
1379  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1380  struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1381  struct cortex_a_brp *brp_list = cortex_a->brp_list;
1382 
1383  if (breakpoint->is_set) {
1384  LOG_WARNING("breakpoint already set");
1385  return retval;
1386  }
1387  /*check available context BRPs*/
1388  while ((brp_list[brp_i].used ||
1389  (brp_list[brp_i].type != BRP_CONTEXT)) && (brp_i < cortex_a->brp_num))
1390  brp_i++;
1391 
1392  if (brp_i >= cortex_a->brp_num) {
1393  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1394  return ERROR_FAIL;
1395  }
1396 
1397  breakpoint_hw_set(breakpoint, brp_i);
1398  control = ((matchmode & 0x7) << 20)
1399  | (byte_addr_select << 5)
1400  | (3 << 1) | 1;
1401  brp_list[brp_i].used = true;
1402  brp_list[brp_i].value = (breakpoint->asid);
1403  brp_list[brp_i].control = control;
1404  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1405  armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
1406  brp_list[brp_i].value);
1407  if (retval != ERROR_OK)
1408  return retval;
1409  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1410  armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
1411  brp_list[brp_i].control);
1412  if (retval != ERROR_OK)
1413  return retval;
1414  LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1415  brp_list[brp_i].control,
1416  brp_list[brp_i].value);
1417  return ERROR_OK;
1418 
1419 }
1420 
1422 {
1423  int retval = ERROR_FAIL;
1424  int brp_1 = 0; /* holds the contextID pair */
1425  int brp_2 = 0; /* holds the IVA pair */
1426  uint32_t control_ctx, control_iva;
1427  uint8_t ctx_byte_addr_select = 0x0F;
1428  uint8_t iva_byte_addr_select = 0x0F;
1429  uint8_t ctx_machmode = 0x03;
1430  uint8_t iva_machmode = 0x01;
1431  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1432  struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1433  struct cortex_a_brp *brp_list = cortex_a->brp_list;
1434 
1435  if (breakpoint->is_set) {
1436  LOG_WARNING("breakpoint already set");
1437  return retval;
1438  }
1439  /*check available context BRPs*/
1440  while ((brp_list[brp_1].used ||
1441  (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < cortex_a->brp_num))
1442  brp_1++;
1443 
1444  LOG_DEBUG("brp(CTX) found num: %d", brp_1);
1445  if (brp_1 >= cortex_a->brp_num) {
1446  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1447  return ERROR_FAIL;
1448  }
1449 
1450  while ((brp_list[brp_2].used ||
1451  (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < cortex_a->brp_num))
1452  brp_2++;
1453 
1454  LOG_DEBUG("brp(IVA) found num: %d", brp_2);
1455  if (brp_2 >= cortex_a->brp_num) {
1456  LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1457  return ERROR_FAIL;
1458  }
1459 
1460  breakpoint_hw_set(breakpoint, brp_1);
1461  breakpoint->linked_brp = brp_2;
1462  control_ctx = ((ctx_machmode & 0x7) << 20)
1463  | (brp_2 << 16)
1464  | (0 << 14)
1465  | (ctx_byte_addr_select << 5)
1466  | (3 << 1) | 1;
1467  brp_list[brp_1].used = true;
1468  brp_list[brp_1].value = (breakpoint->asid);
1469  brp_list[brp_1].control = control_ctx;
1470  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1471  armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].brpn,
1472  brp_list[brp_1].value);
1473  if (retval != ERROR_OK)
1474  return retval;
1475  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1476  armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].brpn,
1477  brp_list[brp_1].control);
1478  if (retval != ERROR_OK)
1479  return retval;
1480 
1481  control_iva = ((iva_machmode & 0x7) << 20)
1482  | (brp_1 << 16)
1483  | (iva_byte_addr_select << 5)
1484  | (3 << 1) | 1;
1485  brp_list[brp_2].used = true;
1486  brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC);
1487  brp_list[brp_2].control = control_iva;
1488  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1489  armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].brpn,
1490  brp_list[brp_2].value);
1491  if (retval != ERROR_OK)
1492  return retval;
1493  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1494  armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].brpn,
1495  brp_list[brp_2].control);
1496  if (retval != ERROR_OK)
1497  return retval;
1498 
1499  return ERROR_OK;
1500 }
1501 
1503 {
1504  int retval;
1505  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1506  struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1507  struct cortex_a_brp *brp_list = cortex_a->brp_list;
1508 
1509  if (!breakpoint->is_set) {
1510  LOG_WARNING("breakpoint not set");
1511  return ERROR_OK;
1512  }
1513 
1514  if (breakpoint->type == BKPT_HARD) {
1515  if ((breakpoint->address != 0) && (breakpoint->asid != 0)) {
1516  int brp_i = breakpoint->number;
1517  int brp_j = breakpoint->linked_brp;
1518  if (brp_i >= cortex_a->brp_num) {
1519  LOG_DEBUG("Invalid BRP number in breakpoint");
1520  return ERROR_OK;
1521  }
1522  LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1523  brp_list[brp_i].control, brp_list[brp_i].value);
1524  brp_list[brp_i].used = false;
1525  brp_list[brp_i].value = 0;
1526  brp_list[brp_i].control = 0;
1527  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1528  armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
1529  brp_list[brp_i].control);
1530  if (retval != ERROR_OK)
1531  return retval;
1532  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1533  armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
1534  brp_list[brp_i].value);
1535  if (retval != ERROR_OK)
1536  return retval;
1537  if ((brp_j < 0) || (brp_j >= cortex_a->brp_num)) {
1538  LOG_DEBUG("Invalid BRP number in breakpoint");
1539  return ERROR_OK;
1540  }
1541  LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_j,
1542  brp_list[brp_j].control, brp_list[brp_j].value);
1543  brp_list[brp_j].used = false;
1544  brp_list[brp_j].value = 0;
1545  brp_list[brp_j].control = 0;
1546  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1547  armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_j].brpn,
1548  brp_list[brp_j].control);
1549  if (retval != ERROR_OK)
1550  return retval;
1551  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1552  armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_j].brpn,
1553  brp_list[brp_j].value);
1554  if (retval != ERROR_OK)
1555  return retval;
1556  breakpoint->linked_brp = 0;
1557  breakpoint->is_set = false;
1558  return ERROR_OK;
1559 
1560  } else {
1561  int brp_i = breakpoint->number;
1562  if (brp_i >= cortex_a->brp_num) {
1563  LOG_DEBUG("Invalid BRP number in breakpoint");
1564  return ERROR_OK;
1565  }
1566  LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1567  brp_list[brp_i].control, brp_list[brp_i].value);
1568  brp_list[brp_i].used = false;
1569  brp_list[brp_i].value = 0;
1570  brp_list[brp_i].control = 0;
1571  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1572  armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
1573  brp_list[brp_i].control);
1574  if (retval != ERROR_OK)
1575  return retval;
1576  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1577  armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
1578  brp_list[brp_i].value);
1579  if (retval != ERROR_OK)
1580  return retval;
1581  breakpoint->is_set = false;
1582  return ERROR_OK;
1583  }
1584  } else {
1585 
1586  /* make sure data cache is cleaned & invalidated down to PoC */
1588  breakpoint->length);
1589 
1590  /* restore original instruction (kept in target endianness) */
1591  if (breakpoint->length == 4) {
1592  retval = target_write_memory(target,
1593  breakpoint->address & 0xFFFFFFFE,
1594  4, 1, breakpoint->orig_instr);
1595  if (retval != ERROR_OK)
1596  return retval;
1597  } else {
1598  retval = target_write_memory(target,
1599  breakpoint->address & 0xFFFFFFFE,
1600  2, 1, breakpoint->orig_instr);
1601  if (retval != ERROR_OK)
1602  return retval;
1603  }
1604 
1605  /* update i-cache at breakpoint location */
1607  breakpoint->length);
1609  breakpoint->length);
1610  }
1611  breakpoint->is_set = false;
1612 
1613  return ERROR_OK;
1614 }
1615 
1617  struct breakpoint *breakpoint)
1618 {
1619  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1620 
1621  if ((breakpoint->type == BKPT_HARD) && (cortex_a->brp_num_available < 1)) {
1622  LOG_INFO("no hardware breakpoint available");
1624  }
1625 
1626  if (breakpoint->type == BKPT_HARD)
1627  cortex_a->brp_num_available--;
1628 
1629  return cortex_a_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
1630 }
1631 
1633  struct breakpoint *breakpoint)
1634 {
1635  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1636 
1637  if ((breakpoint->type == BKPT_HARD) && (cortex_a->brp_num_available < 1)) {
1638  LOG_INFO("no hardware breakpoint available");
1640  }
1641 
1642  if (breakpoint->type == BKPT_HARD)
1643  cortex_a->brp_num_available--;
1644 
1645  return cortex_a_set_context_breakpoint(target, breakpoint, 0x02); /* asid match */
1646 }
1647 
1649  struct breakpoint *breakpoint)
1650 {
1651  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1652 
1653  if ((breakpoint->type == BKPT_HARD) && (cortex_a->brp_num_available < 1)) {
1654  LOG_INFO("no hardware breakpoint available");
1656  }
1657 
1658  if (breakpoint->type == BKPT_HARD)
1659  cortex_a->brp_num_available--;
1660 
1662 }
1663 
1664 
1666 {
1667  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1668 
1669 #if 0
1670 /* It is perfectly possible to remove breakpoints while the target is running */
1671  if (target->state != TARGET_HALTED) {
1672  LOG_WARNING("target not halted");
1673  return ERROR_TARGET_NOT_HALTED;
1674  }
1675 #endif
1676 
1677  if (breakpoint->is_set) {
1679  if (breakpoint->type == BKPT_HARD)
1680  cortex_a->brp_num_available++;
1681  }
1682 
1683 
1684  return ERROR_OK;
1685 }
1686 
1698 {
1699  int retval = ERROR_OK;
1700  int wrp_i = 0;
1701  uint32_t control;
1702  uint32_t address;
1703  uint8_t address_mask;
1704  uint8_t byte_address_select;
1705  uint8_t load_store_access_control = 0x3;
1706  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1707  struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1708  struct cortex_a_wrp *wrp_list = cortex_a->wrp_list;
1709 
1710  if (watchpoint->is_set) {
1711  LOG_WARNING("watchpoint already set");
1712  return retval;
1713  }
1714 
1715  /* check available context WRPs */
1716  while (wrp_list[wrp_i].used && (wrp_i < cortex_a->wrp_num))
1717  wrp_i++;
1718 
1719  if (wrp_i >= cortex_a->wrp_num) {
1720  LOG_ERROR("ERROR Can not find free Watchpoint Register Pair");
1721  return ERROR_FAIL;
1722  }
1723 
1724  if (watchpoint->length == 0 || watchpoint->length > 0x80000000U ||
1725  (watchpoint->length & (watchpoint->length - 1))) {
1726  LOG_WARNING("watchpoint length must be a power of 2");
1727  return ERROR_FAIL;
1728  }
1729 
1730  if (watchpoint->address & (watchpoint->length - 1)) {
1731  LOG_WARNING("watchpoint address must be aligned at length");
1732  return ERROR_FAIL;
1733  }
1734 
1735  /* FIXME: ARM DDI 0406C: address_mask is optional. What to do if it's missing? */
1736  /* handle wp length 1 and 2 through byte select */
1737  switch (watchpoint->length) {
1738  case 1:
1739  byte_address_select = BIT(watchpoint->address & 0x3);
1740  address = watchpoint->address & ~0x3;
1741  address_mask = 0;
1742  break;
1743 
1744  case 2:
1745  byte_address_select = 0x03 << (watchpoint->address & 0x2);
1746  address = watchpoint->address & ~0x3;
1747  address_mask = 0;
1748  break;
1749 
1750  case 4:
1751  byte_address_select = 0x0f;
1752  address = watchpoint->address;
1753  address_mask = 0;
1754  break;
1755 
1756  default:
1757  byte_address_select = 0xff;
1758  address = watchpoint->address;
1759  address_mask = ilog2(watchpoint->length);
1760  break;
1761  }
1762 
1763  watchpoint_set(watchpoint, wrp_i);
1764  control = (address_mask << 24) |
1765  (byte_address_select << 5) |
1766  (load_store_access_control << 3) |
1767  (0x3 << 1) | 1;
1768  wrp_list[wrp_i].used = true;
1769  wrp_list[wrp_i].value = address;
1770  wrp_list[wrp_i].control = control;
1771 
1772  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1773  armv7a->debug_base + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn,
1774  wrp_list[wrp_i].value);
1775  if (retval != ERROR_OK)
1776  return retval;
1777 
1778  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1779  armv7a->debug_base + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn,
1780  wrp_list[wrp_i].control);
1781  if (retval != ERROR_OK)
1782  return retval;
1783 
1784  LOG_DEBUG("wp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, wrp_i,
1785  wrp_list[wrp_i].control,
1786  wrp_list[wrp_i].value);
1787 
1788  return ERROR_OK;
1789 }
1790 
1800 {
1801  int retval;
1802  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1803  struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1804  struct cortex_a_wrp *wrp_list = cortex_a->wrp_list;
1805 
1806  if (!watchpoint->is_set) {
1807  LOG_WARNING("watchpoint not set");
1808  return ERROR_OK;
1809  }
1810 
1811  int wrp_i = watchpoint->number;
1812  if (wrp_i >= cortex_a->wrp_num) {
1813  LOG_DEBUG("Invalid WRP number in watchpoint");
1814  return ERROR_OK;
1815  }
1816  LOG_DEBUG("wrp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, wrp_i,
1817  wrp_list[wrp_i].control, wrp_list[wrp_i].value);
1818  wrp_list[wrp_i].used = false;
1819  wrp_list[wrp_i].value = 0;
1820  wrp_list[wrp_i].control = 0;
1821  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1822  armv7a->debug_base + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn,
1823  wrp_list[wrp_i].control);
1824  if (retval != ERROR_OK)
1825  return retval;
1826  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1827  armv7a->debug_base + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn,
1828  wrp_list[wrp_i].value);
1829  if (retval != ERROR_OK)
1830  return retval;
1831  watchpoint->is_set = false;
1832 
1833  return ERROR_OK;
1834 }
1835 
1845 {
1846  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1847 
1848  if (cortex_a->wrp_num_available < 1) {
1849  LOG_INFO("no hardware watchpoint available");
1851  }
1852 
1853  int retval = cortex_a_set_watchpoint(target, watchpoint);
1854  if (retval != ERROR_OK)
1855  return retval;
1856 
1857  cortex_a->wrp_num_available--;
1858  return ERROR_OK;
1859 }
1860 
1870 {
1871  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1872 
1873  if (watchpoint->is_set) {
1874  cortex_a->wrp_num_available++;
1876  }
1877  return ERROR_OK;
1878 }
1879 
1880 
1881 /*
1882  * Cortex-A Reset functions
1883  */
1884 
1886 {
1887  struct armv7a_common *armv7a = target_to_armv7a(target);
1888 
1889  LOG_DEBUG(" ");
1890 
1891  /* FIXME when halt is requested, make it work somehow... */
1892 
1893  /* This function can be called in "target not examined" state */
1894 
1895  /* Issue some kind of warm reset. */
1898  else if (jtag_get_reset_config() & RESET_HAS_SRST) {
1899  /* REVISIT handle "pulls" cases, if there's
1900  * hardware that needs them to work.
1901  */
1902 
1903  /*
1904  * FIXME: fix reset when transport is not JTAG. This is a temporary
1905  * work-around for release v0.10 that is not intended to stay!
1906  */
1907  if (!transport_is_jtag() ||
1910 
1911  } else {
1912  LOG_ERROR("%s: how to reset?", target_name(target));
1913  return ERROR_FAIL;
1914  }
1915 
1916  /* registers are now invalid */
1917  if (armv7a->arm.core_cache)
1919 
1921 
1922  return ERROR_OK;
1923 }
1924 
1926 {
1927  struct armv7a_common *armv7a = target_to_armv7a(target);
1928  int retval;
1929 
1930  LOG_DEBUG(" ");
1931 
1932  /* be certain SRST is off */
1934 
1935  if (target_was_examined(target)) {
1936  retval = cortex_a_poll(target);
1937  if (retval != ERROR_OK)
1938  return retval;
1939  }
1940 
1941  if (target->reset_halt) {
1942  if (target->state != TARGET_HALTED) {
1943  LOG_WARNING("%s: ran after reset and before halt ...",
1944  target_name(target));
1945  if (target_was_examined(target)) {
1946  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1947  armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
1948  if (retval != ERROR_OK)
1949  return retval;
1950  } else
1952  }
1953  }
1954 
1955  return ERROR_OK;
1956 }
1957 
1958 static int cortex_a_set_dcc_mode(struct target *target, uint32_t mode, uint32_t *dscr)
1959 {
1960  /* Changes the mode of the DCC between non-blocking, stall, and fast mode.
1961  * New desired mode must be in mode. Current value of DSCR must be in
1962  * *dscr, which is updated with new value.
1963  *
1964  * This function elides actually sending the mode-change over the debug
1965  * interface if the mode is already set as desired.
1966  */
1967  uint32_t new_dscr = (*dscr & ~DSCR_EXT_DCC_MASK) | mode;
1968  if (new_dscr != *dscr) {
1969  struct armv7a_common *armv7a = target_to_armv7a(target);
1970  int retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
1971  armv7a->debug_base + CPUDBG_DSCR, new_dscr);
1972  if (retval == ERROR_OK)
1973  *dscr = new_dscr;
1974  return retval;
1975  } else {
1976  return ERROR_OK;
1977  }
1978 }
1979 
1980 static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
1981  uint32_t value, uint32_t *dscr)
1982 {
1983  /* Waits until the specified bit(s) of DSCR take on a specified value. */
1984  struct armv7a_common *armv7a = target_to_armv7a(target);
1985  int64_t then;
1986  int retval;
1987 
1988  if ((*dscr & mask) == value)
1989  return ERROR_OK;
1990 
1991  then = timeval_ms();
1992  while (1) {
1993  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
1994  armv7a->debug_base + CPUDBG_DSCR, dscr);
1995  if (retval != ERROR_OK) {
1996  LOG_ERROR("Could not read DSCR register");
1997  return retval;
1998  }
1999  if ((*dscr & mask) == value)
2000  break;
2001  if (timeval_ms() > then + 1000) {
2002  LOG_ERROR("timeout waiting for DSCR bit change");
2003  return ERROR_FAIL;
2004  }
2005  }
2006  return ERROR_OK;
2007 }
2008 
2009 static int cortex_a_read_copro(struct target *target, uint32_t opcode,
2010  uint32_t *data, uint32_t *dscr)
2011 {
2012  int retval;
2013  struct armv7a_common *armv7a = target_to_armv7a(target);
2014 
2015  /* Move from coprocessor to R0. */
2016  retval = cortex_a_exec_opcode(target, opcode, dscr);
2017  if (retval != ERROR_OK)
2018  return retval;
2019 
2020  /* Move from R0 to DTRTX. */
2021  retval = cortex_a_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), dscr);
2022  if (retval != ERROR_OK)
2023  return retval;
2024 
2025  /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2026  * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2027  * must also check TXfull_l). Most of the time this will be free
2028  * because TXfull_l will be set immediately and cached in dscr. */
2030  DSCR_DTRTX_FULL_LATCHED, dscr);
2031  if (retval != ERROR_OK)
2032  return retval;
2033 
2034  /* Read the value transferred to DTRTX. */
2035  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2036  armv7a->debug_base + CPUDBG_DTRTX, data);
2037  if (retval != ERROR_OK)
2038  return retval;
2039 
2040  return ERROR_OK;
2041 }
2042 
2043 static int cortex_a_read_dfar_dfsr(struct target *target, uint32_t *dfar,
2044  uint32_t *dfsr, uint32_t *dscr)
2045 {
2046  int retval;
2047 
2048  if (dfar) {
2049  retval = cortex_a_read_copro(target, ARMV4_5_MRC(15, 0, 0, 6, 0, 0), dfar, dscr);
2050  if (retval != ERROR_OK)
2051  return retval;
2052  }
2053 
2054  if (dfsr) {
2055  retval = cortex_a_read_copro(target, ARMV4_5_MRC(15, 0, 0, 5, 0, 0), dfsr, dscr);
2056  if (retval != ERROR_OK)
2057  return retval;
2058  }
2059 
2060  return ERROR_OK;
2061 }
2062 
2063 static int cortex_a_write_copro(struct target *target, uint32_t opcode,
2064  uint32_t data, uint32_t *dscr)
2065 {
2066  int retval;
2067  struct armv7a_common *armv7a = target_to_armv7a(target);
2068 
2069  /* Write the value into DTRRX. */
2070  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2071  armv7a->debug_base + CPUDBG_DTRRX, data);
2072  if (retval != ERROR_OK)
2073  return retval;
2074 
2075  /* Move from DTRRX to R0. */
2076  retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), dscr);
2077  if (retval != ERROR_OK)
2078  return retval;
2079 
2080  /* Move from R0 to coprocessor. */
2081  retval = cortex_a_exec_opcode(target, opcode, dscr);
2082  if (retval != ERROR_OK)
2083  return retval;
2084 
2085  /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2086  * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2087  * check RXfull_l). Most of the time this will be free because RXfull_l
2088  * will be cleared immediately and cached in dscr. */
2090  if (retval != ERROR_OK)
2091  return retval;
2092 
2093  return ERROR_OK;
2094 }
2095 
2096 static int cortex_a_write_dfar_dfsr(struct target *target, uint32_t dfar,
2097  uint32_t dfsr, uint32_t *dscr)
2098 {
2099  int retval;
2100 
2101  retval = cortex_a_write_copro(target, ARMV4_5_MCR(15, 0, 0, 6, 0, 0), dfar, dscr);
2102  if (retval != ERROR_OK)
2103  return retval;
2104 
2105  retval = cortex_a_write_copro(target, ARMV4_5_MCR(15, 0, 0, 5, 0, 0), dfsr, dscr);
2106  if (retval != ERROR_OK)
2107  return retval;
2108 
2109  return ERROR_OK;
2110 }
2111 
2112 static int cortex_a_dfsr_to_error_code(uint32_t dfsr)
2113 {
2114  uint32_t status, upper4;
2115 
2116  if (dfsr & (1 << 9)) {
2117  /* LPAE format. */
2118  status = dfsr & 0x3f;
2119  upper4 = status >> 2;
2120  if (upper4 == 1 || upper4 == 2 || upper4 == 3 || upper4 == 15)
2122  else if (status == 33)
2124  else
2125  return ERROR_TARGET_DATA_ABORT;
2126  } else {
2127  /* Normal format. */
2128  status = ((dfsr >> 6) & 0x10) | (dfsr & 0xf);
2129  if (status == 1)
2131  else if (status == 5 || status == 7 || status == 3 || status == 6 ||
2132  status == 9 || status == 11 || status == 13 || status == 15)
2134  else
2135  return ERROR_TARGET_DATA_ABORT;
2136  }
2137 }
2138 
2140  uint32_t size, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
2141 {
2142  /* Writes count objects of size size from *buffer. Old value of DSCR must
2143  * be in *dscr; updated to new value. This is slow because it works for
2144  * non-word-sized objects. Avoid unaligned accesses as they do not work
2145  * on memory address space without "Normal" attribute. If size == 4 and
2146  * the address is aligned, cortex_a_write_cpu_memory_fast should be
2147  * preferred.
2148  * Preconditions:
2149  * - Address is in R0.
2150  * - R0 is marked dirty.
2151  */
2152  struct armv7a_common *armv7a = target_to_armv7a(target);
2153  struct arm *arm = &armv7a->arm;
2154  int retval;
2155 
2156  /* Mark register R1 as dirty, to use for transferring data. */
2157  arm_reg_current(arm, 1)->dirty = true;
2158 
2159  /* Switch to non-blocking mode if not already in that mode. */
2161  if (retval != ERROR_OK)
2162  return retval;
2163 
2164  /* Go through the objects. */
2165  while (count) {
2166  /* Write the value to store into DTRRX. */
2167  uint32_t data, opcode;
2168  if (size == 1)
2169  data = *buffer;
2170  else if (size == 2)
2172  else
2174  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2175  armv7a->debug_base + CPUDBG_DTRRX, data);
2176  if (retval != ERROR_OK)
2177  return retval;
2178 
2179  /* Transfer the value from DTRRX to R1. */
2180  retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), dscr);
2181  if (retval != ERROR_OK)
2182  return retval;
2183 
2184  /* Write the value transferred to R1 into memory. */
2185  if (size == 1)
2186  opcode = ARMV4_5_STRB_IP(1, 0);
2187  else if (size == 2)
2188  opcode = ARMV4_5_STRH_IP(1, 0);
2189  else
2190  opcode = ARMV4_5_STRW_IP(1, 0);
2191  retval = cortex_a_exec_opcode(target, opcode, dscr);
2192  if (retval != ERROR_OK)
2193  return retval;
2194 
2195  /* Check for faults and return early. */
2197  return ERROR_OK; /* A data fault is not considered a system failure. */
2198 
2199  /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture
2200  * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2201  * must also check RXfull_l). Most of the time this will be free
2202  * because RXfull_l will be cleared immediately and cached in dscr. */
2204  if (retval != ERROR_OK)
2205  return retval;
2206 
2207  /* Advance. */
2208  buffer += size;
2209  --count;
2210  }
2211 
2212  return ERROR_OK;
2213 }
2214 
2216  uint32_t count, const uint8_t *buffer, uint32_t *dscr)
2217 {
2218  /* Writes count objects of size 4 from *buffer. Old value of DSCR must be
2219  * in *dscr; updated to new value. This is fast but only works for
2220  * word-sized objects at aligned addresses.
2221  * Preconditions:
2222  * - Address is in R0 and must be a multiple of 4.
2223  * - R0 is marked dirty.
2224  */
2225  struct armv7a_common *armv7a = target_to_armv7a(target);
2226  int retval;
2227 
2228  /* Switch to fast mode if not already in that mode. */
2230  if (retval != ERROR_OK)
2231  return retval;
2232 
2233  /* Latch STC instruction. */
2234  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2235  armv7a->debug_base + CPUDBG_ITR, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
2236  if (retval != ERROR_OK)
2237  return retval;
2238 
2239  /* Transfer all the data and issue all the instructions. */
2240  return mem_ap_write_buf_noincr(armv7a->debug_ap, buffer,
2241  4, count, armv7a->debug_base + CPUDBG_DTRRX);
2242 }
2243 
2245  uint32_t address, uint32_t size,
2246  uint32_t count, const uint8_t *buffer)
2247 {
2248  /* Write memory through the CPU. */
2249  int retval, final_retval;
2250  struct armv7a_common *armv7a = target_to_armv7a(target);
2251  struct arm *arm = &armv7a->arm;
2252  uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
2253 
2254  LOG_DEBUG("Writing CPU memory address 0x%" PRIx32 " size %" PRIu32 " count %" PRIu32,
2255  address, size, count);
2256  if (target->state != TARGET_HALTED) {
2257  LOG_TARGET_ERROR(target, "not halted");
2258  return ERROR_TARGET_NOT_HALTED;
2259  }
2260 
2261  if (!count)
2262  return ERROR_OK;
2263 
2264  /* Clear any abort. */
2265  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2267  if (retval != ERROR_OK)
2268  return retval;
2269 
2270  /* Read DSCR. */
2271  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2272  armv7a->debug_base + CPUDBG_DSCR, &dscr);
2273  if (retval != ERROR_OK)
2274  return retval;
2275 
2276  /* Switch to non-blocking mode if not already in that mode. */
2278  if (retval != ERROR_OK)
2279  return retval;
2280 
2281  /* Mark R0 as dirty. */
2282  arm_reg_current(arm, 0)->dirty = true;
2283 
2284  /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2285  retval = cortex_a_read_dfar_dfsr(target, &orig_dfar, &orig_dfsr, &dscr);
2286  if (retval != ERROR_OK)
2287  return retval;
2288 
2289  /* Get the memory address into R0. */
2290  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2291  armv7a->debug_base + CPUDBG_DTRRX, address);
2292  if (retval != ERROR_OK)
2293  return retval;
2294  retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
2295  if (retval != ERROR_OK)
2296  return retval;
2297 
2298  if (size == 4 && (address % 4) == 0) {
2299  /* We are doing a word-aligned transfer, so use fast mode. */
2301  } else {
2302  /* Use slow path. Adjust size for aligned accesses */
2303  switch (address % 4) {
2304  case 1:
2305  case 3:
2306  count *= size;
2307  size = 1;
2308  break;
2309  case 2:
2310  if (size == 4) {
2311  count *= 2;
2312  size = 2;
2313  }
2314  case 0:
2315  default:
2316  break;
2317  }
2319  }
2320 
2321  final_retval = retval;
2322 
2323  /* Switch to non-blocking mode if not already in that mode. */
2325  if (final_retval == ERROR_OK)
2326  final_retval = retval;
2327 
2328  /* Wait for last issued instruction to complete. */
2329  retval = cortex_a_wait_instrcmpl(target, &dscr, true);
2330  if (final_retval == ERROR_OK)
2331  final_retval = retval;
2332 
2333  /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2334  * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2335  * check RXfull_l). Most of the time this will be free because RXfull_l
2336  * will be cleared immediately and cached in dscr. However, don't do this
2337  * if there is fault, because then the instruction might not have completed
2338  * successfully. */
2339  if (!(dscr & DSCR_STICKY_ABORT_PRECISE)) {
2341  if (retval != ERROR_OK)
2342  return retval;
2343  }
2344 
2345  /* If there were any sticky abort flags, clear them. */
2347  fault_dscr = dscr;
2351  } else {
2352  fault_dscr = 0;
2353  }
2354 
2355  /* Handle synchronous data faults. */
2356  if (fault_dscr & DSCR_STICKY_ABORT_PRECISE) {
2357  if (final_retval == ERROR_OK) {
2358  /* Final return value will reflect cause of fault. */
2359  retval = cortex_a_read_dfar_dfsr(target, &fault_dfar, &fault_dfsr, &dscr);
2360  if (retval == ERROR_OK) {
2361  LOG_ERROR("data abort at 0x%08" PRIx32 ", dfsr = 0x%08" PRIx32, fault_dfar, fault_dfsr);
2362  final_retval = cortex_a_dfsr_to_error_code(fault_dfsr);
2363  } else
2364  final_retval = retval;
2365  }
2366  /* Fault destroyed DFAR/DFSR; restore them. */
2367  retval = cortex_a_write_dfar_dfsr(target, orig_dfar, orig_dfsr, &dscr);
2368  if (retval != ERROR_OK)
2369  LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32, dscr);
2370  }
2371 
2372  /* Handle asynchronous data faults. */
2373  if (fault_dscr & DSCR_STICKY_ABORT_IMPRECISE) {
2374  if (final_retval == ERROR_OK)
2375  /* No other error has been recorded so far, so keep this one. */
2376  final_retval = ERROR_TARGET_DATA_ABORT;
2377  }
2378 
2379  /* If the DCC is nonempty, clear it. */
2380  if (dscr & DSCR_DTRTX_FULL_LATCHED) {
2381  uint32_t dummy;
2382  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2383  armv7a->debug_base + CPUDBG_DTRTX, &dummy);
2384  if (final_retval == ERROR_OK)
2385  final_retval = retval;
2386  }
2387  if (dscr & DSCR_DTRRX_FULL_LATCHED) {
2388  retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr);
2389  if (final_retval == ERROR_OK)
2390  final_retval = retval;
2391  }
2392 
2393  /* Done. */
2394  return final_retval;
2395 }
2396 
2398  uint32_t size, uint32_t count, uint8_t *buffer, uint32_t *dscr)
2399 {
2400  /* Reads count objects of size size into *buffer. Old value of DSCR must be
2401  * in *dscr; updated to new value. This is slow because it works for
2402  * non-word-sized objects. Avoid unaligned accesses as they do not work
2403  * on memory address space without "Normal" attribute. If size == 4 and
2404  * the address is aligned, cortex_a_read_cpu_memory_fast should be
2405  * preferred.
2406  * Preconditions:
2407  * - Address is in R0.
2408  * - R0 is marked dirty.
2409  */
2410  struct armv7a_common *armv7a = target_to_armv7a(target);
2411  struct arm *arm = &armv7a->arm;
2412  int retval;
2413 
2414  /* Mark register R1 as dirty, to use for transferring data. */
2415  arm_reg_current(arm, 1)->dirty = true;
2416 
2417  /* Switch to non-blocking mode if not already in that mode. */
2419  if (retval != ERROR_OK)
2420  return retval;
2421 
2422  /* Go through the objects. */
2423  while (count) {
2424  /* Issue a load of the appropriate size to R1. */
2425  uint32_t opcode, data;
2426  if (size == 1)
2427  opcode = ARMV4_5_LDRB_IP(1, 0);
2428  else if (size == 2)
2429  opcode = ARMV4_5_LDRH_IP(1, 0);
2430  else
2431  opcode = ARMV4_5_LDRW_IP(1, 0);
2432  retval = cortex_a_exec_opcode(target, opcode, dscr);
2433  if (retval != ERROR_OK)
2434  return retval;
2435 
2436  /* Issue a write of R1 to DTRTX. */
2437  retval = cortex_a_exec_opcode(target, ARMV4_5_MCR(14, 0, 1, 0, 5, 0), dscr);
2438  if (retval != ERROR_OK)
2439  return retval;
2440 
2441  /* Check for faults and return early. */
2443  return ERROR_OK; /* A data fault is not considered a system failure. */
2444 
2445  /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2446  * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2447  * must also check TXfull_l). Most of the time this will be free
2448  * because TXfull_l will be set immediately and cached in dscr. */
2450  DSCR_DTRTX_FULL_LATCHED, dscr);
2451  if (retval != ERROR_OK)
2452  return retval;
2453 
2454  /* Read the value transferred to DTRTX into the buffer. */
2455  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2456  armv7a->debug_base + CPUDBG_DTRTX, &data);
2457  if (retval != ERROR_OK)
2458  return retval;
2459  if (size == 1)
2460  *buffer = (uint8_t) data;
2461  else if (size == 2)
2462  target_buffer_set_u16(target, buffer, (uint16_t) data);
2463  else
2465 
2466  /* Advance. */
2467  buffer += size;
2468  --count;
2469  }
2470 
2471  return ERROR_OK;
2472 }
2473 
2475  uint32_t count, uint8_t *buffer, uint32_t *dscr)
2476 {
2477  /* Reads count objects of size 4 into *buffer. Old value of DSCR must be in
2478  * *dscr; updated to new value. This is fast but only works for word-sized
2479  * objects at aligned addresses.
2480  * Preconditions:
2481  * - Address is in R0 and must be a multiple of 4.
2482  * - R0 is marked dirty.
2483  */
2484  struct armv7a_common *armv7a = target_to_armv7a(target);
2485  uint32_t u32;
2486  int retval;
2487 
2488  /* Switch to non-blocking mode if not already in that mode. */
2490  if (retval != ERROR_OK)
2491  return retval;
2492 
2493  /* Issue the LDC instruction via a write to ITR. */
2494  retval = cortex_a_exec_opcode(target, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4), dscr);
2495  if (retval != ERROR_OK)
2496  return retval;
2497 
2498  count--;
2499 
2500  if (count > 0) {
2501  /* Switch to fast mode if not already in that mode. */
2503  if (retval != ERROR_OK)
2504  return retval;
2505 
2506  /* Latch LDC instruction. */
2507  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2508  armv7a->debug_base + CPUDBG_ITR, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
2509  if (retval != ERROR_OK)
2510  return retval;
2511 
2512  /* Read the value transferred to DTRTX into the buffer. Due to fast
2513  * mode rules, this blocks until the instruction finishes executing and
2514  * then reissues the read instruction to read the next word from
2515  * memory. The last read of DTRTX in this call reads the second-to-last
2516  * word from memory and issues the read instruction for the last word.
2517  */
2518  retval = mem_ap_read_buf_noincr(armv7a->debug_ap, buffer,
2519  4, count, armv7a->debug_base + CPUDBG_DTRTX);
2520  if (retval != ERROR_OK)
2521  return retval;
2522 
2523  /* Advance. */
2524  buffer += count * 4;
2525  }
2526 
2527  /* Wait for last issued instruction to complete. */
2528  retval = cortex_a_wait_instrcmpl(target, dscr, false);
2529  if (retval != ERROR_OK)
2530  return retval;
2531 
2532  /* Switch to non-blocking mode if not already in that mode. */
2534  if (retval != ERROR_OK)
2535  return retval;
2536 
2537  /* Check for faults and return early. */
2539  return ERROR_OK; /* A data fault is not considered a system failure. */
2540 
2541  /* Wait until DTRTX is full (according to ARMv7-A/-R architecture manual
2542  * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2543  * check TXfull_l). Most of the time this will be free because TXfull_l
2544  * will be set immediately and cached in dscr. */
2546  DSCR_DTRTX_FULL_LATCHED, dscr);
2547  if (retval != ERROR_OK)
2548  return retval;
2549 
2550  /* Read the value transferred to DTRTX into the buffer. This is the last
2551  * word. */
2552  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2553  armv7a->debug_base + CPUDBG_DTRTX, &u32);
2554  if (retval != ERROR_OK)
2555  return retval;
2557 
2558  return ERROR_OK;
2559 }
2560 
2562  uint32_t address, uint32_t size,
2563  uint32_t count, uint8_t *buffer)
2564 {
2565  /* Read memory through the CPU. */
2566  int retval, final_retval;
2567  struct armv7a_common *armv7a = target_to_armv7a(target);
2568  struct arm *arm = &armv7a->arm;
2569  uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
2570 
2571  LOG_DEBUG("Reading CPU memory address 0x%" PRIx32 " size %" PRIu32 " count %" PRIu32,
2572  address, size, count);
2573  if (target->state != TARGET_HALTED) {
2574  LOG_TARGET_ERROR(target, "not halted");
2575  return ERROR_TARGET_NOT_HALTED;
2576  }
2577 
2578  if (!count)
2579  return ERROR_OK;
2580 
2581  /* Clear any abort. */
2582  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2584  if (retval != ERROR_OK)
2585  return retval;
2586 
2587  /* Read DSCR */
2588  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2589  armv7a->debug_base + CPUDBG_DSCR, &dscr);
2590  if (retval != ERROR_OK)
2591  return retval;
2592 
2593  /* Switch to non-blocking mode if not already in that mode. */
2595  if (retval != ERROR_OK)
2596  return retval;
2597 
2598  /* Mark R0 as dirty. */
2599  arm_reg_current(arm, 0)->dirty = true;
2600 
2601  /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2602  retval = cortex_a_read_dfar_dfsr(target, &orig_dfar, &orig_dfsr, &dscr);
2603  if (retval != ERROR_OK)
2604  return retval;
2605 
2606  /* Get the memory address into R0. */
2607  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2608  armv7a->debug_base + CPUDBG_DTRRX, address);
2609  if (retval != ERROR_OK)
2610  return retval;
2611  retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
2612  if (retval != ERROR_OK)
2613  return retval;
2614 
2615  if (size == 4 && (address % 4) == 0) {
2616  /* We are doing a word-aligned transfer, so use fast mode. */
2617  retval = cortex_a_read_cpu_memory_fast(target, count, buffer, &dscr);
2618  } else {
2619  /* Use slow path. Adjust size for aligned accesses */
2620  switch (address % 4) {
2621  case 1:
2622  case 3:
2623  count *= size;
2624  size = 1;
2625  break;
2626  case 2:
2627  if (size == 4) {
2628  count *= 2;
2629  size = 2;
2630  }
2631  break;
2632  case 0:
2633  default:
2634  break;
2635  }
2637  }
2638 
2639  final_retval = retval;
2640 
2641  /* Switch to non-blocking mode if not already in that mode. */
2643  if (final_retval == ERROR_OK)
2644  final_retval = retval;
2645 
2646  /* Wait for last issued instruction to complete. */
2647  retval = cortex_a_wait_instrcmpl(target, &dscr, true);
2648  if (final_retval == ERROR_OK)
2649  final_retval = retval;
2650 
2651  /* If there were any sticky abort flags, clear them. */
2653  fault_dscr = dscr;
2657  } else {
2658  fault_dscr = 0;
2659  }
2660 
2661  /* Handle synchronous data faults. */
2662  if (fault_dscr & DSCR_STICKY_ABORT_PRECISE) {
2663  if (final_retval == ERROR_OK) {
2664  /* Final return value will reflect cause of fault. */
2665  retval = cortex_a_read_dfar_dfsr(target, &fault_dfar, &fault_dfsr, &dscr);
2666  if (retval == ERROR_OK) {
2667  LOG_ERROR("data abort at 0x%08" PRIx32 ", dfsr = 0x%08" PRIx32, fault_dfar, fault_dfsr);
2668  final_retval = cortex_a_dfsr_to_error_code(fault_dfsr);
2669  } else
2670  final_retval = retval;
2671  }
2672  /* Fault destroyed DFAR/DFSR; restore them. */
2673  retval = cortex_a_write_dfar_dfsr(target, orig_dfar, orig_dfsr, &dscr);
2674  if (retval != ERROR_OK)
2675  LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32, dscr);
2676  }
2677 
2678  /* Handle asynchronous data faults. */
2679  if (fault_dscr & DSCR_STICKY_ABORT_IMPRECISE) {
2680  if (final_retval == ERROR_OK)
2681  /* No other error has been recorded so far, so keep this one. */
2682  final_retval = ERROR_TARGET_DATA_ABORT;
2683  }
2684 
2685  /* If the DCC is nonempty, clear it. */
2686  if (dscr & DSCR_DTRTX_FULL_LATCHED) {
2687  uint32_t dummy;
2688  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2689  armv7a->debug_base + CPUDBG_DTRTX, &dummy);
2690  if (final_retval == ERROR_OK)
2691  final_retval = retval;
2692  }
2693  if (dscr & DSCR_DTRRX_FULL_LATCHED) {
2694  retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr);
2695  if (final_retval == ERROR_OK)
2696  final_retval = retval;
2697  }
2698 
2699  /* Done. */
2700  return final_retval;
2701 }
2702 
2703 
2704 /*
2705  * Cortex-A Memory access
2706  *
2707  * This is same Cortex-M3 but we must also use the correct
2708  * ap number for every access.
2709  */
2710 
2712  target_addr_t address, uint32_t size,
2713  uint32_t count, uint8_t *buffer)
2714 {
2715  int retval;
2716 
2717  if (!count || !buffer)
2719 
2720  LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
2721  address, size, count);
2722 
2723  /* read memory through the CPU */
2725  retval = cortex_a_read_cpu_memory(target, address, size, count, buffer);
2727 
2728  return retval;
2729 }
2730 
2731 static int cortex_a_read_memory(struct target *target, target_addr_t address,
2732  uint32_t size, uint32_t count, uint8_t *buffer)
2733 {
2734  int retval;
2735 
2736  /* cortex_a handles unaligned memory access */
2737  LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
2738  address, size, count);
2739 
2741  retval = cortex_a_read_cpu_memory(target, address, size, count, buffer);
2743 
2744  return retval;
2745 }
2746 
2748  target_addr_t address, uint32_t size,
2749  uint32_t count, const uint8_t *buffer)
2750 {
2751  int retval;
2752 
2753  if (!count || !buffer)
2755 
2756  LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
2757  address, size, count);
2758 
2759  /* write memory through the CPU */
2761  retval = cortex_a_write_cpu_memory(target, address, size, count, buffer);
2763 
2764  return retval;
2765 }
2766 
2767 static int cortex_a_write_memory(struct target *target, target_addr_t address,
2768  uint32_t size, uint32_t count, const uint8_t *buffer)
2769 {
2770  int retval;
2771 
2772  /* cortex_a handles unaligned memory access */
2773  LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
2774  address, size, count);
2775 
2777  retval = cortex_a_write_cpu_memory(target, address, size, count, buffer);
2779  return retval;
2780 }
2781 
2782 static int cortex_a_read_buffer(struct target *target, target_addr_t address,
2783  uint32_t count, uint8_t *buffer)
2784 {
2785  uint32_t size;
2786 
2787  /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2788  * will have something to do with the size we leave to it. */
2789  for (size = 1; size < 4 && count >= size * 2 + (address & size); size *= 2) {
2790  if (address & size) {
2791  int retval = target_read_memory(target, address, size, 1, buffer);
2792  if (retval != ERROR_OK)
2793  return retval;
2794  address += size;
2795  count -= size;
2796  buffer += size;
2797  }
2798  }
2799 
2800  /* Read the data with as large access size as possible. */
2801  for (; size > 0; size /= 2) {
2802  uint32_t aligned = count - count % size;
2803  if (aligned > 0) {
2804  int retval = target_read_memory(target, address, size, aligned / size, buffer);
2805  if (retval != ERROR_OK)
2806  return retval;
2807  address += aligned;
2808  count -= aligned;
2809  buffer += aligned;
2810  }
2811  }
2812 
2813  return ERROR_OK;
2814 }
2815 
2816 static int cortex_a_write_buffer(struct target *target, target_addr_t address,
2817  uint32_t count, const uint8_t *buffer)
2818 {
2819  uint32_t size;
2820 
2821  /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2822  * will have something to do with the size we leave to it. */
2823  for (size = 1; size < 4 && count >= size * 2 + (address & size); size *= 2) {
2824  if (address & size) {
2825  int retval = target_write_memory(target, address, size, 1, buffer);
2826  if (retval != ERROR_OK)
2827  return retval;
2828  address += size;
2829  count -= size;
2830  buffer += size;
2831  }
2832  }
2833 
2834  /* Write the data with as large access size as possible. */
2835  for (; size > 0; size /= 2) {
2836  uint32_t aligned = count - count % size;
2837  if (aligned > 0) {
2838  int retval = target_write_memory(target, address, size, aligned / size, buffer);
2839  if (retval != ERROR_OK)
2840  return retval;
2841  address += aligned;
2842  count -= aligned;
2843  buffer += aligned;
2844  }
2845  }
2846 
2847  return ERROR_OK;
2848 }
2849 
2851 {
2852  struct target *target = priv;
2853  struct armv7a_common *armv7a = target_to_armv7a(target);
2854  int retval;
2855 
2857  return ERROR_OK;
2858  if (!target->dbg_msg_enabled)
2859  return ERROR_OK;
2860 
2861  if (target->state == TARGET_RUNNING) {
2862  uint32_t request;
2863  uint32_t dscr;
2864  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2865  armv7a->debug_base + CPUDBG_DSCR, &dscr);
2866 
2867  /* check if we have data */
2868  int64_t then = timeval_ms();
2869  while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
2870  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2871  armv7a->debug_base + CPUDBG_DTRTX, &request);
2872  if (retval == ERROR_OK) {
2873  target_request(target, request);
2874  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2875  armv7a->debug_base + CPUDBG_DSCR, &dscr);
2876  }
2877  if (timeval_ms() > then + 1000) {
2878  LOG_ERROR("Timeout waiting for dtr tx full");
2879  return ERROR_FAIL;
2880  }
2881  }
2882  }
2883 
2884  return ERROR_OK;
2885 }
2886 
2887 /*
2888  * Cortex-A target information and configuration
2889  */
2890 
2892 {
2893  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
2894  struct armv7a_common *armv7a = &cortex_a->armv7a_common;
2895  struct adiv5_dap *swjdp = armv7a->arm.dap;
2897 
2898  int i;
2899  int retval = ERROR_OK;
2900  uint32_t didr, cpuid, dbg_osreg, dbg_idpfr1;
2901 
2902  if (!armv7a->debug_ap) {
2903  if (pc->ap_num == DP_APSEL_INVALID) {
2904  /* Search for the APB-AP - it is needed for access to debug registers */
2905  retval = dap_find_get_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
2906  if (retval != ERROR_OK) {
2907  LOG_ERROR("Could not find APB-AP for debug access");
2908  return retval;
2909  }
2910  } else {
2911  armv7a->debug_ap = dap_get_ap(swjdp, pc->ap_num);
2912  if (!armv7a->debug_ap) {
2913  LOG_ERROR("Cannot get AP");
2914  return ERROR_FAIL;
2915  }
2916  }
2917  }
2918 
2919  retval = mem_ap_init(armv7a->debug_ap);
2920  if (retval != ERROR_OK) {
2921  LOG_ERROR("Could not initialize the APB-AP");
2922  return retval;
2923  }
2924 
2925  armv7a->debug_ap->memaccess_tck = 80;
2926 
2927  if (!target->dbgbase_set) {
2928  LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
2929  target->cmd_name);
2930  /* Lookup Processor DAP */
2932  &armv7a->debug_base, target->coreid);
2933  if (retval != ERROR_OK) {
2934  LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
2935  target->cmd_name);
2936  return retval;
2937  }
2938  LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT,
2939  target->coreid, armv7a->debug_base);
2940  } else
2941  armv7a->debug_base = target->dbgbase;
2942 
2943  if ((armv7a->debug_base & (1UL<<31)) == 0)
2944  LOG_WARNING("Debug base address for target %s has bit 31 set to 0. Access to debug registers will likely fail!\n"
2945  "Please fix the target configuration.", target_name(target));
2946 
2947  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2948  armv7a->debug_base + CPUDBG_DIDR, &didr);
2949  if (retval != ERROR_OK) {
2950  LOG_DEBUG("Examine %s failed", "DIDR");
2951  return retval;
2952  }
2953 
2954  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2955  armv7a->debug_base + CPUDBG_CPUID, &cpuid);
2956  if (retval != ERROR_OK) {
2957  LOG_DEBUG("Examine %s failed", "CPUID");
2958  return retval;
2959  }
2960 
2961  LOG_DEBUG("didr = 0x%08" PRIx32, didr);
2962  LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
2963 
2964  cortex_a->didr = didr;
2965  cortex_a->cpuid = cpuid;
2966 
2967  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2968  armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
2969  if (retval != ERROR_OK)
2970  return retval;
2971  LOG_TARGET_DEBUG(target, "DBGPRSR 0x%" PRIx32, dbg_osreg);
2972 
2973  if ((dbg_osreg & PRSR_POWERUP_STATUS) == 0) {
2974  LOG_TARGET_ERROR(target, "powered down!");
2975  target->state = TARGET_UNKNOWN; /* TARGET_NO_POWER? */
2976  return ERROR_TARGET_INIT_FAILED;
2977  }
2978 
2979  if (dbg_osreg & PRSR_STICKY_RESET_STATUS)
2980  LOG_TARGET_DEBUG(target, "was reset!");
2981 
2982  /* Read DBGOSLSR and check if OSLK is implemented */
2983  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
2984  armv7a->debug_base + CPUDBG_OSLSR, &dbg_osreg);
2985  if (retval != ERROR_OK)
2986  return retval;
2987  LOG_TARGET_DEBUG(target, "DBGOSLSR 0x%" PRIx32, dbg_osreg);
2988 
2989  /* check if OS Lock is implemented */
2990  if ((dbg_osreg & OSLSR_OSLM) == OSLSR_OSLM0 || (dbg_osreg & OSLSR_OSLM) == OSLSR_OSLM1) {
2991  /* check if OS Lock is set */
2992  if (dbg_osreg & OSLSR_OSLK) {
2993  LOG_TARGET_DEBUG(target, "OSLock set! Trying to unlock");
2994 
2995  retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
2996  armv7a->debug_base + CPUDBG_OSLAR,
2997  0);
2998  if (retval == ERROR_OK)
2999  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
3000  armv7a->debug_base + CPUDBG_OSLSR, &dbg_osreg);
3001 
3002  /* if we fail to access the register or cannot reset the OSLK bit, bail out */
3003  if (retval != ERROR_OK || (dbg_osreg & OSLSR_OSLK) != 0) {
3004  LOG_TARGET_ERROR(target, "OSLock sticky, core not powered?");
3005  target->state = TARGET_UNKNOWN; /* TARGET_NO_POWER? */
3006  return ERROR_TARGET_INIT_FAILED;
3007  }
3008  }
3009  }
3010 
3011  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
3012  armv7a->debug_base + CPUDBG_ID_PFR1, &dbg_idpfr1);
3013  if (retval != ERROR_OK)
3014  return retval;
3015 
3016  if (dbg_idpfr1 & 0x000000f0) {
3017  LOG_TARGET_DEBUG(target, "has security extensions");
3019  }
3020  if (dbg_idpfr1 & 0x0000f000) {
3021  LOG_TARGET_DEBUG(target, "has virtualization extensions");
3022  /*
3023  * overwrite and simplify the checks.
3024  * virtualization extensions require implementation of security extension
3025  */
3027  }
3028 
3029  /* Avoid recreating the registers cache */
3030  if (!target_was_examined(target)) {
3031  retval = cortex_a_dpm_setup(cortex_a, didr);
3032  if (retval != ERROR_OK)
3033  return retval;
3034  }
3035 
3036  /* Setup Breakpoint Register Pairs */
3037  cortex_a->brp_num = ((didr >> 24) & 0x0F) + 1;
3038  cortex_a->brp_num_context = ((didr >> 20) & 0x0F) + 1;
3039  cortex_a->brp_num_available = cortex_a->brp_num;
3040  free(cortex_a->brp_list);
3041  cortex_a->brp_list = calloc(cortex_a->brp_num, sizeof(struct cortex_a_brp));
3042 /* cortex_a->brb_enabled = ????; */
3043  for (i = 0; i < cortex_a->brp_num; i++) {
3044  cortex_a->brp_list[i].used = false;
3045  if (i < (cortex_a->brp_num-cortex_a->brp_num_context))
3046  cortex_a->brp_list[i].type = BRP_NORMAL;
3047  else
3048  cortex_a->brp_list[i].type = BRP_CONTEXT;
3049  cortex_a->brp_list[i].value = 0;
3050  cortex_a->brp_list[i].control = 0;
3051  cortex_a->brp_list[i].brpn = i;
3052  }
3053 
3054  LOG_DEBUG("Configured %i hw breakpoints", cortex_a->brp_num);
3055 
3056  /* Setup Watchpoint Register Pairs */
3057  cortex_a->wrp_num = ((didr >> 28) & 0x0F) + 1;
3058  cortex_a->wrp_num_available = cortex_a->wrp_num;
3059  free(cortex_a->wrp_list);
3060  cortex_a->wrp_list = calloc(cortex_a->wrp_num, sizeof(struct cortex_a_wrp));
3061  for (i = 0; i < cortex_a->wrp_num; i++) {
3062  cortex_a->wrp_list[i].used = false;
3063  cortex_a->wrp_list[i].value = 0;
3064  cortex_a->wrp_list[i].control = 0;
3065  cortex_a->wrp_list[i].wrpn = i;
3066  }
3067 
3068  LOG_DEBUG("Configured %i hw watchpoints", cortex_a->wrp_num);
3069 
3070  /* select debug_ap as default */
3071  swjdp->apsel = armv7a->debug_ap->ap_num;
3072 
3074  return ERROR_OK;
3075 }
3076 
3077 static int cortex_a_examine(struct target *target)
3078 {
3079  int retval = ERROR_OK;
3080 
3081  /* Reestablish communication after target reset */
3082  retval = cortex_a_examine_first(target);
3083 
3084  /* Configure core debug access */
3085  if (retval == ERROR_OK)
3087 
3088  return retval;
3089 }
3090 
3091 /*
3092  * Cortex-A target creation and initialization
3093  */
3094 
3095 static int cortex_a_init_target(struct command_context *cmd_ctx,
3096  struct target *target)
3097 {
3098  /* examine_first() does a bunch of this */
3100  return ERROR_OK;
3101 }
3102 
3104  struct cortex_a_common *cortex_a, struct adiv5_dap *dap)
3105 {
3106  struct armv7a_common *armv7a = &cortex_a->armv7a_common;
3107 
3108  /* Setup struct cortex_a_common */
3109  cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
3110  armv7a->arm.dap = dap;
3111 
3112  /* register arch-specific functions */
3113  armv7a->examine_debug_reason = NULL;
3114 
3116 
3117  armv7a->pre_restore_context = NULL;
3118 
3120 
3121 
3122 /* arm7_9->handle_target_request = cortex_a_handle_target_request; */
3123 
3124  /* REVISIT v7a setup should be in a v7a-specific routine */
3125  armv7a_init_arch_info(target, armv7a);
3128 
3129  return ERROR_OK;
3130 }
3131 
3132 static int cortex_a_target_create(struct target *target, Jim_Interp *interp)
3133 {
3134  struct cortex_a_common *cortex_a;
3135  struct adiv5_private_config *pc;
3136 
3137  if (!target->private_config)
3138  return ERROR_FAIL;
3139 
3140  pc = (struct adiv5_private_config *)target->private_config;
3141 
3142  cortex_a = calloc(1, sizeof(struct cortex_a_common));
3143  if (!cortex_a) {
3144  LOG_ERROR("Out of memory");
3145  return ERROR_FAIL;
3146  }
3147  cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
3148  cortex_a->armv7a_common.is_armv7r = false;
3150 
3151  return cortex_a_init_arch_info(target, cortex_a, pc->dap);
3152 }
3153 
3154 static int cortex_r4_target_create(struct target *target, Jim_Interp *interp)
3155 {
3156  struct cortex_a_common *cortex_a;
3157  struct adiv5_private_config *pc;
3158 
3159  pc = (struct adiv5_private_config *)target->private_config;
3160  if (adiv5_verify_config(pc) != ERROR_OK)
3161  return ERROR_FAIL;
3162 
3163  cortex_a = calloc(1, sizeof(struct cortex_a_common));
3164  if (!cortex_a) {
3165  LOG_ERROR("Out of memory");
3166  return ERROR_FAIL;
3167  }
3168  cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
3169  cortex_a->armv7a_common.is_armv7r = true;
3170 
3171  return cortex_a_init_arch_info(target, cortex_a, pc->dap);
3172 }
3173 
3175 {
3176  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
3177  struct armv7a_common *armv7a = &cortex_a->armv7a_common;
3178  struct arm_dpm *dpm = &armv7a->dpm;
3179  uint32_t dscr;
3180  int retval;
3181 
3182  if (target_was_examined(target)) {
3183  /* Disable halt for breakpoint, watchpoint and vector catch */
3184  retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
3185  armv7a->debug_base + CPUDBG_DSCR, &dscr);
3186  if (retval == ERROR_OK)
3188  armv7a->debug_base + CPUDBG_DSCR,
3190  }
3191 
3192  if (armv7a->debug_ap)
3193  dap_put_ap(armv7a->debug_ap);
3194 
3195  free(cortex_a->wrp_list);
3196  free(cortex_a->brp_list);
3197  arm_free_reg_cache(dpm->arm);
3198  free(dpm->dbp);
3199  free(dpm->dwp);
3200  free(target->private_config);
3201  free(cortex_a);
3202 }
3203 
3204 static int cortex_a_mmu(struct target *target, int *enabled)
3205 {
3206  struct armv7a_common *armv7a = target_to_armv7a(target);
3207 
3208  if (target->state != TARGET_HALTED) {
3209  LOG_TARGET_ERROR(target, "not halted");
3210  return ERROR_TARGET_NOT_HALTED;
3211  }
3212 
3213  if (armv7a->is_armv7r)
3214  *enabled = 0;
3215  else
3217 
3218  return ERROR_OK;
3219 }
3220 
3221 static int cortex_a_virt2phys(struct target *target,
3222  target_addr_t virt, target_addr_t *phys)
3223 {
3224  int retval;
3225  int mmu_enabled = 0;
3226 
3227  /*
3228  * If the MMU was not enabled at debug entry, there is no
3229  * way of knowing if there was ever a valid configuration
3230  * for it and thus it's not safe to enable it. In this case,
3231  * just return the virtual address as physical.
3232  */
3233  cortex_a_mmu(target, &mmu_enabled);
3234  if (!mmu_enabled) {
3235  *phys = virt;
3236  return ERROR_OK;
3237  }
3238 
3239  /* mmu must be enable in order to get a correct translation */
3240  retval = cortex_a_mmu_modify(target, 1);
3241  if (retval != ERROR_OK)
3242  return retval;
3243  return armv7a_mmu_translate_va_pa(target, (uint32_t)virt,
3244  phys, 1);
3245 }
3246 
3247 COMMAND_HANDLER(cortex_a_handle_cache_info_command)
3248 {
3250  struct armv7a_common *armv7a = target_to_armv7a(target);
3251 
3253  &armv7a->armv7a_mmu.armv7a_cache);
3254 }
3255 
3256 
3257 COMMAND_HANDLER(cortex_a_handle_dbginit_command)
3258 {
3260  if (!target_was_examined(target)) {
3261  LOG_ERROR("target not examined yet");
3262  return ERROR_FAIL;
3263  }
3264 
3266 }
3267 
3268 COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command)
3269 {
3271  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
3272 
3273  static const struct nvp nvp_maskisr_modes[] = {
3274  { .name = "off", .value = CORTEX_A_ISRMASK_OFF },
3275  { .name = "on", .value = CORTEX_A_ISRMASK_ON },
3276  { .name = NULL, .value = -1 },
3277  };
3278  const struct nvp *n;
3279 
3280  if (CMD_ARGC > 0) {
3281  n = nvp_name2value(nvp_maskisr_modes, CMD_ARGV[0]);
3282  if (!n->name) {
3283  LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV[0]);
3285  }
3286 
3287  cortex_a->isrmasking_mode = n->value;
3288  }
3289 
3290  n = nvp_value2name(nvp_maskisr_modes, cortex_a->isrmasking_mode);
3291  command_print(CMD, "cortex_a interrupt mask %s", n->name);
3292 
3293  return ERROR_OK;
3294 }
3295 
3296 COMMAND_HANDLER(handle_cortex_a_dacrfixup_command)
3297 {
3299  struct cortex_a_common *cortex_a = target_to_cortex_a(target);
3300 
3301  static const struct nvp nvp_dacrfixup_modes[] = {
3302  { .name = "off", .value = CORTEX_A_DACRFIXUP_OFF },
3303  { .name = "on", .value = CORTEX_A_DACRFIXUP_ON },
3304  { .name = NULL, .value = -1 },
3305  };
3306  const struct nvp *n;
3307 
3308  if (CMD_ARGC > 0) {
3309  n = nvp_name2value(nvp_dacrfixup_modes, CMD_ARGV[0]);
3310  if (!n->name)
3312  cortex_a->dacrfixup_mode = n->value;
3313 
3314  }
3315 
3316  n = nvp_value2name(nvp_dacrfixup_modes, cortex_a->dacrfixup_mode);
3317  command_print(CMD, "cortex_a domain access control fixup %s", n->name);
3318 
3319  return ERROR_OK;
3320 }
3321 
3322 static const struct command_registration cortex_a_exec_command_handlers[] = {
3323  {
3324  .name = "cache_info",
3325  .handler = cortex_a_handle_cache_info_command,
3326  .mode = COMMAND_EXEC,
3327  .help = "display information about target caches",
3328  .usage = "",
3329  },
3330  {
3331  .name = "dbginit",
3332  .handler = cortex_a_handle_dbginit_command,
3333  .mode = COMMAND_EXEC,
3334  .help = "Initialize core debug",
3335  .usage = "",
3336  },
3337  {
3338  .name = "maskisr",
3339  .handler = handle_cortex_a_mask_interrupts_command,
3340  .mode = COMMAND_ANY,
3341  .help = "mask cortex_a interrupts",
3342  .usage = "['on'|'off']",
3343  },
3344  {
3345  .name = "dacrfixup",
3346  .handler = handle_cortex_a_dacrfixup_command,
3347  .mode = COMMAND_ANY,
3348  .help = "set domain access control (DACR) to all-manager "
3349  "on memory access",
3350  .usage = "['on'|'off']",
3351  },
3352  {
3353  .chain = armv7a_mmu_command_handlers,
3354  },
3355  {
3357  },
3358 
3360 };
3361 static const struct command_registration cortex_a_command_handlers[] = {
3362  {
3364  },
3365  {
3367  },
3368  {
3369  .name = "cortex_a",
3370  .mode = COMMAND_ANY,
3371  .help = "Cortex-A command group",
3372  .usage = "",
3374  },
3376 };
3377 
3378 struct target_type cortexa_target = {
3379  .name = "cortex_a",
3380 
3381  .poll = cortex_a_poll,
3382  .arch_state = armv7a_arch_state,
3383 
3384  .halt = cortex_a_halt,
3385  .resume = cortex_a_resume,
3386  .step = cortex_a_step,
3387 
3388  .assert_reset = cortex_a_assert_reset,
3389  .deassert_reset = cortex_a_deassert_reset,
3390 
3391  /* REVISIT allow exporting VFP3 registers ... */
3392  .get_gdb_arch = arm_get_gdb_arch,
3393  .get_gdb_reg_list = arm_get_gdb_reg_list,
3394 
3395  .read_memory = cortex_a_read_memory,
3396  .write_memory = cortex_a_write_memory,
3397 
3398  .read_buffer = cortex_a_read_buffer,
3399  .write_buffer = cortex_a_write_buffer,
3400 
3401  .checksum_memory = arm_checksum_memory,
3402  .blank_check_memory = arm_blank_check_memory,
3403 
3404  .run_algorithm = armv4_5_run_algorithm,
3405 
3406  .add_breakpoint = cortex_a_add_breakpoint,
3407  .add_context_breakpoint = cortex_a_add_context_breakpoint,
3408  .add_hybrid_breakpoint = cortex_a_add_hybrid_breakpoint,
3409  .remove_breakpoint = cortex_a_remove_breakpoint,
3410  .add_watchpoint = cortex_a_add_watchpoint,
3411  .remove_watchpoint = cortex_a_remove_watchpoint,
3412 
3413  .commands = cortex_a_command_handlers,
3414  .target_create = cortex_a_target_create,
3415  .target_jim_configure = adiv5_jim_configure,
3416  .init_target = cortex_a_init_target,
3417  .examine = cortex_a_examine,
3418  .deinit_target = cortex_a_deinit_target,
3419 
3420  .read_phys_memory = cortex_a_read_phys_memory,
3421  .write_phys_memory = cortex_a_write_phys_memory,
3422  .mmu = cortex_a_mmu,
3423  .virt2phys = cortex_a_virt2phys,
3424 };
3425 
3426 static const struct command_registration cortex_r4_exec_command_handlers[] = {
3427  {
3428  .name = "dbginit",
3429  .handler = cortex_a_handle_dbginit_command,
3430  .mode = COMMAND_EXEC,
3431  .help = "Initialize core debug",
3432  .usage = "",
3433  },
3434  {
3435  .name = "maskisr",
3436  .handler = handle_cortex_a_mask_interrupts_command,
3437  .mode = COMMAND_EXEC,
3438  .help = "mask cortex_r4 interrupts",
3439  .usage = "['on'|'off']",
3440  },
3441 
3443 };
3444 static const struct command_registration cortex_r4_command_handlers[] = {
3445  {
3447  },
3448  {
3449  .name = "cortex_r4",
3450  .mode = COMMAND_ANY,
3451  .help = "Cortex-R4 command group",
3452  .usage = "",
3454  },
3456 };
3457 
3458 struct target_type cortexr4_target = {
3459  .name = "cortex_r4",
3460 
3461  .poll = cortex_a_poll,
3462  .arch_state = armv7a_arch_state,
3463 
3464  .halt = cortex_a_halt,
3465  .resume = cortex_a_resume,
3466  .step = cortex_a_step,
3467 
3468  .assert_reset = cortex_a_assert_reset,
3469  .deassert_reset = cortex_a_deassert_reset,
3470 
3471  /* REVISIT allow exporting VFP3 registers ... */
3472  .get_gdb_arch = arm_get_gdb_arch,
3473  .get_gdb_reg_list = arm_get_gdb_reg_list,
3474 
3475  .read_memory = cortex_a_read_phys_memory,
3476  .write_memory = cortex_a_write_phys_memory,
3477 
3478  .checksum_memory = arm_checksum_memory,
3479  .blank_check_memory = arm_blank_check_memory,
3480 
3481  .run_algorithm = armv4_5_run_algorithm,
3482 
3483  .add_breakpoint = cortex_a_add_breakpoint,
3484  .add_context_breakpoint = cortex_a_add_context_breakpoint,
3485  .add_hybrid_breakpoint = cortex_a_add_hybrid_breakpoint,
3486  .remove_breakpoint = cortex_a_remove_breakpoint,
3487  .add_watchpoint = cortex_a_add_watchpoint,
3488  .remove_watchpoint = cortex_a_remove_watchpoint,
3489 
3490  .commands = cortex_r4_command_handlers,
3491  .target_create = cortex_r4_target_create,
3492  .target_jim_configure = adiv5_jim_configure,
3493  .init_target = cortex_a_init_target,
3494  .examine = cortex_a_examine,
3495  .deinit_target = cortex_a_deinit_target,
3496 };
#define BRP_CONTEXT
Definition: aarch64.h:23
#define CPUDBG_CPUID
Definition: aarch64.h:14
#define BRP_NORMAL
Definition: aarch64.h:22
#define CPUDBG_LOCKACCESS
Definition: aarch64.h:19
int arm_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Runs ARM code in the target to check whether a memory block holds all ones.
Definition: armv4_5.c:1673
struct reg * arm_reg_current(struct arm *arm, unsigned int regnum)
Returns handle to the register currently mapped to a given number.
Definition: armv4_5.c:502
@ ARM_VFP_V3
Definition: arm.h:163
int arm_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Runs ARM code in the target to calculate a CRC32 checksum.
Definition: armv4_5.c:1600
const char * arm_get_gdb_arch(const struct target *target)
Definition: armv4_5.c:1267
int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: armv4_5.c:1272
@ ARM_MODE_ANY
Definition: arm.h:106
@ ARM_MODE_SVC
Definition: arm.h:86
void arm_free_reg_cache(struct arm *arm)
Definition: armv4_5.c:761
@ ARM_STATE_JAZELLE
Definition: arm.h:153
@ ARM_STATE_THUMB
Definition: arm.h:152
@ ARM_STATE_ARM
Definition: arm.h:151
@ ARM_STATE_AARCH64
Definition: arm.h:155
@ ARM_STATE_THUMB_EE
Definition: arm.h:154
const struct command_registration arm_command_handlers[]
Definition: armv4_5.c:1247
int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Definition: armv4_5.c:1574
@ ARM_CORE_TYPE_SEC_EXT
Definition: arm.h:47
@ ARM_CORE_TYPE_VIRT_EXT
Definition: arm.h:48
int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type, target_addr_t *addr, int32_t core_id)
Definition: arm_adi_v5.c:2287
int mem_ap_read_buf_noincr(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:734
int adiv5_verify_config(struct adiv5_private_config *pc)
Definition: arm_adi_v5.c:2484
int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Asynchronous (queued) write of a word to memory or a system register.
Definition: arm_adi_v5.c:289
int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
Definition: arm_adi_v5.c:2479
int dap_find_get_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
Definition: arm_adi_v5.c:1107
int mem_ap_write_buf_noincr(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:740
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Synchronous read of a word from memory or a system register.
Definition: arm_adi_v5.c:266
struct adiv5_ap * dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1189
int dap_put_ap(struct adiv5_ap *ap)
Definition: arm_adi_v5.c:1209
int mem_ap_init(struct adiv5_ap *ap)
Initialize a DAP.
Definition: arm_adi_v5.c:888
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Synchronous write of a word to memory or a system register.
Definition: arm_adi_v5.c:318
@ AP_TYPE_APB_AP
Definition: arm_adi_v5.h:491
#define DP_APSEL_INVALID
Definition: arm_adi_v5.h:110
static int dap_run(struct adiv5_dap *dap)
Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they ar...
Definition: arm_adi_v5.h:648
#define ARM_CS_C9_DEVTYPE_CORE_DEBUG
Definition: arm_coresight.h:88
void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
Definition: arm_dpm.c:1055
int arm_dpm_read_current_registers(struct arm_dpm *dpm)
Read basic registers of the current context: R0 to R15, and CPSR; sets the core mode (such as USR or ...
Definition: arm_dpm.c:377
int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
Definition: arm_dpm.c:146
int arm_dpm_setup(struct arm_dpm *dpm)
Hooks up this DPM to its associated target; call only once.
Definition: arm_dpm.c:1093
int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
Definition: arm_dpm.c:208
int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
Writes all modified core registers for all processor modes.
Definition: arm_dpm.c:485
void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
Definition: arm_dpm.c:1031
int arm_dpm_initialize(struct arm_dpm *dpm)
Reinitializes DPM state at the beginning of a new debug session or after a reset which may have affec...
Definition: arm_dpm.c:1160
#define OSLSR_OSLM
Definition: arm_dpm.h:248
#define DRCR_HALT
Definition: arm_dpm.h:223
#define DSCR_INSTR_COMP
Definition: arm_dpm.h:190
#define DRCR_CLEAR_EXCEPTIONS
Definition: arm_dpm.h:225
#define DSCR_INT_DIS
Definition: arm_dpm.h:180
#define OSLSR_OSLM0
Definition: arm_dpm.h:244
#define DSCR_STICKY_ABORT_IMPRECISE
Definition: arm_dpm.h:176
#define DSCR_EXT_DCC_FAST_MODE
Definition: arm_dpm.h:216
#define OSLSR_OSLK
Definition: arm_dpm.h:245
#define DSCR_DTR_TX_FULL
Definition: arm_dpm.h:194
#define DSCR_DTRRX_FULL_LATCHED
Definition: arm_dpm.h:193
#define DRCR_RESTART
Definition: arm_dpm.h:224
#define DSCR_RUN_MODE(dscr)
Definition: arm_dpm.h:198
#define DSCR_STICKY_ABORT_PRECISE
Definition: arm_dpm.h:175
#define OSLSR_OSLM1
Definition: arm_dpm.h:247
#define DSCR_CORE_HALTED
Definition: arm_dpm.h:172
#define DSCR_ITR_EN
Definition: arm_dpm.h:182
#define DSCR_EXT_DCC_NON_BLOCKING
Definition: arm_dpm.h:214
#define PRSR_STICKY_RESET_STATUS
Definition: arm_dpm.h:238
#define PRSR_POWERUP_STATUS
Definition: arm_dpm.h:235
#define DSCR_EXT_DCC_MASK
Definition: arm_dpm.h:189
#define DSCR_DTR_RX_FULL
Definition: arm_dpm.h:195
#define DSCR_CORE_RESTARTED
Definition: arm_dpm.h:173
#define DSCR_HALT_DBG_MODE
Definition: arm_dpm.h:183
#define DSCR_DTRTX_FULL_LATCHED
Definition: arm_dpm.h:192
Macros used to generate various ARM or Thumb opcodes.
#define ARMV5_BKPT(im)
Definition: arm_opcodes.h:227
#define ARMV4_5_STC(p, u, d, w, cp, crd, rn, imm)
Definition: arm_opcodes.h:159
#define ARMV5_T_BKPT(im)
Definition: arm_opcodes.h:313
#define ARMV4_5_LDC(p, u, d, w, cp, crd, rn, imm)
Definition: arm_opcodes.h:174
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:186
#define ARMV4_5_STRH_IP(rd, rn)
Definition: arm_opcodes.h:105
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:209
#define ARMV4_5_LDRH_IP(rd, rn)
Definition: arm_opcodes.h:87
#define ARMV4_5_LDRB_IP(rd, rn)
Definition: arm_opcodes.h:93
#define ARMV4_5_LDRW_IP(rd, rn)
Definition: arm_opcodes.h:81
#define ARMV4_5_STRW_IP(rd, rn)
Definition: arm_opcodes.h:99
#define ARMV4_5_STRB_IP(rd, rn)
Definition: arm_opcodes.h:111
int arm_semihosting(struct target *target, int *retval)
Checks for and processes an ARM semihosting request.
int arm_semihosting_init(struct target *target)
Initialize ARM semihosting support.
enum arm_mode mode
Definition: armv4_5.c:277
int armv7a_handle_cache_info_command(struct command_invocation *cmd, struct armv7a_cache_common *armv7a_cache)
Definition: armv7a.c:230
int armv7a_read_ttbcr(struct target *target)
Definition: armv7a.c:118
int armv7a_arch_state(struct target *target)
Definition: armv7a.c:531
const struct command_registration armv7a_command_handlers[]
Definition: armv7a.c:587
int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
Definition: armv7a.c:515
int armv7a_identify_cache(struct target *target)
Definition: armv7a.c:364
#define CPUDBG_DSMCR
Definition: armv7a.h:164
#define CPUDBG_DSCCR
Definition: armv7a.h:163
#define CPUDBG_OSLAR
Definition: armv7a.h:157
#define CPUDBG_BCR_BASE
Definition: armv7a.h:151
#define CPUDBG_OSLSR
Definition: armv7a.h:158
#define CPUDBG_DSCR
Definition: armv7a.h:139
#define CPUDBG_DRCR
Definition: armv7a.h:140
#define CPUDBG_DIDR
Definition: armv7a.h:134
#define CPUDBG_WCR_BASE
Definition: armv7a.h:153
#define CPUDBG_DTRTX
Definition: armv7a.h:147
static struct armv7a_common * target_to_armv7a(struct target *target)
Definition: armv7a.h:120
#define CPUDBG_WVR_BASE
Definition: armv7a.h:152
#define CPUDBG_WFAR
Definition: armv7a.h:137
#define CPUDBG_BVR_BASE
Definition: armv7a.h:150
#define CPUDBG_DTRRX
Definition: armv7a.h:145
#define CPUDBG_PRSR
Definition: armv7a.h:142
#define CPUDBG_ITR
Definition: armv7a.h:146
#define CPUDBG_ID_PFR1
Definition: armv7a.h:170
int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt, uint32_t size)
Definition: armv7a_cache.c:335
int armv7a_cache_flush_virt(struct target *target, uint32_t virt, uint32_t size)
Definition: armv7a_cache.c:384
int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt, uint32_t size)
Definition: armv7a_cache.c:146
const struct command_registration armv7a_mmu_command_handlers[]
Definition: armv7a_mmu.c:362
int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, target_addr_t *val, int meminfo)
Definition: armv7a_mmu.c:27
@ ARMV7M_PRIMASK
Definition: armv7m.h:144
@ ARMV7M_XPSR
Definition: armv7m.h:127
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:104
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
struct breakpoint * breakpoint_find(struct target *target, target_addr_t address)
Definition: breakpoints.c:489
@ BKPT_HARD
Definition: breakpoints.h:18
@ BKPT_SOFT
Definition: breakpoints.h:19
static void watchpoint_set(struct watchpoint *watchpoint, unsigned int number)
Definition: breakpoints.h:83
static void breakpoint_hw_set(struct breakpoint *breakpoint, unsigned int hw_number)
Definition: breakpoints.h:66
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:443
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:402
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:146
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
@ COMMAND_ANY
Definition: command.h:42
@ COMMAND_EXEC
Definition: command.h:40
static int cortex_a_dpm_finish(struct arm_dpm *dpm)
Definition: cortex_a.c:397
static int cortex_a_read_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: cortex_a.c:2711
static int cortex_a_mmu(struct target *target, int *enabled)
Definition: cortex_a.c:3204
static int cortex_a_target_create(struct target *target, Jim_Interp *interp)
Definition: cortex_a.c:3132
static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
Definition: cortex_a.c:369
static int cortex_a_exec_opcode(struct target *target, uint32_t opcode, uint32_t *dscr_p)
Definition: cortex_a.c:283
static const struct command_registration cortex_a_command_handlers[]
Definition: cortex_a.c:3361
static int cortex_a_write_dcc(struct cortex_a_common *a, uint32_t data)
Definition: cortex_a.c:333
static int cortex_a_write_dfar_dfsr(struct target *target, uint32_t dfar, uint32_t dfsr, uint32_t *dscr)
Definition: cortex_a.c:2096
static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr)
Definition: cortex_a.c:633
static int cortex_a_write_buffer(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer)
Definition: cortex_a.c:2816
static int cortex_a_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer)
Definition: cortex_a.c:2782
static int cortex_a_init_debug_access(struct target *target)
Definition: cortex_a.c:208
static int cortex_a_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
Remove a watchpoint from an Cortex-A target.
Definition: cortex_a.c:1869
static int cortex_a_instr_cpsr_sync(struct arm_dpm *dpm)
Definition: cortex_a.c:483
static const struct command_registration cortex_r4_exec_command_handlers[]
Definition: cortex_a.c:3426
static const struct command_registration cortex_a_exec_command_handlers[]
Definition: cortex_a.c:3322
static int cortex_a_read_cpu_memory_slow(struct target *target, uint32_t size, uint32_t count, uint8_t *buffer, uint32_t *dscr)
Definition: cortex_a.c:2397
static int cortex_a_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: cortex_a.c:2731
static int cortex_a_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Definition: cortex_a.c:987
static int cortex_a_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
Definition: cortex_a.c:1171
static int cortex_a_read_copro(struct target *target, uint32_t opcode, uint32_t *data, uint32_t *dscr)
Definition: cortex_a.c:2009
static int cortex_a_instr_read_data_r0_r1(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Definition: cortex_a.c:551
static int cortex_a_instr_read_data_dcc(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Definition: cortex_a.c:494
static int cortex_a_restore_context(struct target *target, bool bpwp)
Definition: cortex_a.c:1263
static int cortex_a_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_a.c:1665
static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
Definition: cortex_a.c:968
static int cortex_a_handle_target_request(void *priv)
Definition: cortex_a.c:2850
static int cortex_a_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
Add a watchpoint to an Cortex-A target.
Definition: cortex_a.c:1844
static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
Sets a watchpoint for an Cortex-A target in one of the watchpoint units.
Definition: cortex_a.c:1697
static int cortex_a_init_arch_info(struct target *target, struct cortex_a_common *cortex_a, struct adiv5_dap *dap)
Definition: cortex_a.c:3103
static int cortex_a_instr_write_data_r0(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Definition: cortex_a.c:441
static int cortex_a_post_debug_entry(struct target *target)
Definition: cortex_a.c:1101
struct target_type cortexr4_target
Definition: cortex_a.c:3458
static int update_halt_gdb(struct target *target)
Definition: cortex_a.c:689
static int cortex_a_read_cpu_memory_fast(struct target *target, uint32_t count, uint8_t *buffer, uint32_t *dscr)
Definition: cortex_a.c:2474
static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_a.c:1421
static int cortex_r4_target_create(struct target *target, Jim_Interp *interp)
Definition: cortex_a.c:3154
static int cortex_a_add_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_a.c:1648
static int cortex_a_examine(struct target *target)
Definition: cortex_a.c:3077
static int cortex_a_write_cpu_memory_slow(struct target *target, uint32_t size, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
Definition: cortex_a.c:2139
static int cortex_a_halt_smp(struct target *target)
Definition: cortex_a.c:675
static int cortex_a_add_context_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_a.c:1632
static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_a.c:1502
static int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
Definition: cortex_a.c:1148
static int cortex_a_deassert_reset(struct target *target)
Definition: cortex_a.c:1925
static int cortex_a_write_copro(struct target *target, uint32_t opcode, uint32_t data, uint32_t *dscr)
Definition: cortex_a.c:2063
static int cortex_a_read_dfar_dfsr(struct target *target, uint32_t *dfar, uint32_t *dfsr, uint32_t *dscr)
Definition: cortex_a.c:2043
static int cortex_a_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
Unset an existing watchpoint and clear the used watchpoint unit.
Definition: cortex_a.c:1799
static int cortex_a_internal_restore(struct target *target, int current, target_addr_t *address, int handle_breakpoints, int debug_execution)
Definition: cortex_a.c:820
static int cortex_a_set_dcc_mode(struct target *target, uint32_t mode, uint32_t *dscr)
Definition: cortex_a.c:1958
static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t, uint32_t addr, uint32_t control)
Definition: cortex_a.c:574
static int cortex_a_mmu_modify(struct target *target, int enable)
Definition: cortex_a.c:168
static int cortex_a_virt2phys(struct target *target, target_addr_t virt, target_addr_t *phys)
Definition: cortex_a.c:3221
static int cortex_a_examine_first(struct target *target)
Definition: cortex_a.c:2891
static int cortex_a_instr_read_data_r0(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Definition: cortex_a.c:532
static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool force)
Definition: cortex_a.c:255
static int cortex_a_init_target(struct command_context *cmd_ctx, struct target *target)
Definition: cortex_a.c:3095
static int cortex_a_poll(struct target *target)
Definition: cortex_a.c:735
static void cortex_a_deinit_target(struct target *target)
Definition: cortex_a.c:3174
static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t)
Definition: cortex_a.c:609
static int cortex_a_restore_cp15_control_reg(struct target *target)
Definition: cortex_a.c:90
static const struct command_registration cortex_r4_command_handlers[]
Definition: cortex_a.c:3444
static int cortex_a_post_memaccess(struct target *target, int phys_access)
Definition: cortex_a.c:142
static int cortex_a_write_cpu_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: cortex_a.c:2244
COMMAND_HANDLER(cortex_a_handle_cache_info_command)
Definition: cortex_a.c:3247
static int cortex_a_set_breakpoint(struct target *target, struct breakpoint *breakpoint, uint8_t matchmode)
Definition: cortex_a.c:1280
static int cortex_a_halt(struct target *target)
Definition: cortex_a.c:792
static int cortex_a_instr_write_data_dcc(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Definition: cortex_a.c:403
static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data, uint32_t *dscr_p)
Definition: cortex_a.c:340
static int cortex_a_write_cpu_memory_fast(struct target *target, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
Definition: cortex_a.c:2215
static int cortex_a_set_context_breakpoint(struct target *target, struct breakpoint *breakpoint, uint8_t matchmode)
Definition: cortex_a.c:1372
static int cortex_a_prep_memaccess(struct target *target, int phys_access)
Definition: cortex_a.c:112
static int cortex_a_read_cpu_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: cortex_a.c:2561
static int cortex_a_internal_restart(struct target *target)
Definition: cortex_a.c:918
static int cortex_a_dfsr_to_error_code(uint32_t dfsr)
Definition: cortex_a.c:2112
static int cortex_a_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_a.c:1616
static int cortex_a_instr_write_data_r0_r1(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Definition: cortex_a.c:461
static int cortex_a_instr_write_data_rt_dcc(struct arm_dpm *dpm, uint8_t rt, uint32_t data)
Definition: cortex_a.c:420
static int cortex_a_debug_entry(struct target *target)
Definition: cortex_a.c:1022
static int cortex_a_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: cortex_a.c:2767
static int cortex_a_instr_read_data_rt_dcc(struct arm_dpm *dpm, uint8_t rt, uint32_t *data)
Definition: cortex_a.c:512
static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask, uint32_t value, uint32_t *dscr)
Definition: cortex_a.c:1980
static struct cortex_a_common * dpm_to_a(struct arm_dpm *dpm)
Definition: cortex_a.c:328
static int cortex_a_write_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: cortex_a.c:2747
static int cortex_a_assert_reset(struct target *target)
Definition: cortex_a.c:1885
struct target_type cortexa_target
Definition: cortex_a.c:3378
static struct target * get_cortex_a(struct target *target, int32_t coreid)
Definition: cortex_a.c:662
static unsigned int ilog2(unsigned int x)
Definition: cortex_a.c:78
static struct cortex_a_common * target_to_cortex_a(struct target *target)
Definition: cortex_a.h:104
@ CORTEX_A_ISRMASK_OFF
Definition: cortex_a.h:45
@ CORTEX_A_ISRMASK_ON
Definition: cortex_a.h:46
@ CORTEX_A_DACRFIXUP_ON
Definition: cortex_a.h:51
@ CORTEX_A_DACRFIXUP_OFF
Definition: cortex_a.h:50
#define CORTEX_A_COMMON_MAGIC
Definition: cortex_a.h:22
int mask
Definition: esirisc.c:1741
uint8_t type
Definition: esp_usb_jtag.c:0
static struct esp_usb_jtag * priv
Definition: esp_usb_jtag.c:219
bool transport_is_jtag(void)
Returns true if the current debug session is using JTAG as its transport.
Definition: jtag/core.c:1827
int adapter_deassert_reset(void)
Definition: jtag/core.c:1899
enum reset_types jtag_get_reset_config(void)
Definition: jtag/core.c:1734
int adapter_assert_reset(void)
Definition: jtag/core.c:1879
@ RESET_SRST_NO_GATING
Definition: jtag.h:225
@ RESET_HAS_SRST
Definition: jtag.h:219
#define LOG_WARNING(expr ...)
Definition: log.h:129
#define ERROR_FAIL
Definition: log.h:170
#define LOG_TARGET_ERROR(target, fmt_str,...)
Definition: log.h:158
#define LOG_TARGET_DEBUG(target, fmt_str,...)
Definition: log.h:149
#define LOG_ERROR(expr ...)
Definition: log.h:132
#define LOG_INFO(expr ...)
Definition: log.h:126
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:164
const struct nvp * nvp_name2value(const struct nvp *p, const char *name)
Definition: nvp.c:29
const struct nvp * nvp_value2name(const struct nvp *p, int value)
Definition: nvp.c:39
void register_cache_invalidate(struct reg_cache *cache)
Marks the contents of the register cache as invalid (and clean).
Definition: register.c:94
target_addr_t addr
Start address to search for the control block.
Definition: rtt/rtt.c:28
struct target * target
Definition: rtt/rtt.c:26
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
const struct command_registration smp_command_handlers[]
Definition: smp.c:153
#define foreach_smp_target(pos, head)
Definition: smp.h:15
#define BIT(nr)
Definition: stm32l4x.h:18
uint64_t ap_num
ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coheren...
Definition: arm_adi_v5.h:261
struct adiv5_dap * dap
DAP this AP belongs to.
Definition: arm_adi_v5.h:254
uint32_t memaccess_tck
Configures how many extra tck clocks are added after starting a MEM-AP access before we try to read i...
Definition: arm_adi_v5.h:306
This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
Definition: arm_adi_v5.h:348
uint64_t apsel
Definition: arm_adi_v5.h:367
struct adiv5_dap * dap
Definition: arm_adi_v5.h:787
This wraps an implementation of DPM primitives.
Definition: arm_dpm.h:47
int(* instr_read_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from dcc after execution.
Definition: arm_dpm.h:91
uint64_t didr
Cache of DIDR.
Definition: arm_dpm.h:51
int(* instr_write_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to R0 before execution.
Definition: arm_dpm.h:72
struct arm * arm
Definition: arm_dpm.h:48
int(* bpwp_enable)(struct arm_dpm *dpm, unsigned int index_value, uint32_t addr, uint32_t control)
Enables one breakpoint or watchpoint by writing to the hardware registers.
Definition: arm_dpm.h:122
int(* finish)(struct arm_dpm *dpm)
Invoke after a series of instruction operations.
Definition: arm_dpm.h:57
struct dpm_bp * dbp
Definition: arm_dpm.h:139
int(* instr_write_data_dcc)(struct arm_dpm *dpm, uint32_t opcode, uint32_t data)
Runs one instruction, writing data to DCC before execution.
Definition: arm_dpm.h:65
int(* prepare)(struct arm_dpm *dpm)
Invoke before a series of instruction operations.
Definition: arm_dpm.h:54
int(* instr_read_data_r0)(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data)
Runs one instruction, reading data from r0 after execution.
Definition: arm_dpm.h:98
int(* instr_read_data_r0_r1)(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data)
Runs two instructions, reading data from r0 and r1 after execution.
Definition: arm_dpm.h:105
struct dpm_wp * dwp
Definition: arm_dpm.h:140
int(* bpwp_disable)(struct arm_dpm *dpm, unsigned int index_value)
Disables one breakpoint or watchpoint by clearing its hardware control registers.
Definition: arm_dpm.h:130
int(* instr_cpsr_sync)(struct arm_dpm *dpm)
Optional core-specific operation invoked after CPSR writes.
Definition: arm_dpm.h:86
int(* instr_write_data_r0_r1)(struct arm_dpm *dpm, uint32_t opcode, uint64_t data)
Runs two instructions, writing data to R0 and R1 before execution.
Definition: arm_dpm.h:78
uint32_t dscr
Recent value of DSCR.
Definition: arm_dpm.h:150
Represents a generic ARM core, with standard application registers.
Definition: arm.h:175
enum arm_core_type core_type
Indicates what registers are in the ARM state core register set.
Definition: arm.h:193
int(* mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
Read coprocessor register.
Definition: arm.h:230
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
Definition: arm.h:196
struct adiv5_dap * dap
For targets conforming to ARM Debug Interface v5, this handle references the Debug Access Port (DAP) ...
Definition: arm.h:257
struct reg * pc
Handle to the PC; valid in all core modes.
Definition: arm.h:181
struct reg_cache * core_cache
Definition: arm.h:178
int(* mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
Write coprocessor register.
Definition: arm.h:241
struct reg * spsr
Handle to the SPSR; valid only in core modes with an SPSR.
Definition: arm.h:187
int arm_vfp_version
Floating point or VFP version, 0 if disabled.
Definition: arm.h:205
struct target * target
Backpointer to the target.
Definition: arm.h:210
enum arm_state core_state
Record the current core state: ARM, Thumb, or otherwise.
Definition: arm.h:199
int d_u_cache_enabled
Definition: armv7a.h:67
bool is_armv7r
Definition: armv7a.h:103
int(* post_debug_entry)(struct target *target)
Definition: armv7a.h:114
int(* examine_debug_reason)(struct target *target)
Definition: armv7a.h:113
target_addr_t debug_base
Definition: armv7a.h:95
struct arm arm
Definition: armv7a.h:90
struct armv7a_mmu_common armv7a_mmu
Definition: armv7a.h:111
struct arm_dpm dpm
Definition: armv7a.h:94
struct adiv5_ap * debug_ap
Definition: armv7a.h:96
void(* pre_restore_context)(struct target *target)
Definition: armv7a.h:116
struct armv7a_cache_common armv7a_cache
Definition: armv7a.h:83
int(* read_physical_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: armv7a.h:81
uint32_t mmu_enabled
Definition: armv7a.h:84
int linked_brp
Definition: breakpoints.h:36
unsigned int length
Definition: breakpoints.h:29
uint8_t * orig_instr
Definition: breakpoints.h:33
enum breakpoint_type type
Definition: breakpoints.h:30
bool is_set
Definition: breakpoints.h:31
unsigned int number
Definition: breakpoints.h:32
uint32_t asid
Definition: breakpoints.h:28
target_addr_t address
Definition: breakpoints.h:27
const char * name
Definition: command.h:235
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
Definition: command.h:249
uint32_t value
Definition: cortex_a.h:57
uint32_t control
Definition: cortex_a.h:58
bool used
Definition: cortex_a.h:55
uint8_t brpn
Definition: cortex_a.h:59
struct armv7a_common armv7a_common
Definition: cortex_a.h:72
struct cortex_a_wrp * wrp_list
Definition: cortex_a.h:94
uint32_t didr
Definition: cortex_a.h:97
int brp_num_context
Definition: cortex_a.h:88
struct cortex_a_brp * brp_list
Definition: cortex_a.h:91
uint32_t cp15_control_reg_curr
Definition: cortex_a.h:80
enum cortex_a_dacrfixup_mode dacrfixup_mode
Definition: cortex_a.h:100
int wrp_num_available
Definition: cortex_a.h:93
uint32_t cpudbg_dscr
Definition: cortex_a.h:75
uint32_t cp15_dacr_reg
Definition: cortex_a.h:84
unsigned int common_magic
Definition: cortex_a.h:70
enum cortex_a_isrmasking_mode isrmasking_mode
Definition: cortex_a.h:99
uint32_t cpuid
Definition: cortex_a.h:96
enum arm_mode curr_mode
Definition: cortex_a.h:85
uint32_t cp15_control_reg
Definition: cortex_a.h:78
int brp_num_available
Definition: cortex_a.h:90
uint8_t wrpn
Definition: cortex_a.h:66
bool used
Definition: cortex_a.h:63
uint32_t value
Definition: cortex_a.h:64
uint32_t control
Definition: cortex_a.h:65
int32_t core[2]
Definition: target.h:100
struct target * target
Definition: target.h:95
Name Value Pairs, aka: NVP.
Definition: nvp.h:61
int value
Definition: nvp.h:63
const char * name
Definition: nvp.h:62
Definition: register.h:111
bool valid
Definition: register.h:126
uint8_t * value
Definition: register.h:122
bool dirty
Definition: register.h:124
struct target * target
Definition: target.h:214
This holds methods shared between all instances of a given target type.
Definition: target_type.h:26
const char * name
Name of this type of target.
Definition: target_type.h:31
Definition: target.h:116
int32_t coreid
Definition: target.h:120
struct gdb_service * gdb_service
Definition: target.h:199
bool dbgbase_set
Definition: target.h:174
bool dbg_msg_enabled
Definition: target.h:163
enum target_debug_reason debug_reason
Definition: target.h:154
enum target_state state
Definition: target.h:157
uint32_t dbgbase
Definition: target.h:175
void * private_config
Definition: target.h:165
struct list_head * smp_targets
Definition: target.h:188
unsigned int smp
Definition: target.h:187
bool reset_halt
Definition: target.h:144
char * cmd_name
Definition: target.h:118
bool is_set
Definition: breakpoints.h:47
unsigned int length
Definition: breakpoints.h:43
unsigned int number
Definition: breakpoints.h:48
target_addr_t address
Definition: breakpoints.h:42
int target_call_event_callbacks(struct target *target, enum target_event event)
Definition: target.c:1764
void target_free_all_working_areas(struct target *target)
Definition: target.c:2150
void target_buffer_set_u16(struct target *target, uint8_t *buffer, uint16_t value)
Definition: target.c:370
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
Definition: target.c:352
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1265
int target_register_timer_callback(int(*callback)(void *priv), unsigned int time_ms, enum target_timer_type type, void *priv)
The period is very approximate, the callback can happen much more often or much more rarely than spec...
Definition: target.c:1658
uint16_t target_buffer_get_u16(struct target *target, const uint8_t *buffer)
Definition: target.c:334
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
Definition: target.c:1237
bool target_has_event_action(const struct target *target, enum target_event event)
Returns true only if the target has a handler for the specified event.
Definition: target.c:4860
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:458
void target_handle_event(struct target *target, enum target_event e)
Definition: target.c:4667
uint32_t target_buffer_get_u32(struct target *target, const uint8_t *buffer)
Definition: target.c:316
@ DBG_REASON_NOTHALTED
Definition: target.h:74
@ DBG_REASON_DBGRQ
Definition: target.h:69
@ DBG_REASON_SINGLESTEP
Definition: target.h:73
@ DBG_REASON_WATCHPOINT
Definition: target.h:71
@ DBG_REASON_BREAKPOINT
Definition: target.h:70
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:790
#define ERROR_TARGET_INIT_FAILED
Definition: target.h:788
static bool target_was_examined(const struct target *target)
Definition: target.h:436
#define ERROR_TARGET_UNALIGNED_ACCESS
Definition: target.h:792
#define ERROR_TARGET_INVALID
Definition: target.h:787
@ TARGET_TIMER_TYPE_PERIODIC
Definition: target.h:327
@ TARGET_EVENT_DEBUG_RESUMED
Definition: target.h:272
@ TARGET_EVENT_HALTED
Definition: target.h:252
@ TARGET_EVENT_RESUMED
Definition: target.h:253
@ TARGET_EVENT_DEBUG_HALTED
Definition: target.h:271
@ TARGET_EVENT_RESET_ASSERT
Definition: target.h:264
static const char * target_name(const struct target *target)
Returns the instance-specific name of the specified target.
Definition: target.h:233
target_state
Definition: target.h:53
@ TARGET_RESET
Definition: target.h:57
@ TARGET_DEBUG_RUNNING
Definition: target.h:58
@ TARGET_UNKNOWN
Definition: target.h:54
@ TARGET_HALTED
Definition: target.h:56
@ TARGET_RUNNING
Definition: target.h:55
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:794
static void target_set_examined(struct target *target)
Sets the examined flag for the given target.
Definition: target.h:443
#define ERROR_TARGET_DATA_ABORT
Definition: target.h:793
#define ERROR_TARGET_TRANSLATION_FAULT
Definition: target.h:795
int target_request(struct target *target, uint32_t request)
int64_t timeval_ms(void)
#define TARGET_ADDR_FMT
Definition: types.h:342
uint64_t target_addr_t
Definition: types.h:335
#define container_of(ptr, type, member)
Cast a member of a structure out to the containing structure.
Definition: types.h:68
#define NULL
Definition: usb.h:16
uint8_t status[4]
Definition: vdebug.c:17
uint8_t dummy[96]
Definition: vdebug.c:23
uint8_t count[4]
Definition: vdebug.c:22